Re: [coreboot] Port80 isn't working (ASUS P8B75-V) (Konstantin Novikov)

[Константин]

Hello, Peter!
The mistake was found in the following part of the code
(southbridge/intel/bd82x6x/bootblock.c):

static void bootblock_southbridge_init(void)
{
       store_initial_timestamp();
       enable_spi_prefetch();
       enable_port80_on_lpc();
       set_spi_speed();

/* Enable upper 128bytes of CMOS */
       RCBA32(RC) = (1 << 2);
}

This mistake was eliminated in the Haswell-code:

static void map_rcba(void)
{
    pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);

pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
}

static void enable_port80_on_lpc(void)
{
    /* Enable port 80 POST on LPC. */
    u32 gcs = RCBA32(GCS);
    gcs = gcs & ~0x4;
    RCBA32(GCS) = gcs;
}

static void bootblock_southbridge_init(void)
{
    store_initial_timestamp();

map_rcba();
    enable_spi_prefetch();
#if CONFIG_POST_DEVICE_LPC
    enable_port80_on_lpc();
#endif
    set_spi_speed();

/* Enable upper 128bytes of CMOS */
    RCBA32(RC) = (1 << 2);
}

After that all the post-codes are sended correctly.

Also we have found he mistake in the part of the code for the memory-banks.
In the code for SandyBridge/IvyBridge variables are assigned "hardly" while
for the Haswell variables are defined dynamically:

static void configure_mca(void)
{
    msr_t msr;
    int i;

msr.lo = msr.hi = 0;
    /* This should only be done on a cold boot */
    for (i = 0; i < 7; i++)
        wrmsr(IA32_MC0_STATUS + (i * 4), msr);
}

Now I port ASUS P8B75-V motherboard. Everything is OK with using Intel Core
i3, but with Intel Celeron G440 on the seventh iteration we have got a
mistake because there is not the seventh memory bank there. With using
Haswell-code our project runs correctly with both processors:

static void configure_mca(void)
{
    msr_t msr;
    int i;
    int num_banks;
    const unsigned int mcg_cap_msr = 0x179;

msr = rdmsr(mcg_cap_msr);
    num_banks = msr.lo & 0xff;
    msr.lo = msr.hi = 0;
    /* This should only be done on a cold boot */
    for (i = 0; i < num_banks; i++)
        wrmsr(IA32_MC0_STATUS + (i * 4), msr);
}