Hi folks,
I am trying to put coreboot on a T440p that runs the latest OEM Firmware from April 2020. According to the official coreboot documentation, it should be doable by just flashing the (easily accessible) 4MB chip. While I successfully extracted the OEM ROM from this 4 MB chip using an external programmer and obtained the mrc.bin as explained in coreboot's docs, I failed to build coreboot itself. The build fails because I don't have the other proprietary parts (descriptor.bin, me.bin, gbe.bin).
All reports I found extract the ROM from both the 4 MB and 8 MB chips, put them together, and then run ifdtool on it to obtain these parts. If I try running ifdtool on just the 4MB dump, I get the following:
~/coreboot/util/ifdtool$ ./ifdtool -x t440p_4mb.rom File t440p_4mb.rom is 4194304 bytes Unknown descriptor version: 1
Also, I can't extract them using me_cleaner.
Are these parts supposed to be contained in coreboot's 3rdparty repos (where I can't find them)? Or do I need to disassemble the whole device to extract the ROM from the 8MB chip as well in order to obtain these parts using ifdtool? Or is this process meant the way that I should build coreboot without these parts and only flash the BIOS region, not touching them?
Thanks a lot in advance.
Cheers, Daniel
Hi Daniel,
On 13.10.20 21:59, Daniel Kulesz via coreboot wrote:
The build fails because I don't have the other proprietary parts (descriptor.bin, me.bin, gbe.bin).
you can simply omit them. If you don't tell that you have them (in your config), coreboot won't miss them.
Or is this process meant the way that I should build coreboot without these parts and only flash the BIOS region, not touching them?
That's it. Generally, for any retrofit coreboot, they are already on the machine, so you never have to extract them. In case of the T440p, the BIOS region spans the end of the 8MiB and the whole 4MiB chip[1]. Hence, you never need to deal with descriptor/gbe/me if you only flash the latter.
Remember to build coreboot for 12MiB and take the last 4MiB of the resulting `coreboot.rom` and always keep a backup ;)
Nico
[1] https://doc.coreboot.org/_images/flashlayout_Ivy_Bridge.svg
Hi Nico,
thank you, this helped me a lot and I got coreboot running by just flashing the top 4MB to the smaller chip. Yet there are a few things I still don't understand:
- as the bios region spans both chips, how does this work when I only flash the bios region into one part of this region? I assumed some of the original bios would be missing, resulting in a brick. - where is the firmware of the EC controller actually located? It's not mentioned in the ROM layout map. - to my understanding, applying me_cleaner would mean I need to flash the 8MB chip as well. Can this be done internally once I have coreboot running or will the ifd lock in the descriptor (that was left untouched) block this access, so in the end I will need to disassemble the T440p to get physical access to the 8MB chip? - to take advantage of the space gained by applying me_cleaner, the descriptor would need to be reflashed as well, right? Can this be done internally as well? - I tried to compile GRUB as payload first, but it didn't fit in the space so I had to go for SeaBIOS. Is there a way to get GRUB working without touching the 8MB chip? I wonder why it doesn't fit into the 4 MB space of the smaller ... is the size of the CBFS region set correctly to the available maximum by default?
Again, thanks a lot! I will try to submit a merge request for the doc article about the T440p once I get a better understanding of this.
Cheers, Daniel
On Tue, 13 Oct 2020 22:18:23 +0200 Nico Huber nico.h@gmx.de wrote:
Hi Daniel,
On 13.10.20 21:59, Daniel Kulesz via coreboot wrote:
The build fails because I don't have the other proprietary parts (descriptor.bin, me.bin, gbe.bin).
you can simply omit them. If you don't tell that you have them (in your config), coreboot won't miss them.
Or is this process meant the way that I should build coreboot without these parts and only flash the BIOS region, not touching them?
That's it. Generally, for any retrofit coreboot, they are already on the machine, so you never have to extract them. In case of the T440p, the BIOS region spans the end of the 8MiB and the whole 4MiB chip[1]. Hence, you never need to deal with descriptor/gbe/me if you only flash the latter.
Remember to build coreboot for 12MiB and take the last 4MiB of the resulting `coreboot.rom` and always keep a backup ;)
Nico
[1] https://doc.coreboot.org/_images/flashlayout_Ivy_Bridge.svg
hi Daniel,
On Tue, Oct 13, 2020 at 4:48 PM Daniel Kulesz via coreboot coreboot@coreboot.org wrote:
Hi Nico,
thank you, this helped me a lot and I got coreboot running by just flashing the top 4MB to the smaller chip. Yet there are a few things I still don't understand:
- as the bios region spans both chips, how does this work when I only flash the bios region into one part of this region? I assumed some of the original bios would be missing, resulting in a brick.
the top of the BIOS region is at the end of the 4MB chip, and that's where things start from; the part at the end of the 8MB chip doesn't matter uless your CBFS is > 4MB
- where is the firmware of the EC controller actually located? It's not mentioned in the ROM layout map.
on your device, it's on a separate chip, not the main SPI flash
- to my understanding, applying me_cleaner would mean I need to flash the 8MB chip as well. Can this be done internally once I have coreboot running or will the ifd lock in the descriptor (that was left untouched) block this access, so in the end I will need to disassemble the T440p to get physical access to the 8MB chip?
not 'as well,' you would need to flash the 8MB chip only, since that is where the IFD and ME regions are. By default, the IFD locks the IFD/ME regions from being written to internally, so you must flash the IFD (at a minimum) externally first to allow for internal flashing of the IFD/ME regions.
- to take advantage of the space gained by applying me_cleaner, the descriptor would need to be reflashed as well, right? Can this be done internally as well?
yes. not initially -- see above.
- I tried to compile GRUB as payload first, but it didn't fit in the space so I had to go for SeaBIOS. Is there a way to get GRUB working without touching the 8MB chip? I wonder why it doesn't fit into the 4 MB space of the smaller ... is the size of the CBFS region set correctly to the available maximum by default?
the CBFS default is usually much smaller than the BIOS region, I'm guessing 1-2MB. You can set it to 4MB and then use most other payloads, and only flash the 4MB chip.
Again, thanks a lot! I will try to submit a merge request for the doc article about the T440p once I get a better understanding of this.
Cheers, Daniel
cheers, Matt
On Tue, 13 Oct 2020 22:18:23 +0200 Nico Huber nico.h@gmx.de wrote:
Hi Daniel,
On 13.10.20 21:59, Daniel Kulesz via coreboot wrote:
The build fails because I don't have the other proprietary parts (descriptor.bin, me.bin, gbe.bin).
you can simply omit them. If you don't tell that you have them (in your config), coreboot won't miss them.
Or is this process meant the way that I should build coreboot without these parts and only flash the BIOS region, not touching them?
That's it. Generally, for any retrofit coreboot, they are already on the machine, so you never have to extract them. In case of the T440p, the BIOS region spans the end of the 8MiB and the whole 4MiB chip[1]. Hence, you never need to deal with descriptor/gbe/me if you only flash the latter.
Remember to build coreboot for 12MiB and take the last 4MiB of the resulting `coreboot.rom` and always keep a backup ;)
Nico
[1] https://doc.coreboot.org/_images/flashlayout_Ivy_Bridge.svg
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