On Tue, Oct 13, 2020 at 4:48 PM Daniel Kulesz via coreboot
thank you, this helped me a lot and I got coreboot running by just flashing the top 4MB
to the smaller chip. Yet there are a few things I still don't understand:
- as the bios region spans both chips, how does this work when I only flash the bios
region into one part of this region? I assumed some of the original bios would be missing,
resulting in a brick.
the top of the BIOS region is at the end of the 4MB chip, and that's
where things start from; the part at the end of the 8MB chip doesn't
matter uless your CBFS is > 4MB
- where is the firmware of the EC controller actually
located? It's not mentioned in the ROM layout map.
on your device, it's on a separate chip, not the main SPI flash
- to my understanding, applying me_cleaner would mean
I need to flash the 8MB chip as well. Can this be done internally once I have coreboot
running or will the ifd lock in the descriptor (that was left untouched) block this
access, so in the end I will need to disassemble the T440p to get physical access to the
not 'as well,' you would need to flash the 8MB chip only, since that
is where the IFD and ME regions are. By default, the IFD locks the
IFD/ME regions from being written to internally, so you must flash the
IFD (at a minimum) externally first to allow for internal flashing of
the IFD/ME regions.
- to take advantage of the space gained by applying
me_cleaner, the descriptor would need to be reflashed as well, right? Can this be done
internally as well?
yes. not initially -- see above.
- I tried to compile GRUB as payload first, but it
didn't fit in the space so I had to go for SeaBIOS. Is there a way to get GRUB working
without touching the 8MB chip? I wonder why it doesn't fit into the 4 MB space of the
smaller ... is the size of the CBFS region set correctly to the available maximum by
the CBFS default is usually much smaller than the BIOS region, I'm
guessing 1-2MB. You can set it to 4MB and then use most other
payloads, and only flash the 4MB chip.
Again, thanks a lot! I will try to submit a merge request for the doc article about the
T440p once I get a better understanding of this.
> On Tue, 13 Oct 2020 22:18:23 +0200
> Nico Huber <nico.h(a)gmx.de> wrote:
> > Hi Daniel,
> > On 13.10.20 21:59, Daniel Kulesz via coreboot wrote:
> > > The build fails because I don't have the other proprietary parts
(descriptor.bin, me.bin, gbe.bin).
> > you can simply omit them. If you don't tell that you have them (in your
> > config), coreboot won't miss them.
> > > Or is this process meant the way that I should build coreboot without these
parts and only flash the BIOS region, not touching them?
> > That's it. Generally, for any retrofit coreboot, they are already on
> > the machine, so you never have to extract them. In case of the T440p,
> > the BIOS region spans the end of the 8MiB and the whole 4MiB chip.
> > Hence, you never need to deal with descriptor/gbe/me if you only flash
> > the latter.
> > Remember to build coreboot for 12MiB and take the last 4MiB of the
> > resulting `coreboot.rom` and always keep a backup ;)
> > Nico
> >  https://doc.coreboot.org/_images/flashlayout_Ivy_Bridge.svg
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