I have trouble making dual fallback/normal image.
I have booting setup with:
coreboot.rom: 512 kB, bootblocksize 930, romsize 524288, offset 0x0 Alignment: 64 bytes
Name Offset Type Size fallback/romstage 0x0 stage 44154 fallback/coreboot_ram 0xacc0 stage 163868 fallback/payload 0x32d40 payload 33141 (empty) 0x3af00 null 281878
Then I set prefix=normal and set "update existing image" with menuconfig, after make I have this:
coreboot.rom: 512 kB, bootblocksize 930, romsize 524288, offset 0x0 Alignment: 64 bytes
Name Offset Type Size normal/romstage 0x0 stage 44314 normal/coreboot_ram 0xad80 stage 163868 normal/payload 0x32e00 payload 33141 (empty) 0x3afc0 null 281686
So.. it wrote over my fallback. Probably not the intention?
I also tried manually to append that normal/romstage with CONFIG_XIP_ROM_SIZE aligment, but had no success with:
cbfstool coreboot.rom add-stage romstage.elf normal/romstage 0x40000
coreboot.rom: 512 kB, bootblocksize 930, romsize 524288, offset 0x0 Alignment: 64 bytes
Name Offset Type Size fallback/romstage 0x0 stage 44154 fallback/coreboot_ram 0xacc0 stage 163868 fallback/payload 0x32d40 payload 33141 normal/romstage 0x3af00 stage 48478 (empty) 0x46cc0 null 233302
Any thoughts? My util/cbfstool/ matches current git origin/master.
KM
Am Fr 28 Okt 2011 07:18:36 CEST schrieb Kyösti Mälkki:
I have trouble making dual fallback/normal image. [detailed report] Any thoughts?
The change in http://review.coreboot.org/351 should fix it Thank you for the report.
Patrick
On Fri, 2011-10-28 at 22:56 +0200, Patrick Georgi wrote:
Am Fr 28 Okt 2011 07:18:36 CEST schrieb Kyösti Mälkki:
I have trouble making dual fallback/normal image. [detailed report] Any thoughts?
The change in http://review.coreboot.org/351 should fix it Thank you for the report.
Thanks!
Now I have some sort of controlled tiny fallback/normal boot, and I went for the Cache-As-Ram with my AOpen and have new trouble:
When updating existing flash image, if my new normal/romstage is built with ROMCC it is aligned to CONFIG_XIP_ROM_SIZE boundary (excluding some CBFS header) and I can boot with it.
If my new normal/romstage is built with GCC for Cache-As-Ram, the same alignment does not apply and on boot it halts before any serial output. Everything I have should be the latest git, including the MTRR $copy_and_run patch.
CONFIG_XIP_ROM_BASE seems obsolete? Could you take CONFIG_XIP_ROM_SIZE from romstage CBFS-header and round that up? This is now 64kB while my romstage takes <16kB. So this wastes precious space on flash device.
KM
Am Montag, 31. Oktober 2011 07:32:50 schrieb Kyösti Mälkki:
If my new normal/romstage is built with GCC for Cache-As-Ram, the same alignment does not apply and on boot it halts before any serial output.
Does it "halt" or is it just _very_ slow (several minutes until the first life sign on serial)? The latter would indicate wrong MTRR setup, while the former is a more fundamental problem.
CONFIG_XIP_ROM_BASE seems obsolete?
It should. I'll take a look.
Could you take CONFIG_XIP_ROM_SIZE from romstage CBFS-header and round that up? This is now 64kB while my romstage takes<16kB. So this wastes precious space on flash device.
Good suggestion - a "range" operator for looking for the location which aligns the block with the neighbor. Just rounding up isn't enough in all cases.
Patrick
On Mon, 2011-10-31 at 15:20 +0100, Patrick Georgi wrote:
Am Montag, 31. Oktober 2011 07:32:50 schrieb Kyösti Mälkki:
If my new normal/romstage is built with GCC for Cache-As-Ram, the same alignment does not apply and on boot it halts before any serial output.
Does it "halt" or is it just _very_ slow (several minutes until the first life sign on serial)? The latter would indicate wrong MTRR setup, while the former is a more fundamental problem.
It isn't only slow. I did experience the slow version with bad MTRR setup when I did the big->tiny bootblock switch and MTRR setup missed one ~.
My Cache-As-Ram boot enters intel/car/cache_as_ram.inc but never reaches LogicalAP_SIPINotdone in it. I found a note in this file saying LAPIC ID logic works only for processors with two threads, so does a dual Xeon P4/HT setup require re-writing this logic? The car.inc was earlier used for Tyan s2735 that is also dual-Xeon board with same socket.
I happen to have normal/romstage that does not cross CONFIG_XIP_ROM_SIZE boundary. I think it is a bug in cbfstool that normal/romstage placement is unaligned, since early_mtrr_init does not cover cases where normal/romstage crosses said boundary. One would witness the very slow boot effect then, too.
Updated image with normal/romstage compiled with ROMCC:
coreboot.rom: 512 kB, bootblocksize 978, romsize 524288, offset 0x0 Alignment: 64 bytes
Name Offset Type Size fallback/romstage 0x0 stage 43801 fallback/coreboot_ram 0xab80 stage 163868 fallback/payload 0x32c00 payload 33141 (empty) 0x3adc0 null 20888 normal/romstage 0x3ff80 stage 43789 normal/coreboot_ram 0x4ab00 stage 163868 normal/payload 0x72b80 payload 33141 (empty) 0x7ad40 null 20134
Updated image with normal/romstage compiled with GCC:
coreboot.rom: 512 kB, bootblocksize 978, romsize 524288, offset 0x0 Alignment: 64 bytes
Name Offset Type Size fallback/romstage 0x0 stage 43801 fallback/coreboot_ram 0xab80 stage 163868 fallback/payload 0x32c00 payload 33141 normal/romstage 0x3adc0 stage 15121 normal/coreboot_ram 0x3e900 stage 163868 normal/payload 0x66980 payload 33141 (empty) 0x6eb40 null 69798
KM
Am 01.11.2011 14:02, schrieb Kyösti Mälkki:
My Cache-As-Ram boot enters intel/car/cache_as_ram.inc but never reaches LogicalAP_SIPINotdone in it. I found a note in this file saying LAPIC ID logic works only for processors with two threads, so does a dual Xeon P4/HT setup require re-writing this logic?
Possibly. Comparing the code to the datasheets will give you a definitive answer.
I happen to have normal/romstage that does not cross CONFIG_XIP_ROM_SIZE boundary. I think it is a bug in cbfstool that normal/romstage placement is unaligned,
It is aligned...
since early_mtrr_init does not cover cases where normal/romstage crosses said boundary.
... which is why this works.
Patrick
-
Kyösti Mälkki -
Patrick Georgi