New patch to review for coreboot: c3f4e05 Google/snow: romstage that turns on memory and loads a ram stage with cbfs

[Ronald G. Minnich]

Ronald G. Minnich ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2245

-gerrit

commit c3f4e05181484c3ce66ac857c13c13ca2c1ee1bb
Author: Ronald G. Minnich 
Date:   Wed Jan 30 15:55:36 2013 -0800

Google/snow: romstage that turns on memory and loads a ram stage with cbfs

This is a first cut at a romstage. It sets up memory, although that
    needs some work; and finds and loads a ram stage, though that fails
    in the decompress step.

But it's quite a bit more than we had.

Change-Id: I02a0eb48828500bf83c3c57d4bacb396e58bf9a5
    Signed-off-by: Ronald G. Minnich 
---
 src/mainboard/google/snow/romstage.c | 98 ++++++++++++++++++++++++++++++------
 1 file changed, 83 insertions(+), 15 deletions(-)

diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index 3f3f3ec..0026eb9 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -20,26 +20,19 @@
 #include <types.h>
 #include <system.h>
 #include <cache.h>
+#include <cbfs.h>

-#if 0
-#include <arch/io.h>
-
-/* FIXME: make i2c.h use standard types */
-#define uchar unsigned char
-#define uint  unsigned int
-#include <device/i2c.h>
-
-#include <cpu/samsung/s5p-common/s3c24x0_i2c.h>
-#include "cpu/samsung/exynos5250/dmc.h"
-#include <cpu/samsung/exynos5250/power.h>
+#include <cpu/samsung/exynos5250/setup.h>
+#include <cpu/samsung/exynos5250/dmc.h>
 #include <cpu/samsung/exynos5250/clock_init.h>
-#include <cpu/samsung/exynos5-common/uart.h>
-#endif
+
 #include <console/console.h>

void main(void);
+
 void main(void)
 {
+	struct cbfs_media cbfs;
 //	volatile unsigned long *pshold = (unsigned long *)0x1004330c;
 //	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 //	power_init();
@@ -47,7 +40,82 @@ void main(void)
 //	exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
    console_init();
    printk(BIOS_INFO, "hello from romstage\n");
-
+       /* u-boot tends to parameterize lots of things, and you end up
+        * calling things that decode things. In the case of this
+        * part, on this board, we only care about DDR3.  Since we
+        * know what kind of memory we have, and that kind of stuff is
+        * just another path for obscure errors, just call the ddr3
+        * init. Rule: Keep it simple.
+        */
+       extern struct mem_timings mem_timings[];
+       struct mem_timings *mem = mem_timings;
+       int ret;
+       
+       //      mem = clock_get_mem_timings();
+       printk(BIOS_SPEW, "clock_get_mem_timings returns %08lx\n",
+              (unsigned long)mem);
+       printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n",
+              mem->mem_manuf, 
+              mem->mem_type,
+              mem->mpll_mdiv,
+              mem->frequency_mhz);
+       /* the 0x1f is the interleaving size. It's kind of hard to see
+        * where and how this might vary. It might want to be a config
+        * variable, but making it a config variable might actually be
+        * dangerous.
+        */
+       ret = ddr3_mem_ctrl_init(mem, 0x1f);
+       if (ret) {
+               printk(BIOS_ERR, "Memory controller init failed, err: %x\n", 
+                      ret);
+               while(1);
+       }
+       
+       printk(BIOS_INFO, "ddr3_init done\n");
+       /* wow, did it work? */
+       int i;
+       u32 *c = (void *)0x40000000;
+       
 //	*pshold &= ~0x100;	/* shut down */
-	mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024);
+//	mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024);
+//       printk(BIOS_INFO, "mmu_setup done\n");
+	for(i = 0; i < 16384; i++)
+		c[i] = i+32768;
+	for(i = 0; i < 16384; i++)
+		if (c[i] != i+32768)
+			printk(BIOS_SPEW, "BADc[%02x]: %02x,", i, c[i]);
+	for(i = 0; i < 1048576; i++)
+		c[i] = 0;
+	ret = init_default_cbfs_media(&cbfs);
+	if (ret){
+		printk(BIOS_ERR, "init_default_cbfs_media returned %d: HALT\n",
+		       ret);
+		while (1);
+	}
+//     void *start;
+	
+	struct cbfs_stage *stage = (struct cbfs_stage *)
+		cbfs_get_file_content(&cbfs, "fallback/coreboot_ram",
+				      CBFS_TYPE_STAGE);
+	printk(BIOS_ERR, "Stage: %p\n", stage);
+	printk(BIOS_ERR, "loading stage %s @ 0x%x (0x%x bytes),entry @ 0x%p\n",
+	       "ram stage",
+	       (uint32_t) stage->load, stage->memlen,
+	       (void *)(u32)stage->entry);
+	/* for reference and testing ... we should be able to remove soon */
+#if 0
+//	c = (void *)(u32)(stage->load + stage->len);
+	c = (void *)(u32)(stage->load);
+	printk(BIOS_ERR, "memzero 0x%x words starting at %p\n", 
+	       (stage->memlen /*- stage->len*/)/4, c);
+	for(i = 0; i < (stage->memlen /*- stage->len*/)/4; i++){
+		printk(BIOS_INFO, "%p, ", &c[i]);
+		c[i] = 0;
+	}
+#endif
+	void *entry = cbfs_load_stage(&cbfs, "fallback/coreboot_ram");
+	printk(BIOS_INFO, "entry is %p\n", entry);
+	
+	printk(BIOS_ERR, "DONE\nHALT\n");
+	while (1);
 }

New patch to review for coreboot: c3f4e05 Google/snow: romstage that turns on memory and loads a ram stage with cbfs

[Bernhard Urban]

I can't log into gerrit at the moment, so I reply here.

On Thu, Jan 31, 2013 at 1:08 AM, Ronald G. Minnich  wrote:
>   /* wow, did it work? */
>   int i;
>   u32 *c = (void *)0x40000000;

what is at 0x40000000? what is "c"?
Please use a define or a more descriptive name for the pointer.

Thanks,
Bernhard