Siyuan Wang (wangsiyuanbuaa@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1593
-gerrit
commit 1bac59ddc96ed91845725c4d181b4a9e838c35f8 Author: Siyuan Wang wangsiyuanbuaa@gmail.com Date: Tue Oct 23 14:13:38 2012 +0800
pcie init: move to romstage
We move 2 cimx wrappers to romstage: Pcie_Early_Init, Pcie_Late_Init The reasons we do these changes are: 1) The pcie bridge with devices shoud be on and without devices should be off before device enumerate. 2) Now, the code do pcie training in device enable. So the pcie bridge is scanned whether there is a device or not. This could lead to some errors. For example: coreboot scans device tree twice and gets two different VGA devices, so the VGA bios could not be loaded correctly.
Change-Id: I4bb6b54823cd08eae94b224130b46cc20b3ec43f Signed-off-by: Siyuan Wang SiYuan.Wang@amd.com Signed-off-by: Siyuan Wang wangsiyuanbuaa@gmail.com --- src/northbridge/amd/cimx/rd890/Makefile.inc | 2 + src/northbridge/amd/cimx/rd890/early.c | 10 ++ src/northbridge/amd/cimx/rd890/late.c | 159 +++++----------------------- src/northbridge/amd/cimx/rd890/nb_cimx.c | 105 ++++++++++++++++++ src/northbridge/amd/cimx/rd890/nb_cimx.h | 13 ++- 5 files changed, 149 insertions(+), 140 deletions(-)
diff --git a/src/northbridge/amd/cimx/rd890/Makefile.inc b/src/northbridge/amd/cimx/rd890/Makefile.inc index 5eaefd1..546221d 100644 --- a/src/northbridge/amd/cimx/rd890/Makefile.inc +++ b/src/northbridge/amd/cimx/rd890/Makefile.inc @@ -20,6 +20,8 @@
# RD890 Platform Files romstage-y += early.c +romstage-y += nb_cimx.c
ramstage-y += late.c +ramstage-y += nb_cimx.c
diff --git a/src/northbridge/amd/cimx/rd890/early.c b/src/northbridge/amd/cimx/rd890/early.c index 8008223..1b325d3 100644 --- a/src/northbridge/amd/cimx/rd890/early.c +++ b/src/northbridge/amd/cimx/rd890/early.c @@ -111,3 +111,13 @@ void nb_S3_Init(void) { //TODO } + +void nb_Pcie_Early_Init(AMD_NB_CONFIG_BLOCK *pConfig) +{ + LibSystemApiCall(AmdPcieEarlyInit, pConfig); +} + +void nb_Pcie_Late_Init(AMD_NB_CONFIG_BLOCK *pConfig) +{ + LibSystemApiCall(AmdPcieLateInit, pConfig); +} diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c index 33da2b4..801f3cd 100644 --- a/src/northbridge/amd/cimx/rd890/late.c +++ b/src/northbridge/amd/cimx/rd890/late.c @@ -27,150 +27,41 @@ #include "nb_cimx.h" #include "rd890_cfg.h"
- -/** - * Global RD890 CIMX Configuration structure - */ -static NB_CONFIG nb_cfg[MAX_NB_COUNT]; -static HT_CONFIG ht_cfg[MAX_NB_COUNT]; -static PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; -static AMD_NB_CONFIG_BLOCK gConfig; - - -/** - * Reset PCIE Cores, Training the Ports selected by port_enable of devicetree - * After this call EP are fully operational on particular NB - */ -void nb_Pcie_Early_Init(void) -{ - LibSystemApiCall(AmdPcieEarlyInit, &gConfig); //AmdPcieEarlyInit(&gConfig); -} - -void nb_Pcie_Late_Init(void) +void nb_Early_Post_Init(AMD_NB_CONFIG_BLOCK *pConfig) { - LibSystemApiCall(AmdPcieLateInit, &gConfig); + LibSystemApiCall(AmdEarlyPostInit, pConfig); }
-void nb_Early_Post_Init(void) +void nb_Mid_Post_Init(AMD_NB_CONFIG_BLOCK *pConfig) { - LibSystemApiCall(AmdEarlyPostInit, &gConfig); + LibSystemApiCall(AmdMidPostInit, pConfig); }
-void nb_Mid_Post_Init(void) +void nb_Late_Post_Init(AMD_NB_CONFIG_BLOCK *pConfig) { - LibSystemApiCall(AmdMidPostInit, &gConfig); -} - -void nb_Late_Post_Init(void) -{ - LibSystemApiCall(AmdLatePostInit, &gConfig); + LibSystemApiCall(AmdLatePostInit, pConfig); }
static void rd890_enable(device_t dev) { - u32 address = 0; - u32 mask; - u32 val; - u32 devfn; - u32 port; - AMD_NB_CONFIG *NbConfigPtr = NULL; - - u8 nb_index = 0; /* The first IO Hub, TODO: other NBs */ - address = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0); - NbConfigPtr = &(gConfig.Northbridges[nb_index]); - - devfn = dev->path.pci.devfn; - port = devfn >> 3; - printk(BIOS_INFO, "rd890_enable "); - printk(BIOS_INFO, "Bus-%x Dev-%X Fun-%X, enable=%x\n", - 0, (devfn >> 3), (devfn & 0x07), dev->enabled); - if (port != 0) { - if (dev->enabled) { - NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = OFF; - } else { - NbConfigPtr->pPcieConfig->PortConfiguration[port].ForcePortDisable = ON; - } - } - - switch (port) { - case 0x0: /* Root Complex, and ClkConfig */ - - if ((devfn & 0x07) == 1) { /* skip dev-0 fun-1 */ - break; - } - - /* CIMX configuration defualt initialize */ - rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); - if (gConfig.StandardHeader.CalloutPtr != NULL) { - /* NOTE: not use LibNbCallBack */ - gConfig.StandardHeader.CalloutPtr(CB_AmdSetPcieEarlyConfig, (u32)dev, (VOID*)NbConfigPtr); - } - /* Reset PCIE Cores, Training the Ports selected by port_enable of devicetree - * After this call EP are fully operational on particular NB - */ - nb_Pcie_Early_Init(); - break; - - case 0x2: /* Gpp1 Port0 */ - case 0x3: /* Gpp1 Port1 */ - mask = ~(1 << port); - val = (dev->enabled ? 0 : 1) << port; - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - break; - - case 0x4: /* Gpp3a Port0 */ - case 0x5: /* Gpp3a Port1 */ - case 0x6: /* Gpp3a Port2 */ - case 0x7: /* Gpp3a Port3 */ - mask = ~(1 << port); - val = (dev->enabled ? 0 : 1) << port; - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - break; - - case 0x8: /* SB ALink */ - mask = ~(1 << 6); - val = (dev->enabled ? 1 : 0) << 6; - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - break; - - case 0x9: /* Gpp3a Port4 */ - case 0xa: /* Gpp3a Port5 */ - mask = ~(1 << (7 + port)); - val = (dev->enabled ? 0 : 1) << (7 + port); - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - break; - - case 0xb: /* Gpp2 Port0 */ - case 0xc: /* Gpp2 Port1 */ - mask = ~(1 << (7 + port)); - val = (dev->enabled ? 0 : 1) << (7 + port); - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - break; - - case 0xd: /* Gpp3b */ - mask = ~(1 << (7 + port)); - val = (dev->enabled ? 0 : 1) << (7 + port); - LibNbPciIndexRMW(address | NB_MISC_INDEX, NB_MISC_REG0C, AccessS3SaveWidth32, mask, val, NbConfigPtr); - - /* Init NB at Early Post */ - if (gConfig.StandardHeader.CalloutPtr != NULL) { - gConfig.StandardHeader.CalloutPtr(CB_AmdSetEarlyPostConfig, 0, (VOID*)NbConfigPtr); - } - nb_Early_Post_Init();// - if (gConfig.StandardHeader.CalloutPtr != NULL) { - gConfig.StandardHeader.CalloutPtr(CB_AmdSetMidPostConfig, 0, (VOID*)NbConfigPtr); - } - nb_Mid_Post_Init(); - nb_Pcie_Late_Init(); - if (gConfig.StandardHeader.CalloutPtr != NULL) { - gConfig.StandardHeader.CalloutPtr(CB_AmdSetLatePostConfig, 0, (VOID*)NbConfigPtr); - } - nb_Late_Post_Init(); - break; - - default: - printk(BIOS_INFO, "Buggy Device Tree\n"); - break; + NB_CONFIG nb_cfg[MAX_NB_COUNT]; + HT_CONFIG ht_cfg[MAX_NB_COUNT]; + PCIE_CONFIG pcie_cfg[MAX_NB_COUNT]; + AMD_NB_CONFIG_BLOCK gConfig; + u32 devfn = dev->path.pci.devfn; + + /* only do Post init once */ + if(devfn == 0) + { + printk(BIOS_INFO, "cimx Post init start...\n"); + rd890_cimx_config(&gConfig, &nb_cfg[0], &ht_cfg[0], &pcie_cfg[0]); + nb_pcie_config(&gConfig); + + //nb_Pcie_Late_Init(&gConfig); + nb_Early_Post_Init(&gConfig); + nb_Mid_Post_Init(&gConfig); + nb_Late_Post_Init(&gConfig); + printk(BIOS_INFO, "cimx Post init exit...\n"); } }
@@ -179,7 +70,6 @@ struct chip_operations northbridge_amd_cimx_rd890_ops = { .enable_dev = rd890_enable, };
- static void ioapic_init(struct device *dev) { u32 ioapic_base; @@ -196,7 +86,6 @@ static void rd890_read_resource(struct device *dev) /* rpr6.2.(1). Write the Base Address Register (BAR) */ pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */ - compact_resources(dev); }
diff --git a/src/northbridge/amd/cimx/rd890/nb_cimx.c b/src/northbridge/amd/cimx/rd890/nb_cimx.c new file mode 100644 index 0000000..56bac9d --- /dev/null +++ b/src/northbridge/amd/cimx/rd890/nb_cimx.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "NbPlatform.h" +#include "rd890_cfg.h" +#include "northbridge/amd/cimx/rd890/chip.h" +#include "nbInitializer.h" +#include <string.h> +#include <arch/ioapic.h> +#include <device/device.h> + +extern ROMSTAGE_CONST struct device dev_root; + +/** + * Platform dependent configuration at ramstage + */ +void nb_pcie_config(AMD_NB_CONFIG_BLOCK *pConfig) +{ + u16 i; + struct device *pdev; + AMD_NB_CONFIG *NbConfigPtr = &(pConfig->Northbridges[0]); + PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig; + struct northbridge_amd_cimx_rd890_config *rd890_info = NULL; + DEFAULT_PLATFORM_CONFIG(platform_config); + + /* find rd890 in device list */ + for (pdev = &dev_root; pdev; pdev=pdev->next) { + if ((pdev->path.type == DEVICE_PATH_PCI) && (pdev->path.pci.devfn == 0)) + break; + } + rd890_info = pdev->chip_info; + + /* update the platform depentent configuration by devicetree */ + platform_config.PortEnableMap = rd890_info->port_enable; + if (rd890_info->gpp1_configuration == 0) { + platform_config.Gpp1Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp1_configuration == 1) { + platform_config.Gpp1Config = GFX_CONFIG_AABB; + } + if (rd890_info->gpp2_configuration == 0) { + platform_config.Gpp2Config = GFX_CONFIG_AAAA; + } else if (rd890_info->gpp2_configuration == 1) { + platform_config.Gpp2Config = GFX_CONFIG_AABB; + } + platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration; + + if (platform_config.Gpp1Config != 0) { + pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config; + } + if (platform_config.Gpp2Config != 0) { + pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config; + } + if (platform_config.Gpp3aConfig != 0) { + pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig; + } + + pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20); + for (i = 0; i <= MAX_CORE_ID; i++) { + NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF; + NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF; + } + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2; + } + + for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) { + if ((platform_config.PortEnableMap & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortPresent = ON; + if ((platform_config.PortGen1Map & (1 << i)) != 0) { + pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1; + } + if ((platform_config.PortHotplugMap & (1 << i)) != 0) { + u16 j; + pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */ + /* Set Hotplug descriptor info */ + for (j = 0; j < 8; j++) { + u32 PortDescriptor; + PortDescriptor = platform_config.PortHotplugDescriptors[j]; + if ((PortDescriptor & 0xF) == j) { + pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap = (PortDescriptor >> 4) & 3; + pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6) & 1; + break; + } + } + } + } + } +} + diff --git a/src/northbridge/amd/cimx/rd890/nb_cimx.h b/src/northbridge/amd/cimx/rd890/nb_cimx.h index a6f77db..86e67b5 100644 --- a/src/northbridge/amd/cimx/rd890/nb_cimx.h +++ b/src/northbridge/amd/cimx/rd890/nb_cimx.h @@ -20,6 +20,8 @@ #ifndef _NB_CIMX_H_ #define _NB_CIMX_H_
+#include "NbPlatform.h" + /** * @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b * @@ -34,11 +36,12 @@ void sr56x0_rd890_disable_pcie_bridge(void); void nb_Poweron_Init(void); void nb_Ht_Init(void); void nb_S3_Init(void); -void nb_Early_Post_Init(void); -void nb_Mid_Post_Init(void); -void nb_Late_Post_Init(void); -void nb_Pcie_Early_Init(void); -void nb_Pcie_Late_Init(void); +void nb_Pcie_Early_Init(AMD_NB_CONFIG_BLOCK *pConfig); +void nb_Pcie_Late_Init(AMD_NB_CONFIG_BLOCK *pConfig); +void nb_Early_Post_Init(AMD_NB_CONFIG_BLOCK *pConfig); +void nb_Mid_Post_Init(AMD_NB_CONFIG_BLOCK *pConfig); +void nb_Late_Post_Init(AMD_NB_CONFIG_BLOCK *pConfig); +void nb_platform_config(AMD_NB_CONFIG_BLOCK *pConfig);
#endif//_RD890_EARLY_H_
-
Siyuan Wang