There is motherboard based on the Intel Rangeley Atom C2000 (C2758) series processor. How to enable the SMBus0 in coreboot? If I use OEM BIOS or BIOS from Intel (EDVLCRB1.86B.0048.R00.1508181657_MPK) for mohon peak crb, then I see on the SMBus0 (i2c-1 in Fedora 28) memory DIMM spd (0x50 & 0x52), clock generator (0x69) and other devices. If I use a coreboot based bios for the Mohon peak platform - I do not see any devices on i2c-1. I see an data exchange on the SMBus0 with oscilloscope at boot time only. When I send "i2cdetect -y 1" command in Linux no activity on SMBus0 and no device found.
Hi,
Could you check if you could read the BIOS image from FIT (Flash Image Tool) and see Smbus is disabled in the descriptor(in the SoC Straps), which is outside of coreboot BIOS image. enable Smbus in the descriptor if it is disabled, FSP will populate the DIMM in MRC code atleast for BayTrail similar behaviour is observed, not sure on Rangeley Atom
Thanks Ranga
-----Original Message----- From: dponamorev@gmail.com dponamorev@gmail.com Sent: Wednesday 29 May 2019 15:48 To: coreboot@coreboot.org Subject: [coreboot] How to enable the SMBus0 in coreboot for Intel Atom C2000?
There is motherboard based on the Intel Rangeley Atom C2000 (C2758) series processor. How to enable the SMBus0 in coreboot? If I use OEM BIOS or BIOS from Intel (EDVLCRB1.86B.0048.R00.1508181657_MPK) for mohon peak crb, then I see on the SMBus0 (i2c-1 in Fedora 28) memory DIMM spd (0x50 & 0x52), clock generator (0x69) and other devices. If I use a coreboot based bios for the Mohon peak platform - I do not see any devices on i2c-1. I see an data exchange on the SMBus0 with oscilloscope at boot time only. When I send "i2cdetect -y 1" command in Linux no activity on SMBus0 and no device found. _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
On Wed, May 29, 2019 at 5:48 PM dponamorev@gmail.com wrote:
There is motherboard based on the Intel Rangeley Atom C2000 (C2758) series processor. How to enable the SMBus0 in coreboot? If I use OEM BIOS or BIOS from Intel (EDVLCRB1.86B.0048.R00.1508181657_MPK) for mohon peak crb, then I see on the SMBus0 (i2c-1 in Fedora 28) memory DIMM spd (0x50 & 0x52), clock generator (0x69) and other devices. If I use a coreboot based bios for the Mohon peak platform - I do not see any devices on i2c-1. I see an data exchange on the SMBus0 with oscilloscope at boot time only. When I send "i2cdetect -y 1" command in Linux no activity on SMBus0 and no device found.
Your chances of getting support are much better when you provide more context and logfiles. We would probably need relevant lines from system logs (dmesg) and outputs from 'i2cdetect' and 'lspci -xx' here, both OEM BIOS and coreboot. For coreboot, also 'cbmem -1'. Would not hurt if you pushed your mainboard port as a draft to gerrit or make your work otherwise accesible.
What we have in rangeley_smbus_read_resources() does not look that good, it may leave SMBUS IO BAR unset in the hardware. Might be simply case of calling enable_smbus() in romstage for the board to get that fixed.
Regards, Kyösti Mälkki
Unfortunately, FITs does not have any settings for SMBus enable/disable and so on. In general, this program for Edisonville_Rangeley is very poor settings.
Thanks for youre advice Kyösti! I add files with logs. I tried to play with the enable_smbus() function but without result. Rather, the result is the same - no devices on i2c-1. You can see the comparison of devices on (SMBus0) i2c-1 bus with the OEM Bios and with Coreboot bios in i2cdetect.log. Could nuvoton superio somehow affect the SMBus?
I also noticed errors in dmesg output such: [ 93.737732] i801_smbus 0000:00:1f.3: Timeout waiting for interrupt! [ 93.744750] i801_smbus 0000:00:1f.3: Transaction timeout
Best Regards, Dmitry Ponamorev
пт, 31 мая 2019 г. в 07:50, Kyösti Mälkki kyosti.malkki@gmail.com:
On Wed, May 29, 2019 at 5:48 PM dponamorev@gmail.com wrote:
There is motherboard based on the Intel Rangeley Atom C2000 (C2758)
series processor. How to enable the SMBus0 in coreboot? If I use OEM BIOS or BIOS from Intel (EDVLCRB1.86B.0048.R00.1508181657_MPK) for mohon peak crb, then I see on the SMBus0 (i2c-1 in Fedora 28) memory DIMM spd (0x50 & 0x52), clock generator (0x69) and other devices. If I use a coreboot based bios for the Mohon peak platform - I do not see any devices on i2c-1. I see an data exchange on the SMBus0 with oscilloscope at boot time only. When I send "i2cdetect -y 1" command in Linux no activity on SMBus0 and no device found.
Your chances of getting support are much better when you provide more context and logfiles. We would probably need relevant lines from system logs (dmesg) and outputs from 'i2cdetect' and 'lspci -xx' here, both OEM BIOS and coreboot. For coreboot, also 'cbmem -1'. Would not hurt if you pushed your mainboard port as a draft to gerrit or make your work otherwise accesible.
What we have in rangeley_smbus_read_resources() does not look that good, it may leave SMBUS IO BAR unset in the hardware. Might be simply case of calling enable_smbus() in romstage for the board to get that fixed.
Regards, Kyösti Mälkki
On Fri, May 31, 2019 at 5:24 PM Дмитрий Понаморев dponamorev@gmail.com wrote:
Unfortunately, FITs does not have any settings for SMBus enable/disable and so on. In general, this program for Edisonville_Rangeley is very poor settings.
Thanks for youre advice Kyösti! I add files with logs. I tried to play with the enable_smbus() function but without result. Rather, the result is the same - no devices on i2c-1. You can see the comparison of devices on (SMBus0) i2c-1 bus with the OEM Bios and with Coreboot bios in i2cdetect.log. Could nuvoton superio somehow affect the SMBus?
I also noticed errors in dmesg output such: [ 93.737732] i801_smbus 0000:00:1f.3: Timeout waiting for interrupt! [ 93.744750] i801_smbus 0000:00:1f.3: Transaction timeout
That is a fairly strong suggestion that PCI 0:1f.3 does not have correct interrupt routing, but I did not check the logs yet.
You might be able to use polling instead and add more verbose debug logging for driver i2c-i801, just to get further now with the SMBus part.
Kyösti
Yes, most likely you are right! I could not completely fix the problem but was able to get around it. The problem arose when connecting an external video card to an PCI-E slot through riser. Without connecting the video card the SMBus0 (i2c-1 bus) works fine. I was able to experiments with IDT clock synthesizer (9VRS4420DKLFT). I turned on the 48 MHz clock for Nuvoton and finally saw it in Linux. Thanks for the help! While I am serving problems with interruptions and I’ll do the nuvoton configuration in coreboot.
Best Regards, Dmitry Ponamorev
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dponamorev＠gmail.com -
Kyösti Mälkki -
Ranga Rao -
Дмитрий Понаморев