The source code for SuperIOTool says of the Standard Microsystems (SMSC/SMC) LPC47B387:
'We cannot find a public datasheet for this Super I/O.' This still seems to be
the case. However, I found a Hewlett-Packard manual called 'Technical Reference
Guide: HP Compaq d330 and d530 Series Personal Computers' (file name
'340154_rev001_us.pdf', Document Part Number 340154-001). It gives some
information on that I/O Controller, that maybe is enough to have SuperIOTool (and maybe,
CoreBoot) support it.
Here is page 4-30, with minor additions:
The LPC47B387 I/O controller contains various functions such as the keyboard/mouse
interfaces, diskette interface, serial interfaces, and parallel interface. While the
control of these interfaces uses standard AT-type I/O addressing (as described in Chapter
5), the configuration of these functions uses indexed ports unique to the LPC47B387. In
these [Hewlett-Packard] systems, hardware strapping selects I/O addresses 02Eh and 02Fh at
reset as the Index/Data ports for accessing the logical devices within the LPC47B387.
Table 4-16 lists the PnP standard control registers for the LPC47B387.
LPC47B387 I/O Controller Control Registers
Index Function Reset Value
02h Configuration Control 00h
07h Logical Device (Interface) Select: 00h
00h = Diskette Drive I/F
01h = Reserved
02h = Reserved
03h = Parallel I/F
04h = Serial I/F (UART 1/Port A)
05h = Serial I/F (UART 2/Port B)
06h = Reserved
07h = Keyboard I/F
08h = Reserved
09h = Reserved
0Ah = Run-time Registers (GPIO Config.)
0Bh = SMBus Configuration
20h Super I/O ID Register (SID) 56h
21h Revision --
22h Logical Device Power Control 00h
23h Logical Device Power Management 00h
24h PLL/Oscillator Control 04h
26h Configuration Address (Low Byte)
27h Configuration Address (High Byte)
For a detailed description of registers refer to appropriate SMC documentation. [But there
isn't any. The manual has things inherited from its predecessor manual.]
The configuration registers are accessed through I/O registers 2Eh (index) and 2Fh (data),
after the configuration phase has been activated by writing 55h to I/O port 2Eh. The
desired interface (logical device) is initiated by firmware selecting logical device
number of the 47B347 using the following sequence:
1. Write 07h to I/O register 2Eh.
2. Write value of logical device to I/O register 2Fh.
3. Write 30h to I/O register 2Eh.
4. Write 01h to I/O register 2Fh (this activates the interface).
Writing AAh to 2Eh deactivates the configuration phase.
The next page doesn't relate to SuperIOTool, but may be useful in making CoreBoot
support the two motherboards used in the machines given in the title of the manual. All
but one of the machines use an ASUS P4SD motherboard (which is similar to their P4SD-LA).
ASUS don't give information on it. Hewlett-Packard just refer to it as Part Number
323091-001 and don't let on that it's made by ASUS.
The [Hewlett-Packard] systems covered in this guide utilize the following specialized
functions built into the LPC47B387 I/O Controller:
Power/Hard drive LED control The I/O controller provides color and blink control for
the front panel LEDs used for indicating system events (refer to Table 4-14).
Intruder sensing Supported on SFF, DT, MT, and CMT [Small Form Factor, Desktop,
Microtower, and Configurable Minitower] form factors, battery-backed D-latch logic
internal to the LPC47B387 is connected to the hood sensor switch to record hood (cover)
Hood lock/unlock Supported on SFF, DT, MT, and CMT [as above] form factors, logic
internal to the LPC47B387 controls the lock bar mechanism.
I/O security The parallel, serial, and diskette interfaces may be disabled
individually by software and the LPC47B387s disabling register locked. If the disabling
register is locked, a system reset through a cold boot is required to gain access to the
disabling (Device Disable) register.
Processor present/speed detection One of the battery-backed general-purpose inputs
(GPI26) of the LPC47B387 detects if the processor has been removed. The occurrence of this
event is passed to the [Intel south bridge] ICH5 that will, during the next boot sequence,
initiate the speed selection routine for the processor.
Legacy/ACPI power button mode control The LPC47B387 receives the pulse signal from
the systems power button and produces the PS On signal according to the mode (legacy or
ACPI) selected. Refer to Chapter 7 for more information regarding power management.
I don't think there is anything else useful on this I/O Controller in the manual.
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