On Sun, Oct 4, 2020 at 7:37 AM Matej Voľanský email@example.com wrote:
Hello, I have P8H61-m LX2 in my desktop right now. I want to switch from Win10 to Arch Linux and thought about also switching to coreboot. Unfortunately, I can’t find this MBO in your board status. There’s P8H61-m LX, LX3 R2.0, PRO, but LX2 not even mentioned. I’m not sure if I’m contacting the right person, but I need help. I’ve never done coreboot before ( though I’m not a newbie in electronics so I’m confident ) and I don’t know if it’s worth trying corebooting this MBO if it’s not in your list. I do have needed tools for this.
The mailing list is a perfect place to ask for help. Welcome!
If you haven't installed Arch already, I suggest that you use GRUB as a bootloader, and set up both legacy BIOS boot and UEFI boot. This is so that you can boot using either SeaBIOS, GRUB or TianoCore as payloads.
The P8H61-M LX2 is similar to both the P8H61-M LX and the P8H61-M LX3 R2.0 (I ported this one). The SPI flash chip is socketed, so you can carefully remove it from its socket and plug it into an external programmer (ideally, one that is supported by flashrom). The first thing you can try to do is to make a backup of its contents. Make sure to verify the read contents (flashrom has the -v option to do so). This will allow you to go back to a known-working state later on.
Then, you would want to check out `util/autoport`. While it does not do everything, it at least provides a good starting point to add a new Sandy/Ivy Bridge mainboard. Check out its README.md as it contains useful information. Then, use it, and it will hopefully create the `src/mainboard/asus/p8h61-m_lx2` folder with some files.
The most significant thing that will be missing from autoport-generated files is the Super I/O configuration. The serial port is connected to the Super I/O, and it can be used to get log messages from coreboot, so it would be great to make it work. You can use `util/superiotool` to dump the Super I/O settings programmed by vendor firmware, and add them to the coreboot port. You can use the existing P8H61-M LX and P8H61-M LX3 R2.0 board ports as an example.
Once this is done, selecting the board vendor/model should result in a bootable coreboot image. However, a scary warning appears at the end of the build process that tells you not to flash the resulting image as-is. Although the region sizes may differ, this is what the firmware on Sandy/Ivy Bridge systems looks like: https://doc.coreboot.org/_images/flashlayout_Sandy_Bridge.svg
coreboot goes into the BIOS region. By default, the build system generates an image that only contains coreboot, so the other regions are empty. Flashing everything would erase the other regions, which renders the hardware unable to boot (same symptoms as trying to boot without a flash chip). So, the warning is just reminding you to make sure to only flash the BIOS region. With flashrom, you can use the command that appears here: https://doc.coreboot.org/flash_tutorial/index.html#using-an-ifd-to-determine...
If this works, or if you get stuck, please push your code to review.coreboot.org so that anyone can take a look. For board ports, we prefer to have a single commit adding the board in a working state. Changes in Gerrit are identified by its Change-Id line in the commit message, so you can amend your commits and push them again to upload a new revision of the same change. You can follow this guide to get started: https://doc.coreboot.org/tutorial/part2.html
Here's the changes that added the existing boards, as an example:
I didn't add documentation when I ported my board, but it is a good idea to do so. Alternatively, one could adapt the existing P8H61-M LX page so that it covers all three LX boards. Documentation can be added in a different commit, so it's not critical.
Sincerely Matej Volansky.
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Best regards, Angel