RCA RM4100 Build Tutorial

Hello,
I added a Build Tutorial to the wiki:
http://www.coreboot.org/RCA_RM4100_Build_Tutorial
and linked it to the Supported Motherboards page.
I am going to send some users from my website to try it out. Some of  
the info may be redundent but it is meant for a coreboot newby?
Does it look like newby material?

Thanks - Joe

[Uwe Hermann]

Hi,

On Mon, Mar 10, 2008 at 07:41:28PM -0400, [e-mail] wrote:
> I added a Build Tutorial to the wiki:
> http://www.coreboot.org/RCA_RM4100_Build_Tutorial
> and linked it to the Supported Motherboards page.

Great, thanks!

I've done some cleanups on the page (small cosmetic fixes mostly). Some
more comments on the contents:

- It would be nice if you could add one or two photos from the board.

- Also, please add a license tag to all your wiki pages and wiki
   images. You can use {{PD-self}} or {{CC-by-sa-3.0}} etc. See for
   example http://www.coreboot.org/ASUS_A8V-E_Deluxe_Build_Tutorial.

- Are you sure the L2 cache is enabled? Check 'dmesg', IIRC this is not
   done for most Intel chipsets yet (?) Also, you can run x86info
   or cpuinfo for more info, I think.

- How did you test the CDROM drive? Mounting something in Linux or
   booting from CDROM? If the latter, how (which FILO options etc)?

- Does the modem really work and how was that tested? Does it need
   special support in coreboot?

- Is there really an onboard-CF slot on the board? Or did you test
   using an Cf-to-IDE adapter? Or both?

- How was IR tested? Which Linux tools? Any coreboot/superio changes
   required?

- You marked 'PC Speaker' as N/A. Why? Try 'modprobe pcspkr' and then
   do some beeping, e.g. using the tool 'beep' (apt-get install beep).
   It should work, usually.

As for Wake-on-LAN, it can usually be implemented either fully in
hardware or in the BIOS/firmware. If the latter you probably need some
extra code in coreboot. If it's implemented in hardware it will probably
work out of the box.
> I am going to send some users from my website to try it out. Some of  
> the info may be redundent but it is meant for a coreboot newby?
> Does it look like newby material?

It's fine, IMO, users should be able to follow the instructions.

Btw, can you post a full boot log (coreboot + Linux) here for reference?

Thanks, Uwe.

Quoting Uwe Hermann :
> Hi,
>
> On Mon, Mar 10, 2008 at 07:41:28PM -0400, [e-mail] wrote:
> > I added a Build Tutorial to the wiki:
> > http://www.coreboot.org/RCA_RM4100_Build_Tutorial
> > and linked it to the Supported Motherboards page.
>
> Great, thanks!
>
> I've done some cleanups on the page (small cosmetic fixes mostly). Some
> more comments on the contents:
> It would be nice if you could add one or two photos from the board.

Ok, I can do that.
> Also, please add a license tag to all your wiki pages and wiki
> images. You can use {{PD-self}} or {{CC-by-sa-3.0}} etc. See for
> example http://www.coreboot.org/ASUS_A8V-E_Deluxe_Build_Tutorial.

Ok, I can do that.
> Are you sure the L2 cache is enabled? Check 'dmesg', IIRC this is not
> done for most Intel chipsets yet (?) Also, you can run x86info
> or cpuinfo for more info, I think.

CPU: After generic identify, caps: 0383f9ff 00000000 00000000 00000000  
00000000 00000000 00000000 00000000
CPU: L1 I cache: 16K, L1 D cache: 16K
CPU: L2 cache: 256K
CPU: After all inits, caps: 0383f1ff 00000000 00000000 00000040  
00000000 00000000 00000000 00000000
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
Compat vDSO mapped to ffffe000.
Checking 'hlt' instruction... OK.
SMP alternatives: switching to UP code
Freeing SMP alternatives: 14k freed
CPU0: Intel Mobile Intel(R) Celeron(TM) CPU          733MHz stepping 04

[root@localhost ~]# cat /proc/cpuinfo
processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 11
model name	: Mobile Intel(R) Celeron(TM) CPU          733MHz
stepping	: 4
cpu MHz		: 733.160
cache size	: 256 KB
fdiv_bug	: no
hlt_bug		: no
f00f_bug	: no
coma_bug	: no
fpu		: yes
fpu_exception	: yes
cpuid level	: 2
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 mtrr pge mca cmov pat  
pse36 mmx fxsr sse up
bogomips	: 1467.20
clflush size	: 32
> How did you test the CDROM drive? Mounting something in Linux or
> booting from CDROM? If the latter, how (which FILO options etc)?

Mounting a disk in Linux
> Does the modem really work and how was that tested? Does it need
> special support in coreboot?

It is detected by the kernel ok, but I have not used it yet.
> Is there really an onboard-CF slot on the board? Or did you test
> using an Cf-to-IDE adapter? Or both?

Yes there is an onboard CF slot. It is connected to the primary IDE  
controller. I did use a CF-to-IDE adapter, and that works fine.
> How was IR tested? Which Linux tools? Any coreboot/superio changes
> required?

The IR is for the wireless keyboard, connected to COM2, as long as  
COM2 is enabled it works fine. I have not tested it with lirc and a  
remote yet.
> You marked 'PC Speaker' as N/A. Why? Try 'modprobe pcspkr' and then
> do some beeping, e.g. using the tool 'beep' (apt-get install beep).
> It should work, usually.

Even if there is no PC Speaker onboard? Would the beeping happen on  
the audio out?
> As for Wake-on-LAN, it can usually be implemented either fully in
> hardware or in the BIOS/firmware. If the latter you probably need some
> extra code in coreboot. If it's implemented in hardware it will probably
> work out of the box.

I agree but I have not tested it yet. It is enabled in the nics eeprom
> > I am going to send some users from my website to try it out. Some of
> > the info may be redundent but it is meant for a coreboot newby?
> > Does it look like newby material?
>
> It's fine, IMO, users should be able to follow the instructions.
>
> Btw, can you post a full boot log (coreboot + Linux) here for reference?

Do you want me to send it to the list, or post it on the wiki??

Thanks - Joe

[Uwe Hermann]

On Wed, Mar 12, 2008 at 10:24:05AM -0400, [e-mail] wrote:
> > Are you sure the L2 cache is enabled? Check 'dmesg', IIRC this is not
> > done for most Intel chipsets yet (?) Also, you can run x86info
> > or cpuinfo for more info, I think.
>
> CPU: After generic identify, caps: 0383f9ff 00000000 00000000 00000000  
> 00000000 00000000 00000000 00000000
> CPU: L1 I cache: 16K, L1 D cache: 16K
> CPU: L2 cache: 256K

Hm, interesting. I wonder how this can work. Or maybe the kernel just
"knows" that this CPU should have 256KB cache, but didn't actually check
whether it's enabled? Or, well, maybe it's on by default and cannot be
disabled at all on this CPU? Need to check some datasheets.

Various Pentium II/III CPUs I tried on 440BX boards did not have their
L2 cache initialized when I last checked, so I'm surprised this seems
to work here...
> > How did you test the CDROM drive? Mounting something in Linux or
> > booting from CDROM? If the latter, how (which FILO options etc)?
>
> Mounting a disk in Linux

OK, please mention that in the status table.
> > Does the modem really work and how was that tested? Does it need
> > special support in coreboot?
>
> It is detected by the kernel ok, but I have not used it yet.

Ditto.
> > Is there really an onboard-CF slot on the board? Or did you test
> > using an Cf-to-IDE adapter? Or both?
>
> Yes there is an onboard CF slot. It is connected to the primary IDE  
> controller. I did use a CF-to-IDE adapter, and that works fine.

OK.
> > How was IR tested? Which Linux tools? Any coreboot/superio changes
> > required?
>
> The IR is for the wireless keyboard, connected to COM2, as long as COM2 
> is enabled it works fine. I have not tested it with lirc and a remote 
> yet.

OK, fine. Please also mention that in the status table.
> > You marked 'PC Speaker' as N/A. Why? Try 'modprobe pcspkr' and then
> > do some beeping, e.g. using the tool 'beep' (apt-get install beep).
> > It should work, usually.
>
> Even if there is no PC Speaker onboard?

Oh, so none at all? That cannot work then, of course. I assumed there is
a speaker, or at least a pin header where you can connect one.
> > Btw, can you post a full boot log (coreboot + Linux) here for reference?
>
> Do you want me to send it to the list, or post it on the wiki??

To the list, just attach it to your next mail. You can then link to the
list archive in the wiki then, if you want.

Uwe.

Quoting Uwe Hermann :
> On Wed, Mar 12, 2008 at 10:24:05AM -0400, [e-mail] wrote:
> > > Are you sure the L2 cache is enabled? Check 'dmesg', IIRC this is not
> > > done for most Intel chipsets yet (?) Also, you can run x86info
> > > or cpuinfo for more info, I think.
> >
> > CPU: After generic identify, caps: 0383f9ff 00000000 00000000 00000000
> > 00000000 00000000 00000000 00000000
> > CPU: L1 I cache: 16K, L1 D cache: 16K
> > CPU: L2 cache: 256K
>
> Hm, interesting. I wonder how this can work. Or maybe the kernel just
> "knows" that this CPU should have 256KB cache, but didn't actually check
> whether it's enabled? Or, well, maybe it's on by default and cannot be
> disabled at all on this CPU? Need to check some datasheets.
>
> Various Pentium II/III CPUs I tried on 440BX boards did not have their
> L2 cache initialized when I last checked, so I'm surprised this seems
> to work here...

Really? It seems to work fine on this board, have you tried any socket  
370's? Maybe it is just an issue with slot 1's?
> > > Btw, can you post a full boot log (coreboot + Linux) here for reference?
> >
> > Do you want me to send it to the list, or post it on the wiki??
>
> To the list, just attach it to your next mail. You can then link to the
> list archive in the wiki then, if you want.

Will do as soon as I get a chance. So I added a hardware section with  
two pics, does that look ok?

Thanks - Joe

[Uwe Hermann]

On Wed, Mar 12, 2008 at 07:18:47PM -0400, [e-mail] wrote:
> Will do as soon as I get a chance. So I added a hardware section with  
> two pics, does that look ok?

Yep, thanks. But please add {{PD-self}} to all your images, too, e.g. here:

http://www.coreboot.org/Image:Rca_rm4100_modded.jpg

Uwe.

> Btw, can you post a full boot log (coreboot + Linux) here for reference?

Here is a bootlog with debug set to the max.

Thanks - Joe

RCA RM4100 howto on smittys.pointclark.net

Hello,
I was wondering if anyone would check out my howto to double check I  
got all the coreboot parts correct.

http://www.smittys.pointclark.net/rm4100/viewtopic.php?t=1

Thanks - Joe

[ron minnich]

Quick question. Have you tested that you absolutely have to do this:
Edit src/mainboard/rca/rm4100/Config.lb and comment out these lines so
it looks like this:

#    chip drivers/pci/onboard		# Onboard VGA
     device pci 2.0 on end		# VGA (Intel 82830 CGC)
#      register "rom_address" = "0xfff00000"
#    end

i.e. did you just try all the other mods without doing this? I realize
2.0 is on  its way out in the next year, but having to modify this
file says something is very, very wrong.

thanks

ron

Quoting ron minnich :
> Quick question. Have you tested that you absolutely have to do this:
> Edit src/mainboard/rca/rm4100/Config.lb and comment out these lines so
> it looks like this:
>
> #    chip drivers/pci/onboard		# Onboard VGA
>      device pci 2.0 on end		# VGA (Intel 82830 CGC)
> #      register "rom_address" = "0xfff00000"
> #    end
>
> i.e. did you just try all the other mods without doing this? I realize
> 2.0 is on  its way out in the next year, but having to modify this
> file says something is very, very wrong.

Not quite sure what you mean? If your not going to use VGA you should  
comment the rom stuff right? I tried something like:

if CONFIG_VIDEO_MB
    chip drivers/pci/onboard		# Onboard VGA
       device pci 2.0 on end		# VGA (Intel 82830 CGC)
          register "rom_address" = "0xfff00000"
    end
else
    device pci 2.0 on end		# VGA (Intel 82830 CGC)
end

But I kept getting build errors. Is it ok to leave the rom stuff with no VGA?

Thanks - Joe

[ron minnich]

On Tue, Mar 11, 2008 at 4:42 PM,   wrote:
> Quoting ron minnich :
> > i.e. did you just try all the other mods without doing this? I realize
> > 2.0 is on  its way out in the next year, but having to modify this
> > file says something is very, very wrong.
>
> Not quite sure what you mean? If your not going to use VGA you should
>  comment the rom stuff right? I tried something like:

you should never need to change Config.lb files in the src/ tree. If
you do, they are incorrectly
set up. Or there is a bug in the config/build system -- I won't rule
that out either :-)
> if CONFIG_VIDEO_MB
> chip drivers/pci/onboard            # Onboard VGA
>    device pci 2.0 on end            # VGA (Intel 82830 CGC)
>       register "rom_address" = "0xfff00000"
> end
>
> else
> device pci 2.0 on end               # VGA (Intel 82830 CGC)
>
> end
>
> But I kept getting build errors. Is it ok to leave the rom stuff with no VGA?

Yes, probably. the setting will be ignored since there is nothing
there to look at it.

I think you can just leave it all unchanged and build the bios. If you
don't mind, I'd appreciate it if you could try it.

thanks

ron

Quoting ron minnich :
> On Tue, Mar 11, 2008 at 4:42 PM,   wrote:
> > Quoting ron minnich :
> > > i.e. did you just try all the other mods without doing this? I realize
> > > 2.0 is on  its way out in the next year, but having to modify this
> > > file says something is very, very wrong.
> >
> > Not quite sure what you mean? If your not going to use VGA you should
> >  comment the rom stuff right? I tried something like:
>
> you should never need to change Config.lb files in the src/ tree. If
> you do, they are incorrectly
> set up. Or there is a bug in the config/build system -- I won't rule
> that out either :-)
> > if CONFIG_VIDEO_MB
> > chip drivers/pci/onboard            # Onboard VGA
> >    device pci 2.0 on end            # VGA (Intel 82830 CGC)
> >       register "rom_address" = "0xfff00000"
> > end
> >
> > else
> > device pci 2.0 on end               # VGA (Intel 82830 CGC)
> >
> > end
> >
> > But I kept getting build errors. Is it ok to leave the rom stuff   
> > with no VGA?
>
> Yes, probably. the setting will be ignored since there is nothing
> there to look at it.
>
> I think you can just leave it all unchanged and build the bios. If you
> don't mind, I'd appreciate it if you could try it.

Ok, I will try and report back, then update the wiki page.

Thanks - Joe

Quoting ron minnich :
> On Tue, Mar 11, 2008 at 4:42 PM,   wrote:
> > Quoting ron minnich :
> > > i.e. did you just try all the other mods without doing this? I realize
> > > 2.0 is on  its way out in the next year, but having to modify this
> > > file says something is very, very wrong.
> >
> > Not quite sure what you mean? If your not going to use VGA you should
> >  comment the rom stuff right? I tried something like:
>
> you should never need to change Config.lb files in the src/ tree. If
> you do, they are incorrectly
> set up. Or there is a bug in the config/build system -- I won't rule
> that out either :-)
> > if CONFIG_VIDEO_MB
> > chip drivers/pci/onboard            # Onboard VGA
> >    device pci 2.0 on end            # VGA (Intel 82830 CGC)
> >       register "rom_address" = "0xfff00000"
> > end
> >
> > else
> > device pci 2.0 on end               # VGA (Intel 82830 CGC)
> >
> > end
> >
> > But I kept getting build errors. Is it ok to leave the rom stuff   
> > with no VGA?
>
> Yes, probably. the setting will be ignored since there is nothing
> there to look at it.
>
> I think you can just leave it all unchanged and build the bios. If you
> don't mind, I'd appreciate it if you could try it.

Yep boots ok without touching mainboard Config.lb. See attached  
bootlog. I will update the wiki.

Thanks - Joe