[commit] r5677 - in trunk/src: mainboard/jetway/j7f24 northbridge/via/cn700 southbridge/via/vt8237r

[repository service]

Author: stepan
Date: Sun Aug  1 19:20:20 2010
New Revision: 5677
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5677

Log:
Clarify a comment on an old hack, remove the call to early_mtrr_init
that causes CAR to hang, provide more debugging output wrt memory size,
and correct the numbering on the ram init sequence.

Signed-off-by: Corey Osgood 
Acked-by: Stefan Reinauer

Modified:
   trunk/src/mainboard/jetway/j7f24/romstage.c
   trunk/src/northbridge/via/cn700/northbridge.c
   trunk/src/northbridge/via/cn700/raminit.c
   trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c

Modified: trunk/src/mainboard/jetway/j7f24/romstage.c
==============================================================================
--- trunk/src/mainboard/jetway/j7f24/romstage.c	Sun Aug  1 17:41:14 2010	(r5676)
+++ trunk/src/mainboard/jetway/j7f24/romstage.c	Sun Aug  1 19:20:20 2010	(r5677)
@@ -99,11 +99,6 @@
    enable_smbus();
    smbus_fixup(&ctrl);

-	if (bist == 0) {
-		print_debug("doing early_mtrr\n");
-		early_mtrr_init();
-	}
-
    /* Halt if there was a built-in self test failure. */
    report_bist_failure(bist);

Modified: trunk/src/northbridge/via/cn700/northbridge.c
==============================================================================
--- trunk/src/northbridge/via/cn700/northbridge.c	Sun Aug  1 17:41:14 2010	(r5676)
+++ trunk/src/northbridge/via/cn700/northbridge.c	Sun Aug  1 19:20:20 2010	(r5677)
@@ -177,7 +177,7 @@
    	}

tomk = rambits * 64 * 1024;
-		printk(BIOS_SPEW, "tomk is 0x%lx\n", tomk);
+		printk(BIOS_DEBUG, "tomk is 0x%lx\n", tomk);
    	/* Compute the Top Of Low Memory (TOLM), in Kb. */
    	tolmk = pci_tolm >> 10;
    	if (tolmk >= tomk) {

Modified: trunk/src/northbridge/via/cn700/raminit.c
==============================================================================
--- trunk/src/northbridge/via/cn700/raminit.c	Sun Aug  1 17:41:14 2010	(r5676)
+++ trunk/src/northbridge/via/cn700/raminit.c	Sun Aug  1 19:20:20 2010	(r5677)
@@ -183,6 +183,8 @@

if (result == 0xff)
    	die("DRAM module size too big, not supported by CN700\n");
+	else
+		printk(BIOS_DEBUG, "Found %iMB of ram\n", result * ranks * 64);

pci_write_config8(ctrl->d0f3, 0x40, result);
    pci_write_config8(ctrl->d0f3, 0x48, 0x00);
@@ -400,18 +402,18 @@
    read32(rank_address + 0x10);

/* 3. Mode register set. */
-	PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n");
+	PRINT_DEBUG_MEM("RAM Enable 3: Mode register set\n");
    do_ram_command(dev, RAM_COMMAND_MRS);
    read32(rank_address + 0x120000);	/* EMRS DLL Enable */
    read32(rank_address + 0x800);		/* MRS DLL Reset */

/* 4. Precharge all again. */
-	PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n");
+	PRINT_DEBUG_MEM("RAM Enable 4: Precharge all\n");
    do_ram_command(dev, RAM_COMMAND_PRECHARGE);
    read32(rank_address + 0x0);

/* 5. Perform 8 refresh cycles. Wait tRC each time. */
-	PRINT_DEBUG_MEM("RAM Enable 3: CBR\n");
+	PRINT_DEBUG_MEM("RAM Enable 5: CBR\n");
    do_ram_command(dev, RAM_COMMAND_CBR);
    for (i = 0; i < 8; i++) {
    	read32(rank_address + 0x20);
@@ -419,7 +421,7 @@
    }

/* 6. Mode register set. */
-	PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n");
+	PRINT_DEBUG_MEM("RAM Enable 6: Mode register set\n");
    /* Safe value for now, BL=8, WR=5, CAS=4 */
    /*
     * (E)MRS values are from the BPG. No direct explanation is given, but
@@ -432,7 +434,7 @@
    read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */

/* 8. Normal operation */
-	PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\n");
+	PRINT_DEBUG_MEM("RAM Enable 7: Normal operation\n");
    do_ram_command(dev, RAM_COMMAND_NORMAL);
    read32(rank_address + 0x30);
 }

Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
==============================================================================
--- trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	Sun Aug  1 17:41:14 2010	(r5676)
+++ trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c	Sun Aug  1 19:20:20 2010	(r5677)
@@ -61,8 +61,10 @@

PRINT_DEBUG("Waiting until SMBus ready\n");

-	/* Yes, this is a mess, but it's the easiest way to do it. */
-	/* XXX not so messy, but an explanation of the hack would have been better */
+	/* Loop up to SMBUS_TIMEOUT times, waiting for bit 0 of the
+	 * SMBus Host Status register to go to 0, indicating the operation
+	 * was completed successfully. I don't remember why I did it this way,
+	 * but I think it was because ROMCC was running low on registers */
    loops = 0;
    while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT)
    	++loops;