ron minnich wrote:
I'm still convinced this is an issue with the code, not the insertion of the DIMMs.
Me too.
Are the DIMMs identical w.r.t. timing? Are you always plugging the same DIMMs into the same slots, or did you try swapping them around?
And are they known to be error free?
//Peter
On Sat, Sep 13, 2014 at 12:28:45AM +0200, Peter Stuge wrote:
ron minnich wrote:
I'm still convinced this is an issue with the code, not the insertion of the DIMMs.
Me too.
Are the DIMMs identical w.r.t. timing? Are you always plugging the same DIMMs into the same slots, or did you try swapping them around?
And are they known to be error free?
//Peter
Testing for more than 12 hours with MemTest86+ having both DIMMs installed at the same time and booted with coreboot resulted in 12 passes with 0 errors. Other than that I do not know if they have errors.
with best regards Mono
Here's the problem. There is caching of the DRAM configuration going on. So, a restart is not stateless.
I would be happier if you could guarantee that the mrc cache is disabled, or never used, each time you change the dram setup (move DIMMs, whatever). Because from your earlier description it sounds to me like that is skewing your tests.
If this makes no sense let me know.
ron
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Mono -
Peter Stuge -
ron minnich