Hi all- I wrote up an article (or, more like a step-by-step guide) on how to resize the BIOS chip from 8MB to 16MB. This is particularly handy for people (like myself) who want more space for payloads.
This was done on an X210, but theoretically it should work fine on other platforms as well, as long the target chip size is supported by one's chipset.
Feel free to point out any issues or clarifications that need to happen, and don't look at the rest of my site (just kidding, but I haven't really touched it in years and it's horribly out of date).
https://rsend.wordpress.com/x210-coreboot/increasing-rom-chip-size-on-an-x21...
Cheers, Rafael
Good writeup!
While completely achieving the objective, there is also a shorter version here which has less steps, but aimed at the heads user. Basically the way I did it for heads was to ifdtool -D a normal build to 16MB then just extract the IFD and use that to rebuild coreboot.
https://github.com/osresearch/heads/issues/547#issuecomment-485887948
Your writeup is eway more concise though and will enable many more users to work it through.
You may also want to look at modifying the VSCC table when you swap out the SPI chip (if you intend ME to function on all boards) from 0xDF0 ( kernel/blob/master/drivers/mtd/spi-nor/spi-nor.c https://github.com/openSUSE/kernel/blob/master/drivers/mtd/spi-nor/spi-nor.c provides a good reference for which chips have which identifier) . Without VSCC being correct, ME wont know how to perform wirtes and on many boards a wrong VSCC can cause problems or even an alternate ME neuter method ( see https://github.com/corna/me_cleaner/issues/80 )
Great work, thanks for contributing!
On Tue, 5 May 2020 at 22:05, Rafael Send flyingfishfinger@gmail.com wrote:
Hi all- I wrote up an article (or, more like a step-by-step guide) on how to resize the BIOS chip from 8MB to 16MB. This is particularly handy for people (like myself) who want more space for payloads.
This was done on an X210, but theoretically it should work fine on other platforms as well, as long the target chip size is supported by one's chipset.
Feel free to point out any issues or clarifications that need to happen, and don't look at the rest of my site (just kidding, but I haven't really touched it in years and it's horribly out of date).
https://rsend.wordpress.com/x210-coreboot/increasing-rom-chip-size-on-an-x21...
Cheers, Rafael _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Hi, Ha, I think I actually read that post - someone might have shared it with me when I first started poking at this. I found that it was hard to follow, especially starting with zero knowledge around BIOSes, but it definitely got me on the right track.
And I'll take a look at the VSSC table thing - but the reference link in that post is dead. Do you have an update?
R
On Tue, May 5, 2020 at 3:23 PM Simon Newton simon.newton@gmail.com wrote:
Good writeup!
While completely achieving the objective, there is also a shorter version here which has less steps, but aimed at the heads user. Basically the way I did it for heads was to ifdtool -D a normal build to 16MB then just extract the IFD and use that to rebuild coreboot.
https://github.com/osresearch/heads/issues/547#issuecomment-485887948
Your writeup is eway more concise though and will enable many more users to work it through.
You may also want to look at modifying the VSCC table when you swap out the SPI chip (if you intend ME to function on all boards) from 0xDF0 ( kernel/blob/master/drivers/mtd/spi-nor/spi-nor.c https://github.com/openSUSE/kernel/blob/master/drivers/mtd/spi-nor/spi-nor.c provides a good reference for which chips have which identifier) . Without VSCC being correct, ME wont know how to perform wirtes and on many boards a wrong VSCC can cause problems or even an alternate ME neuter method ( see https://github.com/corna/me_cleaner/issues/80 )
Great work, thanks for contributing!
On Tue, 5 May 2020 at 22:05, Rafael Send flyingfishfinger@gmail.com wrote:
Hi all- I wrote up an article (or, more like a step-by-step guide) on how to resize the BIOS chip from 8MB to 16MB. This is particularly handy for people (like myself) who want more space for payloads.
This was done on an X210, but theoretically it should work fine on other platforms as well, as long the target chip size is supported by one's chipset.
Feel free to point out any issues or clarifications that need to happen, and don't look at the rest of my site (just kidding, but I haven't really touched it in years and it's horribly out of date).
https://rsend.wordpress.com/x210-coreboot/increasing-rom-chip-size-on-an-x21...
Cheers, Rafael _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
-- Kind Regards,
Simon Newton
E: Simon.newton@gmail.com
glad it was useful! Its not easy to follow as its not a full writeup, like i said yours is a lot better for people to follow. Steps are way more clearer.
Thanks for the link pointer, you are right, it moved formats in later kernels. The hex needed for each chip is now split out into manufacturers, from what I can tell
https://github.com/torvalds/linux/tree/master/drivers/mtd/spi-nor
eg, in winbond.c "w25q16dw", INFO(0xef6015
On Tue, 5 May 2020 at 23:55, Rafael Send flyingfishfinger@gmail.com wrote:
Hi, Ha, I think I actually read that post - someone might have shared it with me when I first started poking at this. I found that it was hard to follow, especially starting with zero knowledge around BIOSes, but it definitely got me on the right track.
And I'll take a look at the VSSC table thing - but the reference link in that post is dead. Do you have an update?
R
On Tue, May 5, 2020 at 3:23 PM Simon Newton simon.newton@gmail.com wrote:
Good writeup!
While completely achieving the objective, there is also a shorter version here which has less steps, but aimed at the heads user. Basically the way I did it for heads was to ifdtool -D a normal build to 16MB then just extract the IFD and use that to rebuild coreboot.
https://github.com/osresearch/heads/issues/547#issuecomment-485887948
Your writeup is eway more concise though and will enable many more users to work it through.
You may also want to look at modifying the VSCC table when you swap out the SPI chip (if you intend ME to function on all boards) from 0xDF0 ( kernel/blob/master/drivers/mtd/spi-nor/spi-nor.c https://github.com/openSUSE/kernel/blob/master/drivers/mtd/spi-nor/spi-nor.c provides a good reference for which chips have which identifier) . Without VSCC being correct, ME wont know how to perform wirtes and on many boards a wrong VSCC can cause problems or even an alternate ME neuter method ( see https://github.com/corna/me_cleaner/issues/80 )
Great work, thanks for contributing!
On Tue, 5 May 2020 at 22:05, Rafael Send flyingfishfinger@gmail.com wrote:
Hi all- I wrote up an article (or, more like a step-by-step guide) on how to resize the BIOS chip from 8MB to 16MB. This is particularly handy for people (like myself) who want more space for payloads.
This was done on an X210, but theoretically it should work fine on other platforms as well, as long the target chip size is supported by one's chipset.
Feel free to point out any issues or clarifications that need to happen, and don't look at the rest of my site (just kidding, but I haven't really touched it in years and it's horribly out of date).
https://rsend.wordpress.com/x210-coreboot/increasing-rom-chip-size-on-an-x21...
Cheers, Rafael _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
-- Kind Regards,
Simon Newton
E: Simon.newton@gmail.com
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Rafael Send -
Simon Newton