I forgot to mention that if I took one of the cpus out, coreboot wouldn't start at all. If I put that one back in and took the other out, I got the same output as before.
-------- Original Message -------- Subject: Re: [coreboot] [Fwd: Re: arima hdama problem] Date: Tue, 20 Oct 2009 09:35:13 -0600 From: Hugh Greenberg hng@lanl.gov To: ron minnich rminnich@gmail.com CC: Myles Watson mylesgw@gmail.com, coreboot@coreboot.org References: 4AD8CE7F.1080909@lanl.gov 2831fecf0910161306m26767a4ft56b14f0d92f231a0@mail.gmail.com 2831fecf0910161316q4d9b7b04x51d1b04556b16e82@mail.gmail.com 4AD8D764.7060908@lanl.gov 2831fecf0910161415o29ca7b7dl4ae498a8b678c151@mail.gmail.com 4AD8E7AF.2090908@lanl.gov 2831fecf0910161552g39819ef6m2a33cb5b1adc2260@mail.gmail.com 13426df10910161746s1924d7f6ub4ba20aa4a63f0be@mail.gmail.com
It didn't work after I took the cpu out. I got the same output. Is there anything else I could try?
On Tue, Oct 20, 2009 at 9:43 AM, Hugh Greenberg hng@lanl.gov wrote:
I forgot to mention that if I took one of the cpus out, coreboot wouldn't start at all. If I put that one back in and took the other out, I got the same output as before.
Strange.
Could you try this patch so we can see what APIC it's trying to read?
Thanks, Myles
Myles,
Here is the full output after flashing the latest revision and the patch:
coreboot-2.3 Tue Oct 20 11:36:27 MDT 2009 starting... Enabling routing table for node 00 done. Enabling SMP settings (0,1) link=01 (1,0) link=01 setup_remote_node: done Renaming current temporary node to 01 done. Enabling routing table for node 01 done. 02 nodes initialized. coherent_ht_finalize done SBLink=00 NC node|link=00 iapicen taepriicn gi d ht_0o1p mize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x35 freq_cap1=0x35, freq_cap2=0x15 dev1 old_freq=0x4, freq=0x4, needs_reset=0x0 dev2 old_freq=0x4, freq=0x4, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 entering ht_optimize_link pos=0xd2, unfiltered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x1 pos=0xce, filtered freq_cap=0x1 freq_cap1=0x15, freq_cap2=0x1 dev1 old_freq=0x0, freq=0x0, needs_reset=0x0 dev2 old_freq=0x0, freq=0x0, needs_reset=0x0 width_cap1=0x0, width_cap2=0x0 dev1 input ln_width1=0x3, ln_width2=0x3 dev1 input width=0x0 dev1 output ln_width1=0x3, ln_width2=0x3 dev1 input|output width=0x0 old dev1 input|output width=0x0 dev2 input|output width=0x0 old dev2 input|output width=0x0 SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram1.01 setting up CPU01 northbridge registers done. Ram2.00 Enabling dual channel memory Registered 166Mhz RAM end at 0x00100000 kB Lower RAM end at 0x00100000 kB Ram2.01 Enabling dual channel memory Registered 166Mhz RAM end at 0x00200000 kB Lower RAM end at 0x00200000 kB Ram3 print_k8regs: func 0 (c0000) 0x40 (Routing 0) 50101 0x44 (Routing 1) 10404 0x60 (Node ID) 10010 print_k8regs: func 1 (c1000) 0x40 (DRAM Base) 3 0x44 (DRAM Lim) 3f0000 0x48 (DRAM Base) 400003 0x4C (DRAM Lim) 7f0001 b8 fc0003 bc ffff00 c0 3 c4 1fff000 e0 3f000003 print_k8regs: func 2 (c2000) nonzero only 40 (DRAM Base) 1 60 (DRAM Base) 3e0fe00 80 (DRAM Base) 4 while waiting for BSP signal to STOP, timeout in ap 01 BSP apic id 00
On Tue, Oct 20, 2009 at 11:45 AM, Hugh Greenberg hng@lanl.gov wrote:
Myles,
Here is the full output after flashing the latest revision and the patch:
Thanks. The IDs that got printed looked fine. How about disabling SMP (patch attached) after updating to the latest?
Thanks, Myles
On Tue, Oct 20, 2009 at 12:21 PM, Myles Watson mylesgw@gmail.com wrote:
On Tue, Oct 20, 2009 at 11:45 AM, Hugh Greenberg hng@lanl.gov wrote:
Myles,
Here is the full output after flashing the latest revision and the patch:
Thanks. The IDs that got printed looked fine. How about disabling SMP (patch attached) after updating to the latest?
By the way, I still haven't seen the "ht_reset" I'd expect from a cold boot in your logs. At least until we figure something out, could you make sure to power cycle each time?
Thanks, Myles
On Tue, Oct 20, 2009 at 12:59 PM, Myles Watson mylesgw@gmail.com wrote:
On Tue, Oct 20, 2009 at 12:21 PM, Myles Watson mylesgw@gmail.com wrote:
On Tue, Oct 20, 2009 at 11:45 AM, Hugh Greenberg hng@lanl.gov wrote:
Myles,
Here is the full output after flashing the latest revision and the patch:
Thanks. The IDs that got printed looked fine. How about disabling SMP (patch attached) after updating to the latest?
By the way, I still haven't seen the "ht_reset" I'd expect from a cold boot in your logs. At least until we figure something out, could you make sure to power cycle each time?
I was wondering if it is getting stuck in the chipset reset code. The last message seems to be that it is ignoring the other AP and going to do the reset.
Marc
I have been power cycling since you pointed it out last time.
On Tue, Oct 20, 2009 at 1:31 PM, Hugh Greenberg hng@lanl.gov wrote:
I have been power cycling since you pointed it out last time.
So have you been editing the logs (removing the first bit before the HT reset)?
pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x35 freq_cap1=0x35, freq_cap2=0x15 dev1 old_freq=0x4, freq=0x4, needs_reset=0x0 dev2 old_freq=0x4, freq=0x4, needs_reset=0x0
This is link 0, and it says it is already running at the maximum frequency, so it doesn't need a reset. A cold boot should start at 200MHz and always need a reset. Here's an example from SimNOW:
dev1 old_freq=0x0, freq=0x4, needs_reset=0x1 dev2 old_freq=0x0, freq=0x4, needs_reset=0x1
If you haven't been editing the logs, then maybe there's something wrong with the early serial port initialization. That would be good to know.
Thanks, Myles
No, I haven't been editing the logs. I sent you exactly what I saw on the serial port.
On Tue, Oct 20, 2009 at 1:50 PM, Hugh Greenberg hng@lanl.gov wrote:
No, I haven't been editing the logs. I sent you exactly what I saw on the serial port.
Good to know. I didn't think you would, but there's a big chunk missing.
Thanks, Myles
Oops. I did miss a big chunk of the log :). I thought it was part of the previous output. Here is the full log:
coreboot-2.3 Tue Oct 20 11:36:27 MDT 2009 starting... Enabling routing table for node 00 done. Enabling SMP settings (0,1) link=01 (1,0) link=01 setup_remote_node: done Renaming current temporary node to 01 done. Enabling routing table for node 01 done. 02 nodes initialized. coherent_ht_finalize done SBLink=00 NC node|link=00 enterinlg ahpti_co patpiimci zied_ li0n1k
pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x35 freq_cap1=0x35, freq_cap2=0x15 dev1 old_freq=0x0, freq=0x4, needs_reset=0x1 dev2 old_freq=0x0, freq=0x4, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 entering ht_optimize_link pos=0xd2, unfiltered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x1 pos=0xce, filtered freq_cap=0x1 freq_cap1=0x15, freq_cap2=0x1 dev1 old_freq=0x0, freq=0x0, needs_reset=0x0 dev2 old_freq=0x0, freq=0x0, needs_reset=0x0 width_cap1=0x0, width_cap2=0x0 dev1 input ln_width1=0x3, ln_width2=0x3 dev1 input width=0x0 dev1 output ln_width1=0x3, ln_width2=0x3 dev1 input|output width=0x0 old dev1 input|output width=0x0 dev2 input|output width=0x0 old dev2 input|output width=0x0 ht reset -
coreboot-2.3 Tue Oct 20 11:36:27 MDT 2009 starting... Enabling routing table for node 00 done. Enabling SMP settings (0,1) link=01 (1,0) link=01 setup_remote_node: done Renaming current temporary node to 01 done. Enabling routing table for node 01 done. 02 nodes initialized. coherent_ht_finalize done SBLink=00 NC node|link=00 iapicen taepriicn gi d ht_0o1p mize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x35 freq_cap1=0x35, freq_cap2=0x15 dev1 old_freq=0x4, freq=0x4, needs_reset=0x0 dev2 old_freq=0x4, freq=0x4, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 entering ht_optimize_link pos=0xd2, unfiltered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x1 pos=0xce, filtered freq_cap=0x1 freq_cap1=0x15, freq_cap2=0x1 dev1 old_freq=0x0, freq=0x0, needs_reset=0x0 dev2 old_freq=0x0, freq=0x0, needs_reset=0x0 width_cap1=0x0, width_cap2=0x0 dev1 input ln_width1=0x3, ln_width2=0x3 dev1 input width=0x0 dev1 output ln_width1=0x3, ln_width2=0x3 dev1 input|output width=0x0 old dev1 input|output width=0x0 dev2 input|output width=0x0 old dev2 input|output width=0x0 SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram1.01 setting up CPU01 northbridge registers done. Ram2.00 Enabling dual channel memory Registered 166Mhz RAM end at 0x00100000 kB Lower RAM end at 0x00100000 kB Ram2.01 Enabling dual channel memory Registered 166Mhz RAM end at 0x00200000 kB Lower RAM end at 0x00200000 kB Ram3
On Tue, Oct 20, 2009 at 2:01 PM, Hugh Greenberg hng@lanl.gov wrote:
Oops. I did miss a big chunk of the log :). I thought it was part of the previous output. Here is the full log:
OK. That looks better. Now did you try applying no_smp.diff?
Thanks, Myles
Yes. Here is the output:
coreboot-2.3 Tue Oct 20 14:42:33 MDT 2009 starting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done SBLink=00 NC node|link=00 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x35 freq_cap1=0x35, freq_cap2=0x15 dev1 old_freq=0x0, freq=0x4, needs_reset=0x1 dev2 old_freq=0x0, freq=0x4, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 entering ht_optimize_link pos=0xd2, unfiltered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x1 pos=0xce, filtered freq_cap=0x1 freq_cap1=0x15, freq_cap2=0x1 dev1 old_freq=0x0, freq=0x0, needs_reset=0x0 dev2 old_freq=0x0, freq=0x0, needs_reset=0x0 width_cap1=0x0, width_cap2=0x0 dev1 input ln_width1=0x3, ln_width2=0x3 dev1 input width=0x0 dev1 output ln_width1=0x3, ln_width2=0x3 dev1 input|output width=0x0 old dev1 input|output width=0x0 dev2 input|output width=0x0 old dev2 input|output width=0x0 ht reset -
coreboot-2.3 Tue Oct 20 14:42:33 MDT 2009 starting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done SBLink=00 NC node|link=00 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x35 freq_cap1=0x35, freq_cap2=0x15 dev1 old_freq=0x4, freq=0x4, needs_reset=0x0 dev2 old_freq=0x4, freq=0x4, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 entering ht_optimize_link pos=0xd2, unfiltered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x1 pos=0xce, filtered freq_cap=0x1 freq_cap1=0x15, freq_cap2=0x1 dev1 old_freq=0x0, freq=0x0, needs_reset=0x0 dev2 old_freq=0x0, freq=0x0, needs_reset=0x0 width_cap1=0x0, width_cap2=0x0 dev1 input ln_width1=0x3, ln_width2=0x3 dev1 input width=0x0 dev1 output ln_width1=0x3, ln_width2=0x3 dev1 input|output width=0x0 old dev1 input|output width=0x0 dev2 input|output width=0x0 old dev2 input|output width=0x0 SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram2.00 Enabling dual channel memory Registered 166Mhz RAM end at 0x00100000 kB Lower RAM end at 0x00100000 kB Ram3
On Tue, Oct 20, 2009 at 2:53 PM, Hugh Greenberg hng@lanl.gov wrote:
Yes. Here is the output:
RAM end at 0x00100000 kB Lower RAM end at 0x00100000 kB Ram3
OK. So it's actually hanging in RAM init, not starting the other processors.
Here's another patch :)
Thanks, Myles
Ok, here is the output:
coreboot-2.3 Tue Oct 20 15:20:40 MDT 2009 starting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done started ap apicid: SBLink=00 NC node|link=00 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x35 freq_cap1=0x35, freq_cap2=0x15 dev1 old_freq=0x0, freq=0x4, needs_reset=0x1 dev2 old_freq=0x0, freq=0x4, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 entering ht_optimize_link pos=0xd2, unfiltered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x1 pos=0xce, filtered freq_cap=0x1 freq_cap1=0x15, freq_cap2=0x1 dev1 old_freq=0x0, freq=0x0, needs_reset=0x0 dev2 old_freq=0x0, freq=0x0, needs_reset=0x0 width_cap1=0x0, width_cap2=0x0 dev1 input ln_width1=0x3, ln_width2=0x3 dev1 input width=0x0 dev1 output ln_width1=0x3, ln_width2=0x3 dev1 input|output width=0x0 old dev1 input|output width=0x0 dev2 input|output width=0x0 old dev2 input|output width=0x0 ht reset -
coreboot-2.3 Tue Oct 20 15:20:40 MDT 2009 starting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done started ap apicid: SBLink=00 NC node|link=00 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x35 freq_cap1=0x35, freq_cap2=0x15 dev1 old_freq=0x4, freq=0x4, needs_reset=0x0 dev2 old_freq=0x4, freq=0x4, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 entering ht_optimize_link pos=0xd2, unfiltered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x1 pos=0xce, filtered freq_cap=0x1 freq_cap1=0x15, freq_cap2=0x1 dev1 old_freq=0x0, freq=0x0, needs_reset=0x0 dev2 old_freq=0x0, freq=0x0, needs_reset=0x0 width_cap1=0x0, width_cap2=0x0 dev1 input ln_width1=0x3, ln_width2=0x3 dev1 input width=0x0 dev1 output ln_width1=0x3, ln_width2=0x3 dev1 input|output width=0x0 old dev1 input|output width=0x0 dev2 input|output width=0x0 old dev2 input|output width=0x0 SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram2.00 Enabling dual channel memory Registered 166Mhz RAM end at 0x00100000 kB Lower RAM end at 0x00100000 kB Ram3 Before starting clocks: Before memreset:
On Tue, Oct 20, 2009 at 3:27 PM, Hugh Greenberg hng@lanl.gov wrote:
Ram3 Before starting clocks: Before memreset:
It looks like it's dying in udelay. I don't know why, but I put in a timeout to see if that helps us get past it.
Thanks, Myles
Seems to have gotten farther:
coreboot-2.3 Tue Oct 20 15:51:22 MDT 2009 starting... Enabling routing table for node 00 done. Enabling SMP settings (0,1) link=01 (1,0) link=01 setup_remote_node: done Renaming current temporary node to 01 done. Enabling routing table for node 01 done. 02 nodes initialized. coherent_ht_finalize done started ap apicid: SBLink=00 NC node|link=00 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x35 freq_cap1=0x35, freq_cap2=0x15 dev1 old_freq=0x0, freq=0x4, needs_reset=0x1 dev2 old_freq=0x0, freq=0x4, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 entering ht_optimize_link pos=0xd2, unfiltered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x1 pos=0xce, filtered freq_cap=0x1 freq_cap1=0x15, freq_cap2=0x1 dev1 old_freq=0x0, freq=0x0, needs_reset=0x0 dev2 old_freq=0x0, freq=0x0, needs_reset=0x0 width_cap1=0x0, width_cap2=0x0 dev1 input ln_width1=0x3, ln_width2=0x3 dev1 input width=0x0 dev1 output ln_width1=0x3, ln_width2=0x3 dev1 input|output width=0x0 old dev1 input|output width=0x0 dev2 input|output width=0x0 old dev2 input|output width=0x0 ht reset -
coreboot-2.3 Tue Oct 20 15:51:22 MDT 2009 starting... Enabling routing table for node 00 done. Enabling SMP settings (0,1) link=01 (1,0) link=01 setup_remote_node: done Renaming current temporary node to 01 done. Enabling routing table for node 01 done. 02 nodes initialized. coherent_ht_finalize done started ap apicid: SBLink=00 NC node|link=00 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x35 freq_cap1=0x35, freq_cap2=0x15 dev1 old_freq=0x4, freq=0x4, needs_reset=0x0 dev2 old_freq=0x4, freq=0x4, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 entering ht_optimize_link pos=0xd2, unfiltered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x1 pos=0xce, filtered freq_cap=0x1 freq_cap1=0x15, freq_cap2=0x1 dev1 old_freq=0x0, freq=0x0, needs_reset=0x0 dev2 old_freq=0x0, freq=0x0, needs_reset=0x0 width_cap1=0x0, width_cap2=0x0 dev1 input ln_width1=0x3, ln_width2=0x3 dev1 input width=0x0 dev1 output ln_width1=0x3, ln_width2=0x3 dev1 input|output width=0x0 old dev1 input|output width=0x0 dev2 input|output width=0x0 old dev2 input|output width=0x0 SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram1.01 setting up CPU01 northbridge registers done. Ram2.00 Enabling dual channel memory Registered 166Mhz RAM end at 0x00100000 kB Lower RAM end at 0x00100000 kB Ram2.01 Enabling dual channel memory Registered 166Mhz RAM end at 0x00200000 kB Lower RAM end at 0x00200000 kB Ram3 Before starting clocks: Before memreset: cpu is pre_c0 after first udelay after second udelay Before controllers loop: ECC enabled ECC enabled Before 2nd controllers loop: Initializing memory: done Initializing memory: done Before hole: Ram4 v_esp=000ced88 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Jumping to image. Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram Stage: load fallback/coreboot_ram @ 1048576/409600 bytes, enter @ 100000 Stage: done loading. Jumping to image. POST: 0x80 POST: 0x39 coreboot-2.3 Tue Oct 20 15:51:22 MDT 2009 booting... POST: 0x40 Enumerating buses... Show all devs...Before Device Enumeration. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PCI: 00:01.1: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:00.2: enabled 0, 0 resources PCI: 00:01.0: enabled 0, 0 resources PCI: 00:06.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 2 resources PNP: 002e.2: enabled 0, 2 resources PNP: 002e.3: enabled 1, 2 resources PNP: 002e.4: enabled 0, 0 resources PNP: 002e.5: enabled 0, 0 resources PNP: 002e.6: enabled 1, 3 resources PNP: 002e.7: enabled 0, 0 resources PNP: 002e.8: enabled 0, 0 resources PNP: 002e.9: enabled 0, 0 resources PNP: 002e.a: enabled 0, 0 resources PCI: 00:01.1: enabled 1, 0 resources PCI: 00:01.2: enabled 1, 0 resources PCI: 00:01.3: enabled 1, 0 resources I2C: 00:70: enabled 1, 0 resources I2C: 00:2c: enabled 1, 0 resources I2C: 00:50: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources I2C: 00:52: enabled 1, 0 resources I2C: 00:53: enabled 1, 0 resources I2C: 00:54: enabled 1, 0 resources I2C: 00:55: enabled 1, 0 resources I2C: 00:56: enabled 1, 0 resources I2C: 00:57: enabled 1, 0 resources PCI: 00:01.5: enabled 0, 0 resources PCI: 00:01.6: enabled 1, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources PCI: 00:19.0: enabled 1, 0 resources PCI: 00:19.1: enabled 1, 0 resources PCI: 00:19.2: enabled 1, 0 resources PCI: 00:19.3: enabled 1, 0 resources Compare with tree... Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PCI: 00:01.1: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:00.2: enabled 0, 0 resources PCI: 00:01.0: enabled 0, 0 resources PCI: 00:06.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 2 resources PNP: 002e.2: enabled 0, 2 resources PNP: 002e.3: enabled 1, 2 resources PNP: 002e.4: enabled 0, 0 resources PNP: 002e.5: enabled 0, 0 resources PNP: 002e.6: enabled 1, 3 resources PNP: 002e.7: enabled 0, 0 resources PNP: 002e.8: enabled 0, 0 resources PNP: 002e.9: enabled 0, 0 resources PNP: 002e.a: enabled 0, 0 resources PCI: 00:01.1: enabled 1, 0 resources PCI: 00:01.2: enabled 1, 0 resources PCI: 00:01.3: enabled 1, 0 resources I2C: 00:70: enabled 1, 0 resources I2C: 00:2c: enabled 1, 0 resources I2C: 00:50: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources I2C: 00:52: enabled 1, 0 resources I2C: 00:53: enabled 1, 0 resources I2C: 00:54: enabled 1, 0 resources I2C: 00:55: enabled 1, 0 resources I2C: 00:56: enabled 1, 0 resources I2C: 00:57: enabled 1, 0 resources PCI: 00:01.5: enabled 0, 0 resources PCI: 00:01.6: enabled 1, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources PCI: 00:19.0: enabled 1, 0 resources PCI: 00:19.1: enabled 1, 0 resources PCI: 00:19.2: enabled 1, 0 resources PCI: 00:19.3: enabled 1, 0 resources scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=0 CPU: APIC: 00 enabled PCI: 00:19.3 siblings=0 malloc Enter, size 1100, free_mem_ptr 00160000 malloc 00160000 CPU: APIC: 01 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 PCI: 00:18.0 [1022/1100] bus ops PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:18.4, bad id 0xffffffff PCI: 00:18.5, bad id 0xffffffff PCI: 00:18.6, bad id 0xffffffff PCI: 00:18.7, bad id 0xffffffff PCI: 00:19.0 [1022/1100] bus ops PCI: 00:19.0 [1022/1100] enabled PCI: 00:19.1 [1022/1101] enabled PCI: 00:19.2 [1022/1102] enabled PCI: 00:19.3 [1022/1103] ops PCI: 00:19.3 [1022/1103] enabled PCI: 00:19.4, bad id 0xffffffff PCI: 00:19.5, bad id 0xffffffff PCI: 00:19.6, bad id 0xffffffff PCI: 00:19.7, bad id 0xffffffff PCI: 00:1a.0, bad id 0xffffffff PCI: 00:1b.0, bad id 0xffffffff PCI: 00:1c.0, bad id 0xffffffff PCI: 00:1d.0, bad id 0xffffffff PCI: 00:1e.0, bad id 0xffffffff PCI: 00:1f.0, bad id 0xffffffff POST: 0x25
On Tue, Oct 20, 2009 at 3:58 PM, Hugh Greenberg hng@lanl.gov wrote:
Seems to have gotten farther:
OK. So for some reason you can't read the LAPIC. I have no idea why that could be.
Anyone else wnat to chime in? His board hangs in udelay(), which just does lapi_read in a loop.
start = lapic_read(LAPIC_TMCCT); do { value = lapic_read(LAPIC_TMCCT); } while((start - value) < ticks);
If I make it time out after 1000000 reads, it continues, otherwise it hangs.
The only thing I can think is that the timer didn't get initialized. But I don't know why it would hang later. Maybe we should try no_smp with the workaround.
Patch attached to initialize the timer.
Thanks, Myles
Below is the output with the no_smp patch and the previous patch. Is there another problem since the payload is not being loaded?
coreboot-2.3 Tue Oct 20 16:46:25 MDT 2009 starting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done started ap apicid: SBLink=00 NC node|link=00 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x35 freq_cap1=0x35, freq_cap2=0x15 dev1 old_freq=0x0, freq=0x4, needs_reset=0x1 dev2 old_freq=0x0, freq=0x4, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 entering ht_optimize_link pos=0xd2, unfiltered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x1 pos=0xce, filtered freq_cap=0x1 freq_cap1=0x15, freq_cap2=0x1 dev1 old_freq=0x0, freq=0x0, needs_reset=0x0 dev2 old_freq=0x0, freq=0x0, needs_reset=0x0 width_cap1=0x0, width_cap2=0x0 dev1 input ln_width1=0x3, ln_width2=0x3 dev1 input width=0x0 dev1 output ln_width1=0x3, ln_width2=0x3 dev1 input|output width=0x0 old dev1 input|output width=0x0 dev2 input|output width=0x0 old dev2 input|output width=0x0 ht reset -
coreboot-2.3 Tue Oct 20 16:46:25 MDT 2009 starting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. coherent_ht_finalize done started ap apicid: SBLink=00 NC node|link=00 entering ht_optimize_link pos=0x8a, unfiltered freq_cap=0x8075 pos=0x8a, filtered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x35 freq_cap1=0x35, freq_cap2=0x15 dev1 old_freq=0x4, freq=0x4, needs_reset=0x0 dev2 old_freq=0x4, freq=0x4, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 entering ht_optimize_link pos=0xd2, unfiltered freq_cap=0x35 pos=0xce, unfiltered freq_cap=0x1 pos=0xce, filtered freq_cap=0x1 freq_cap1=0x15, freq_cap2=0x1 dev1 old_freq=0x0, freq=0x0, needs_reset=0x0 dev2 old_freq=0x0, freq=0x0, needs_reset=0x0 width_cap1=0x0, width_cap2=0x0 dev1 input ln_width1=0x3, ln_width2=0x3 dev1 input width=0x0 dev1 output ln_width1=0x3, ln_width2=0x3 dev1 input|output width=0x0 old dev1 input|output width=0x0 dev2 input|output width=0x0 old dev2 input|output width=0x0 SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram2.00 Enabling dual channel memory Registered 166Mhz RAM end at 0x00100000 kB Lower RAM end at 0x00100000 kB Ram3 Before starting clocks: Before memreset: cpu is pre_c0 after first udelay after second udelay Before controllers loop: ECC enabled Before 2nd controllers loop: Initializing memory: done Before hole: Ram4 v_esp=000cedb8 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Jumping to image. Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check fallback/coreboot_ram Stage: load fallback/coreboot_ram @ 1048576/245760 bytes, enter @ 100000 Stage: done loading. Jumping to image. POST: 0x80 POST: 0x39 coreboot-2.3 Tue Oct 20 16:46:25 MDT 2009 booting... POST: 0x40 Enumerating buses... Show all devs...Before Device Enumeration. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PCI: 00:01.1: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:00.2: enabled 0, 0 resources PCI: 00:01.0: enabled 0, 0 resources PCI: 00:06.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 2 resources PNP: 002e.2: enabled 0, 2 resources PNP: 002e.3: enabled 1, 2 resources PNP: 002e.4: enabled 0, 0 resources PNP: 002e.5: enabled 0, 0 resources PNP: 002e.6: enabled 1, 3 resources PNP: 002e.7: enabled 0, 0 resources PNP: 002e.8: enabled 0, 0 resources PNP: 002e.9: enabled 0, 0 resources PNP: 002e.a: enabled 0, 0 resources PCI: 00:01.1: enabled 1, 0 resources PCI: 00:01.2: enabled 1, 0 resources PCI: 00:01.3: enabled 1, 0 resources I2C: 00:70: enabled 1, 0 resources I2C: 00:2c: enabled 1, 0 resources I2C: 00:50: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources I2C: 00:52: enabled 1, 0 resources I2C: 00:53: enabled 1, 0 resources I2C: 00:54: enabled 1, 0 resources I2C: 00:55: enabled 1, 0 resources I2C: 00:56: enabled 1, 0 resources I2C: 00:57: enabled 1, 0 resources PCI: 00:01.5: enabled 0, 0 resources PCI: 00:01.6: enabled 1, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources PCI: 00:19.0: enabled 1, 0 resources PCI: 00:19.1: enabled 1, 0 resources PCI: 00:19.2: enabled 1, 0 resources PCI: 00:19.3: enabled 1, 0 resources Compare with tree... Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PCI: 00:01.1: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:00.1: enabled 1, 0 resources PCI: 00:00.2: enabled 0, 0 resources PCI: 00:01.0: enabled 0, 0 resources PCI: 00:06.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PNP: 002e.0: enabled 0, 3 resources PNP: 002e.1: enabled 0, 2 resources PNP: 002e.2: enabled 0, 2 resources PNP: 002e.3: enabled 1, 2 resources PNP: 002e.4: enabled 0, 0 resources PNP: 002e.5: enabled 0, 0 resources PNP: 002e.6: enabled 1, 3 resources PNP: 002e.7: enabled 0, 0 resources PNP: 002e.8: enabled 0, 0 resources PNP: 002e.9: enabled 0, 0 resources PNP: 002e.a: enabled 0, 0 resources PCI: 00:01.1: enabled 1, 0 resources PCI: 00:01.2: enabled 1, 0 resources PCI: 00:01.3: enabled 1, 0 resources I2C: 00:70: enabled 1, 0 resources I2C: 00:2c: enabled 1, 0 resources I2C: 00:50: enabled 1, 0 resources I2C: 00:51: enabled 1, 0 resources I2C: 00:52: enabled 1, 0 resources I2C: 00:53: enabled 1, 0 resources I2C: 00:54: enabled 1, 0 resources I2C: 00:55: enabled 1, 0 resources I2C: 00:56: enabled 1, 0 resources I2C: 00:57: enabled 1, 0 resources PCI: 00:01.5: enabled 0, 0 resources PCI: 00:01.6: enabled 1, 0 resources PCI: 00:18.1: enabled 1, 0 resources PCI: 00:18.2: enabled 1, 0 resources PCI: 00:18.3: enabled 1, 0 resources PCI: 00:19.0: enabled 1, 0 resources PCI: 00:19.1: enabled 1, 0 resources PCI: 00:19.2: enabled 1, 0 resources PCI: 00:19.3: enabled 1, 0 resources scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=0 CPU: APIC: 00 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 PCI: 00:18.0 [1022/1100] bus ops PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: 00:18.4, bad id 0xffffffff PCI: 00:18.5, bad id 0xffffffff PCI: 00:18.6, bad id 0xffffffff PCI: 00:18.7, bad id 0xffffffff Disabling static device: PCI: 00:19.0 Disabling static device: PCI: 00:19.1 Disabling static device: PCI: 00:19.2 Disabling static device: PCI: 00:19.3 PCI: 00:19.4, bad id 0xffffffff PCI: 00:19.5, bad id 0xffffffff PCI: 00:19.6, bad id 0xffffffff PCI: 00:19.7, bad id 0xffffffff PCI: 00:1a.0, bad id 0xffffffff PCI: 00:1b.0, bad id 0xffffffff PCI: 00:1c.0, bad id 0xffffffff PCI: 00:1d.0, bad id 0xffffffff PCI: 00:1e.0, bad id 0xffffffff PCI: 00:1f.0, bad id 0xffffffff POST: 0x25
Below is the output with the no_smp patch and the previous patch. Is there another problem since the payload is not being loaded?
There's definitely some problem. It hangs before the devices are enumerated :(
coreboot-2.3 Tue Oct 20 16:46:25 MDT 2009 starting... Enabling routing table for node 00 done. Enabling UP settings Disabling read/write/fill probes for UP... done. Ram2.00 Enabling dual channel memory coreboot-2.3 Tue Oct 20 16:46:25 MDT 2009 booting... POST: 0x40 Enumerating buses... Show all devs...Before Device Enumeration. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:18.0: enabled 1, 0 resources
...
PCI: 00:1e.0, bad id 0xffffffff PCI: 00:1f.0, bad id 0xffffffff POST: 0x25
This is another strange place to hang. I don't understand why it would hang here. It's probably time to put a few print statements around there and see if we can get it to go a little farther.
Have you tried it with the init call, but not the timeout? It would be nice if we could say that bug was squashed and we could move on. If init wasn't the problem, we should probably figure out why you can't get to the lapic before we move on.
Thanks, Myles
Do you to mean apply your last patch without the
do { ... timeout++;} while(((start - value) < ticks) && (timeout < 1000000));
in apic_timer.c ?
-
Hugh Greenberg -
Marc Jones -
Myles Watson