Author: libv Date: 2009-07-23 18:04:58 +0200 (Thu, 23 Jul 2009) New Revision: 4465
Added: trunk/coreboot-v2/src/southbridge/via/k8t890/k8m890_chrome.c Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout trunk/coreboot-v2/src/southbridge/via/k8t890/Config.lb trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890.h trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_dram.c Log: sb/via/k8t890: add vga textmode code for k8m890 chrome igp.
Add initialisation for the VIA Chrome 9 IGP on the k8m890 through native code and through the general vga infrastructure i committed a month or two ago. Add videoram_size option for k8m890 and the Asus M2V-MX SE.
Now the Asus M2V-MX SE will magically come up with a working standard VGA 80x25 textmode.
Many thanks to the people who worked hard on the Asus M2V-MX SE, and all of its components; this vga bringup was a breeze thanks to your hard work for this excellently supported board. And separate thanks to Rudolf Marek for spurring me on and for providing a register dump.
Signed-off-by: Luc Verhaegen libv@skynet.be Acked-by: Peter Stuge peter@stuge.se
Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2009-07-23 08:10:51 UTC (rev 4464) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2009-07-23 16:04:58 UTC (rev 4465) @@ -44,7 +44,7 @@ uses CONFIG_XIP_ROM_BASE uses CONFIG_STACK_SIZE uses CONFIG_HEAP_SIZE -# uses CONFIG_USE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_LB_MEM_TOPK uses CONFIG_HAVE_ACPI_TABLES uses CONFIG_HAVE_MAINBOARD_RESOURCES @@ -74,6 +74,7 @@ uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB +uses CONFIG_VGA uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN # bx_b001- uses K8_HW_MEM_HOLE_SIZEK @@ -101,7 +102,7 @@ default CONFIG_HAVE_PIRQ_TABLE = 0 default CONFIG_IRQ_SLOT_COUNT = 11 # FIXME? default CONFIG_HAVE_MP_TABLE = 0 -default CONFIG_HAVE_OPTION_TABLE = 0 # FIXME +default CONFIG_HAVE_OPTION_TABLE = 1 # FIXME # Move the default coreboot CMOS range off of AMD RTC registers. default CONFIG_LB_CKS_RANGE_START = 49 default CONFIG_LB_CKS_RANGE_END = 122 @@ -136,6 +137,7 @@ # Only offset for SB chain?, default is yes(1). default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
+default CONFIG_VGA = 1 default CONFIG_CONSOLE_VGA = 1 # Needed for VGA. default CONFIG_PCI_ROM_RUN = 0 # Needed for VGA. default CONFIG_USE_DCACHE_RAM = 1 @@ -157,6 +159,7 @@ default CONFIG_LB_MEM_TOPK = 32768 # to 1MB default CONFIG_RAMBASE = 0x1F00000 +default CONFIG_USE_OPTION_TABLE = 0 # default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE default CONFIG_ROM_PAYLOAD = 1 default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout =================================================================== --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout 2009-07-23 08:10:51 UTC (rev 4464) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout 2009-07-23 16:04:58 UTC (rev 4465) @@ -43,6 +43,7 @@ 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu +448 3 e 10 videoram_size 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -90,6 +91,13 @@ 9 5 37.5% 9 6 25.0% 9 7 12.5% +# videoram_size: mimics the bits in the ramcontroller. +10 1 8MB +10 2 16MB +10 3 32MB +10 4 64MB +10 5 128MB +10 6 256MB
checksums
Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/Config.lb =================================================================== --- trunk/coreboot-v2/src/southbridge/via/k8t890/Config.lb 2009-07-23 08:10:51 UTC (rev 4464) +++ trunk/coreboot-v2/src/southbridge/via/k8t890/Config.lb 2009-07-23 16:04:58 UTC (rev 4465) @@ -25,3 +25,4 @@ driver k8t890_pcie.o driver k8t890_traf_ctrl.o driver k8t890_error.o +driver k8m890_chrome.o
Added: trunk/coreboot-v2/src/southbridge/via/k8t890/k8m890_chrome.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/k8t890/k8m890_chrome.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/via/k8t890/k8m890_chrome.c 2009-07-23 16:04:58 UTC (rev 4465) @@ -0,0 +1,179 @@ +/* + * Copyright (C) 2007-2009 Luc Verhaegen libv@skynet.be + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., 51 + * Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> /* for memset */ +#include "k8t890.h" + +#if CONFIG_VGA == 1 +#include <pc80/vga_io.h> +#include <pc80/vga.h> +#include <arch/io.h> + +/* + * + */ +static void +chrome_vga_init(struct device *dev) +{ + vga_sr_write(0x10, 0x01); /* unlock extended regs */ + + vga_sr_mask(0x1A, 0x02, 0x02); /* enable mmio */ + + vga_sr_mask(0x1A, 0x40, 0x40); /* Software Reset */ + + vga_cr_mask(0x6A, 0x00, 0xC8); /* Disable CRTC2 & Simultaneous */ + + /* Make sure that non of the primary VGA overflow registers are set */ + vga_cr_write(0x33, 0x00); + vga_cr_write(0x35, 0x00); + vga_cr_mask(0x11, 0x00, 0x30); + + vga_sr_mask(0x16, 0x00, 0x40); /* Wire CRT to CRTC1 */ + vga_cr_mask(0x36, 0x00, 0x30); /* Power on CRT */ + + /* Disable Extended Display Mode */ + vga_sr_mask(0x15, 0x00, 0x02); + + /* Disable Wrap-around */ + vga_sr_mask(0x15, 0x00, 0x20); + + /* Disable Extended Mode memory access */ + vga_sr_mask(0x1A, 0x00, 0x08); + + /* Make sure that we only touch CRTC1s DAC */ + vga_sr_mask(0x1A, 0x00, 0x01); + + /* Set up power to the clocks/crtcs */ + vga_sr_mask(0x19, 0x7F, 0x7F); /* enable clock gating for all. */ + vga_sr_mask(0x1B, 0xC0, 0xC0); /* secondary clock according to pm */ + vga_sr_mask(0x1B, 0x20, 0x30); /* primary clock is always on */ + + /* set everything according to PM/Engine idle state except pci dma */ + vga_sr_write(0x2D, 0xFF); /* Power management control 1 */ + vga_sr_write(0x2E, 0xFB); /* Power management control 2 */ + vga_sr_write(0x3F, 0xFF); /* Power management control 3 */ + + /* now set up the engine clock. */ + vga_sr_write(0x47, 0xB8); + vga_sr_write(0x48, 0x08); + vga_sr_write(0x49, 0x03); + + /* trigger engine clock setting */ + vga_sr_mask(0x40, 0x01, 0x01); + vga_sr_mask(0x40, 0, 0x01); + + vga_cr_mask(0x30, 0x04, 0x04); /* Enable PowerNow in primary path */ + vga_cr_mask(0x36, 0x01, 0x01); /* Enable PCI Power Management */ + + /* Power now indicators... */ + vga_cr_write(0x41, 0xB9); + vga_cr_write(0x42, 0xB4); + /* could these be the CRTC2 power now indicators? */ + vga_cr_write(0x9D, 0x80); /* Power Now Ending position enable */ + vga_cr_write(0x9E, 0xB4); /* Power Now Control 3 */ + + /* primary fifo setting */ + vga_sr_mask(0x16, 0x28, 0xBF); /* pthreshold: 160 */ + vga_sr_write(0x17, 0x60); /* max depth: 194 */ + vga_sr_mask(0x18, 0x0E, 0xBF); /* high priority threshold: 56 */ + vga_sr_write(0x1C, 0x54); /* Fetch count */ + + vga_sr_write(0x20, 0x40); /* display queue typical arbiter control 0 */ + vga_sr_write(0x21, 0x40); /* display queue typical arbiter control 1 */ + vga_sr_mask(0x22, 0x14, 0x1F); /* display queue expire number */ + + /* Typical Arbiter Control */ + vga_sr_mask(0x41, 0x40, 0xF0); /* Request threshold */ + vga_sr_mask(0x42, 0x20, 0x20); /* Support Fetch Cycle with Length 2 */ + + vga_sr_write(0x50, 0x1F); /* AGP Control Register */ + vga_sr_write(0x51, 0xF5); /* AGP FIFO Control 1 */ + + vga_cr_mask(0x33, 0x08, 0x08); /* Enable Prefetch Mode */ +} + +#endif /* CONFIG_VGA */ + +/* + * + */ +static void +chrome_init(struct device *dev) +{ + uint32_t fb_size, fb_address; + + fb_size = k8m890_host_fb_size_get(); + if (!fb_size) { + printk_warning("Chrome: Device has not been initialised in the" + " ramcontroller!\n"); + return; + } + + fb_address = pci_read_config32(dev, 0x10); + fb_address &= ~0x0F; + if (!fb_address) { + printk_warning("Chrome: No FB BAR assigned!\n"); + return; + } + + printk_info("Chrome: Using %dMB Framebuffer at 0x%08X.\n", + fb_size, fb_address); + + //k8m890_host_fb_direct_set(fb_address); + +#if CONFIG_VGA == 1 + /* Now set up the VGA console */ + vga_io_init(); /* Enable full IO access */ + + chrome_vga_init(dev); + + vga_textmode_init(); + +#if CONFIG_CONSOLE_VGA == 1 + vga_console_init(); +#endif + + printk_info("Chrome VGA Textmode initialized.\n"); + +#if CONFIG_CONSOLE_VGA == 0 + /* if we don't have console, at least print something... */ + vga_line_write(0, "Chrome VGA Textmode initialized."); +#endif + +#endif /* CONFIG_VGA */ +} + +static struct device_operations +chrome_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = chrome_init, + .scan_bus = 0, + .enable = 0, +}; + +static const struct pci_driver unichrome_driver __pci_driver = { + .ops = &chrome_ops, + .vendor = 0x1106, + .device = 0x3230, +};
Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890.h =================================================================== --- trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890.h 2009-07-23 08:10:51 UTC (rev 4464) +++ trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890.h 2009-07-23 16:04:58 UTC (rev 4465) @@ -43,4 +43,7 @@ extern void writeback(struct device *dev, u16 where, u8 what); extern void dump_south(device_t dev);
+int k8m890_host_fb_size_get(void); +//void k8m890_host_fb_direct_set(uint32_t fb_address); + #endif
Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_dram.c =================================================================== --- trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_dram.c 2009-07-23 08:10:51 UTC (rev 4464) +++ trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_dram.c 2009-07-23 16:04:58 UTC (rev 4465) @@ -23,6 +23,7 @@ #include <console/console.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> +#include <pc80/mc146818rtc.h> #include <bitops.h> #include "k8t890.h"
@@ -104,19 +105,53 @@ #endif }
+/* + * + */ +int +k8m890_host_fb_size_get(void) +{ + struct device *dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M890CE_3, 0); + unsigned char tmp;
+ tmp = pci_read_config8(dev, 0xA1); + tmp >>= 4; + if (tmp & 0x08) + return 4 << (tmp & 7); + else + return 0; +} + static void dram_init_fb(struct device *dev) { /* Important bits: * Enable the internal GFX bit 7 of reg 0xa1 plus in same reg: - * bits 6:4 X fbuffer size will be 2^(X+2) or 100 = 64MB, 101 = 128MB + * bits 6:4 X fbuffer size will be 2^(X+2) or 100 = 64MB, 101 = 128MB * bits 3:0 BASE [31:28] * reg 0xa0 bits 7:1 BASE [27:21] bit0 enable CPU access */ u8 tmp; uint64_t proposed_base; - unsigned int fbsize = (K8M890_FBSIZEMB * 1024 * 1024); + unsigned int fbbits = 0; + unsigned int fbsize; + int ret;
+ + ret = get_option(&fbbits, "videoram_size"); + if (ret) { + printk_warning("Failed to get videoram size (error %d), using default.\n", ret); + fbbits = 5; + } + + if ((fbbits < 1) || (fbbits > 7)) { + printk_warning("Invalid videoram size (%d), using default.\n", + 4 << fbbits); + fbbits = 5; + } + + fbsize = 4 << (fbbits + 20); + resmax = NULL; search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, @@ -131,13 +166,13 @@ proposed_base = resmax->base + resmax->size - fbsize; resmax->size -= fbsize;
- printk_debug("VIA FB proposed base: %llx\n", proposed_base); + printk_info("K8M890: Using a %dMB framebuffer.\n", 4 << fbbits);
/* Step 1: enable UMA but no FB */ pci_write_config8(dev, 0xa1, 0x80);
/* Step 2: enough is just the FB size, the CPU accessible address is not needed */ - tmp = ((log2(K8M890_FBSIZEMB) - 2) << 4) | 0x80; + tmp = (fbbits << 4) | 0x80; pci_write_config8(dev, 0xa1, tmp);
/* TODO K8 needs some UMA fine tuning too maybe call some generic routine here? */
-
svn＠coreboot.org