r569 - in coreboot-v3: mainboard/adl/msm800sev mainboard/amd/norwich mainboard/artecgroup/dbe61 mainboard/emulation/qemu-x86 mainboard/pcengines/alix1c northbridge/intel/i440bxemulation superio/winbond/w83627hf

Author: rminnich
Date: 2008-01-31 04:08:32 +0100 (Thu, 31 Jan 2008)
New Revision: 569

Modified:
   coreboot-v3/mainboard/adl/msm800sev/dts
   coreboot-v3/mainboard/amd/norwich/dts
   coreboot-v3/mainboard/artecgroup/dbe61/dts
   coreboot-v3/mainboard/emulation/qemu-x86/dts
   coreboot-v3/mainboard/pcengines/alix1c/dts
   coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c
   coreboot-v3/superio/winbond/w83627hf/superio.c
Log:
Fix compilation after switch to explicit dts naming.
One additional cosmetic fix.

Signed-off-by: Carl-Daniel Hailfinger 
Acked-by: Ronald G. Minnich

Modified: coreboot-v3/mainboard/adl/msm800sev/dts
===================================================================
--- coreboot-v3/mainboard/adl/msm800sev/dts	2008-01-30 00:48:41 UTC (rev 568)
+++ coreboot-v3/mainboard/adl/msm800sev/dts	2008-01-31 03:08:32 UTC (rev 569)
@@ -34,12 +34,12 @@
    		pcipath = "1,0";
    	};
    	southbridge {
-			/config/("southbridge/amd/cs5536");
+			/config/("southbridge/amd/cs5536/dts");
    		pcipath = "1,1";
    		enabled;
    	};
    	superio {
-			/config/("superio/winbond/w83627hf");
+			/config/("superio/winbond/w83627hf/dts");
    		com1enable = "1";
    	};
    };

Modified: coreboot-v3/mainboard/amd/norwich/dts
===================================================================
--- coreboot-v3/mainboard/amd/norwich/dts	2008-01-30 00:48:41 UTC (rev 568)
+++ coreboot-v3/mainboard/amd/norwich/dts	2008-01-31 03:08:32 UTC (rev 569)
@@ -33,7 +33,7 @@
    		pcipath = "1,0";
    	};
    	southbridge {
-			/config/("southbridge/amd/cs5536");
+			/config/("southbridge/amd/cs5536/dts");
    		pcipath = "1,1";
    		enabled;
    	};

Modified: coreboot-v3/mainboard/artecgroup/dbe61/dts
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe61/dts	2008-01-30 00:48:41 UTC (rev 568)
+++ coreboot-v3/mainboard/artecgroup/dbe61/dts	2008-01-31 03:08:32 UTC (rev 569)
@@ -87,7 +87,7 @@
    		pcipath = "1,0";
    	};
    	southbridge {
-			/config/("southbridge/amd/cs5536");
+			/config/("southbridge/amd/cs5536/dts");
    		pcipath = "1,1";
    		enabled;
    	};

Modified: coreboot-v3/mainboard/emulation/qemu-x86/dts
===================================================================
--- coreboot-v3/mainboard/emulation/qemu-x86/dts	2008-01-30 00:48:41 UTC (rev 568)
+++ coreboot-v3/mainboard/emulation/qemu-x86/dts	2008-01-31 03:08:32 UTC (rev 569)
@@ -27,7 +27,7 @@
    	enabled;
    };
    domain0 {
-		/config/("northbridge/intel/i440bxemulation");
+		/config/("northbridge/intel/i440bxemulation/dts");
    	ops = "i440bxemulation_pcidomainops";
    	enabled;
    	pcidomain = "0";
@@ -36,7 +36,7 @@
    		pcipath = "0,0";
    	};
    	southbridge,intel,i82371eb {
-			/config/("southbridge/intel/i82371eb");
+			/config/("southbridge/intel/i82371eb/dts");
    		pcipath = "1,0";
    		enabled;
    	};

Modified: coreboot-v3/mainboard/pcengines/alix1c/dts
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/dts	2008-01-30 00:48:41 UTC (rev 568)
+++ coreboot-v3/mainboard/pcengines/alix1c/dts	2008-01-31 03:08:32 UTC (rev 569)
@@ -26,7 +26,7 @@
    	enabled;
    };
    domain0 {
-		/config/("northbridge/amd/geodelx");
+		/config/("northbridge/amd/geodelx/dts");
    	enabled;
    	pcidomain = "0";
    	device0,0 {
@@ -34,12 +34,12 @@
    		pcipath = "1,0";
    	};
    	southbridge {
-			/config/("southbridge/amd/cs5536");
+			/config/("southbridge/amd/cs5536/dts");
    		pcipath = "0xf,1";
    		enabled;
    	};
    	superio {
-			/config/("superio/winbond/w83627hf");
+			/config/("superio/winbond/w83627hf/dts");
    		com1enable = "1";
    	};
    };

Modified: coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c
===================================================================
--- coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c	2008-01-30 00:48:41 UTC (rev 568)
+++ coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c	2008-01-31 03:08:32 UTC (rev 569)
@@ -53,7 +53,7 @@
    struct device *mc_dev;
    u32 tolmk;		/* Top of low mem, Kbytes. */
    int idx;
-	struct northbridge_intel_i440bxemulation_config *device_configuration =
+	struct northbridge_intel_i440bxemulation_dts_config *device_configuration =
        dev->device_configuration;
    tolmk = device_configuration->ramsize * 1024;
    mc_dev = dev->link[0].children;

Modified: coreboot-v3/superio/winbond/w83627hf/superio.c
===================================================================
--- coreboot-v3/superio/winbond/w83627hf/superio.c	2008-01-30 00:48:41 UTC (rev 568)
+++ coreboot-v3/superio/winbond/w83627hf/superio.c	2008-01-31 03:08:32 UTC (rev 569)
@@ -115,7 +115,7 @@

static void w83627hf_init(struct device * dev)
 {
-	struct superio_winbond_w83627hf_config *conf;
+	struct superio_winbond_w83627hf_dts_config *conf;
    struct resource *res0, *res1;
    struct pc_keyboard keyboard;