Thank you, your prompt reply. It is very useful to me.
I'll study the document of FSP. and tools.
2016-06-02 오전 5:23에 Martin Roth 이(가) 쓴 글:
- The MRC cache is a location for saving the state of the memory
registers. These values are typically used to restore the memory controller state on resume from S3 suspend, or to help the system boot faster. On systems using the Rangeley FSP it is not optional as it is on some other platforms.
- The file you see in cbfs is actually just a placeholder. If you
look in that area of the rom, you'll see that it's empty. It's just there to reserve the space for coreboot to write the memory register information into, and to prevent anything else from being put into that location.
- The memory code for Rangeley is part of the FSP. This is currently
only available for the Rangeley chip as a binary blob. You can download it, along with the FSP documentation and the Binary Configuration Tool, from Intel's website: http://intel.com/fsp
On Tue, May 31, 2016 at 10:38 PM, 김유석 책임연구원 email@example.com wrote:
Platform : intel atom rangeley mohon peak CRB(C2358)
This time, I'm try to study for MRC(Memory Reference Code).
But, I'm can not found a some example code on coreboot source tree.(rangely)
Anyway, I'm get a some hint on last image.
Performing operation on 'COREBOOT' region... Name Offset Type Size cbfs master header 0x0 cbfs header 32 fallback/romstage 0x80 stage 24356 config 0x6040 raw 440 revision 0x6240 raw 567 cmos_layout.bin 0x64c0 cmos_layout 1316 fallback/dsdt.aml 0x6a40 raw 8074 payload_config 0x8a40 raw 1574 payload_revision 0x90c0 raw 244 (empty) 0x9200 null 27800 mrc.cache 0xfec0 mrc_cache 65536 cpu_microcode_blob.bin 0x1ff00 microcode 167936 fallback/ramstage 0x48f80 stage 48170 fallback/payload 0x54c00 payload 61309 (empty) 0x63bc0 null 1163992 fsp.bin 0x17fec0 fsp 389120 (empty) 0x1def00 null 133528 bootblock 0x1ff8c0 bootblock 1528
What purpose the "mrc.cache"?
Where to location the source code for "mrc.cache" ?
How modify the MRC ? for the sdram.
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