[v2] r4364 - in trunk/coreboot-v2/src: mainboard/gigabyte/m57sli southbridge/nvidia/mcp55

Author: hargut
Date: 2009-06-19 14:03:40 +0200 (Fri, 19 Jun 2009)
New Revision: 4364

Added:
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/acpi_tables.c
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/dsdt.asl
   trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_fadt.c
Modified:
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb
   trunk/coreboot-v2/src/southbridge/nvidia/mcp55/Config.lb
   trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c
Log:
ChangeLog:
Add initial ACPI support for M57SLI.
    Activates/Enables:
    	* native Coreboot ACPI for M57SLI
    	* Soft-Power-Off
    	* PowerNow!
    	* High Precision Event Timer
    	* Windows booting with ACPI support

Signed-off-by: Harald Gutmann 
Acked-by: Myles Watson 
Acked-by: Peter Stuge

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb	2009-06-18 16:38:35 UTC (rev 4363)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb	2009-06-19 12:03:40 UTC (rev 4364)
@@ -164,6 +164,19 @@
    end

##
+## ACPI Support
+##
+if HAVE_ACPI_TABLES
+	object acpi_tables.o
+	makerule dsdt.c
+		depends "$(MAINBOARD)/dsdt.asl"
+		action  "iasl -p $(PWD)/dsdt -tc $(MAINBOARD)/dsdt.asl"
+		action  "mv dsdt.hex dsdt.c"
+	end
+	object ./dsdt.o
+end
+
+##
 ## Include the secondary Configuration files 
 ##
 config chip.h

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb	2009-06-18 16:38:35 UTC (rev 4363)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Options.lb	2009-06-19 12:03:40 UTC (rev 4364)
@@ -175,7 +175,7 @@
 default HAVE_HIGH_TABLES=1

## ACPI tables will be included
-default HAVE_ACPI_TABLES=0
+default HAVE_ACPI_TABLES=1

##
 ## Build code to export a CMOS option table

Added: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/acpi_tables.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/acpi_tables.c	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/acpi_tables.c	2009-06-19 12:03:40 UTC (rev 4364)
@@ -0,0 +1,203 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Written by Stefan Reinauer .
+ * ACPI FADT, FACS, and DSDT table support added by 
+ *
+ * Copyright (C) 2004 Stefan Reinauer 
+ * Copyright (C) 2005 Nick Barker 
+ * Copyright (C) 2007, 2008 Rudolf Marek 
+ * Copyright (C) 2009 Harald Gutmann 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include <../../../northbridge/amd/amdk8/amdk8_acpi.h>
+#include <cpu/amd/model_fxx_powernow.h>
+#include <device/pci.h>
+#include <cpu/amd/amdk8_sysconf.h>
+
+extern unsigned char AmlCode[];
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	/* Not implemented */
+	return current;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	unsigned int gsi_base = 0x18;
+	extern unsigned char bus_mcp55[8];
+	extern unsigned apicid_mcp55;
+	extern void get_bus_conf(void);
+	unsigned sbdn;
+	struct resource *res;
+	device_t dev;
+
+	get_bus_conf();
+	sbdn = sysconf.sbdn;
+	
+	/* Create all subtables for processors. */
+	current = acpi_create_madt_lapics(current);
+
+	/* Write SB IOAPIC. */
+	dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
+	if (dev) {
+		res = find_resource(dev, PCI_BASE_ADDRESS_1);
+		if (res) {
+			current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				apicid_mcp55, res->base,  0);
+		}
+	}
+
+	/* Write NB IOAPIC. */
+	dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x12,1));
+	if (dev) {
+		res = find_resource(dev, PCI_BASE_ADDRESS_1);
+		if (res) {
+			current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				apicid_mcp55++, res->base,  gsi_base);
+		}
+	}
+
+	/* IRQ9 ACPI active low. */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW);
+
+	/* IRQ0 -> APIC IRQ2. */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		current, 0, 0, 2, 0x0);	
+
+	/* Create all subtables for processors. */
+	current = acpi_create_madt_lapic_nmis(current,
+		MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1);
+
+	return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id) 
+{
+	k8acpi_write_vars();
+	amd_model_fxx_generate_powernow(0, 0, 0);
+	return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	acpi_rsdp_t *rsdp;
+	acpi_srat_t *srat;
+	acpi_rsdt_t *rsdt;
+	acpi_mcfg_t *mcfg;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+	acpi_slit_t *slit;
+	acpi_header_t *ssdt;
+	acpi_header_t *dsdt;
+
+	/* Align ACPI tables to 16 byte. */
+	start = (start + 0x0f) & -0x10;
+	current = start;
+
+	printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+
+	/* We need at least an RSDP and an RSDT table. */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+
+	/* Clear all table memory. */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt);
+	acpi_write_rsdt(rsdt);
+
+	/* We explicitly add these tables later on: */
+	printk_debug("ACPI:     * FACS\n");
+
+	/* we should align FACS to 64B as per ACPI specs */
+	current = ALIGN(current, 64);
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	acpi_create_facs(facs);
+
+	dsdt = (acpi_header_t *) current;
+	current += ((acpi_header_t *) AmlCode)->length;
+	memcpy((void *) dsdt, (void *) AmlCode,
+	       ((acpi_header_t *) AmlCode)->length);
+	dsdt->checksum = 0;	/* Don't trust iasl to get this right. */
+	dsdt->checksum = acpi_checksum(dsdt, dsdt->length);
+	printk_debug("ACPI:     * DSDT @ %08x Length %x\n", dsdt,
+		     dsdt->length);
+	printk_debug("ACPI:     * FADT\n");
+
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdt, fadt);
+
+	printk_debug("ACPI:    * HPET\n");
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	acpi_create_hpet(hpet);
+	acpi_add_table(rsdt, hpet);
+
+	/* If we want to use HPET timers Linux wants an MADT. */
+	printk_debug("ACPI:    * MADT\n");
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	acpi_add_table(rsdt, madt);
+
+	printk_debug("ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	acpi_add_table(rsdt, mcfg);
+
+	printk_debug("ACPI:    * SRAT\n");
+	srat = (acpi_srat_t *) current;
+	acpi_create_srat(srat);
+	current += srat->header.length;
+	acpi_add_table(rsdt, srat);
+
+	/* SLIT */
+	printk_debug("ACPI:    * SLIT\n");
+	slit = (acpi_slit_t *) current;
+	acpi_create_slit(slit);
+	current+=slit->header.length;
+	acpi_add_table(rsdt,slit);
+
+	/* SSDT */
+	printk_debug("ACPI:    * SSDT\n");
+	ssdt = (acpi_header_t *)current;
+
+	acpi_create_ssdt_generator(ssdt, "DYNADATA");
+	current += ssdt->length;
+	acpi_add_table(rsdt, ssdt);
+
+	printk_info("ACPI: done.\n");
+	return current;
+}

Added: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/dsdt.asl
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/dsdt.asl	                        (rev 0)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/dsdt.asl	2009-06-19 12:03:40 UTC (rev 4364)
@@ -0,0 +1,266 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * (C) Copyright 2004 Nick Barker 
+ * (C) Copyright 2007, 2008 Rudolf Marek 
+ * (C) Copyright 2009 Harald Gutmann 
+ *
+ * ISA portions taken from QEMU acpi-dsdt.dsl.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "LXBIOS", "LXB-DSDT", 1)
+{
+	Include ("../../../../src/northbridge/amd/amdk8/amdk8_util.asl")
+
+	/* For now only define 2 power states:
+	 *  - S0 which is fully on
+	 *  - S5 which is soft off
+	 */
+	Name (_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+	Name (_S5, Package () { 0x07, 0x00, 0x00, 0x00 })
+
+	/* Root of the bus hierarchy */
+	Scope (_SB)
+	{
+		/* Top PCI device */
+		Device (PCI0)
+		{
+			Name (_HID, EisaId ("PNP0A03"))
+			Name (_ADR, 0x00)
+			Name (_UID, 0x00)
+			Name (_BBN, 0x00)
+
+			External (BUSN)
+			External (MMIO)
+			External (PCIO)
+			External (SBLK)
+			External (TOM1)
+			External (HCLK)
+			External (SBDN)
+			External (HCDN)
+                    
+			Method (_CRS, 0, NotSerialized)
+                        {
+				Name (BUF0, ResourceTemplate ()
+				{
+					IO (Decode16,
+					0x0CF8,             // Address Range Minimum
+					0x0CF8,             // Address Range Maximum
+					0x01,               // Address Alignment
+					0x08,               // Address Length
+					)
+					WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+					0x0000,             // Address Space Granularity
+					0x0000,             // Address Range Minimum
+					0x0CF7,             // Address Range Maximum
+					0x0000,             // Address Translation Offset
+					0x0CF8,             // Address Length
+					,, , TypeStatic)
+				})
+				/* Methods bellow use SSDT to get actual MMIO regs
+				   The IO ports are from 0xd00, optionally an VGA,
+				   otherwise the info from MMIO is used.
+				 */
+				Concatenate (_SB.GMEM (0x00, _SB.PCI0.SBLK), BUF0, Local1)
+				Concatenate (_SB.GIOR (0x00, _SB.PCI0.SBLK), Local1, Local2)
+				Concatenate (_SB.GWBN (0x00, _SB.PCI0.SBLK), Local2, Local3)
+				Return (Local3)
+			}
+
+			/* PCI Routing Table */
+			Name (_PRT, Package () {
+				Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x0A }, /* 0x1 - 00:01.1 - IRQ 10 - SMBus */
+				Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x16 }, /* 0x2 - 00:02.0 - IRQ 22 - USB */
+				Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x17 }, /* 0x2 - 00:01.1 - IRQ 23 - USB */
+				Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x15 }, /* 0x4 - 00:04.0 - IRQ 21 - IDE */
+				Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x14 }, /* 0x5 - 00:05.0 - IRQ 20 - SATA */
+				Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x15 }, /* 0x5 - 00:05.1 - IRQ 21 - SATA */
+				Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x16 }, /* 0x5 - 00:05.2 - IRQ 22 - SATA */
+				Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x17 }, /* 0x6 - 00:06.1 - IRQ 23 - HD Audio */
+				Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x14 }, /* 0x8 - 00:08.0 - IRQ 20 - GBit Ethernet */
+			})
+
+			Device (PEBF) /* PCI-E Bridge F */
+			{
+				Name (_ADR, 0x000F0000)
+				Name (_UID, 0x00)
+				Name (_BBN, 0x07)
+				Name (_PRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 },
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
+				})
+			}
+
+			Device (PEBE) /* PCI-E Bridge E */
+			{
+				Name (_ADR, 0x000E0000)
+				Name (_UID, 0x00)
+				Name (_BBN, 0x06)
+				Name (_PRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 },
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
+				})
+			}
+
+			Device (PEBD) /* PCI-E Bridge D */
+			{
+				Name (_ADR, 0x000D0000)
+				Name (_UID, 0x00)
+				Name (_BBN, 0x05)
+				Name (_PRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x13 },
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x10 },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x11 },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x12 },
+				})
+			}
+
+			Device (PEBC) /* PCI-E Bridge C */
+			{
+				Name (_ADR, 0x000C0000)
+				Name (_UID, 0x00)
+				Name (_BBN, 0x04)
+				Name (_PRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
+				})
+			}
+
+			Device (PEBB) /* PCI-E Bridge B */
+			{
+				Name (_ADR, 0x000B0000)
+				Name (_UID, 0x00)
+				Name (_BBN, 0x03)
+				Name (_PRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x11 },
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x12 },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x13 },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
+				})
+			}
+
+			Device (PEBA) /* PCI-E Bridge A */
+			{
+				Name (_ADR, 0x000A0000)
+				Name (_UID, 0x00)
+				Name (_BBN, 0x02)
+				Name (_PRT, Package () {
+					Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x12 },
+					Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
+					Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x10 },
+					Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x11 },
+				})
+			}
+
+			Device (PCID)	/* PCI Device */
+			{
+				Name (_ADR, 0x00060000)
+				Name (_UID, 0x00)
+				Name (_BBN, 0x01)
+				Name (_PRT, Package () {
+					Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x12 },
+					Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x13 },
+					Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x10 },
+					Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x11 },
+					Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x13 }, /* PCI slot 1 */
+					Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x10 },
+					Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x11 },
+					Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x12 },
+					Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x10 }, /* PCI slot 2 */
+					Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x11 },
+					Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x12 },
+					Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x13 },
+					Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x11 },
+					Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x12 },
+					Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x13 },
+					Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x10 },
+					Package (0x04) { 0x000AFFFF, 0x00, 0x00, 0x12 }, /* FireWire */
+					Package (0x04) { 0x000AFFFF, 0x01, 0x00, 0x13 },
+					Package (0x04) { 0x000AFFFF, 0x02, 0x00, 0x10 },
+					Package (0x04) { 0x000AFFFF, 0x03, 0x00, 0x11 },
+				})
+			}
+		}
+
+		Device (ISA) {
+			Name (_ADR, 0x000010000)
+
+			/* PS/2 keyboard (seems to be important for WinXP install) */
+			Device (KBD)
+			{
+				Name (_HID, EisaId ("PNP0303"))
+				Method (_STA, 0, NotSerialized)
+				{
+					Return (0x0f)
+				}
+				Method (_CRS, 0, NotSerialized)
+				{
+					Name (TMP, ResourceTemplate () {
+						IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+						IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+						IRQNoFlags () {1}
+					})
+					Return (TMP)
+				}
+			}
+
+			/* PS/2 mouse */
+			Device (MOU)
+			{
+				Name (_HID, EisaId ("PNP0F13"))
+				Method (_STA, 0, NotSerialized)
+				{
+					Return (0x0f)
+				}
+				Method (_CRS, 0, NotSerialized)
+				{
+					Name (TMP, ResourceTemplate () {
+						IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+						IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+						IRQNoFlags () {12}
+					})
+					Return (TMP)
+				}
+			}
+
+			/* PS/2 floppy controller */
+			Device (FDC0)
+			{
+				Name (_HID, EisaId ("PNP0700"))
+				Method (_STA, 0, NotSerialized)
+				{
+					Return (0x0f)
+				}
+				Method (_CRS, 0, NotSerialized)
+				{
+					Name (BUF0, ResourceTemplate () {
+						IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)
+						IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
+						IRQNoFlags () {6}
+						DMA (Compatibility, NotBusMaster, Transfer8) {2}
+					})
+					Return (BUF0)
+				}
+			}
+		}
+	}
+}

Modified: trunk/coreboot-v2/src/southbridge/nvidia/mcp55/Config.lb
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/mcp55/Config.lb	2009-06-18 16:38:35 UTC (rev 4363)
+++ trunk/coreboot-v2/src/southbridge/nvidia/mcp55/Config.lb	2009-06-19 12:03:40 UTC (rev 4364)
@@ -19,6 +19,8 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##

+uses HAVE_ACPI_TABLES
+
 config chip.h
 driver mcp55.o
 driver mcp55_usb.o
@@ -33,3 +35,6 @@
 driver mcp55_pcie.o
 driver mcp55_ht.o
 object mcp55_reset.o
+if HAVE_ACPI_TABLES
+	object mcp55_fadt.o
+end

Added: trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_fadt.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_fadt.c	                        (rev 0)
+++ trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_fadt.c	2009-06-19 12:03:40 UTC (rev 4364)
@@ -0,0 +1,173 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Nick Barker 
+ * Copyright (C) 2007 Rudolf Marek 
+ * Copyright (C) 2009 Harald Gutmann 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+
+extern unsigned pm_base;
+
+/* Create the Fixed ACPI Description Tables (FADT) for this board. */
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+	device_t dev;
+	int is_mcp55 = 0;	
+	dev = dev_find_device(PCI_VENDOR_ID_NVIDIA,
+		PCI_DEVICE_ID_NVIDIA_MCP55_LPC, 0);
+	if (dev)
+		is_mcp55 = 1;
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 1;
+	memcpy(header->oem_id, "GBT", 6);
+	memcpy(header->oem_table_id, "COREBOOT ", 8);
+	memcpy(header->asl_compiler_id, "CORE", 4);
+	header->asl_compiler_revision = 42;
+
+	printk_info("ACPI: pm_base: %u...\n", pm_base);
+
+	fadt->firmware_ctrl = facs;
+	fadt->dsdt = dsdt;
+	fadt->preferred_pm_profile = 1; //check
+	fadt->sci_int = 9;
+	/* disable system management mode by setting to 0 */
+	fadt->smi_cmd = 0x0; //pm_base+0x42e; (value from proprietary acpi fadt) 
+	fadt->acpi_enable = 0xa1;
+	fadt->acpi_disable = 0xa0;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0x0;
+
+	fadt->pm1a_evt_blk = pm_base;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pm_base + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pm_base + 0x1c;
+	fadt->pm_tmr_blk = pm_base + 0x8;
+	fadt->gpe0_blk = pm_base + 0x20;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	if (is_mcp55) {
+		fadt->gpe1_blk = pm_base + 0x4a0;
+		fadt->gpe1_base = 0x20;
+		fadt->gpe1_blk_len = 0x10;
+	}
+	else {
+		fadt->gpe1_blk = 0x0;
+		fadt->gpe1_base = 0x0;
+		fadt->gpe1_blk_len = 0x0;
+	}
+
+	fadt->cst_cnt = 0;
+	fadt->p_lvl2_lat = 0x65;
+	fadt->p_lvl3_lat = 0x3e9;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 3;	
+	fadt->day_alrm = 0x7d;
+	fadt->mon_alrm = 0x7e;
+	fadt->century = 0x32;
+
+	fadt->iapc_boot_arch = 0x0;
+
+	fadt->flags = 0x4a5;
+	fadt->reset_reg.space_id = 0;
+	fadt->reset_reg.bit_width = 0;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0x0;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 0;
+	fadt->x_firmware_ctl_l = facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = fadt->pm1_evt_len * 8;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = fadt->gpe1_blk_len * 8;;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = fadt->gpe1_blk;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum = acpi_checksum((void *) fadt, header->length);
+}

Modified: trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c	2009-06-18 16:38:35 UTC (rev 4363)
+++ trunk/coreboot-v2/src/southbridge/nvidia/mcp55/mcp55_lpc.c	2009-06-19 12:03:40 UTC (rev 4364)
@@ -155,7 +155,6 @@
    lpc_common_init(dev, 0);
 }

-#if 0
 static void enable_hpet(struct device *dev)
 {
    unsigned long hpet_address;
@@ -164,7 +163,6 @@
    hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
    printk_debug("enabling HPET @0x%x\n", hpet_address);
 }
-#endif

static void lpc_init(device_t dev)
 {
@@ -242,7 +240,7 @@
    isa_dma_init();

/* Initialize the High Precision Event Timers */
-//	enable_hpet(dev);
+	enable_hpet(dev);

}