Patch set updated for coreboot: f6e19b9 Add infrastructure to distribute MSRs across CPUs on init

[Kyösti Mälkki]

Kyösti Mälkki ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1386

-gerrit

commit f6e19b99e7d4ec6d082670cbfa1e40bd68303e38
Author: Kyösti Mälkki 
Date:   Tue Jul 31 20:52:47 2012 +0300

Add infrastructure to distribute MSRs across CPUs on init

Some MSRs need to be replicated from one CPU to another.
    As the first step handle TOP_MEM and TOP_MEM2 for AMD CPUs.

There is no need to regenerate MTRR setup from the registered memory
    resources separately for each CPU, doing it once and saving a copy
    in a table should do it. Also writing of MTRR MSRs to CPUs should be
    synchronized, reading from a table should simplify that process.

The created table can be moved to cbmem to use it on S2/S3 resumes.

Change-Id: I9bf0c47f825f7174b5108a32fba56e9fec5bb62b
    Signed-off-by: Kyösti Mälkki 
---
 src/cpu/x86/mtrr/Makefile.inc |    1 +
 src/cpu/x86/mtrr/msr.c        |   51 +++++++++++++++++++++++++++++++++++++++++
 src/include/cpu/x86/msr.h     |    7 +++++
 3 files changed, 59 insertions(+), 0 deletions(-)

diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc
index cecb826..65a53d3 100644
--- a/src/cpu/x86/mtrr/Makefile.inc
+++ b/src/cpu/x86/mtrr/Makefile.inc
@@ -1 +1,2 @@
 ramstage-y += mtrr.c
+ramstage-y += msr.c
diff --git a/src/cpu/x86/mtrr/msr.c b/src/cpu/x86/mtrr/msr.c
new file mode 100644
index 0000000..b79c75e
--- /dev/null
+++ b/src/cpu/x86/mtrr/msr.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Kyösti Mälkki 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <cpu/x86/msr.h>
+
+/* Storage for MSRs that need to be replicated over
+ * all CPUs after power-on and S2/S3 resumes.
+ */
+static struct msr_non_volatile_struct {
+	uint64_t	tolm;		/* Top of low RAM < 4GB. */
+	uint64_t	tom;		/* Top of RAM. */
+
+#if 0
+	msrinit_t	mtrr[MAX_MTRRS];	/* TODO */
+#endif
+} msr_non_volatile;
+
+void msr_nv_setup_ramtop(uint64_t tolm, uint64_t tom)
+{
+	msr_non_volatile.tolm = tolm;
+	msr_non_volatile.tom = tom;
+}
+
+uint64_t msr_nv_get_tolm(void)
+{
+	return msr_non_volatile.tolm;
+}
+
+uint64_t msr_nv_get_tom(void)
+{
+	return msr_non_volatile.tom;
+}
+
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index 40926df..17d105d 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -17,6 +17,8 @@ static void wrmsr(unsigned long index, msr_t msr)

#else

+#include <stdint.h>
+
 typedef struct msr_struct
 {
    unsigned lo;
@@ -59,6 +61,11 @@ static inline __attribute__((always_inline)) void wrmsr(unsigned index, msr_t ms
    	);
 }

+/* Utility functions for non-volatile copy of MSRs. */
+void msr_nv_setup_ramtop(uint64_t tolm, uint64_t tom);
+uint64_t msr_nv_get_tolm(void);
+uint64_t msr_nv_get_tom(void);
+
 #endif /* __ROMCC__ */

#endif /* CPU_X86_MSR_H */