I've been trying to accomplish several things:
1) LB on Via Epia ML 5000 2) VGA working 3) Figuring out weird boot errors that seem to be "fixed" by the factory BIOS. Running memtest86+ under LB.
I _was_ on step 3, but in the course of events, I went back to step 2. VGA is now NOT working again, but with a different error; see below.
Since I was messing around with making an ML tree, adding a bit of custom stuff, and removing initializations for devices that don't exist on the ML (floppy, CF reader), I figured I had done something wrong.
Soooo, I went back to the "stock" LinuxBIOSv2, revision 2100, known to work with the Epia M. This particular revision worked for me, albeit with the long delay at the beginning because of the firewire search.
Essentially, whenever, I add ...
#VGA Console option CONFIG_CONSOLE_VGA=1 option CONFIG_PCI_ROM_RUN=1
... to the Config.lb, it doesn't work, giving the error below.
Mysteriously, my "weird boot crashes that are fixed by factory CMOS" problems aren't exhibiting themselves.
Unfortunately, I cannot run memtest86 under LB without VGA.
Any ideas?
--------------------------------------------------------------------
0
LinuxBIOS-1.1.8.0Fallback Sat Apr 29 22:12:48 PDT 2006 starting... Enabling mainboard devices Enabling shadow ram vt8623 init starting Detecting Memory Number of Banks 04 Number of Rows 0d Priamry DRAM width08 No Columns 0a MA type e0 Bank 0 (*16 Mb) 10 No Physical Banks 01 Total Memory (*16 Mb) 10 CAS Supported 2 2.5 3 Cycle time at CL X (nS)50 Cycle time at CL X-0.5 (nS)60 Cycle time at CL X-1 (nS)75 Starting at CAS 3 We can do CAS 2.5 We can do CAS 2 tRP 48 tRCD 48 tRAS 28 Low Bond 00 High Bondbe Setting DQS delay7evt8623 done 00:06 11 23 31 06 00 30 22 00 00 00 06 00 00 00 00 10:08 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00 20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40:00 18 88 80 82 44 00 00 18 99 88 80 82 44 00 00 50:c8 de cf 88 e0 07 00 00 e0 00 10 10 10 10 00 00 60:02 ff 00 30 d6 32 01 2a 42 2d 43 58 00 44 00 00 70:82 48 00 01 01 08 50 00 01 00 00 00 00 00 00 02 80:0f 65 00 00 80 00 00 00 02 00 00 00 00 00 00 00 90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0:02 c0 20 00 07 02 00 1f 04 00 00 00 2f 02 04 00 b0:00 00 00 00 80 00 00 00 88 00 00 00 00 00 00 00 c0:01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0:00 dd 00 00 00 00 01 00 40 00 00 00 00 00 00 00 f0:00 00 00 00 00 00 12 13 00 00 00 00 00 00 00 00 AGP Doing MTRR init. Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.8.0Fallback Sat Apr 29 22:12:48 PDT 2006 booting... clocks_per_usec: 838 Enumerating buses... Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 enabled PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [1106/3123] enabled PCI: 00:01.0 [1106/b091] enabled Disabling static device: PCI: 00:0a.0 Disabling static device: PCI: 00:0a.1 In vt8235_enable 1106 3038. PCI: 00:10.0 [1106/3038] enabled In vt8235_enable 1106 3038. PCI: 00:10.1 [1106/3038] enabled In vt8235_enable 1106 3038. PCI: 00:10.2 [1106/3038] enabled In vt8235_enable 1106 3104. PCI: 00:10.3 [1106/3104] enabled In vt8235_enable 1106 3177. Initialising Devices PCI: 00:11.0 [1106/3177] enabled In vt8235_enable 1106 0571. PCI: 00:11.1 [1106/0571] enabled In vt8235_enable 1106 3059. PCI: 00:11.5 [1106/3059] enabled In vt8235_enable ffff ffff. In vt8235_enable 1106 3065. PCI: 00:12.0 [1106/3065] enabled PCI: pci_scan_bus for bus 1 PCI: 01:00.0 [1106/3122] enabled PCI: pci_scan_bus returning with max=01 vt1211 enabling PNP devices. PNP: 002e.0 enabled vt1211 enabling PNP devices. PNP: 002e.1 enabled vt1211 enabling PNP devices. PNP: 002e.2 enabled vt1211 enabling PNP devices. PNP: 002e.3 enabled vt1211 enabling PNP devices. PNP: 002e.b enabled PCI: pci_scan_bus returning with max=01 done Allocating resources... Reading resources... Done reading resources. Allocating VGA resource PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Setting resources... I would set ram size to 0x40000 Kbytes PCI: 00:10.0 20 <- [0x0000001800 - 0x000000181f] io PCI: 00:10.1 20 <- [0x0000001820 - 0x000000183f] io PCI: 00:10.2 20 <- [0x0000001840 - 0x000000185f] io PCI: 00:10.3 10 <- [0x00febff000 - 0x00febff0ff] mem PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] io PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] irq PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] drq PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] io PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] irq PNP: 002e.1 74 <- [0x0000000003 - 0x0000000003] drq PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] irq PNP: 002e.b 60 <- [0x000000ec00 - 0x000000ecff] io PCI: 00:11.1 20 <- [0x0000001860 - 0x000000186f] io PCI: 00:11.5 10 <- [0x0000001000 - 0x00000010ff] io PCI: 00:12.0 10 <- [0x0000001400 - 0x00000014ff] io PCI: 00:12.0 14 <- [0x00fec00000 - 0x00fec000ff] mem Done setting resources. Done allocating resources. Enabling resourcess... PCI: 00:00.0 cmd <- 146 PCI: 00:01.0 bridge ctrl <- 000f PCI: 00:01.0 cmd <- 147 PCI: 01:00.0 cmd <- 143 PCI: 00:10.0 subsystem <- 00/00 PCI: 00:10.0 cmd <- 141 PCI: 00:10.1 subsystem <- 00/00 PCI: 00:10.1 cmd <- 141 PCI: 00:10.2 subsystem <- 00/00 PCI: 00:10.2 cmd <- 141 PCI: 00:10.3 subsystem <- 00/00 PCI: 00:10.3 cmd <- 142 PCI: 00:11.0 cmd <- 147 PNP: 002e.0 - enabling PNP: 002e.1 - enabling PNP: 002e.2 - enabling PNP: 002e.3 - enabling PNP: 002e.b - enabling PCI: 00:11.1 cmd <- 147 PCI: 00:11.5 subsystem <- 00/00 PCI: 00:11.5 cmd <- 141 PCI: 00:12.0 cmd <- 1c3 done. Initializing devices... Root Device init PCI: 00:10.0 init PCI: 00:10.1 init PCI: 00:10.2 init PCI: 00:10.3 init PCI: 00:11.0 init vt8235 init RTC Init Invalid CMOS LB checksum pci_routing_fixup: dev is 0001ad40 setting firewire setting usb Assigning IRQ 5 to 0:10.0 Readback = 5 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 Assigning IRQ 9 to 0:10.1 Readback = 9 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 Assigning IRQ 9 to 0:10.2 Readback = 9 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 Assigning IRQ 5 to 0:10.3 Readback = 5 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 setting vt8235 Assigning IRQ 5 to 0:11.1 Readback = 5 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 Assigning IRQ 9 to 0:11.5 Readback = 9 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 setting ethernet Assigning IRQ 5 to 0:12.0 Readback = 5 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 setting vga Assigning IRQ 5 to 1:0.0 Readback = 5 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 setting pci slot setting cardbus slot setting riser slot PNP: 002e.0 init PNP: 002e.1 init PNP: 002e.2 init PNP: 002e.3 init PNP: 002e.b init PCI: 00:11.1 init Enabling VIA IDE. ide_init: enabling compatibility IDE addresses enables in reg 0x42 0x0 enables in reg 0x42 read back as 0x0 enables in reg 0x40 0x13 enables in reg 0x40 read back as 0x13 enables in reg 0x9 0x8a enables in reg 0x9 read back as 0x8a command in reg 0x4 0x7 command in reg 0x4 reads back as 0x7 PCI: 00:11.5 init PCI: 00:12.0 init Configuring VIA Rhine LAN APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor Centaur device 673 Enabling cache
Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 128MB, type WB Setting variable MTRR 1, base: 128MB, range: 64MB, type WB Setting variable MTRR 2, base: 192MB, range: 32MB, type WB DONE variable MTRRs Clear out the extra MTRR's
MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
Disabling local apic...done. CPU #0 Initialized PCI: 00:00.0 init VT8623 random fixup ... Frame buffer at d0000000 PCI: 00:01.0 init VT8623 AGP random fixup ... PCI: 01:00.0 init VGA random fixup ... INSTALL REAL-MODE IDT DO THE VGA BIOS found VGA: vid=1106, did=3122 rom base, size: fffc0000 write_protect_vgabios bus/devfn = 0x100 Unexpected Exception: 13 @ 10:000121c3 - Halting Code: 0 eflags: 00010012 eax: 00000012 ebx: 00024530 ecx: 00023fa8 edx: 00000012 edi: 00018a90 esi: ffff946b ebp: 00023f84 esp: 00023f84
Mysteriously, my "weird boot crashes that are fixed by factory CMOS" problems aren't exhibiting themselves.
Unfortunately, I cannot run memtest86 under LB without VGA.
You can recompile memtest86 to use the serial port rather than VGA.
-- Richard A. Smith
Eric Poulsen schrieb:
I went back to the "stock" LinuxBIOSv2, revision 2100, known to work with the Epia M. This particular revision worked for me, albeit with the long delay at the beginning because of the firewire search.
Essentially, whenever, I add ...
#VGA Console option CONFIG_CONSOLE_VGA=1 option CONFIG_PCI_ROM_RUN=1.... to the Config.lb, it doesn't work, giving the error below.
Any ideas?
[...] VGA random fixup ... INSTALL REAL-MODE IDT DO THE VGA BIOS found VGA: vid=1106, did=3122 rom base, size: fffc0000 write_protect_vgabios
^^^^^^^^^^^^^^^^^^^^^ Did you change the line in mainboard.c from dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3123, 0); to dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CLE266_VGA, 0); in order to write-protect the vgabios correctly?
bus/devfn = 0x100 Unexpected Exception: 13 @ 10:000121c3 - Halting Code: 0 eflags: 00010012 eax: 00000012 ebx: 00024530 ecx: 00023fa8 edx: 00000012 edi: 00018a90 esi: ffff946b ebp: 00023f84 esp: 00023f84
Daniel.
Daniel,
mainboard.c already looks like this in src/mainboard/via/epia-m. It seems to take care of both the $3122 and $3123 devices.
There are other weird things happening. LB _does not_ compile the way it used to out-of-the-box, even for older revisions. It gives me linking errors every time I try to enable VGA (CONFIG_CONSOLE_VGA,CONFIG_PCI_ROM_RUN), unless I increase the ROM_IMAGE_SIZE, as recommended by Stefan. I figured maybe my payload was too large and pushing the image > $10000, so I recompiled filo with a bunch fewer options, and it was only 26K (vs 39K before), and it still won't link without increasing ROM_IMAGE_SIZE to $12000. I'm not sure if this is related, but it is weird. Can ROM_IMAGE_SIZE be changed w/o changing any of the other parameters?
Also, does anyone have a good explaination of:
ROM_SIZE (Appears to be total size of your rom chip) ROM_IMAGE_SIZE (Size of this rom image, fallback or normal), defaults to $10000 (64K) ROM_SECTION_OFFSET=0x10000 ??? ROM_SECTION_SIZE=0x30000 ??? ROM section == total used by LB minus VGA rom size???
void write_protect_vgabios(void) { device_t dev;
printk_info("write_protect_vgabios\n"); /* there are two possible devices. Just do both. */ dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3122, 0); if(dev) pci_write_config8(dev, 0x61, 0xaa);
dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3123, 0); if(dev) pci_write_config8(dev, 0x61, 0xaa); }
Daniel Parthey wrote:
Eric Poulsen schrieb:
I went back to the "stock" LinuxBIOSv2, revision 2100, known to work with the Epia M. This particular revision worked for me, albeit with the long delay at the beginning because of the firewire search.
Essentially, whenever, I add ...
#VGA Console option CONFIG_CONSOLE_VGA=1 option CONFIG_PCI_ROM_RUN=1
.... to the Config.lb, it doesn't work, giving the error below.
Any ideas?
[...] VGA random fixup ... INSTALL REAL-MODE IDT DO THE VGA BIOS found VGA: vid=1106, did=3122 rom base, size: fffc0000 write_protect_vgabios
^^^^^^^^^^^^^^^^^^^^^ Did you change the line in mainboard.c from dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3123, 0); to dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CLE266_VGA, 0); in order to write-protect the vgabios correctly?
bus/devfn = 0x100 Unexpected Exception: 13 @ 10:000121c3 - Halting Code: 0 eflags: 00010012 eax: 00000012 ebx: 00024530 ecx: 00023fa8 edx: 00000012 edi: 00018a90 esi: ffff946b ebp: 00023f84 esp: 00023f84
Daniel.
Eric Poulsen wrote:
Daniel,
mainboard.c already looks like this in src/mainboard/via/epia-m. It seems to take care of both the $3122 and $3123 devices.
There are other weird things happening. LB _does not_ compile the way it used to out-of-the-box, even for older revisions. It gives me linking errors every time I try to enable VGA (CONFIG_CONSOLE_VGA,CONFIG_PCI_ROM_RUN), unless I increase the ROM_IMAGE_SIZE, as recommended by Stefan. I figured maybe my payload was too large and pushing the image > $10000, so I recompiled filo with a bunch fewer options, and it was only 26K (vs 39K before), and it still won't link without increasing ROM_IMAGE_SIZE to $12000. I'm not sure if this is related, but it is weird. Can ROM_IMAGE_SIZE be changed w/o changing any of the other parameters?
Also, does anyone have a good explaination of:
ROM_SIZE (Appears to be total size of your rom chip) ROM_IMAGE_SIZE (Size of this rom image, fallback or normal), defaults to $10000 (64K) ROM_SECTION_OFFSET=0x10000 ??? ROM_SECTION_SIZE=0x30000 ??? ROM section == total used by LB minus VGA rom size???
see my linux journal article on the web. I think that's where it is. There is a figure there that might clear it up.
Or I can send you the article directly.
ron
Found it, posting it to the list for the benefit of others:
"Porting LinuxBIOS to the AMD SC520: A Follow-up Report" [This has the nifty diagram of how all the *_SIZE options work together] http://www.linuxjournal.com/article/8310
"LinuxBIOS at Four" http://www.linuxjournal.com/article/7170
Ronald G Minnich wrote:
Also, does anyone have a good explaination of:
ROM_SIZE (Appears to be total size of your rom chip) ROM_IMAGE_SIZE (Size of this rom image, fallback or normal), defaults to $10000 (64K) ROM_SECTION_OFFSET=0x10000 ??? ROM_SECTION_SIZE=0x30000 ??? ROM section == total used by LB minus VGA rom size???
see my linux journal article on the web. I think that's where it is. There is a figure there that might clear it up.
Or I can send you the article directly.
ron
Okay, I got it to work again. This is weird, but I figured out what the issue is. I think the build system for LB (at least for the Epia-M branch) is bad. I don't have any experience with romcc or building BIOSes, but I do have quite a bit of experience with C,C++, and using makefiles -- something seems very wrong here, especially when you look at the details of the two build processes shown below. IMHO, "make clean" should set you back to the beginning (as it seems to), and a compile after that should fix any weirdnesses with linking.
Just in case it's not clear, in both examples below, there are NO "real" code changes between them, only configuration changes. Also, this is with my own Epia-ML branch (derived from Epia-M) -- the only difference is that I removed the ieee1394 init code in auto.c and edited the Config.lb for the mainboard so that it doesn't init the floppy and the CF card reader, which don't exist on the ML. I was having the exact same issues with the out-of-the-box Epia-M branch. When I built it (both Epia-M and Epia-ML branches) successfully in the past, I _never_ used make clean because I figured buildtarget would fix any issues, especially since a 'make' after 'buildtarget' resulted in recompilation of several files.
In short, my recent use of 'make clean' seems to be hosing the process.
This _DOES NOT WORK_ (but it should):
(pseudocode -- not literal) ]Set CONFIG_CONSOLE_VGA=1, CONFIG_PCI_ROM_RUN=1 in Config.lb ]buildtarget via/epia-m ]cd via/epia-m/epia-m ]make clean ]make ][Bunches of link errors because of overlapping sections] |set ROM_IMAGE_SIZE to 0x12000 (previously 0x10000), as per Stefan's suggestion. buildtarget make clean make [successful compile] cat vga_bios linuxbios.rom > lb.rom flashrom [Reboot] Crash, exception 13 just after vga write protect
This _DOES WORK_
Start with default epia-m config.lb buildtarget [compiles clean, but no vga options on -- If I were to flash and reboot, this would work as-is, sans VGA] Edit Config.lb add CONFIG_CONSOLE_VGA=1 buildtarget make [_IMPORTANT_ -- NOTICE THERE IS NO 'make clean' LINE!] [compiles clean] Edit Config.lb add CONFIG_PCI_ROM_RUN=1 buildtarget make [_IMPORTANT_ -- NOTICE THERE IS NO 'make clean' LINE!] [compiles clean] cat vga_bios linuxbios.rom flashrom [reboot] [Everything works -- boots, VGA works, etc. ] [Important thing to note about the above is that the ROM_IMAGE_SIZE _was not_ increased]
Eric Poulsen wrote:
I've been trying to accomplish several things:
- LB on Via Epia ML 5000 2) VGA working 3) Figuring out weird boot
errors that seem to be "fixed" by the factory BIOS. Running memtest86+ under LB.
I _was_ on step 3, but in the course of events, I went back to step 2. VGA is now NOT working again, but with a different error; see below.
Since I was messing around with making an ML tree, adding a bit of custom stuff, and removing initializations for devices that don't exist on the ML (floppy, CF reader), I figured I had done something wrong.
Soooo, I went back to the "stock" LinuxBIOSv2, revision 2100, known to work with the Epia M. This particular revision worked for me, albeit with the long delay at the beginning because of the firewire search.
Essentially, whenever, I add ...
#VGA Console option CONFIG_CONSOLE_VGA=1 option CONFIG_PCI_ROM_RUN=1
... to the Config.lb, it doesn't work, giving the error below.
Mysteriously, my "weird boot crashes that are fixed by factory CMOS" problems aren't exhibiting themselves.
Unfortunately, I cannot run memtest86 under LB without VGA.
Any ideas?
0
LinuxBIOS-1.1.8.0Fallback Sat Apr 29 22:12:48 PDT 2006 starting... Enabling mainboard devices Enabling shadow ram vt8623 init starting Detecting Memory Number of Banks 04 Number of Rows 0d Priamry DRAM width08 No Columns 0a MA type e0 Bank 0 (*16 Mb) 10 No Physical Banks 01 Total Memory (*16 Mb) 10 CAS Supported 2 2.5 3 Cycle time at CL X (nS)50 Cycle time at CL X-0.5 (nS)60 Cycle time at CL X-1 (nS)75 Starting at CAS 3 We can do CAS 2.5 We can do CAS 2 tRP 48 tRCD 48 tRAS 28 Low Bond 00 High Bondbe Setting DQS delay7evt8623 done 00:06 11 23 31 06 00 30 22 00 00 00 06 00 00 00 00 10:08 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00 20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40:00 18 88 80 82 44 00 00 18 99 88 80 82 44 00 00 50:c8 de cf 88 e0 07 00 00 e0 00 10 10 10 10 00 00 60:02 ff 00 30 d6 32 01 2a 42 2d 43 58 00 44 00 00 70:82 48 00 01 01 08 50 00 01 00 00 00 00 00 00 02 80:0f 65 00 00 80 00 00 00 02 00 00 00 00 00 00 00 90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0:02 c0 20 00 07 02 00 1f 04 00 00 00 2f 02 04 00 b0:00 00 00 00 80 00 00 00 88 00 00 00 00 00 00 00 c0:01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0:00 dd 00 00 00 00 01 00 40 00 00 00 00 00 00 00 f0:00 00 00 00 00 00 12 13 00 00 00 00 00 00 00 00 AGP Doing MTRR init. Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.8.0Fallback Sat Apr 29 22:12:48 PDT 2006 booting... clocks_per_usec: 838 Enumerating buses... Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 enabled PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [1106/3123] enabled PCI: 00:01.0 [1106/b091] enabled Disabling static device: PCI: 00:0a.0 Disabling static device: PCI: 00:0a.1 In vt8235_enable 1106 3038. PCI: 00:10.0 [1106/3038] enabled In vt8235_enable 1106 3038. PCI: 00:10.1 [1106/3038] enabled In vt8235_enable 1106 3038. PCI: 00:10.2 [1106/3038] enabled In vt8235_enable 1106 3104. PCI: 00:10.3 [1106/3104] enabled In vt8235_enable 1106 3177. Initialising Devices PCI: 00:11.0 [1106/3177] enabled In vt8235_enable 1106 0571. PCI: 00:11.1 [1106/0571] enabled In vt8235_enable 1106 3059. PCI: 00:11.5 [1106/3059] enabled In vt8235_enable ffff ffff. In vt8235_enable 1106 3065. PCI: 00:12.0 [1106/3065] enabled PCI: pci_scan_bus for bus 1 PCI: 01:00.0 [1106/3122] enabled PCI: pci_scan_bus returning with max=01 vt1211 enabling PNP devices. PNP: 002e.0 enabled vt1211 enabling PNP devices. PNP: 002e.1 enabled vt1211 enabling PNP devices. PNP: 002e.2 enabled vt1211 enabling PNP devices. PNP: 002e.3 enabled vt1211 enabling PNP devices. PNP: 002e.b enabled PCI: pci_scan_bus returning with max=01 done Allocating resources... Reading resources... Done reading resources. Allocating VGA resource PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Setting resources... I would set ram size to 0x40000 Kbytes PCI: 00:10.0 20 <- [0x0000001800
- 0x000000181f] io PCI: 00:10.1 20 <- [0x0000001820 - 0x000000183f]
io PCI: 00:10.2 20 <- [0x0000001840 - 0x000000185f] io PCI: 00:10.3 10 <- [0x00febff000 - 0x00febff0ff] mem PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] io PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] irq PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] drq PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] io PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] irq PNP: 002e.1 74 <- [0x0000000003 - 0x0000000003] drq PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] irq PNP: 002e.b 60 <- [0x000000ec00 - 0x000000ecff] io PCI: 00:11.1 20 <- [0x0000001860 - 0x000000186f] io PCI: 00:11.5 10 <- [0x0000001000 - 0x00000010ff] io PCI: 00:12.0 10 <- [0x0000001400
- 0x00000014ff] io PCI: 00:12.0 14 <- [0x00fec00000 - 0x00fec000ff]
mem Done setting resources. Done allocating resources. Enabling resourcess... PCI: 00:00.0 cmd <- 146 PCI: 00:01.0 bridge ctrl <- 000f PCI: 00:01.0 cmd <- 147 PCI: 01:00.0 cmd <- 143 PCI: 00:10.0 subsystem <- 00/00 PCI: 00:10.0 cmd <- 141 PCI: 00:10.1 subsystem <- 00/00 PCI: 00:10.1 cmd <- 141 PCI: 00:10.2 subsystem <- 00/00 PCI: 00:10.2 cmd <- 141 PCI: 00:10.3 subsystem <- 00/00 PCI: 00:10.3 cmd <- 142 PCI: 00:11.0 cmd <- 147 PNP: 002e.0 - enabling PNP: 002e.1 - enabling PNP: 002e.2 - enabling PNP: 002e.3 - enabling PNP: 002e.b - enabling PCI: 00:11.1 cmd <- 147 PCI: 00:11.5 subsystem <- 00/00 PCI: 00:11.5 cmd <- 141 PCI: 00:12.0 cmd <- 1c3 done. Initializing devices... Root Device init PCI: 00:10.0 init PCI: 00:10.1 init PCI: 00:10.2 init PCI: 00:10.3 init PCI: 00:11.0 init vt8235 init RTC Init Invalid CMOS LB checksum pci_routing_fixup: dev is 0001ad40 setting firewire setting usb Assigning IRQ 5 to 0:10.0 Readback = 5 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 Assigning IRQ 9 to 0:10.1 Readback = 9 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 Assigning IRQ 9 to 0:10.2 Readback = 9 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 Assigning IRQ 5 to 0:10.3 Readback = 5 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 setting vt8235 Assigning IRQ 5 to 0:11.1 Readback = 5 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 Assigning IRQ 9 to 0:11.5 Readback = 9 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 setting ethernet Assigning IRQ 5 to 0:12.0 Readback = 5 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 setting vga Assigning IRQ 5 to 1:0.0 Readback = 5 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 setting pci slot setting cardbus slot setting riser slot PNP: 002e.0 init PNP: 002e.1 init PNP: 002e.2 init PNP: 002e.3 init PNP: 002e.b init PCI: 00:11.1 init Enabling VIA IDE. ide_init: enabling compatibility IDE addresses enables in reg 0x42 0x0 enables in reg 0x42 read back as 0x0 enables in reg 0x40 0x13 enables in reg 0x40 read back as 0x13 enables in reg 0x9 0x8a enables in reg 0x9 read back as 0x8a command in reg 0x4 0x7 command in reg 0x4 reads back as 0x7 PCI: 00:11.5 init PCI: 00:12.0 init Configuring VIA Rhine LAN APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor Centaur device 673 Enabling cache
Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 128MB, type WB Setting variable MTRR 1, base: 128MB, range: 64MB, type WB Setting variable MTRR 2, base: 192MB, range: 32MB, type WB DONE variable MTRRs Clear out the extra MTRR's
MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
Disabling local apic...done. CPU #0 Initialized PCI: 00:00.0 init VT8623 random fixup ... Frame buffer at d0000000 PCI: 00:01.0 init VT8623 AGP random fixup ... PCI: 01:00.0 init VGA random fixup ... INSTALL REAL-MODE IDT DO THE VGA BIOS found VGA: vid=1106, did=3122 rom base, size: fffc0000 write_protect_vgabios bus/devfn = 0x100 Unexpected Exception: 13 @ 10:000121c3 - Halting Code: 0 eflags: 00010012 eax: 00000012 ebx: 00024530 ecx: 00023fa8 edx: 00000012 edi: 00018a90 esi: ffff946b ebp: 00023f84 esp: 00023f84
Can anyone confirm that this is a problem? Or am I barking up the wrong tree?
Eric Poulsen wrote:
Okay, I got it to work again. This is weird, but I figured out what the issue is. I think the build system for LB (at least for the Epia-M branch) is bad. I don't have any experience with romcc or building BIOSes, but I do have quite a bit of experience with C,C++, and using makefiles -- something seems very wrong here, especially when you look at the details of the two build processes shown below. IMHO, "make clean" should set you back to the beginning (as it seems to), and a compile after that should fix any weirdnesses with linking.
Just in case it's not clear, in both examples below, there are NO "real" code changes between them, only configuration changes. Also, this is with my own Epia-ML branch (derived from Epia-M) -- the only difference is that I removed the ieee1394 init code in auto.c and edited the Config.lb for the mainboard so that it doesn't init the floppy and the CF card reader, which don't exist on the ML. I was having the exact same issues with the out-of-the-box Epia-M branch. When I built it (both Epia-M and Epia-ML branches) successfully in the past, I _never_ used make clean because I figured buildtarget would fix any issues, especially since a 'make' after 'buildtarget' resulted in recompilation of several files.
In short, my recent use of 'make clean' seems to be hosing the process.
This _DOES NOT WORK_ (but it should):
(pseudocode -- not literal) ]Set CONFIG_CONSOLE_VGA=1, CONFIG_PCI_ROM_RUN=1 in Config.lb ]buildtarget via/epia-m ]cd via/epia-m/epia-m ]make clean ]make ][Bunches of link errors because of overlapping sections] |set ROM_IMAGE_SIZE to 0x12000 (previously 0x10000), as per Stefan's suggestion. buildtarget make clean make [successful compile] cat vga_bios linuxbios.rom > lb.rom flashrom [Reboot] Crash, exception 13 just after vga write protect
This _DOES WORK_
Start with default epia-m config.lb buildtarget [compiles clean, but no vga options on -- If I were to flash and reboot, this would work as-is, sans VGA] Edit Config.lb add CONFIG_CONSOLE_VGA=1 buildtarget make [_IMPORTANT_ -- NOTICE THERE IS NO 'make clean' LINE!] [compiles clean] Edit Config.lb add CONFIG_PCI_ROM_RUN=1 buildtarget make [_IMPORTANT_ -- NOTICE THERE IS NO 'make clean' LINE!] [compiles clean] cat vga_bios linuxbios.rom flashrom [reboot] [Everything works -- boots, VGA works, etc. ] [Important thing to note about the above is that the ROM_IMAGE_SIZE _was not_ increased]
Eric Poulsen wrote:
I've been trying to accomplish several things:
- LB on Via Epia ML 5000 2) VGA working 3) Figuring out weird boot
errors that seem to be "fixed" by the factory BIOS. Running memtest86+ under LB.
I _was_ on step 3, but in the course of events, I went back to step 2. VGA is now NOT working again, but with a different error; see below.
Since I was messing around with making an ML tree, adding a bit of custom stuff, and removing initializations for devices that don't exist on the ML (floppy, CF reader), I figured I had done something wrong.
Soooo, I went back to the "stock" LinuxBIOSv2, revision 2100, known to work with the Epia M. This particular revision worked for me, albeit with the long delay at the beginning because of the firewire search.
Essentially, whenever, I add ...
#VGA Console option CONFIG_CONSOLE_VGA=1 option CONFIG_PCI_ROM_RUN=1
... to the Config.lb, it doesn't work, giving the error below.
Mysteriously, my "weird boot crashes that are fixed by factory CMOS" problems aren't exhibiting themselves.
Unfortunately, I cannot run memtest86 under LB without VGA.
Any ideas?
0
LinuxBIOS-1.1.8.0Fallback Sat Apr 29 22:12:48 PDT 2006 starting... Enabling mainboard devices Enabling shadow ram vt8623 init starting Detecting Memory Number of Banks 04 Number of Rows 0d Priamry DRAM width08 No Columns 0a MA type e0 Bank 0 (*16 Mb) 10 No Physical Banks 01 Total Memory (*16 Mb) 10 CAS Supported 2 2.5 3 Cycle time at CL X (nS)50 Cycle time at CL X-0.5 (nS)60 Cycle time at CL X-1 (nS)75 Starting at CAS 3 We can do CAS 2.5 We can do CAS 2 tRP 48 tRCD 48 tRAS 28 Low Bond 00 High Bondbe Setting DQS delay7evt8623 done 00:06 11 23 31 06 00 30 22 00 00 00 06 00 00 00 00 10:08 00 00 d0 00 00 00 00 00 00 00 00 00 00 00 00 20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40:00 18 88 80 82 44 00 00 18 99 88 80 82 44 00 00 50:c8 de cf 88 e0 07 00 00 e0 00 10 10 10 10 00 00 60:02 ff 00 30 d6 32 01 2a 42 2d 43 58 00 44 00 00 70:82 48 00 01 01 08 50 00 01 00 00 00 00 00 00 02 80:0f 65 00 00 80 00 00 00 02 00 00 00 00 00 00 00 90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0:02 c0 20 00 07 02 00 1f 04 00 00 00 2f 02 04 00 b0:00 00 00 00 80 00 00 00 88 00 00 00 00 00 00 00 c0:01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0:00 dd 00 00 00 00 01 00 40 00 00 00 00 00 00 00 f0:00 00 00 00 00 00 12 13 00 00 00 00 00 00 00 00 AGP Doing MTRR init. Copying LinuxBIOS to ram. Jumping to LinuxBIOS. LinuxBIOS-1.1.8.0Fallback Sat Apr 29 22:12:48 PDT 2006 booting... clocks_per_usec: 838 Enumerating buses... Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 enabled PCI: pci_scan_bus for bus 0 PCI: 00:00.0 [1106/3123] enabled PCI: 00:01.0 [1106/b091] enabled Disabling static device: PCI: 00:0a.0 Disabling static device: PCI: 00:0a.1 In vt8235_enable 1106 3038. PCI: 00:10.0 [1106/3038] enabled In vt8235_enable 1106 3038. PCI: 00:10.1 [1106/3038] enabled In vt8235_enable 1106 3038. PCI: 00:10.2 [1106/3038] enabled In vt8235_enable 1106 3104. PCI: 00:10.3 [1106/3104] enabled In vt8235_enable 1106 3177. Initialising Devices PCI: 00:11.0 [1106/3177] enabled In vt8235_enable 1106 0571. PCI: 00:11.1 [1106/0571] enabled In vt8235_enable 1106 3059. PCI: 00:11.5 [1106/3059] enabled In vt8235_enable ffff ffff. In vt8235_enable 1106 3065. PCI: 00:12.0 [1106/3065] enabled PCI: pci_scan_bus for bus 1 PCI: 01:00.0 [1106/3122] enabled PCI: pci_scan_bus returning with max=01 vt1211 enabling PNP devices. PNP: 002e.0 enabled vt1211 enabling PNP devices. PNP: 002e.1 enabled vt1211 enabling PNP devices. PNP: 002e.2 enabled vt1211 enabling PNP devices. PNP: 002e.3 enabled vt1211 enabling PNP devices. PNP: 002e.b enabled PCI: pci_scan_bus returning with max=01 done Allocating resources... Reading resources... Done reading resources. Allocating VGA resource PCI: 01:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Setting resources... I would set ram size to 0x40000 Kbytes PCI: 00:10.0 20 <- [0x0000001800
- 0x000000181f] io PCI: 00:10.1 20 <- [0x0000001820 - 0x000000183f]
io PCI: 00:10.2 20 <- [0x0000001840 - 0x000000185f] io PCI: 00:10.3 10 <- [0x00febff000 - 0x00febff0ff] mem PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] io PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] irq PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] drq PNP: 002e.1 60 <- [0x0000000378 - 0x000000037f] io PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] irq PNP: 002e.1 74 <- [0x0000000003 - 0x0000000003] drq PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] io PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] irq PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] io PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] irq PNP: 002e.b 60 <- [0x000000ec00 - 0x000000ecff] io PCI: 00:11.1 20 <- [0x0000001860 - 0x000000186f] io PCI: 00:11.5 10 <- [0x0000001000 - 0x00000010ff] io PCI: 00:12.0 10 <- [0x0000001400
- 0x00000014ff] io PCI: 00:12.0 14 <- [0x00fec00000 - 0x00fec000ff]
mem Done setting resources. Done allocating resources. Enabling resourcess... PCI: 00:00.0 cmd <- 146 PCI: 00:01.0 bridge ctrl <- 000f PCI: 00:01.0 cmd <- 147 PCI: 01:00.0 cmd <- 143 PCI: 00:10.0 subsystem <- 00/00 PCI: 00:10.0 cmd <- 141 PCI: 00:10.1 subsystem <- 00/00 PCI: 00:10.1 cmd <- 141 PCI: 00:10.2 subsystem <- 00/00 PCI: 00:10.2 cmd <- 141 PCI: 00:10.3 subsystem <- 00/00 PCI: 00:10.3 cmd <- 142 PCI: 00:11.0 cmd <- 147 PNP: 002e.0 - enabling PNP: 002e.1 - enabling PNP: 002e.2 - enabling PNP: 002e.3 - enabling PNP: 002e.b - enabling PCI: 00:11.1 cmd <- 147 PCI: 00:11.5 subsystem <- 00/00 PCI: 00:11.5 cmd <- 141 PCI: 00:12.0 cmd <- 1c3 done. Initializing devices... Root Device init PCI: 00:10.0 init PCI: 00:10.1 init PCI: 00:10.2 init PCI: 00:10.3 init PCI: 00:11.0 init vt8235 init RTC Init Invalid CMOS LB checksum pci_routing_fixup: dev is 0001ad40 setting firewire setting usb Assigning IRQ 5 to 0:10.0 Readback = 5 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 Assigning IRQ 9 to 0:10.1 Readback = 9 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 Assigning IRQ 9 to 0:10.2 Readback = 9 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 Assigning IRQ 5 to 0:10.3 Readback = 5 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 setting vt8235 Assigning IRQ 5 to 0:11.1 Readback = 5 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 Assigning IRQ 9 to 0:11.5 Readback = 9 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 setting ethernet Assigning IRQ 5 to 0:12.0 Readback = 5 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 setting vga Assigning IRQ 5 to 1:0.0 Readback = 5 pci_level_irq: lower order bits are wrong: want 0x0, got 0x20 setting pci slot setting cardbus slot setting riser slot PNP: 002e.0 init PNP: 002e.1 init PNP: 002e.2 init PNP: 002e.3 init PNP: 002e.b init PCI: 00:11.1 init Enabling VIA IDE. ide_init: enabling compatibility IDE addresses enables in reg 0x42 0x0 enables in reg 0x42 read back as 0x0 enables in reg 0x40 0x13 enables in reg 0x40 read back as 0x13 enables in reg 0x9 0x8a enables in reg 0x9 read back as 0x8a command in reg 0x4 0x7 command in reg 0x4 reads back as 0x7 PCI: 00:11.5 init PCI: 00:12.0 init Configuring VIA Rhine LAN APIC_CLUSTER: 0 init Initializing CPU #0 CPU: vendor Centaur device 673 Enabling cache
Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB Setting fixed MTRRs(24-88) Type: WB DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 128MB, type WB Setting variable MTRR 1, base: 128MB, range: 64MB, type WB Setting variable MTRR 2, base: 192MB, range: 32MB, type WB DONE variable MTRRs Clear out the extra MTRR's
MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled
Disabling local apic...done. CPU #0 Initialized PCI: 00:00.0 init VT8623 random fixup ... Frame buffer at d0000000 PCI: 00:01.0 init VT8623 AGP random fixup ... PCI: 01:00.0 init VGA random fixup ... INSTALL REAL-MODE IDT DO THE VGA BIOS found VGA: vid=1106, did=3122 rom base, size: fffc0000 write_protect_vgabios bus/devfn = 0x100 Unexpected Exception: 13 @ 10:000121c3 - Halting Code: 0 eflags: 00010012 eax: 00000012 ebx: 00024530 ecx: 00023fa8 edx: 00000012 edi: 00018a90 esi: ffff946b ebp: 00023f84 esp: 00023f84
* Eric Poulsen eric@zyxod.com [060501 06:45]:
buildtarget make clean make Crash, exception 13 just after vga write protect
- vs -
buildtarget make [Everything works -- boots, VGA works, etc. ] [Important thing to note about the above is that the ROM_IMAGE_SIZE _was not_ increased]
This sounds very weird. Are you doing this on the same system using the same compiler? I suspect this is on 2 systems or using different compilers or binutils, since these factors can and do affect code size a lot (and make things break)
I just tried a "make clean" in a freshly created buildtree (using buildtarget) and its exactly the same as without "make clean"
Can you try the same and check whether its different?
Stefan
On 5/2/06, Eric Poulsen eric@zyxod.com wrote:
Can anyone confirm that this is a problem? Or am I barking up the wrong tree?
Do a diff between your target trees that have just a buildtarget and one that has a buildtarget followed by a make clean. Don't actually do a compile.
They should be identical.
-- Richard A. Smith
I just checked ... they are identical.
I don't think this addresses the issue, however. It happens to _work_ when I do a make, update Config.lb, buildtarget, then a final make. If I put a make clean in after the buildtarget, that's where it fails.
Here's what I think might be going on:
The first make w/o the options compiles all of the object files correctly, but without VGA (as expected). After the buildtarget, _some_ of the object files need to be updated to support the new options. This subset of object files is recompiled correctly, and then all of the object files are linked into a working executable. When you do a 'make clean' after the build target, all of the object files are wiped out and recompiled. Some of the object files that wouldn't normally be touched on the second make are now re-compiled, but they're re-compiled incorrectly because of the updated options.
*shrug*
Richard Smith wrote:
On 5/2/06, Eric Poulsen eric@zyxod.com wrote:
Can anyone confirm that this is a problem? Or am I barking up the wrong tree?
Do a diff between your target trees that have just a buildtarget and one that has a buildtarget followed by a make clean. Don't actually do a compile.
They should be identical.
-- Richard A. Smith
recompiled. Some of the object files that wouldn't normally be touched on the second make are now re-compiled, but they're re-compiled incorrectly because of the updated options.
So that would mean that a fresh buildtarget and make with the vga options enabled should fail? Is this what you orginally reported?
-- Richard A. Smith
* Eric Poulsen eric@zyxod.com [060502 16:29]:
I don't think this addresses the issue, however. It happens to _work_ when I do a make, update Config.lb, buildtarget, then a final make. If I put a make clean in after the buildtarget, that's where it fails.
So could you diff the object files so see where the difference is?
S.
Referring only to the epia-m target:
Yes, it will fail, but strangely. You'll get a bunch of linking errors that says sections are overlapping. You can increase ROM_IMAGE_SIZE, buildtarget, make clean, make, and it will then compile, but it won't actually run in-situ (Exception 13 just after protect vga bios).
Richard Smith wrote:
recompiled. Some of the object files that wouldn't normally be touched on the second make are now re-compiled, but they're re-compiled incorrectly because of the updated options.
So that would mean that a fresh buildtarget and make with the vga options enabled should fail? Is this what you orginally reported?
-- Richard A. Smith
Attached below.
The LinuxBIOSv2.bad directory is the one that doesn't complete the compile, because of linking errors. This is why some files are missing. The LinuxBIOSv2 directory is the "working" build.
Here's the build process (done in a way so that the diff file won't be cluttered with directory names):
1. svn download LinuxBIOS 2. Enter via/epia-m target 3. Edit Config.lb, adding CONFIG_CONSOLE_VGA, CONFIG_PCI_ROM_RUN 4. builtarget 5. make 6. [link errors] 7. Copy entire LinuxBIOSv2 tree to LinuxBIOSv2.bad. 8. (still within LinuxBIOSv2, _not_ .bad version), Edit Config.lb, _removing_ CONFIG_CONSOLE_VGA, CONFIG_PCI_ROM_RUN 9. buildtarget 10. make clean (merely to clear out the "bad" object files) 11. make 12. Edit Config.lb, re-enable CONFIG_CONSOLE_VGA, CONFIG_PCI_ROM_RUN 13. buildtarget 14. make [Note, _no_ use of make clean] 15. [successful compile, working linuxbios.rom] 16. diff LinuxBIOSv2 LinuxBIOSv2.bad -r > diff.txt [Attached below]
That's all, folks.
Stefan Reinauer wrote:
- Eric Poulsen eric@zyxod.com [060502 16:29]:
I don't think this addresses the issue, however. It happens to _work_ when I do a make, update Config.lb, buildtarget, then a final make. If I put a make clean in after the buildtarget, that's where it fails.
So could you diff the object files so see where the difference is?
S.
diff -r LinuxBIOSv2/targets/via/epia-m/epia-m/fallback/auto.inc LinuxBIOSv2.bad/targets/via/epia-m/epia-m/fallback/auto.inc 61c61 < .byte 0x33 ---
.byte 0x32
63,64c63,64 < .byte 0x35 < .byte 0x30 ---
.byte 0x33 .byte 0x31
Only in LinuxBIOSv2/targets/via/epia-m/epia-m/fallback: buildrom Binary files LinuxBIOSv2/targets/via/epia-m/epia-m/fallback/crt0.o and LinuxBIOSv2.bad/targets/via/epia-m/epia-m/fallback/crt0.o differ diff -r LinuxBIOSv2/targets/via/epia-m/epia-m/fallback/crt0.s LinuxBIOSv2.bad/targets/via/epia-m/epia-m/fallback/crt0.s 276c276 < .byte 0x33 ---
.byte 0x32
278,279c278,279 < .byte 0x35 < .byte 0x30 ---
.byte 0x33 .byte 0x31
Binary files LinuxBIOSv2/targets/via/epia-m/epia-m/fallback/device.o and LinuxBIOSv2.bad/targets/via/epia-m/epia-m/fallback/device.o differ Only in LinuxBIOSv2/targets/via/epia-m/epia-m/fallback: linuxbios Binary files LinuxBIOSv2/targets/via/epia-m/epia-m/fallback/linuxbios.a and LinuxBIOSv2.bad/targets/via/epia-m/epia-m/fallback/linuxbios.a differ Only in LinuxBIOSv2/targets/via/epia-m/epia-m/fallback: linuxbios.map Only in LinuxBIOSv2/targets/via/epia-m/epia-m/fallback: linuxbios.rom Only in LinuxBIOSv2/targets/via/epia-m/epia-m/fallback: linuxbios.strip Binary files LinuxBIOSv2/targets/via/epia-m/epia-m/fallback/linuxbios_ram and LinuxBIOSv2.bad/targets/via/epia-m/epia-m/fallback/linuxbios_ram differ Binary files LinuxBIOSv2/targets/via/epia-m/epia-m/fallback/linuxbios_ram.bin and LinuxBIOSv2.bad/targets/via/epia-m/epia-m/fallback/linuxbios_ram.bin differ diff -r LinuxBIOSv2/targets/via/epia-m/epia-m/fallback/linuxbios_ram.map LinuxBIOSv2.bad/targets/via/epia-m/epia-m/fallback/linuxbios_ram.map 171,499c171,537 < 0000611c T pci_probe_dev < 0000643d T pci_scan_bus < 00006591 T do_pci_scan_bridge < 0000666e T pci_scan_bridge < 00006683 T pci_assign_irqs < 000067c4 T console_init < 000067f9 t __console_tx_byte < 00006823 T console_tx_flush < 00006845 T console_tx_byte < 0000686e T console_rx_byte < 000068af T console_tst_byte < 000068da T post_code < 000068e4 T die < 00006908 T hardwaremain < 000069ac T setup_i8259 < 000069d8 T mdelay < 000069fb T delay < 00006a20 T x86_exception < 00006a68 t ht_lookup_slave_capability < 00006a9e T hypertransport_scan_chain < 00006fce T ht_scan_bridge < 00006fe4 t skip_atoi < 00007019 t number < 0000720b T vtxprintf < 00007594 T root_dev_read_resources < 0000764e T root_dev_set_resources < 00007695 T scan_static_bus < 000077ca T enable_childrens_resources < 0000780e T root_dev_enable_resources < 00007817 T root_dev_scan_bus < 00007820 T root_dev_init < 00007825 T root_dev_reset < 0000783c t cardbus_record_bridge_resource < 0000791b t cardbus_size_bridge_resource < 00007970 T cardbus_read_resources < 00007b22 T cardbus_enable_resources < 00007b7d T cardbus_scan_bus < 00007b86 T cardbus_scan_bridge < 00007c68 T uart8250_tx_byte < 00007c8a T uart8250_can_rx_byte < 00007c99 T uart8250_rx_byte < 00007cb2 T uart8250_init < 00007cf3 T init_uart8250 < 00007d24 T dev_find_slot < 00007d5f T dev_find_slot_on_smbus < 00007d9a T dev_find_device < 00007dc4 T dev_find_class < 00007ded T path_eq < 00007e4c T find_dev_path < 00007e7c T alloc_find_dev < 00007ea4 T dev_path < 00007f93 T bus_path < 00007fbe T compact_resources < 00008024 T probe_resource < 00008055 T new_resource < 000080f4 T find_resource < 0000813c T resource_end < 0000819c T resource_max < 000081f7 T resource_type < 0000827c T report_resource_stored < 00008314 T search_bus_resources < 00008395 T search_global_resources < 000083f1 T dev_set_enabled < 0000843f T disable_children < 0000848c T alloc_dev < 00008525 t round < 00008574 t read_resources < 00008642 t pick_largest_resource < 000086ca T compute_allocate_resource < 000088f0 T assign_resources < 00008946 T enable_resources < 00008982 T reset_bus < 000089b9 T scan_bus < 00008a50 T dev_enumerate < 00008aa9 T dev_configure < 00008b8c T dev_enable < 00008bb3 T dev_initialize < 00008c50 T init_timer < 00008c93 T udelay < 00008cf4 T memcpy < 00008d18 T memmove < 00008d60 t pci_conf2_read_config8 < 00008da8 t pci_conf2_read_config16 < 00008df1 t pci_conf2_read_config32 < 00008e38 t pci_conf2_write_config8 < 00008e7b t pci_conf2_write_config16 < 00008ebf t pci_conf2_write_config32 < 00008f00 t pci_conf1_read_config8 < 00008f38 t pci_conf1_read_config16 < 00008f71 t pci_conf1_read_config32 < 00008f9b t pci_conf1_write_config8 < 00008fd7 t pci_conf1_write_config16 < 00009014 t pci_conf1_write_config32 < 00009044 t rtc_checksum_valid < 00009089 T rtc_init < 00009188 T x86_enable_cache < 000091b0 t str_tx_byte < 000091c5 T vsprintf < 000091eb T sprintf < 00009200 T malloc_mark < 00009210 T malloc_release < 0000921f T malloc < 00009267 T free < 0000926c T memset < 00009288 T pciexp_scan_bus < 000092ee T pciexp_scan_bridge < 00009304 T move_gdt < 00009357 T write_tables < 000093dc T acpi_fill_madt < 000093e1 T acpi_fill_srat < 000093e6 T write_acpi_tables < 000094c0 T write_pirq_routing_table < 000094cc T pcix_scan_bus < 000095ce T pcix_speed < 00009618 T pcix_scan_bridge < 00009684 T acpi_create_fadt < 00009988 T verify_ip_checksum < 00009a6f T elfload < 0000a2bb T elfboot < 0000a424 T elf_check_arch < 0000a44b T jmp_to_elf_entry < 0000a518 T memcmp < 0000a544 T acpi_checksum < 0000a561 T acpi_add_table < 0000a5cd T acpi_create_madt_lapic < 0000a5f4 T acpi_create_madt_ioapic < 0000a61e T acpi_create_madt_irqoverride < 0000a64b T acpi_create_madt_lapic_nmi < 0000a672 T acpi_create_madt < 0000a6fc T acpi_create_srat_lapic < 0000a723 T acpi_create_srat_mem < 0000a768 T acpi_create_srat < 0000a7eb T acpi_create_hpet < 0000a888 T acpi_create_facs < 0000a8e0 T acpi_write_rsdt < 0000a942 T acpi_write_rsdp < 0000a994 t rl5c476_init < 0000aad0 T rl5c476_read_resources < 0000ab2a T rl5c476_set_resources < 0000abbd T southbridge_init < 0000abd4 T compute_ip_checksum < 0000ac25 T add_ip_checksums < 0000ac6c t northbridge_init < 0000ad87 t nullfunc < 0000ad8c t agp_init < 0000adef t vga_init < 0000ae6c t vga_read_resources < 0000ae86 t pci_domain_read_resources < 0000aed5 t ram_resource < 0000af15 t tolm_test < 0000af47 t pci_domain_set_resources < 0000b05f t pci_domain_scan_bus < 0000b07c t cpu_bus_init < 0000b08c t cpu_bus_noop < 0000b091 t enable_dev < 0000b0c0 t gdtarg < 0000b0c6 t __mygdtaddr < 0000b0cc t __mygdt < 0000b104 t __mygdt_end < 0000b104 t __myidt < 0000b10c T vga_enable_console < 0000b10c t real_mode_switch_end < 0000b125 t __vga_ec_16bit < 0000b141 t __vga_ec_real < 0000b18b t vga_ec_restart < 0000b1a8 t vga_ec_exit < 0000b1b1 T do_vgabios < 0000b292 t __stack < 0000b2aa t __rms_16bit < 0000b2c6 t __rms_real < 0000b301 t vgarestart < 0000b31e T vga_exit < 0000b365 T handler < 0000b368 t idthandle < 0000b371 t end_idthandle < 0000b373 T debughandler < 0000b376 t debughandle < 0000b37a t dbh1 < 0000b37e t end_debughandle < 0000b380 T callbiosint < 0000b383 t callbiosint16 < 0000b3a3 t biosprotect < 0000b3c4 t __rms_16bit2 < 0000b3e0 t __rms_real2 < 0000b40a T handleint21 < 0000b4ac T setup_realmode_idt < 0000b544 T pcibios < 0000b741 T biosint < 0000b8f0 T copy_pirq_routing_table < 0000ba88 t pnp_enter_ext_func_mode < 0000ba96 t pnp_exit_ext_func_mode < 0000baa4 t vt1211_init < 0000bb29 T vt1211_pnp_enable_resources < 0000bb60 T vt1211_pnp_set_resources < 0000bce9 T vt1211_pnp_enable < 0000bd1e t enable_dev < 0000bd44 T stream_init < 0000bd6f T stream_fini < 0000bd74 T stream_skip < 0000bdbf T stream_read < 0000bde8 T initialize_cpus < 0000be28 t pci_sanity_check < 0000be9c T pci_check_direct < 0000bf44 T pci_set_method < 0000bf78 T lb_table_init < 0000bfb8 T lb_first_record < 0000bfc3 T lb_last_record < 0000bfd1 T lb_next_record < 0000bfdc T lb_new_record < 0000c01d T lb_memory < 0000c037 T lb_mainboard < 0000c113 T lb_cmos_checksum < 0000c149 T lb_strings < 0000c1a7 T lb_memory_range < 0000c20c T get_lb_mem < 0000c216 T lb_table_fini < 0000c3d4 t lb_cleanup_memory_ranges < 0000c66f t lb_add_memory_range < 0000c94e t build_lb_mem_range < 0000c96b T write_linuxbios_table < 0000ca38 T set_boot_successful < 0000ca63 T boot_successful < 0000ca6c T pnp_write_config < 0000ca86 T pnp_read_config < 0000ca9c T pnp_set_logical_device < 0000cab1 T pnp_set_enable < 0000caca T pnp_read_enable < 0000cae3 T pnp_set_iobase < 0000cb23 T pnp_set_irq < 0000cb3a T pnp_set_drq < 0000cb51 T pnp_read_resources < 0000cb56 T pnp_set_resources < 0000cc43 T pnp_enable_resources < 0000cc5d T pnp_enable < 0000cc80 t pnp_get_ioresource < 0000ccff T pnp_enable_devices < 0000ce80 t have_cpuid_p < 0000cea2 T cpu_initialize < 0000d0e0 R _rodata < 0000d0e0 R console_drivers < 0000d0e0 T _etext < 0000d0e0 r uart8250_console < 0000d0f4 r vga_console < 0000d108 R econsole_drivers < 0000d108 R pci_drivers < 0000d108 r lpc_driver < 0000d110 r northbridge_driver < 0000d118 r northbridge_driver < 0000d120 r ricoh_rl5c476_driver < 0000d128 r vga_driver < 0000d130 r agp_driver < 0000d138 r northbridge_driver < 0000d140 R cpu_drivers < 0000d140 R epci_drivers < 0000d140 r driver < 0000d148 R ecpu_drivers < 0000d160 r riserPins < 0000d164 r cbPins < 0000d168 r slotPins < 0000d16c r vgaPins < 0000d170 r enetPins < 0000d174 r vt8235Pins < 0000d178 r usbPins < 0000d17c r firewirePins < 0000d180 r pciIrqs < 0000d184 r __FUNCTION__.0 < 0000d196 r div.0 < 0000d19e r __FUNCTION__.0 < 0000d1a7 r __func__.0 < 0000d1c0 R linuxbios_assembler < 0000d220 R linuxbios_linker < 0000d260 R linuxbios_compiler < 0000d2a2 R linuxbios_compile_domain < 0000d2a3 R linuxbios_compile_host < 0000d2a6 R linuxbios_compile_by < 0000d2ab R linuxbios_compile_time < 0000d2b4 R linuxbios_build < 0000d2d1 R linuxbios_extra_version < 0000d2dc R linuxbios_version < 0000d2e2 R mainboard_part_number < 0000d2e9 R mainboard_vendor < 0000d2ed r link_width_to_pow2.0 < 0000d2f5 r pow2_to_link_width.1 < 0000d348 R pci_cf8_conf2 < 0000d360 R pci_cf8_conf1 < 0000d380 R intel_irq_routing_table < 0000d3f0 r conventional.0 < 0000d401 r pcix_66mhz.1 < 0000d40d r pcix_100mhz.2 < 0000d41a r pcix_133mhz.3 < 0000d427 r pcix_266mhz.4 < 0000d434 r pcix_533mhz.5 < 0000d441 r unknown.6 < 0000d48c r ramregs.0 < 0000d4a8 r __FUNCTION__.0 < 0000d4f4 r __FUNCTION__.1 < 0000d500 r __FUNCTION__.0 < 0000d520 r strings.0 < 0000eed4 R _erodata < 0000eee0 D _data < 0000eee0 D gdt < 0000ef08 D gdt_end < 0000ef08 D idtarg < 0000ef10 d _idt < 0000efb0 d _idt_end < 0000efc0 d vt8235_lpc_ops < 0000efec D southbridge_via_vt8235_ops < 0000f000 d ide_ops < 0000f040 d nic_ops < 0000f080 d cpu_table < 0000f100 d cpu_dev_ops < 0000f140 d mtrr_msr < 0000f16c D default_console_loglevel < 0000f170 D minimum_console_loglevel < 0000f174 D default_message_loglevel < 0000f178 D console_loglevel < 0000f180 D default_pci_ops_bus < 0000f1c0 D default_pci_ops_dev < 0000f1ec d pci_dev_ops_pci < 0000f200 D default_ht_ops_bus < 0000f240 D default_dev_ops_root < 0000f280 D default_cardbus_ops_bus < 0000f2ac D all_devices < 0000f2c0 D _dev25 < 0000f560 D _dev22 < 0000f800 D _dev21 < 0000faa0 D _dev15 < 0000fd40 D _dev14 < 0000ffe0 D _dev13 ---
00006142 T pci_probe_dev 00006461 T pci_scan_bus 000065b5 T do_pci_scan_bridge 00006692 T pci_scan_bridge 000066a7 T pci_assign_irqs 000067e8 T console_init 0000681d t __console_tx_byte 00006847 T console_tx_flush 00006869 T console_tx_byte 00006892 T console_rx_byte 000068d3 T console_tst_byte 000068fe T post_code 00006908 T die 0000692c T hardwaremain 000069d0 T setup_i8259 000069fc T mdelay 00006a1f T delay 00006a44 T x86_exception 00006a8c t ht_lookup_slave_capability 00006ac2 T hypertransport_scan_chain 00006ff2 T ht_scan_bridge 00007008 t skip_atoi 0000703d t number 0000722f T vtxprintf 000075b8 T root_dev_read_resources 00007672 T root_dev_set_resources 000076b9 T scan_static_bus 000077ee T enable_childrens_resources 00007832 T root_dev_enable_resources 0000783b T root_dev_scan_bus 00007844 T root_dev_init 00007849 T root_dev_reset 00007860 t cardbus_record_bridge_resource 0000793f t cardbus_size_bridge_resource 00007994 T cardbus_read_resources 00007b46 T cardbus_enable_resources 00007ba1 T cardbus_scan_bus 00007baa T cardbus_scan_bridge 00007c8c T uart8250_tx_byte 00007cae T uart8250_can_rx_byte 00007cbd T uart8250_rx_byte 00007cd6 T uart8250_init 00007d17 T init_uart8250 00007d48 T dev_find_slot 00007d83 T dev_find_slot_on_smbus 00007dbe T dev_find_device 00007de8 T dev_find_class 00007e11 T path_eq 00007e70 T find_dev_path 00007ea0 T alloc_find_dev 00007ec8 T dev_path 00007fb7 T bus_path 00007fe2 T compact_resources 00008048 T probe_resource 00008079 T new_resource 00008118 T find_resource 00008160 T resource_end 000081c0 T resource_max 0000821b T resource_type 000082a0 T report_resource_stored 00008338 T search_bus_resources 000083b9 T search_global_resources 00008415 T dev_set_enabled 00008463 T disable_children 000084b0 T alloc_dev 00008549 t round 00008598 t read_resources 00008666 t pick_largest_resource 000086ee T compute_allocate_resource 00008914 T assign_resources 0000896a T enable_resources 000089a6 T reset_bus 000089dd T scan_bus 00008a74 T dev_enumerate 00008acd T dev_configure 00008c69 T dev_enable 00008c90 T dev_initialize 00008d2c T init_timer 00008d6f T udelay 00008dd0 T memcpy 00008df4 T memmove 00008e3c T pci_rom_probe 00008f1d T pci_rom_load 00008fd8 t pci_conf2_read_config8 00009020 t pci_conf2_read_config16 00009069 t pci_conf2_read_config32 000090b0 t pci_conf2_write_config8 000090f3 t pci_conf2_write_config16 00009137 t pci_conf2_write_config32 00009178 t pci_conf1_read_config8 000091b0 t pci_conf1_read_config16 000091e9 t pci_conf1_read_config32 00009213 t pci_conf1_write_config8 0000924f t pci_conf1_write_config16 0000928c t pci_conf1_write_config32 000092bc t rtc_checksum_valid 00009301 T rtc_init 00009400 T x86_enable_cache 00009428 T getIntVect 00009455 T pushw 0000947f T run_bios_int 000094d5 T x_inb 000094e1 T x_inw 000094ee T x_inl 000094f7 T x_outb 00009503 T x_outw 00009510 T x_outl 0000951c T do_int 00009583 T run_bios 000096d4 t str_tx_byte 000096e9 T vsprintf 0000970f T sprintf 00009724 T malloc_mark 00009734 T malloc_release 00009743 T malloc 0000978b T free 00009790 T memset 000097ac T pciexp_scan_bus 00009812 T pciexp_scan_bridge 00009828 T move_gdt 0000987b T write_tables 00009900 T acpi_fill_madt 00009905 T acpi_fill_srat 0000990a T write_acpi_tables 000099e4 T write_pirq_routing_table 000099f0 T pcix_scan_bus 00009af2 T pcix_speed 00009b3c T pcix_scan_bridge 00009ba8 T x86emu_intr_raise 00009be1 T X86EMU_exec 00009ceb T X86EMU_halt_sys 00009cfd T fetch_decode_modrm 00009d49 T fetch_byte_imm 00009d76 T fetch_word_imm 00009da0 T fetch_long_imm 00009dc7 t get_data_segment 00009e69 T fetch_data_byte 00009e83 T fetch_data_word 00009e9d T fetch_data_long 00009ebb T fetch_data_byte_abs 00009ed3 T fetch_data_word_abs 00009eeb T fetch_data_long_abs 00009f03 T store_data_byte 00009f28 T store_data_word 00009f4d T store_data_long 00009f6b T store_data_byte_abs 00009f8c T store_data_word_abs 00009fad T store_data_long_abs 00009fcd T decode_rm_byte_register 0000a036 T decode_rm_word_register 0000a09f T decode_rm_long_register 0000a108 T decode_rm_seg_register 0000a163 T decode_sib_si 0000a1d3 T decode_sib_address 0000a2b9 T decode_rm00_address 0000a3ba T decode_rm01_address 0000a4e3 T decode_rm10_address 0000a61d T decode_rmXX_address 0000a648 T acpi_create_fadt 0000a94c T verify_ip_checksum 0000aa33 T elfload 0000b27f T elfboot 0000b3e8 T elf_check_arch 0000b40f T jmp_to_elf_entry 0000b4dc T memcmp 0000b508 T acpi_checksum 0000b525 T acpi_add_table 0000b591 T acpi_create_madt_lapic 0000b5b8 T acpi_create_madt_ioapic 0000b5e2 T acpi_create_madt_irqoverride 0000b60f T acpi_create_madt_lapic_nmi 0000b636 T acpi_create_madt 0000b6c0 T acpi_create_srat_lapic 0000b6e7 T acpi_create_srat_mem 0000b72c T acpi_create_srat 0000b7af T acpi_create_hpet 0000b84c T acpi_create_facs 0000b8a4 T acpi_write_rsdt 0000b906 T acpi_write_rsdp 0000b958 T pcibios_handler 0000bb88 T x86emuOp_illegal_op 0000bbb4 T x86emuOp_genop_byte_RM_R 0000bc66 T x86emuOp_genop_word_RM_R 0000bd88 T x86emuOp_genop_byte_R_RM 0000be0e T x86emuOp_genop_word_R_RM 0000bef6 T x86emuOp_genop_byte_AL_IMM 0000bf32 T x86emuOp_genop_word_AX_IMM 0000bfa7 T x86emuOp_push_ES 0000bfc3 T x86emuOp_pop_ES 0000bfdd T x86emuOp_push_CS 0000bff9 T x86emuOp_two_byte 0000c032 T x86emuOp_push_SS 0000c04e T x86emuOp_pop_SS 0000c068 T x86emuOp_push_DS 0000c084 T x86emuOp_pop_DS 0000c09e T x86emuOp_segovr_ES 0000c0aa T x86emuOp_daa 0000c0cb T x86emuOp_segovr_CS 0000c0d7 T x86emuOp_das 0000c0f8 T x86emuOp_segovr_SS 0000c104 T x86emuOp_aaa 0000c126 T x86emuOp_segovr_DS 0000c132 T x86emuOp_aas 0000c154 T x86emuOp_inc_register 0000c1a5 T x86emuOp_dec_register 0000c1f6 T x86emuOp_push_register 0000c23a T x86emuOp_pop_register 0000c284 T x86emuOp_push_all 0000c366 T x86emuOp_pop_all 0000c422 T x86emuOp_segovr_FS 0000c42e T x86emuOp_segovr_GS 0000c43a T x86emuOp_prefix_data 0000c449 T x86emuOp_prefix_addr 0000c458 T x86emuOp_push_word_IMM 0000c49a T x86emuOp_imul_word_IMM 0000c5f4 T x86emuOp_push_byte_IMM 0000c613 T x86emuOp_imul_byte_IMM 0000c778 T x86emuOp_ins_byte 0000c78e T x86emuOp_ins_word 0000c7b2 T x86emuOp_outs_byte 0000c7c8 T x86emuOp_outs_word 0000c7ec T x86emuOp_jump_near_cond 0000c827 T x86emuOp_opc80_byte_RM_IMM 0000c8c3 T x86emuOp_opc81_word_RM_IMM 0000c9c3 T x86emuOp_opc82_byte_RM_IMM 0000ca5f T x86emuOp_opc83_word_RM_IMM 0000cb6d T x86emuOp_test_byte_RM_R 0000cbec T x86emuOp_test_word_RM_R 0000cca8 T x86emuOp_xchg_byte_RM_R 0000cd29 T x86emuOp_xchg_word_RM_R 0000cdf8 T x86emuOp_mov_byte_RM_R 0000ce64 T x86emuOp_mov_word_RM_R 0000cf10 T x86emuOp_mov_byte_R_RM 0000cf7a T x86emuOp_mov_word_R_RM 0000d02d T x86emuOp_mov_word_RM_SR 0000d09b T x86emuOp_lea_word_R_M 0000d0e6 T x86emuOp_mov_word_SR_RM 0000d153 T x86emuOp_pop_RM 0000d20f T x86emuOp_nop 0000d21e T x86emuOp_xchg_word_AX_register 0000d275 T x86emuOp_cbw 0000d2c0 T x86emuOp_cwd 0000d2fe T x86emuOp_call_far_IMM 0000d34a T x86emuOp_wait 0000d359 T x86emuOp_pushf_word 0000d38d T x86emuOp_popf_word 0000d3b9 T x86emuOp_sahf 0000d3d4 T x86emuOp_lahf 0000d3f0 T x86emuOp_mov_AL_M_IMM 0000d412 T x86emuOp_mov_AX_M_IMM 0000d44c T x86emuOp_mov_M_AL_IMM 0000d471 T x86emuOp_mov_M_AX_IMM 0000d4af T x86emuOp_movs_byte 0000d542 T x86emuOp_movs_word 0000d61e T x86emuOp_cmps_byte 0000d729 T x86emuOp_cmps_word 0000d8a1 T x86emuOp_test_AL_IMM 0000d8c6 T x86emuOp_test_AX_IMM 0000d917 T x86emuOp_stos_byte 0000d9bf T x86emuOp_stos_word 0000da83 T x86emuOp_lods_byte 0000db11 T x86emuOp_lods_word 0000dbc0 T x86emuOp_scas_byte 0000dce9 T x86emuOp_scas_word 0000deab T x86emuOp_mov_byte_register_IMM 0000ded4 T x86emuOp_mov_word_register_IMM 0000df1e T x86emuOp_opcC0_byte_RM_MEM 0000dfb6 T x86emuOp_opcC1_word_RM_MEM 0000e0b5 T x86emuOp_ret_near_IMM 0000e0df T x86emuOp_ret_near 0000e0f9 T x86emuOp_les_R_IMM 0000e15e T x86emuOp_lds_R_IMM 0000e1c3 T x86emuOp_mov_byte_RM_IMM 0000e24a T x86emuOp_mov_word_RM_IMM 0000e30e T x86emuOp_enter 0000e3a7 T x86emuOp_leave 0000e3cd T x86emuOp_ret_far_IMM 0000e402 T x86emuOp_ret_far 0000e427 T x86emuOp_int3 0000e49c T x86emuOp_int_IMM 0000e52a T x86emuOp_into 0000e5a8 T x86emuOp_iret 0000e5da T x86emuOp_opcD0_byte_RM_1 0000e65b T x86emuOp_opcD1_word_RM_1 0000e72f T x86emuOp_opcD2_byte_RM_CL 0000e7c4 T x86emuOp_opcD3_word_RM_CL 0000e8b6 T x86emuOp_aam 0000e8ff T x86emuOp_aad 0000e926 T x86emuOp_xlat 0000e952 T x86emuOp_loopne 0000e993 T x86emuOp_loope 0000e9d4 T x86emuOp_loop 0000ea0c T x86emuOp_jcxz 0000ea39 T x86emuOp_in_byte_AL_IMM 0000ea5c T x86emuOp_in_word_AX_IMM 0000ea9b T x86emuOp_out_byte_IMM_AL 0000eac1 T x86emuOp_out_word_IMM_AX 0000eb06 T x86emuOp_call_near_IMM 0000eb36 T x86emuOp_jump_near_IMM 0000eb52 T x86emuOp_jump_far_IMM 0000eb7c T x86emuOp_jump_byte_IMM 0000eb99 T x86emuOp_in_byte_AL_DX 0000ebbb T x86emuOp_in_word_AX_DX 0000ebfb T x86emuOp_out_byte_DX_AL 0000ec20 T x86emuOp_out_word_DX_AX 0000ec65 T x86emuOp_lock 0000ec74 T x86emuOp_repne 0000ec8b T x86emuOp_repe 0000eca1 T x86emuOp_halt 0000eccb T x86emuOp_cmc 0000ece1 T x86emuOp_opcF6_byte_RM 0000ee2d T x86emuOp_opcF7_word_RM 0000f08a T x86emuOp_clc 0000f0a0 T x86emuOp_stc 0000f0b6 T x86emuOp_cli 0000f0cf T x86emuOp_sti 0000f0e8 T x86emuOp_cld 0000f101 T x86emuOp_std 0000f11a T x86emuOp_opcFE_byte_RM 0000f1b4 T x86emuOp_opcFF_word_RM 0000f438 t set_parity_flag 0000f469 t set_szp_flags_8 0000f4a2 t set_szp_flags_16 0000f4e0 t set_szp_flags_32 0000f519 t no_carry_byte_side_eff 0000f52f t no_carry_word_side_eff 0000f545 t no_carry_long_side_eff 0000f555 t calc_carry_chain 0000f5d5 t calc_borrow_chain 0000f650 T aaa_word 0000f694 T aas_word 0000f6d8 T aad_word 0000f6fa T aam_word 0000f732 T adc_byte 0000f77a T adc_word 0000f7c2 T adc_long 0000f83c T add_byte 0000f874 T add_word 0000f8ac T add_long 0000f8f7 T and_byte 0000f910 T and_word 0000f929 T and_long 0000f93f T cmp_byte 0000f975 T cmp_word 0000f9a9 T cmp_long 0000f9da T daa_byte 0000fa29 T das_byte 0000fa74 T dec_byte 0000faa8 T dec_word 0000fada T dec_long 0000fb06 T inc_byte 0000fb3a T inc_word 0000fb6c T inc_long 0000fb98 T or_byte 0000fbb1 T or_word 0000fbca T or_long 0000fbe0 T neg_byte 0000fc2b T neg_word 0000fc74 T neg_long 0000fcb6 T not_byte 0000fcc3 T not_word 0000fcd0 T not_long 0000fcda T rcl_byte 0000fd8a T rcl_word 0000fe3a T rcl_long 0000fedd T rcr_byte 0000ffb2 T rcr_word
503,578c541,863 < 00010280 D _dev12 < 00010520 D _dev11 < 000107c0 D _dev19 < 00010a60 D _dev18 < 00010d00 D _dev17 < 00010fa0 D _dev16 < 00011240 D _dev9 < 000114e0 D _dev8 < 00011780 D _dev7 < 00011a20 D _dev6 < 00011cc0 D _dev5 < 00011f5c D southbridge_ricoh_rl5c476_info_20 < 00011f60 D _dev23 < 00012200 D _dev3 < 000124a0 D dev_root < 0001273c D last_dev_p < 00012740 d free_mem_end_ptr < 00012744 d free_mem_ptr < 00012760 D default_pciexp_ops_bus < 000127a0 D AmlCode < 00012ba0 D default_pcix_ops_bus < 00012be0 d elf_boot_notes < 00012c40 D southbridge_ricoh_rl5c476_ops < 00012c60 d ricoh_rl5c476_ops < 00012ca0 D northbridge_via_vt8623_ops < 00012cc0 d vga_operations < 00012d00 d agp_operations < 00012d40 d northbridge_operations < 00012d80 d cpu_bus_ops < 00012dc0 d pci_domain_ops < 00012e00 D superio_via_vt1211_ops < 00012e20 D ops < 00012e60 d vt1211hwmonitorinits < 00012ee0 d pnp_dev_info < 00012fbc D rom_end < 00012fc0 D rom_start < 00012fe0 D pnp_ops < 00013020 D option_table < 000134c0 d x86_vendors < 00013520 d x86_vendor_name < 0001354c A _bss < 0001354c D _edata < 00013560 b Irqs.1 < 00013564 B mainboard_via_epia_m_ops < 00013568 B vga_inited < 0001356c b vga_console_inited < 00013570 b vidmem < 00013574 b pci_bus_ops_pci < 00013578 b initialized < 0001357c b ht_bus_ops_pci < 00013580 b smbus_max < 000135a0 b buffer.2 < 000135c0 b buffer.1 < 000135e8 b buffer.0 < 000135fc b clocks_per_usec < 00013600 b str_buf < 00013604 b pciexp_bus_ops_pci < 00013608 b pcix_bus_ops_pci < 00013620 b header.0 < 00015620 b enable_cf_boot < 00015624 b cf_base < 00015628 b rom < 0001562c b mem_ranges < 00015630 B northbridge_via_vt8623_info_2 < 00015630 B superio_via_vt1211_info_10 < 00015638 B southbridge_via_vt8235_info_4 < 00015650 B vga_col < 00015654 B vga_line < 00015658 B mainboard_via_epia_m_info_0 < 0001565c A _ebss < 0001565c A _end < 00016000 A _stack < 00018000 A _estack < 00018000 A _heap < 0001c000 A _eheap < 0001c000 A _eram_seg ---
00010083 T rcr_long 0001014f T rol_byte 000101fe T rol_word 000102ab T rol_long 00010356 T ror_byte 000103f6 T ror_word 00010498 T ror_long 00010534 T shl_byte 000105f1 T shl_word 000106aa T shl_long 00010750 T shr_byte 0001080b T shr_word 000108a1 T shr_long 0001092c T sar_byte 000109d2 T sar_word 00010a74 T sar_long 00010b16 T shld_word 00010bdd T shld_long 00010c8e T shrd_word 00010d3a T shrd_long 00010dd7 T sbb_byte 00010e7c T sbb_word 00010f19 T sbb_long 00010fa6 T sub_byte 00011027 T sub_word 000110aa T sub_long 00011123 T test_byte 00011147 T test_word 0001116b T test_long 0001118c T xor_byte 000111a5 T xor_word 000111be T xor_long 000111d4 T imul_byte 00011218 T imul_word 00011263 T imul_long_direct 00011278 T imul_long 000112c9 T mul_byte 000112fb T mul_word 00011337 T mul_long 0001136c T idiv_byte 000113b4 T idiv_word 0001143b T idiv_long 000114d6 T div_byte 00011514 T div_word 0001159c T div_long 00011636 t single_in 000116c2 T ins 0001174a t single_out 000117d4 T outs 0001185c T mem_access_word 0001186d T push_word 0001189e T push_long 000118cd T pop_word 000118f7 T pop_long 00011920 T mem_ptr 0001195b T rdb 0001196d T rdw 0001197f T rdl 00011990 T wrb 000119a8 T wrw 000119c1 T wrl 000119d5 t p_inb 000119e1 t p_inw 000119ee t p_inl 000119f7 t p_outb 00011a03 t p_outw 00011a10 t p_outl 00011a1c T X86EMU_setupMemFuncs 00011a53 T X86EMU_setupPioFuncs 00011a8a T X86EMU_setupIntrFuncs 00011ac1 T X86EMU_prepareForInt 00011b26 T X86EMU_setMemBase 00011b3c t rl5c476_init 00011c78 T rl5c476_read_resources 00011cd2 T rl5c476_set_resources 00011d65 T southbridge_init 00011d7c T compute_ip_checksum 00011dcd T add_ip_checksums 00011e14 t northbridge_init 00011f2f t nullfunc 00011f34 t agp_init 00011f97 t vga_init 00012014 t vga_read_resources 0001202e t pci_domain_read_resources 0001207d t ram_resource 000120bd t tolm_test 000120ef t pci_domain_set_resources 00012207 t pci_domain_scan_bus 00012224 t cpu_bus_init 00012234 t cpu_bus_noop 00012239 t enable_dev 00012268 t gdtarg 0001226e t __mygdtaddr 00012274 t __mygdt 000122ac t __mygdt_end 000122ac t __myidt 000122b4 T vga_enable_console 000122b4 t real_mode_switch_end 000122cd t __vga_ec_16bit 000122e9 t __vga_ec_real 00012333 t vga_ec_restart 00012350 t vga_ec_exit 00012359 T do_vgabios 0001243a t __stack 00012452 t __rms_16bit 0001246e t __rms_real 000124a9 t vgarestart 000124c6 T vga_exit 0001250d T handler 00012510 t idthandle 00012519 t end_idthandle 0001251b T debughandler 0001251e t debughandle 00012522 t dbh1 00012526 t end_debughandle 00012528 T callbiosint 0001252b t callbiosint16 0001254b t biosprotect 0001256c t __rms_16bit2 00012588 t __rms_real2 000125b2 T handleint21 00012654 T setup_realmode_idt 000126ec T pcibios 000128e9 T biosint 00012a98 T copy_pirq_routing_table 00012c30 t pnp_enter_ext_func_mode 00012c3e t pnp_exit_ext_func_mode 00012c4c t vt1211_init 00012cd1 T vt1211_pnp_enable_resources 00012d08 T vt1211_pnp_set_resources 00012e91 T vt1211_pnp_enable 00012ec6 t enable_dev 00012eec T x86emuOp_esc_coprocess_d8 00012efb T x86emuOp_esc_coprocess_d9 00012f55 T x86emuOp_esc_coprocess_da 00012faf T x86emuOp_esc_coprocess_db 00013009 T x86emuOp_esc_coprocess_dc 00013063 T x86emuOp_esc_coprocess_dd 000130bd T x86emuOp_esc_coprocess_de 00013117 T x86emuOp_esc_coprocess_df 00013174 T stream_init 0001319f T stream_fini 000131a4 T stream_skip 000131ef T stream_read 00013218 T x86emu_dump_regs 0001342c T x86emu_dump_xregs 00013630 T x86emuOp2_illegal_op 00013673 T x86emu_check_jump_condition 00013738 T x86emuOp2_long_jump 00013777 T x86emuOp2_set_byte 000138aa T x86emuOp2_push_FS 000138c6 T x86emuOp2_pop_FS 000138e0 T x86emuOp2_bt_R 000139e0 T x86emuOp2_shld_IMM 00013aff T x86emuOp2_shld_CL 00013c08 T x86emuOp2_push_GS 00013c24 T x86emuOp2_pop_GS 00013c3e T x86emuOp2_bts_R 00013dcd T x86emuOp2_shrd_IMM 00013eec T x86emuOp2_shrd_CL 00013ff5 T x86emuOp2_imul_R_RM 00014131 T x86emuOp2_lss_R_IMM 00014196 T x86emuOp2_btr_R 0001432d T x86emuOp2_lfs_R_IMM 00014392 T x86emuOp2_lgs_R_IMM 000143f7 T x86emuOp2_movzx_byte_R_RM 000144b3 T x86emuOp2_movzx_word_R_RM 00014521 T x86emuOp2_btX_I 00014769 T x86emuOp2_btc_R 000148f8 T x86emuOp2_bsf 00014a82 T x86emuOp2_bsr 00014c08 T x86emuOp2_movsx_byte_R_RM 00014cc2 T x86emuOp2_movsx_word_R_RM 00014d30 T initialize_cpus 00014d70 t pci_sanity_check 00014de4 T pci_check_direct 00014e8c T pci_set_method 00014ec0 T lb_table_init 00014f00 T lb_first_record 00014f0b T lb_last_record 00014f19 T lb_next_record 00014f24 T lb_new_record 00014f65 T lb_memory 00014f7f T lb_mainboard 0001505b T lb_cmos_checksum 00015091 T lb_strings 000150ef T lb_memory_range 00015154 T get_lb_mem 0001515e T lb_table_fini 0001531c t lb_cleanup_memory_ranges 000155b7 t lb_add_memory_range 00015896 t build_lb_mem_range 000158b3 T write_linuxbios_table 00015980 T set_boot_successful 000159ab T boot_successful 000159b4 T pnp_write_config 000159ce T pnp_read_config 000159e4 T pnp_set_logical_device 000159f9 T pnp_set_enable 00015a12 T pnp_read_enable 00015a2b T pnp_set_iobase 00015a6b T pnp_set_irq 00015a82 T pnp_set_drq 00015a99 T pnp_read_resources 00015a9e T pnp_set_resources 00015b8b T pnp_enable_resources 00015ba5 T pnp_enable 00015bc8 t pnp_get_ioresource 00015c47 T pnp_enable_devices 00015dc8 t have_cpuid_p 00015dea T cpu_initialize 00016030 T __divdi3 000161c0 T __moddi3 000163f0 T __udivdi3 00016540 T __umoddi3 00016720 R _rodata 00016720 R console_drivers 00016720 T _etext 00016720 r uart8250_console 00016734 r vga_console 00016748 R econsole_drivers 00016748 R pci_drivers 00016748 r lpc_driver 00016750 r northbridge_driver 00016758 r northbridge_driver 00016760 r ricoh_rl5c476_driver 00016768 r vga_driver 00016770 r agp_driver 00016778 r northbridge_driver 00016780 R cpu_drivers 00016780 R epci_drivers 00016780 r driver 00016788 R ecpu_drivers 000167a0 r riserPins 000167a4 r cbPins 000167a8 r slotPins 000167ac r vgaPins 000167b0 r enetPins 000167b4 r vt8235Pins 000167b8 r usbPins 000167bc r firewirePins 000167c0 r pciIrqs 000167c4 r __FUNCTION__.0 000167d6 r div.0 000167de r __FUNCTION__.0 000167e7 r __func__.0 00016800 R linuxbios_assembler 00016860 R linuxbios_linker 000168a0 R linuxbios_compiler 000168e2 R linuxbios_compile_domain 000168e3 R linuxbios_compile_host 000168e6 R linuxbios_compile_by 000168eb R linuxbios_compile_time 000168f4 R linuxbios_build 00016911 R linuxbios_extra_version 0001691c R linuxbios_version 00016922 R mainboard_part_number 00016929 R mainboard_vendor 0001692d r link_width_to_pow2.0 00016935 r pow2_to_link_width.1 00016988 R pci_cf8_conf2 000169a0 R pci_cf8_conf1 000169c0 R intel_irq_routing_table 00016a30 r conventional.0 00016a41 r pcix_66mhz.1 00016a4d r pcix_100mhz.2 00016a5a r pcix_133mhz.3 00016a67 r pcix_266mhz.4 00016a74 r pcix_533mhz.5 00016a81 r unknown.6 00016acc r __func__.0 00016d7c r ramregs.0 00016d98 r __FUNCTION__.0 00016de4 r __FUNCTION__.1 00016df0 r __FUNCTION__.0 00016e80 r strings.0 00018c84 R _erodata 00018d20 D _data 00018d20 D gdt 00018d48 D gdt_end 00018d48 D idtarg 00018d50 d _idt 00018df0 d _idt_end 00018e00 d vt8235_lpc_ops 00018e2c D southbridge_via_vt8235_ops 00018e40 d ide_ops 00018e80 d nic_ops 00018ec0 d cpu_table 00018f40 d cpu_dev_ops 00018f80 d mtrr_msr 00018fac D default_console_loglevel 00018fb0 D minimum_console_loglevel 00018fb4 D default_message_loglevel 00018fb8 D console_loglevel 00018fc0 D default_pci_ops_bus 00019000 D default_pci_ops_dev 0001902c d pci_dev_ops_pci 00019040 D default_ht_ops_bus 00019080 D default_dev_ops_root 000190c0 D default_cardbus_ops_bus 000190ec D all_devices 000190f0 d pci_ram_image_start 000190f4 D myfuncs 00019120 D _dev25 000193c0 D _dev22 00019660 D _dev21 00019900 D _dev15 00019ba0 D _dev14 00019e40 D _dev13 0001a0e0 D _dev12 0001a380 D _dev11 0001a620 D _dev19 0001a8c0 D _dev18 0001ab60 D _dev17 0001ae00 D _dev16 0001b0a0 D _dev9 0001b340 D _dev8 0001b5e0 D _dev7 0001b880 D _dev6 0001bb20 D _dev5 0001bdbc D southbridge_ricoh_rl5c476_info_20 0001bdc0 D _dev23 0001c060 D _dev3
579a865,937
0001c300 D dev_root 0001c59c D last_dev_p 0001c5a0 d free_mem_end_ptr 0001c5a4 d free_mem_ptr 0001c5c0 D default_pciexp_ops_bus 0001c600 D AmlCode 0001ca00 D default_pcix_ops_bus 0001ca40 d elf_boot_notes 0001caa0 D x86emu_optab 0001cea0 d opcD1_word_operation 0001cec0 d opcD1_long_operation 0001cee0 d opcD0_byte_operation 0001cf00 d genop_word_operation 0001cf20 d genop_long_operation 0001cf40 d genop_byte_operation 0001cf60 d x86emu_parity_tab 0001cf80 D sys_outl 0001cf84 D sys_outw 0001cf88 D sys_outb 0001cf8c D sys_inl 0001cf90 D sys_inw 0001cf94 D sys_inb 0001cf98 D sys_wrl 0001cf9c D sys_wrw 0001cfa0 D sys_wrb 0001cfa4 D sys_rdl 0001cfa8 D sys_rdw 0001cfac D sys_rdb 0001cfc0 D southbridge_ricoh_rl5c476_ops 0001cfe0 d ricoh_rl5c476_ops 0001d020 D northbridge_via_vt8623_ops 0001d040 d vga_operations 0001d080 d agp_operations 0001d0c0 d northbridge_operations 0001d100 d cpu_bus_ops 0001d140 d pci_domain_ops 0001d180 D superio_via_vt1211_ops 0001d1a0 D ops 0001d1e0 d vt1211hwmonitorinits 0001d260 d pnp_dev_info 0001d33c D rom_end 0001d340 D rom_start 0001d360 D x86emu_optab2 0001d760 D pnp_ops 0001d7a0 D option_table 0001dc40 d x86_vendors 0001dca0 d x86_vendor_name 0001dccc A _bss 0001dccc D _edata 0001dce0 b Irqs.1 0001dce4 B mainboard_via_epia_m_ops 0001dce8 B vga_inited 0001dcec b vga_console_inited 0001dcf0 b vidmem 0001dcf4 b pci_bus_ops_pci 0001dcf8 b initialized 0001dcfc b ht_bus_ops_pci 0001dd00 b smbus_max 0001dd20 b buffer.2 0001dd40 b buffer.1 0001dd68 b buffer.0 0001dd7c B vga_pri 0001dd80 b clocks_per_usec 0001dd84 b str_buf 0001dd88 b pciexp_bus_ops_pci 0001dd8c b pcix_bus_ops_pci 0001dda0 b header.0 0001fda0 b enable_cf_boot 0001fda4 b cf_base 0001fda8 b rom 0001fdac b mem_ranges 0001fdc0 B _X86EMU_intrTab 0001fdc0 B northbridge_via_vt8623_info_2
580a939,951
000201c0 B superio_via_vt1211_info_10 000201c8 B southbridge_via_vt8235_info_4 000201e0 B vga_col 000201e4 B vga_line 000201e8 B mainboard_via_epia_m_info_0 00020200 B _X86EMU_env 00020384 A _ebss 00020384 A _end 00022000 A _stack 00024000 A _estack 00024000 A _heap 00028000 A _eheap 00028000 A _eram_seg
Binary files LinuxBIOSv2/targets/via/epia-m/epia-m/fallback/linuxbios_ram.nrv2b and LinuxBIOSv2.bad/targets/via/epia-m/epia-m/fallback/linuxbios_ram.nrv2b differ Binary files LinuxBIOSv2/targets/via/epia-m/epia-m/fallback/linuxbios_ram.o and LinuxBIOSv2.bad/targets/via/epia-m/epia-m/fallback/linuxbios_ram.o differ Binary files LinuxBIOSv2/targets/via/epia-m/epia-m/fallback/linuxbios_ram.rom and LinuxBIOSv2.bad/targets/via/epia-m/epia-m/fallback/linuxbios_ram.rom differ Only in LinuxBIOSv2/targets/via/epia-m/epia-m/fallback: payload Binary files LinuxBIOSv2/targets/via/epia-m/epia-m/fallback/pci_device.o and LinuxBIOSv2.bad/targets/via/epia-m/epia-m/fallback/pci_device.o differ Binary files LinuxBIOSv2/targets/via/epia-m/epia-m/fallback/version.o and LinuxBIOSv2.bad/targets/via/epia-m/epia-m/fallback/version.o differ Only in LinuxBIOSv2/targets/via/epia-m/epia-m: linuxbios.rom
Stefan Reinauer wrote:
- Eric Poulsen eric@zyxod.com [060501 06:45]:
buildtarget make clean make Crash, exception 13 just after vga write protect
- vs -
buildtarget make [Everything works -- boots, VGA works, etc. ] [Important thing to note about the above is that the ROM_IMAGE_SIZE _was not_ increased]
This sounds very weird. Are you doing this on the same system using the same compiler? I suspect this is on 2 systems or using different compilers or binutils, since these factors can and do affect code size a lot (and make things break)
I just tried a "make clean" in a freshly created buildtree (using buildtarget) and its exactly the same as without "make clean"
Can you try the same and check whether its different?
It's the same for me, too.
Stefan
-
Daniel Parthey -
Eric Poulsen -
Richard Smith -
Ronald G Minnich -
Stefan Reinauer