Re: [coreboot] vga not working

[Kevin O'Connor]

On Sun, Jul 26, 2009 at 01:00:52PM +0200, Arnaud Maye wrote:
> I've been on IRC for a GFX output issue on Friday. Actually the
> output is always black or full of non sense square on the screen. I
> have tried two graphic cards and in this respect it is fair to point
> the issue outside of the vgarom.

[...]
> Scan for VGA option rom
> Attempting to init PCI bdf 07:00.0 (dev/ven 42110de)
> Searching CBFS for data file pci10de,0421.rom
> Found CBFS file fallback/payload
> Found CBFS file fallback/coreboot_ram
> Found CBFS file pci10de,0421.rom
> Copying data 58368@0xffe17a98 to 196608@0x000c0000
> Checking rom 0x000c0000 (sig aa55 size 114)
> Running option rom at c000:0003

How did you obtain the vgabios?  Is this a vga adapter built-in to the
motherboard, or one on an external card?

For vga adapters on external cards, one should not add the vgabios to
CBFS - SeaBIOS can extract the vgabios directly from the card.

-Kevin

vga not working

[Arnaud Maye]

Hello Kevin,

So the vgabios came from the manufacturer in fact. I have removed the 
vgabios from the cbfs and
indeed seabios seems to execute the vgabios extracted from the card.

I have tried two GFX cards :
- Matrox G550 pci express 1 lane
- Club3D 8500GT Silent edition 16 lanes

Both of the cards behaving same besides colors of the squares. As an 
additional note, seabios does
boot my Linux from the HDD as there is a lot of activity on the hard 
disk led. It seems the faulty output
is displaying something as we can see the output moving in sync with 
what is supposed to be the linux
boot.

Attached is the boot log when the 8500GT card is attached. Being unsure 
about the maximum attachment
size in the mailing list I've been uploading video of the faulty output 
there :

http://www.gigasize.com/get.php?d=z15rwqb3zqc

The G550 output look same as the 8500GT output. The only difference is 
that most of the grey square are
black.

Any idea what I could be doing wrong Kevin?

Thank you.

Arnaud

Kevin O'Connor wrote:
> On Sun, Jul 26, 2009 at 01:00:52PM +0200, Arnaud Maye wrote:
> > I've been on IRC for a GFX output issue on Friday. Actually the
> > output is always black or full of non sense square on the screen. I
> > have tried two graphic cards and in this respect it is fair to point
> > the issue outside of the vgarom.
>
> [...]
> > Scan for VGA option rom
> > Attempting to init PCI bdf 07:00.0 (dev/ven 42110de)
> > Searching CBFS for data file pci10de,0421.rom
> > Found CBFS file fallback/payload
> > Found CBFS file fallback/coreboot_ram
> > Found CBFS file pci10de,0421.rom
> > Copying data 58368@0xffe17a98 to 196608@0x000c0000
> > Checking rom 0x000c0000 (sig aa55 size 114)
> > Running option rom at c000:0003
>
> How did you obtain the vgabios?  Is this a vga adapter built-in to the
> motherboard, or one on an external card?
>
> For vga adapters on external cards, one should not add the vgabios to
> CBFS - SeaBIOS can extract the vgabios directly from the card.
>
> -Kevin

*
*

coreboot-2.0.0-r4463M" Mon Jul 27 19:21:56 CEST 2009 starting...
PCI: 00:00.00
PCI: 00:10.00
PCI: 02:00.00
PCI: 05:00.00
PCI: 0e:10.00
PCI: 0e:1e.00
PCI: 0f:10.00
PCI: 0f:14.00
PCI: 0f:16.00
PCI: 0f:18.00
SMBus controller enabled

dimm 50
00: bad device: 01

dimm 51
00: bad device: 01

dimm 52
00: 80 08 08 0e 0a 60 48 00 05 30 45 06 82 08 08 00 
10: 0c 04 38 01 01 04 07 3d 50 50 60 3c 1e 3c 27 80 
20: 20 27 10 17 3c 1e 1e 00 00 36 69 80 18 22 0f 00 
30: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 12 94 
40: 7f 98 00 00 00 00 00 00 04 00 00 00 00 00 00 00 
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 09 17 e5 
60: 04 60 ae 00 00 00 00 00 00 00 00 00 00 00 00 00 
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
f0: 39 39 36 35 33 34 31 2d 30 30 31 2e 41 30 32 4c

dimm 53
00: bad device: 01

dimm 54
00: bad device: 01

dimm 55
00: bad device: 01

dimm 56
00: bad device: 01

dimm 57
00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
10: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
30: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
40: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
50: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
60: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
70: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
80: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
90: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
b0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
c0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
d0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
e0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
f0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
Ram1.00
Ram2.00
spd 52 = 08
spd 53 = ff
Ram3
spd 52 = 08
spd 53 = ff
Starting SDRAM Enable
cycle = 30
msr 0xcd = 0000000000000201
533 MHz FSB
333 MHz DDR
DRC = c0100017
dimm 52 size = 20.00
DRB = 08080808
TOM = 0004
TOLM = 2000
dimm 00 reg = 1a
DRA00 = 20804555
cl = 05
trc = 13
trfc = 23
tras = 0d
trtp = 03
twtr = 03
drt0 = 24368492
drt1 = 52718000
magic = 009a62b1
mrs = 09520000

0000: 00000000 00000000 00000000 00000000 
0010: 00000000 00000000 00000000 00000000 
0020: 00000000 00000000 00000000 00000000 
0030: 00000000 00000000 00000000 00000000 
0040: 00000000 00000000 00000000 00000000 
0050: 00000000 00000000 00000000 00000000 
0060: 00000000 00000000 00000000 00000000 
0070: 00000000 00000000 00000000 00000000 
0080: 00000000 00000000 00000000 00000000 
0090: 000f000f 00180810 5c141400 00000000 
00a0: 00000000 06060606 06060606 00000000 
00b0: 00000000 00000000 00000000 00000000 
00c0: 00000000 00000006 000db6c0 00000000 
00d0: 00000000 aaaa0a05 5b339c5d aaabffff 
00e0: db339ce1 00000000 55555555 aaaaaaaa 
00f0: 00000000 00000000 00001011 00000000 
0100: 00000000 00000000 00000000 00000000 
0110: 00000000 00000000 00000000 00000000 
0120: 00000000 00000000 00000000 00000000 
0130: 00000000 00000000 00000000 00000000 
0140: 00000000 00000000 00000000 00000000 
0150: 00000000 00000000 00000000 00000000 
0160: 00000000 00000000 00000000 00000000 
0170: 00000000 00000000 00000000 00000000 
0180: 00000000 00000000 00000000 00000000 
0190: 00000000 00000000 00000000 00000000 
01a0: 00000000 00000000 00000000 00000000 
01b0: 00000000 00000000 00000000 00000000 
01c0: 00000000 00000000 00000000 00000000 
01d0: 00000000 00000000 00000000 00000000 
01e0: 00000000 00000000 00000000 00000000 
01f0: 00000000 00000000 00000000 00000000 
0200: 00000000 00000000 00000000 00000000 
0210: 00000000 00000000 00000000 00000000 
0220: 00000000 00000000 00000000 00000000 
0230: 00000000 00000000 00000000 00000000 
0240: 00000000 00000000 00000000 00000000 
0250: 00000000 00000000 00000000 00000000 
0260: 00000078 52520000 039e6000 00000000 
0270: 00000000 00000000 00000000 00000000 
0280: 00010002 00000000 00000000 00000000 
0290: 00000000 00000000 00000000 00000000 
NOP CS00
NOP CS01
NOP CS00
NOP CS01
Precharge CS00
Precharge CS01
EMRS CS00
EMRS CS01
MRS CS00
MRS CS01
Precharge CS00
Precharge CS01
Refresh CS00
Refresh CS01
Refresh CS00
Refresh CS01
MRS CS00
MRS CS01
EMRS CS00
EMRS CS01
ODT Value = 00000010
ODT CS00
ODT CS01

0000: 00100000 00000000 00000000 00000000 
0010: 00000000 00000000 00000000 00000000 
0020: 00000000 00000000 00000000 00000000 
0030: 00000000 00000000 00000000 00000000 
0040: 00400003 0b840001 00000000 00000000 
0050: 00000000 00000000 00000000 00000000 
0060: 00000000 00000000 00000000 00000000 
0070: 00000000 00000000 00000000 00000000 
0080: 00000000 00000000 00000000 00000000 
0090: 000f000f 00180810 5c141400 00000000 
00a0: 00000000 06060606 06060606 00000000 
00b0: 00000000 00000000 00000000 00000000 
00c0: 00000000 00000006 000db6c0 00000000 
00d0: 00000000 aaaa0a05 5b339c5d aaabffff 
00e0: db339ce1 00000000 55555555 aaaaaaaa 
00f0: 00000000 00000000 00001011 00000000 
0100: 00000000 00000000 00000000 00000000 
0110: 00000000 00000000 00000000 00000000 
0120: 00000000 00000000 00000000 00000000 
0130: 00000000 00000000 00000000 00000000 
0140: 00000000 00000000 00000000 00000000 
0150: 00000000 00000000 00000000 00000000 
0160: 00000000 00000000 00000000 00000000 
0170: 00000000 00000000 00000000 00000000 
0180: 00000000 00000000 00000000 00000000 
0190: 00000000 00000000 00000000 00000000 
01a0: 00000000 00000000 00000000 00000000 
01b0: 00000000 00000000 00000000 00000000 
01c0: 00000000 00000000 00000000 00000000 
01d0: 00000000 00000000 00000000 00000000 
01e0: 00000000 00000000 00000000 00000000 
01f0: 00000000 00000000 00000000 00000000 
0200: 00000000 00000000 00000000 00000000 
0210: 00000000 00000000 00000000 00000000 
0220: 00000000 00000000 00000000 00000000 
0230: 00000000 00000000 00000000 00000000 
0240: 00000000 00000000 00000000 00000000 
0250: 00000000 00000000 00000000 00000000 
0260: 00000078 52520000 039e6000 00000000 
0270: 00000000 00000000 00000000 00000000 
0280: 00010002 00000000 00000000 00000000 
0290: 00000000 00000000 00000000 00000000 
receive enable calibration CS00

0000: 00100000 00000000 00000000 00000000 
0010: 00000000 00000000 00000000 00000000 
0020: 00000000 00000000 00000000 00000000 
0030: 00000000 00000000 00000000 00000000 
0040: 0020000c 0b840001 f834f834 e834e834 
0050: f834f834 f834f834 e834e834 e834e834 
0060: f834f834 f834f834 f834f834 f834f834 
0070: e834e834 f834f834 f834f834 e834e834 
0080: e834e834 f834f834 f834f834 f834f834 
0090: 000f000f 00180810 5c141400 00000000 
00a0: 00000000 24242424 24242424 00000000 
00b0: 00000000 00000000 00000000 00000000 
00c0: 00000000 00000024 000db6c0 00000000 
00d0: 00000000 aaaa0a05 5b339c5d aaabffff 
00e0: db339ce1 00000000 55555555 aaaaaaaa 
00f0: 00000000 00000000 00001011 00000000 
0100: 00000000 00000000 00000000 00000000 
0110: 00000000 00000000 00000000 00000000 
0120: 00000000 00000000 00000000 00000000 
0130: 00000000 00000000 00000000 00000000 
0140: 00000000 00000000 00000000 00000000 
0150: 00000000 00000000 00000000 00000000 
0160: 00000000 00000000 00000000 00000000 
0170: 00000000 00000000 00000000 00000000 
0180: 00000000 00000000 00000000 00000000 
0190: 00000000 00000000 00000000 00000000 
01a0: 00000000 00000000 00000000 00000000 
01b0: 00000000 00000000 00000000 00000000 
01c0: 00000000 00000000 00000000 00000000 
01d0: 00000000 00000000 00000000 00000000 
01e0: 00000000 00000000 00000000 00000000 
01f0: 00000000 00000000 00000000 00000000 
0200: 00000000 00000000 00000000 00000000 
0210: 00000000 00000000 00000000 00000000 
0220: 00000000 00000000 00000000 00000000 
0230: 00000000 00000000 00000000 00000000 
0240: 00000000 00000000 00000000 00000000 
0250: 00000000 00000000 00000000 00000000 
0260: 00000078 52520000 039e6000 00000000 
0270: 00000000 00000000 00000000 00000000 
0280: 00010002 00000000 00000000 00000000 
0290: 00000000 00000000 00000000 00000000

0000: 00100000 00000000 00000000 00000000 
0010: 00000000 00000000 00000000 00000000 
0020: 00000000 00000000 00000000 00000000 
0030: 00000000 00000000 00000000 00000000 
0040: 0020000c 0b840001 f834f834 e834e834 
0050: f834f834 f834f834 e834e834 e834e834 
0060: f834f834 f834f834 f834f834 f834f834 
0070: e834e834 f834f834 f834f834 e834e834 
0080: e834e834 f834f834 f834f834 f834f834 
0090: 000f000f 00180810 5c141400 00000000 
00a0: 00000000 24242424 24242424 00000000 
00b0: 00000000 00000000 00000000 00000000 
00c0: 00000000 00000024 000db6c0 00000000 
00d0: 00000000 aaaa0a05 5b339c5d aaabffff 
00e0: db339ce1 00000000 55555555 aaaaaaaa 
00f0: 00000000 00000000 00001011 00000000 
0100: 00000000 00000000 00000000 00000000 
0110: 00000000 00000000 00000000 00000000 
0120: 00000000 00000000 00000000 00000000 
0130: 00000000 00000000 00000000 00000000 
0140: 00000000 00000000 00000000 00000000 
0150: 00000000 00000000 00000000 00000000 
0160: 00000000 00000000 00000000 00000000 
0170: 00000000 00000000 00000000 00000000 
0180: 00000000 00000000 00000000 00000000 
0190: 00000000 00000000 00000000 00000000 
01a0: 00000000 00000000 00000000 00000000 
01b0: 00000000 00000000 00000000 00000000 
01c0: 00000000 00000000 00000000 00000000 
01d0: 00000000 00000000 00000000 00000000 
01e0: 00000000 00000000 00000000 00000000 
01f0: 00000000 00000000 00000000 00000000 
0200: 00000000 00000000 00000000 00000000 
0210: 00000000 00000000 00000000 00000000 
0220: 00000000 00000000 00000000 00000000 
0230: 00000000 00000000 00000000 00000000 
0240: 00000000 00000000 00000000 00000000 
0250: 00000000 00000000 00000000 00000000 
0260: 00000078 52520000 039b6000 00000000 
0270: 00000000 00000000 00000000 00000000 
0280: 00010002 00000000 00000000 00000000 
0290: 00000000 00000000 00000000 00000000 
clear memory CS00
clear read/write fifo pointers

0000: 00100000 00000000 00000000 00000000 
0010: 00000000 00000000 00000000 00000000 
0020: 00000000 00000000 00000000 00000000 
0030: 00000000 00000000 00000000 00000000 
0040: 0000000f 0b840001 f834f834 e834e834 
0050: f834f834 f834f834 e834e834 e834e834 
0060: f834f834 f834f834 f834f834 f834f834 
0070: e834e834 f834f834 f834f834 e834e834 
0080: e834e834 f834f834 f834f834 f834f834 
0090: 000f000f 00180810 5c141400 00000000 
00a0: 00000000 24242424 24242424 00000000 
00b0: 00000000 00000000 00000000 00000000 
00c0: 00000000 00000024 000db6c0 00000000 
00d0: 00000000 aaaa0a05 5b339c5d aaabffff 
00e0: db339ce1 00000000 55555555 aaaaaaaa 
00f0: 00000000 00000000 00001011 00000000 
0100: 00000000 00000000 00000000 00000000 
0110: 00000000 00000000 00000000 00000000 
0120: 00000000 00000000 00000000 00000000 
0130: 00000000 00000000 00000000 00000000 
0140: 201000f0 00000000 00000000 00000000 
0150: 00000000 00000000 00000000 00000000 
0160: 00000000 00000000 00000000 00000000 
0170: 00000000 00000000 00000000 00000000 
0180: 00000000 00000000 00000000 00000000 
0190: 00000000 00000000 00000000 00000000 
01a0: 00000000 00000000 00000000 00000000 
01b0: 00000000 00000000 00000000 00000000 
01c0: 00000000 00000000 00000000 00000000 
01d0: 00000000 00000000 00000000 00000000 
01e0: 00000000 00000000 00000000 00000000 
01f0: 00000000 00000000 00000000 00000000 
0200: 00000000 00000000 00000000 00000000 
0210: 00000000 00000000 00000000 00000000 
0220: 00000000 00000000 00000000 00000000 
0230: 00000000 00000000 00000000 00000000 
0240: 00000000 00000000 00000000 00000000 
0250: 00000000 00000000 00000000 00000000 
0260: 00000078 52520000 039b6000 00000000 
0270: 00000000 00000000 00000000 00000000 
0280: 00010002 00000000 00000000 00000000 
0290: 00000000 00000000 00000000 00000000 
Done
Ram4
PCI: 00:00.00
00: 86 80 20 50 06 00 10 20 01 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 90 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
40: 09 00 05 21 7f 00 00 00 00 00 00 00 00 00 00 00
50: 0c 00 00 00 00 00 00 00 00 30 33 33 33 33 33 33
60: 08 08 08 08 00 80 71 52 00 00 00 00 00 00 00 00
70: 55 45 80 20 15 05 00 00 92 84 36 24 17 00 10 e0
80: 11 00 00 00 00 00 00 00 30 2c 00 a0 00 00 00 00
90: 00 00 00 00 00 00 00 00 aa 02 00 00 1f 08 42 07
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b0: 10 00 00 00 00 00 00 00 ff ff 0f 00 00 00 00 00
c0: 44 c0 50 11 00 20 ff 03 00 00 00 00 04 00 00 e0
d0: 00 00 00 00 03 00 00 00 00 60 31 b5 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 3a 00 40 00 90 0f 01 00 00 00 03 00
PCI: 00:02.00
00: 86 80 21 50 00 00 00 00 01 00 00 ff 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 20 00 00 00 20 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 09 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 20 00 00 00 04 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 00:10.00
00: 86 80 23 50 00 00 10 00 01 00 80 08 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 b0 00 00 00 00 00 00 00 00 01 00 00
40: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 05 00 02 00 00 00 e0 fe 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 01:00.00
00: 86 80 24 50 00 00 10 00 01 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00
20: f0 ff 00 00 f1 ff 01 00 0f 00 00 00 00 00 00 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 00 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 58 22 c8 00 00 00 00 05 64 02 00 00 00 e0 fe
60: 00 00 00 00 10 00 41 00 01 00 00 00 00 00 00 00
70: 81 e4 03 02 01 00 01 10 00 00 00 00 c0 01 40 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 30 00 0c 00 01 00 08 00 00 00 84 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 40 00 30 00 0c 00 01 00 08 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 01:10.00
00: 86 80 25 50 00 00 10 00 01 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00
20: f0 ff 00 00 f1 ff 01 00 0f 00 00 00 00 00 00 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 00 01 00 00
40: 00 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00
50: 01 58 22 c8 00 00 00 00 05 64 02 00 00 00 e0 fe
60: 00 00 00 00 10 00 41 00 01 00 00 00 00 00 00 00
70: 41 e4 03 03 01 00 41 30 00 00 00 00 c0 01 40 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 30 00 0c 00 01 00 08 00 00 00 84 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 48 00 30 00 0c 00 01 00 08 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 02:00.00
00: 86 80 37 50 00 00 10 00 01 00 04 06 00 00 01 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 f0 00 00 00
20: f0 ff 00 00 f1 ff 01 00 0f 00 00 00 00 00 00 00
30: 00 00 00 00 dc 00 00 00 00 00 00 00 00 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 23 00
e0: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 04:00.00
00: 86 80 26 50 00 00 80 00 01 00 80 08 00 00 00 00
10: 00 00 00 20 00 00 00 40 00 00 00 60 00 00 00 80
20: 00 00 00 a0 00 00 00 c0 00 00 00 e0 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 40 62 00 00 00 00 00 00 00 00 00 00 8c 64 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 10 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 08 00 14 00 00 00 00 00 00 00 00 00
c0: 00 08 00 00 00 00 00 00 00 00 00 00 b1 62 9a 00
d0: 00 00 00 20 00 00 00 00 00 00 00 00 00 00 00 00
e0: 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 40 00 f8 ff ff ff ff ff 1f 00 00 00 00 00
PCI: 06:10.00
00: 86 80 22 50 00 00 00 00 01 00 00 ff 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 06:12.00
00: 86 80 4d 50 00 00 00 00 01 00 00 ff 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
PCI: 0e:10.00
00: 86 80 33 50 00 00 80 02 01 00 03 0c 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 90 0f 01 00 00 00 00 00
PCI: 0e:1e.00
00: 86 80 35 50 00 00 90 02 01 20 03 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 ef db 6c f7
30: 00 00 00 00 50 00 00 00 00 00 00 00 00 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 58 c2 c9 00 00 00 00 0a 00 a0 20 00 00 00 00
60: 20 20 ff 01 00 00 00 00 01 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: ff 7f 00 18 3c fc 00 58 00 0c 00 00 24 09 00 00
d0: 00 00 00 00 00 aa ff 00 92 f4 ff 00 20 00 90 00
e0: 00 00 00 00 00 18 f0 4f 00 00 00 00 00 00 00 00
f0: 00 80 00 09 88 8c 40 00 90 0f 01 00 06 17 00 00
PCI: 0f:10.00
00: 86 80 31 50 07 00 00 02 01 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 01 40 00 00 00 00 00 00 01 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 80 80 80 80 10 00 00 00 80 80 80 80 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 10 00 0f 34 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 02 04 00 32 00 00 00 00 00 00 00 00 00 30 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 33 22 11 00 67 45 00 00 cf ff 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 90 0f 01 00 00 00 00 00
PCI: 0f:14.00
00: 86 80 28 50 00 00 b0 02 01 8a 01 01 00 00 00 00
10: 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00
20: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 70 00 00 00 00 00 00 00 00 02 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 01 00 02 40 00 00 00 00 00 00 00 00 00 00 00 00
80: 05 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 90 0f 01 00 00 00 00 00
PCI: 0f:16.00
00: 86 80 32 50 01 00 80 02 01 00 05 0c 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 01 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 02 00 00
40: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 90 0f 01 00 00 00 00 00
PCI: 0f:18.00
00: 86 80 36 50 00 00 b0 02 01 00 01 11 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 70 00 00 00 00 00 00 00 00 04 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 01 00 22 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 90 0f 01 00 00 00 00 00
PCI: 00:00.00
00: 86 80 20 50 06 00 10 20 01 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 90 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
40: 09 00 05 21 7f 00 00 00 00 00 00 00 00 00 00 00
50: 0c 00 00 00 00 00 00 00 00 30 33 33 33 33 33 33
60: 08 08 08 08 00 80 71 52 00 00 00 00 00 00 00 00
70: 55 45 80 20 15 05 00 00 92 84 36 24 17 00 10 e0
80: 11 00 00 00 00 00 00 00 30 2c 00 a0 00 00 00 00
90: 00 00 00 00 00 00 00 00 aa 02 00 00 1f 08 42 07
a0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
b0: 10 00 00 00 00 00 00 00 ff ff 0f 00 00 00 00 00
c0: 44 c0 50 11 00 20 ff 03 00 00 00 00 04 00 00 e0
d0: 00 00 00 00 03 00 00 00 00 60 31 b5 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 3a 00 40 00 90 0f 01 00 00 00 03 00
BAR 14 Dump

0000 00100000 
0004 00000000 
0008 00000000 
000c 00000000 
0010 00000000 
0014 00000000 
0018 00000000 
001c 00000000 
0020 00000000 
0024 00000000 
0028 00000000 
002c 00000000 
0030 00000000 
0034 00000000 
0038 00000000 
003c 00000000 
0040 0000000f 
0044 0b840001 
0048 f834f834 
004c e834e834 
0050 f834f834 
0054 f834f834 
0058 e834e834 
005c e834e834 
0060 f834f834 
0064 f834f834 
0068 f834f834 
006c f834f834 
0070 e834e834 
0074 f834f834 
0078 f834f834 
007c e834e834 
0080 e834e834 
0084 f834f834 
0088 f834f834 
008c f834f834 
0090 000f000f 
0094 00180810 
0098 5c141400 
009c 00000000 
00a0 00000000 
00a4 24242424 
00a8 24242424 
00ac 00000000 
00b0 00000000 
00b4 00000000 
00b8 00000000 
00bc 00000000 
00c0 00000000 
00c4 00000024 
00c8 000db6c0 
00cc 00000000 
00d0 00000000 
00d4 aaaa0a05 
00d8 5b339c5d 
00dc aaabffff 
00e0 db339ce1 
00e4 00000000 
00e8 55555555 
00ec aaaaaaaa 
00f0 00000000 
00f4 00000000 
00f8 00001011 
00fc 00000000 
0100 00000000 
0104 00000000 
0108 00000000 
010c 00000000 
0110 00000000 
0114 00000000 
0118 00000000 
011c 00000000 
0120 00000000 
0124 00000000 
0128 00000000 
012c 00000000 
0130 00000000 
0134 00000000 
0138 00000000 
013c 00000000 
0140 201000f0 
0144 00000000 
0148 00000000 
014c 00000000 
0150 00000000 
0154 00000000 
0158 00000000 
015c 00000000 
0160 00000000 
0164 00000000 
0168 00000000 
016c 00000000 
0170 00000000 
0174 00000000 
0178 00000000 
017c 00000000 
0180 00000000 
0184 00000000 
0188 00000000 
018c 00000000 
0190 00000000 
0194 00000000 
0198 00000000 
019c 00000000 
01a0 00000000 
01a4 00000000 
01a8 00000000 
01ac 00000000 
01b0 00000000 
01b4 00000000 
01b8 00000000 
01bc 00000000 
01c0 00000000 
01c4 00000000 
01c8 00000000 
01cc 00000000 
01d0 00000000 
01d4 00000000 
01d8 00000000 
01dc 00000000 
01e0 00000000 
01e4 00000000 
01e8 00000000 
01ec 00000000 
01f0 00000000 
01f4 00000000 
01f8 00000000 
01fc 00000000 
0200 00000000 
0204 00000000 
0208 00000000 
020c 00000000 
0210 00000000 
0214 00000000 
0218 00000000 
021c 00000000 
0220 00000000 
0224 00000000 
0228 00000000 
022c 00000000 
0230 00000000 
0234 00000000 
0238 00000000 
023c 00000000 
0240 00000000 
0244 00000000 
0248 00000000 
024c 00000000 
0250 00000000 
0254 00000000 
0258 00000000 
025c 00000000 
0260 00000078 
0264 52520000 
0268 039b6000 
026c 00000000 
0270 00000000 
0274 00000000 
0278 00000000 
027c 00000000 
0280 00010002 
0284 00000000 
0288 00000000 
028c 00000000 
0290 00000000 
0294 00000000 
0298 00000000 
029c 00000000 
02a0 00000000 
02a4 00000000 
02a8 00000000 
02ac 00000000 
02b0 00000000 
02b4 00000000 
02b8 00000000 
02bc 00000000 
02c0 00000000 
02c4 00000000 
02c8 00000000 
02cc 00000000 
02d0 00000000 
02d4 00000000 
02d8 00000000 
02dc 00000000 
02e0 00000000 
02e4 00000000 
02e8 00000000 
02ec 00000000 
02f0 00000000 
02f4 00000000 
02f8 00000000 
02fc 00000000 
0300 00000000 
DRAM fill: 00000000-02000000
00000000 
00100000 
00200000 
00300000 
00400000 
00500000 
00600000 
00700000 
00800000 
00900000 
00a00000 
00b00000 
00c00000 
00d00000 
00e00000 
00f00000 
01000000 
01100000 
01200000 
01300000 
01400000 
01500000 
01600000 
01700000 
01800000 
01900000 
01a00000 
01b00000 
01c00000 
01d00000 
01e00000 
01f00000 
02000000
DRAM filled
DRAM verify: 00000000-02000000
00000000 
00100000 
00200000 
00300000 
00400000 
00500000 
00600000 
00700000 
00800000 
00900000 
00a00000 
00b00000 
00c00000 
00d00000 
00e00000 
00f00000 
01000000 
01100000 
01200000 
01300000 
01400000 
01500000 
01600000 
01700000 
01800000 
01900000 
01a00000 
01b00000 
01c00000 
01d00000 
01e00000 
01f00000 
02000000
DRAM range verified.
Uncompressing coreboot to RAM.
Jumping to image.

Check CBFS header at fffdffd0
magic is 4f524243
Found CBFS header at fffdffd0
Check fallback/payload
CBFS: follow chain: ffe00000 + 38 + 10056 + align -> ffe10090
Check fallback/coreboot_ram
Stage: load fallback/coreboot_ram @ 16384/155648 bytes, enter @ 4000
Stage: done loading.
Jumping to image.

coreboot-2.0.0-r4463M Mon Jul 27 19:21:56 CEST 2009 booting...
Calibrating delay loop...
end 198ea587f, start 165e1150c
32-bit delta 816
calibrate_tsc 32-bit result is 816
clocks_per_usec: 816
Enumerating buses...
Show all devs...Before Device Enumeration.
Root Device: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 0 resources
PCI: 00:00.0: enabled 1, 0 resources
PCI: 00:00.1: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 0 resources
PCI: 00:02.0: enabled 1, 0 resources
PCI: 00:03.0: enabled 1, 0 resources
PCI: 00:04.0: enabled 1, 0 resources
PCI: 00:08.0: enabled 0, 0 resources
PCI: 00:0d.0: enabled 0, 0 resources
PCI: 00:0d.1: enabled 0, 0 resources
PCI: 00:1d.0: enabled 1, 0 resources
PCI: 00:1d.7: enabled 1, 0 resources
PCI: 00:1f.0: enabled 1, 0 resources
PNP: 004e.4: enabled 1, 2 resources
PNP: 004e.5: enabled 1, 2 resources
PCI: 00:1f.2: enabled 1, 0 resources
PCI: 00:1f.3: enabled 1, 0 resources
PCI: 00:1f.4: enabled 1, 0 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
Compare with tree...
Root Device: enabled 1, 0 resources
 PCI_DOMAIN: 0000: enabled 1, 0 resources
  PCI: 00:00.0: enabled 1, 0 resources
  PCI: 00:00.1: enabled 1, 0 resources
  PCI: 00:01.0: enabled 1, 0 resources
  PCI: 00:02.0: enabled 1, 0 resources
  PCI: 00:03.0: enabled 1, 0 resources
  PCI: 00:04.0: enabled 1, 0 resources
  PCI: 00:08.0: enabled 0, 0 resources
  PCI: 00:0d.0: enabled 0, 0 resources
  PCI: 00:0d.1: enabled 0, 0 resources
  PCI: 00:1d.0: enabled 1, 0 resources
  PCI: 00:1d.7: enabled 1, 0 resources
  PCI: 00:1f.0: enabled 1, 0 resources
   PNP: 004e.4: enabled 1, 2 resources
   PNP: 004e.5: enabled 1, 2 resources
  PCI: 00:1f.2: enabled 1, 0 resources
  PCI: 00:1f.3: enabled 1, 0 resources
  PCI: 00:1f.4: enabled 1, 0 resources
 APIC_CLUSTER: 0: enabled 1, 0 resources
  APIC: 00: enabled 1, 0 resources
scan_static_bus for Root Device
PCI_DOMAIN: 0000 enabled
APIC_CLUSTER: 0 enabled
PCI_DOMAIN: 0000 scanning...
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/5020] enabled
PCI: 00:00.1 [8086/5021] enabled
PCI: 00:00.2, bad id 0xffffffff
PCI: 00:00.3, bad id 0xffffffff
PCI: 00:00.4, bad id 0xffffffff
PCI: 00:00.5, bad id 0xffffffff
PCI: 00:00.6, bad id 0xffffffff
PCI: 00:00.7, bad id 0xffffffff
PCI: 00:01.0 [8086/5023] enabled
Capability: type 0x01 @ 0x50
Capability: type 0x05 @ 0x58
Capability: type 0x10 @ 0x64
Capability: type 0x01 @ 0x50
Capability: type 0x05 @ 0x58
Capability: type 0x10 @ 0x64
Capability: type 0x01 @ 0x50
Capability: type 0x05 @ 0x58
Capability: type 0x10 @ 0x64
PCI: 00:02.0 subbordinate bus PCI Express
PCI: 00:02.0 [8086/5024] enabled
Capability: type 0x01 @ 0x50
Capability: type 0x05 @ 0x58
Capability: type 0x10 @ 0x64
Capability: type 0x01 @ 0x50
Capability: type 0x05 @ 0x58
Capability: type 0x10 @ 0x64
Capability: type 0x01 @ 0x50
Capability: type 0x05 @ 0x58
Capability: type 0x10 @ 0x64
PCI: 00:03.0 subbordinate bus PCI Express
PCI: 00:03.0 [8086/5025] enabled
Capability: type 0x01 @ 0xdc
Capability: type 0x01 @ 0xdc
Capability: type 0x01 @ 0xdc
PCI: 00:04.0 [8086/5037] enabled
PCI: 00:05.0, bad id 0xffffffff
PCI: 00:06.0, bad id 0xffffffff
PCI: 00:07.0, bad id 0xffffffff
PCI: 00:08.0 [8086/5026] disabled
PCI: 00:08.1, bad id 0xffffffff
PCI: 00:08.2, bad id 0xffffffff
PCI: 00:08.3, bad id 0xffffffff
PCI: 00:08.4, bad id 0xffffffff
PCI: 00:08.5, bad id 0xffffffff
PCI: 00:08.6, bad id 0xffffffff
PCI: 00:08.7, bad id 0xffffffff
PCI: 00:09.0, bad id 0xffffffff
PCI: 00:0a.0, bad id 0xffffffff
PCI: 00:0b.0, bad id 0xffffffff
PCI: 00:0c.0, bad id 0xffffffff
PCI: 00:0d.0 [8086/5022] disabled
PCI: 00:0d.1 [8086/504d] disabled
PCI: 00:0d.2, bad id 0xffffffff
PCI: 00:0d.3, bad id 0xffffffff
PCI: 00:0d.4, bad id 0xffffffff
PCI: 00:0d.5, bad id 0xffffffff
PCI: 00:0d.6, bad id 0xffffffff
PCI: 00:0d.7, bad id 0xffffffff
PCI: 00:0e.0, bad id 0xffffffff
PCI: 00:0f.0, bad id 0xffffffff
PCI: 00:10.0, bad id 0xffffffff
PCI: 00:11.0, bad id 0xffffffff
PCI: 00:12.0, bad id 0xffffffff
PCI: 00:13.0, bad id 0xffffffff
PCI: 00:14.0, bad id 0xffffffff
PCI: 00:15.0, bad id 0xffffffff
PCI: 00:16.0, bad id 0xffffffff
PCI: 00:17.0, bad id 0xffffffff
PCI: 00:18.0, bad id 0xffffffff
PCI: 00:19.0, bad id 0xffffffff
PCI: 00:1a.0, bad id 0xffffffff
PCI: 00:1b.0, bad id 0xffffffff
PCI: 00:1c.0, bad id 0xffffffff
PCI: 00:1d.0 [8086/5033] ops
PCI: 00:1d.0 [8086/5033] enabled
PCI: 00:1d.1, bad id 0xffffffff
PCI: 00:1d.2, bad id 0xffffffff
PCI: 00:1d.3, bad id 0xffffffff
PCI: 00:1d.4, bad id 0xffffffff
PCI: 00:1d.5, bad id 0xffffffff
PCI: 00:1d.6, bad id 0xffffffff
PCI: 00:1d.7 [8086/5035] ops
PCI: 00:1d.7 [8086/5035] enabled
PCI: 00:1e.0, bad id 0xffffffff
PCI: 00:1f.0 [8086/5031] bus ops
PCI: 00:1f.0 [8086/5031] enabled
PCI: 00:1f.1, bad id 0xffffffff
PCI: 00:1f.2 [8086/5028] ops
PCI: 00:1f.2 [8086/5028] enabled
PCI: 00:1f.3 [8086/5032] bus ops
PCI: 00:1f.3 [8086/5032] enabled
PCI: 00:1f.4 [8086/5036] enabled
PCI: 00:1f.5, bad id 0xffffffff
PCI: 00:1f.6, bad id 0xffffffff
PCI: 00:1f.7, bad id 0xffffffff
do_pci_scan_bridge for PCI: 00:02.0
PCI: pci_scan_bus for bus 01
PCI: 01:00.0, bad id 0xffffffff
PCI: 01:01.0, bad id 0xffffffff
PCI: 01:02.0, bad id 0xffffffff
PCI: 01:03.0, bad id 0xffffffff
PCI: 01:04.0, bad id 0xffffffff
PCI: 01:05.0, bad id 0xffffffff
PCI: 01:06.0, bad id 0xffffffff
PCI: 01:07.0, bad id 0xffffffff
PCI: 01:08.0, bad id 0xffffffff
PCI: 01:09.0, bad id 0xffffffff
PCI: 01:0a.0, bad id 0xffffffff
PCI: 01:0b.0, bad id 0xffffffff
PCI: 01:0c.0, bad id 0xffffffff
PCI: 01:0d.0, bad id 0xffffffff
PCI: 01:0e.0, bad id 0xffffffff
PCI: 01:0f.0, bad id 0xffffffff
PCI: 01:10.0, bad id 0xffffffff
PCI: 01:11.0, bad id 0xffffffff
PCI: 01:12.0, bad id 0xffffffff
PCI: 01:13.0, bad id 0xffffffff
PCI: 01:14.0, bad id 0xffffffff
PCI: 01:15.0, bad id 0xffffffff
PCI: 01:16.0, bad id 0xffffffff
PCI: 01:17.0, bad id 0xffffffff
PCI: 01:18.0, bad id 0xffffffff
PCI: 01:19.0, bad id 0xffffffff
PCI: 01:1a.0, bad id 0xffffffff
PCI: 01:1b.0, bad id 0xffffffff
PCI: 01:1c.0, bad id 0xffffffff
PCI: 01:1d.0, bad id 0xffffffff
PCI: 01:1e.0, bad id 0xffffffff
PCI: 01:1f.0, bad id 0xffffffff
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
do_pci_scan_bridge for PCI: 00:03.0
PCI: pci_scan_bus for bus 02
malloc Enter, size 1100, free_mem_ptr 00022000
malloc 00022000
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x68
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x68
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x68
PCI: 02:00.0 subbordinate bus PCI Express
PCI: 02:00.0 [10b5/8508] enabled
PCI: 02:01.0, bad id 0xffffffff
PCI: 02:02.0, bad id 0xffffffff
PCI: 02:03.0, bad id 0xffffffff
PCI: 02:04.0, bad id 0xffffffff
PCI: 02:05.0, bad id 0xffffffff
PCI: 02:06.0, bad id 0xffffffff
PCI: 02:07.0, bad id 0xffffffff
PCI: 02:08.0, bad id 0xffffffff
PCI: 02:09.0, bad id 0xffffffff
PCI: 02:0a.0, bad id 0xffffffff
PCI: 02:0b.0, bad id 0xffffffff
PCI: 02:0c.0, bad id 0xffffffff
PCI: 02:0d.0, bad id 0xffffffff
PCI: 02:0e.0, bad id 0xffffffff
PCI: 02:0f.0, bad id 0xffffffff
PCI: 02:10.0, bad id 0xffffffff
PCI: 02:11.0, bad id 0xffffffff
PCI: 02:12.0, bad id 0xffffffff
PCI: 02:13.0, bad id 0xffffffff
PCI: 02:14.0, bad id 0xffffffff
PCI: 02:15.0, bad id 0xffffffff
PCI: 02:16.0, bad id 0xffffffff
PCI: 02:17.0, bad id 0xffffffff
PCI: 02:18.0, bad id 0xffffffff
PCI: 02:19.0, bad id 0xffffffff
PCI: 02:1a.0, bad id 0xffffffff
PCI: 02:1b.0, bad id 0xffffffff
PCI: 02:1c.0, bad id 0xffffffff
PCI: 02:1d.0, bad id 0xffffffff
PCI: 02:1e.0, bad id 0xffffffff
PCI: 02:1f.0, bad id 0xffffffff
do_pci_scan_bridge for PCI: 02:00.0
PCI: pci_scan_bus for bus 03
PCI: 03:00.0, bad id 0xffffffff
malloc Enter, size 1100, free_mem_ptr 0002244c
malloc 0002244c
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x68
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x68
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x68
PCI: 03:01.0 subbordinate bus PCI Express
PCI: 03:01.0 [10b5/8508] enabled
malloc Enter, size 1100, free_mem_ptr 00022898
malloc 00022898
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x68
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x68
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x68
PCI: 03:02.0 subbordinate bus PCI Express
PCI: 03:02.0 [10b5/8508] enabled
malloc Enter, size 1100, free_mem_ptr 00022ce4
malloc 00022ce4
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x68
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x68
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x68
PCI: 03:03.0 subbordinate bus PCI Express
PCI: 03:03.0 [10b5/8508] enabled
malloc Enter, size 1100, free_mem_ptr 00023130
malloc 00023130
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x68
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x68
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x68
PCI: 03:04.0 subbordinate bus PCI Express
PCI: 03:04.0 [10b5/8508] enabled
PCI: 03:05.0, bad id 0xffffffff
PCI: 03:06.0, bad id 0xffffffff
PCI: 03:07.0, bad id 0xffffffff
PCI: 03:08.0, bad id 0xffffffff
PCI: 03:09.0, bad id 0xffffffff
PCI: 03:0a.0, bad id 0xffffffff
PCI: 03:0b.0, bad id 0xffffffff
PCI: 03:0c.0, bad id 0xffffffff
PCI: 03:0d.0, bad id 0xffffffff
PCI: 03:0e.0, bad id 0xffffffff
PCI: 03:0f.0, bad id 0xffffffff
PCI: 03:10.0, bad id 0xffffffff
PCI: 03:11.0, bad id 0xffffffff
PCI: 03:12.0, bad id 0xffffffff
PCI: 03:13.0, bad id 0xffffffff
PCI: 03:14.0, bad id 0xffffffff
PCI: 03:15.0, bad id 0xffffffff
PCI: 03:16.0, bad id 0xffffffff
PCI: 03:17.0, bad id 0xffffffff
PCI: 03:18.0, bad id 0xffffffff
PCI: 03:19.0, bad id 0xffffffff
PCI: 03:1a.0, bad id 0xffffffff
PCI: 03:1b.0, bad id 0xffffffff
PCI: 03:1c.0, bad id 0xffffffff
PCI: 03:1d.0, bad id 0xffffffff
PCI: 03:1e.0, bad id 0xffffffff
PCI: 03:1f.0, bad id 0xffffffff
do_pci_scan_bridge for PCI: 03:01.0
PCI: pci_scan_bus for bus 04
PCI: 04:00.0, bad id 0xffffffff
PCI: 04:01.0, bad id 0xffffffff
PCI: 04:02.0, bad id 0xffffffff
PCI: 04:03.0, bad id 0xffffffff
PCI: 04:04.0, bad id 0xffffffff
PCI: 04:05.0, bad id 0xffffffff
PCI: 04:06.0, bad id 0xffffffff
PCI: 04:07.0, bad id 0xffffffff
PCI: 04:08.0, bad id 0xffffffff
PCI: 04:09.0, bad id 0xffffffff
PCI: 04:0a.0, bad id 0xffffffff
PCI: 04:0b.0, bad id 0xffffffff
PCI: 04:0c.0, bad id 0xffffffff
PCI: 04:0d.0, bad id 0xffffffff
PCI: 04:0e.0, bad id 0xffffffff
PCI: 04:0f.0, bad id 0xffffffff
PCI: 04:10.0, bad id 0xffffffff
PCI: 04:11.0, bad id 0xffffffff
PCI: 04:12.0, bad id 0xffffffff
PCI: 04:13.0, bad id 0xffffffff
PCI: 04:14.0, bad id 0xffffffff
PCI: 04:15.0, bad id 0xffffffff
PCI: 04:16.0, bad id 0xffffffff
PCI: 04:17.0, bad id 0xffffffff
PCI: 04:18.0, bad id 0xffffffff
PCI: 04:19.0, bad id 0xffffffff
PCI: 04:1a.0, bad id 0xffffffff
PCI: 04:1b.0, bad id 0xffffffff
PCI: 04:1c.0, bad id 0xffffffff
PCI: 04:1d.0, bad id 0xffffffff
PCI: 04:1e.0, bad id 0xffffffff
PCI: 04:1f.0, bad id 0xffffffff
PCI: pci_scan_bus returning with max=004
do_pci_scan_bridge returns max 4
do_pci_scan_bridge for PCI: 03:02.0
PCI: pci_scan_bus for bus 05
PCI: 05:00.0, bad id 0xffffffff
PCI: 05:01.0, bad id 0xffffffff
PCI: 05:02.0, bad id 0xffffffff
PCI: 05:03.0, bad id 0xffffffff
PCI: 05:04.0, bad id 0xffffffff
PCI: 05:05.0, bad id 0xffffffff
PCI: 05:06.0, bad id 0xffffffff
PCI: 05:07.0, bad id 0xffffffff
PCI: 05:08.0, bad id 0xffffffff
PCI: 05:09.0, bad id 0xffffffff
PCI: 05:0a.0, bad id 0xffffffff
PCI: 05:0b.0, bad id 0xffffffff
PCI: 05:0c.0, bad id 0xffffffff
PCI: 05:0d.0, bad id 0xffffffff
PCI: 05:0e.0, bad id 0xffffffff
PCI: 05:0f.0, bad id 0xffffffff
PCI: 05:10.0, bad id 0xffffffff
PCI: 05:11.0, bad id 0xffffffff
PCI: 05:12.0, bad id 0xffffffff
PCI: 05:13.0, bad id 0xffffffff
PCI: 05:14.0, bad id 0xffffffff
PCI: 05:15.0, bad id 0xffffffff
PCI: 05:16.0, bad id 0xffffffff
PCI: 05:17.0, bad id 0xffffffff
PCI: 05:18.0, bad id 0xffffffff
PCI: 05:19.0, bad id 0xffffffff
PCI: 05:1a.0, bad id 0xffffffff
PCI: 05:1b.0, bad id 0xffffffff
PCI: 05:1c.0, bad id 0xffffffff
PCI: 05:1d.0, bad id 0xffffffff
PCI: 05:1e.0, bad id 0xffffffff
PCI: 05:1f.0, bad id 0xffffffff
PCI: pci_scan_bus returning with max=005
do_pci_scan_bridge returns max 5
do_pci_scan_bridge for PCI: 03:03.0
PCI: pci_scan_bus for bus 06
PCI: 06:00.0, bad id 0xffffffff
PCI: 06:01.0, bad id 0xffffffff
PCI: 06:02.0, bad id 0xffffffff
PCI: 06:03.0, bad id 0xffffffff
PCI: 06:04.0, bad id 0xffffffff
PCI: 06:05.0, bad id 0xffffffff
PCI: 06:06.0, bad id 0xffffffff
PCI: 06:07.0, bad id 0xffffffff
PCI: 06:08.0, bad id 0xffffffff
PCI: 06:09.0, bad id 0xffffffff
PCI: 06:0a.0, bad id 0xffffffff
PCI: 06:0b.0, bad id 0xffffffff
PCI: 06:0c.0, bad id 0xffffffff
PCI: 06:0d.0, bad id 0xffffffff
PCI: 06:0e.0, bad id 0xffffffff
PCI: 06:0f.0, bad id 0xffffffff
PCI: 06:10.0, bad id 0xffffffff
PCI: 06:11.0, bad id 0xffffffff
PCI: 06:12.0, bad id 0xffffffff
PCI: 06:13.0, bad id 0xffffffff
PCI: 06:14.0, bad id 0xffffffff
PCI: 06:15.0, bad id 0xffffffff
PCI: 06:16.0, bad id 0xffffffff
PCI: 06:17.0, bad id 0xffffffff
PCI: 06:18.0, bad id 0xffffffff
PCI: 06:19.0, bad id 0xffffffff
PCI: 06:1a.0, bad id 0xffffffff
PCI: 06:1b.0, bad id 0xffffffff
PCI: 06:1c.0, bad id 0xffffffff
PCI: 06:1d.0, bad id 0xffffffff
PCI: 06:1e.0, bad id 0xffffffff
PCI: 06:1f.0, bad id 0xffffffff
PCI: pci_scan_bus returning with max=006
do_pci_scan_bridge returns max 6
do_pci_scan_bridge for PCI: 03:04.0
PCI: pci_scan_bus for bus 07
malloc Enter, size 1100, free_mem_ptr 0002357c
malloc 0002357c
PCI: 07:00.0 [10de/0421] enabled
PCI: 07:01.0, bad id 0xffffffff
PCI: 07:02.0, bad id 0xffffffff
PCI: 07:03.0, bad id 0xffffffff
PCI: 07:04.0, bad id 0xffffffff
PCI: 07:05.0, bad id 0xffffffff
PCI: 07:06.0, bad id 0xffffffff
PCI: 07:07.0, bad id 0xffffffff
PCI: 07:08.0, bad id 0xffffffff
PCI: 07:09.0, bad id 0xffffffff
PCI: 07:0a.0, bad id 0xffffffff
PCI: 07:0b.0, bad id 0xffffffff
PCI: 07:0c.0, bad id 0xffffffff
PCI: 07:0d.0, bad id 0xffffffff
PCI: 07:0e.0, bad id 0xffffffff
PCI: 07:0f.0, bad id 0xffffffff
PCI: 07:10.0, bad id 0xffffffff
PCI: 07:11.0, bad id 0xffffffff
PCI: 07:12.0, bad id 0xffffffff
PCI: 07:13.0, bad id 0xffffffff
PCI: 07:14.0, bad id 0xffffffff
PCI: 07:15.0, bad id 0xffffffff
PCI: 07:16.0, bad id 0xffffffff
PCI: 07:17.0, bad id 0xffffffff
PCI: 07:18.0, bad id 0xffffffff
PCI: 07:19.0, bad id 0xffffffff
PCI: 07:1a.0, bad id 0xffffffff
PCI: 07:1b.0, bad id 0xffffffff
PCI: 07:1c.0, bad id 0xffffffff
PCI: 07:1d.0, bad id 0xffffffff
PCI: 07:1e.0, bad id 0xffffffff
PCI: 07:1f.0, bad id 0xffffffff
PCI: pci_scan_bus returning with max=007
Capability: type 0x01 @ 0x60
Capability: type 0x05 @ 0x68
Capability: type 0x10 @ 0x78
PCIe: tuning PCI: 07:00.0
do_pci_scan_bridge returns max 7
PCI: pci_scan_bus returning with max=007
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x68
PCIe: tuning PCI: 03:01.0
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x68
PCIe: tuning PCI: 03:02.0
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x68
PCIe: tuning PCI: 03:03.0
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x68
PCIe: tuning PCI: 03:04.0
do_pci_scan_bridge returns max 7
PCI: pci_scan_bus returning with max=007
Capability: type 0x01 @ 0x40
Capability: type 0x05 @ 0x48
Capability: type 0x10 @ 0x68
PCIe: tuning PCI: 02:00.0
do_pci_scan_bridge returns max 7
do_pci_scan_bridge for PCI: 00:04.0
PCI: pci_scan_bus for bus 08
malloc Enter, size 1100, free_mem_ptr 000239c8
malloc 000239c8
PCI: 08:00.0 [8086/5041] enabled
malloc Enter, size 1100, free_mem_ptr 00023e14
malloc 00023e14
PCI: 08:01.0 [8086/5045] enabled
malloc Enter, size 1100, free_mem_ptr 00024260
malloc 00024260
PCI: 08:02.0 [8086/5049] enabled
malloc Enter, size 1100, free_mem_ptr 000246ac
malloc 000246ac
PCI: 08:03.0 [8086/503e] enabled
malloc Enter, size 1100, free_mem_ptr 00024af8
malloc 00024af8
PCI: 08:04.0 [8086/5039] enabled
malloc Enter, size 1100, free_mem_ptr 00024f44
malloc 00024f44
PCI: 08:05.0 [8086/503a] enabled
malloc Enter, size 1100, free_mem_ptr 00025390
malloc 00025390
PCI: 08:06.0 [8086/503b] enabled
malloc Enter, size 1100, free_mem_ptr 000257dc
malloc 000257dc
PCI: 08:07.0 [8086/503c] enabled
malloc Enter, size 1100, free_mem_ptr 00025c28
malloc 00025c28
PCI: 08:08.0 [8086/503d] enabled
malloc Enter, size 1100, free_mem_ptr 00026074
malloc 00026074
PCI: 08:09.0 [8086/502d] enabled
malloc Enter, size 1100, free_mem_ptr 000264c0
malloc 000264c0
PCI: 08:0a.0 [8086/503f] enabled
malloc Enter, size 1100, free_mem_ptr 0002690c
malloc 0002690c
PCI: 08:0b.0 [8086/504c] enabled
malloc Enter, size 1100, free_mem_ptr 00026d58
malloc 00026d58
PCI: 08:0c.0 [8086/5030] enabled
PCI: 08:0d.0, bad id 0xffffffff
PCI: 08:0e.0, bad id 0xffffffff
PCI: 08:0f.0, bad id 0xffffffff
PCI: 08:10.0, bad id 0xffffffff
PCI: 08:11.0, bad id 0xffffffff
PCI: 08:12.0, bad id 0xffffffff
PCI: 08:13.0, bad id 0xffffffff
PCI: 08:14.0, bad id 0xffffffff
PCI: 08:15.0, bad id 0xffffffff
PCI: 08:16.0, bad id 0xffffffff
PCI: 08:17.0, bad id 0xffffffff
PCI: 08:18.0, bad id 0xffffffff
PCI: 08:19.0, bad id 0xffffffff
PCI: 08:1a.0, bad id 0xffffffff
PCI: 08:1b.0, bad id 0xffffffff
PCI: 08:1c.0, bad id 0xffffffff
PCI: 08:1d.0, bad id 0xffffffff
PCI: 08:1e.0, bad id 0xffffffff
PCI: 08:1f.0, bad id 0xffffffff
PCI: pci_scan_bus returning with max=008
do_pci_scan_bridge returns max 8
scan_static_bus for PCI: 00:1f.0
PNP: 004e.4 enabled
PNP: 004e.5 enabled
scan_static_bus for PCI: 00:1f.0 done
scan_static_bus for PCI: 00:1f.3
scan_static_bus for PCI: 00:1f.3 done
PCI: pci_scan_bus returning with max=008
scan_static_bus for Root Device done
done
Setting up VGA for PCI: 07:00.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 03:04.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 02:00.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:03.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
Root Device read_resources bus 0 link: 0
PCI_DOMAIN: 0000 read_resources bus 0 link: 0
PCI: 00:02.0 read_resources bus 1 link: 0
PCI: 00:02.0 read_resources bus 1 link: 0 done
PCI: 00:03.0 read_resources bus 2 link: 0
PCI: 02:00.0 read_resources bus 3 link: 0
PCI: 03:01.0 read_resources bus 4 link: 0
PCI: 03:01.0 read_resources bus 4 link: 0 done
PCI: 03:02.0 read_resources bus 5 link: 0
PCI: 03:02.0 read_resources bus 5 link: 0 done
PCI: 03:03.0 read_resources bus 6 link: 0
PCI: 03:03.0 read_resources bus 6 link: 0 done
PCI: 03:04.0 read_resources bus 7 link: 0
PCI: 03:04.0 read_resources bus 7 link: 0 done
PCI: 02:00.0 read_resources bus 3 link: 0 done
PCI: 00:03.0 read_resources bus 2 link: 0 done
PCI: 00:04.0 read_resources bus 8 link: 0
PCI: 00:04.0 read_resources bus 8 link: 0 done
PCI: 00:1f.0 read_resources bus 0 link: 0
PCI: 00:1f.0 read_resources bus 0 link: 0 done
PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done
APIC_CLUSTER: 0 read_resources bus 0 link: 0
APIC: 00 missing read_resources
APIC_CLUSTER: 0 read_resources bus 0 link: 0 done
Root Device read_resources bus 0 link: 0 done
Done reading resources.
Show resources in subtree (Root Device)...After reading.
 Root Device links 1 child on link 0 Root Device
  PCI_DOMAIN: 0000 links 1 child on link 0 PCI_DOMAIN: 0000
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
   PCI: 00:00.0 links 0 child on link 0 NULL
   PCI: 00:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
   PCI: 00:00.1 links 0 child on link 0 NULL
   PCI: 00:01.0 links 0 child on link 0 NULL
   PCI: 00:01.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
   PCI: 00:02.0 links 1 child on link 0 NULL
   PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit fffffffff flags 81202 index 24
   PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
   PCI: 00:03.0 links 1 child on link 0 PCI: 00:03.0
   PCI: 00:03.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit fffffffff flags 81202 index 24
   PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 02:00.0 links 1 child on link 0 PCI: 02:00.0
    PCI: 02:00.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
    PCI: 02:00.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
    PCI: 02:00.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 02:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
     PCI: 03:01.0 links 1 child on link 0 NULL
     PCI: 03:01.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
     PCI: 03:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
     PCI: 03:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
     PCI: 03:02.0 links 1 child on link 0 NULL
     PCI: 03:02.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
     PCI: 03:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
     PCI: 03:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
     PCI: 03:03.0 links 1 child on link 0 NULL
     PCI: 03:03.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
     PCI: 03:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
     PCI: 03:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
     PCI: 03:04.0 links 1 child on link 0 PCI: 03:04.0
     PCI: 03:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
     PCI: 03:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
     PCI: 03:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
      PCI: 07:00.0 links 0 child on link 0 NULL
      PCI: 07:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10
      PCI: 07:00.0 resource base 0 size 20000000 align 29 gran 29 limit ffffffffffffffff flags 1201 index 14
      PCI: 07:00.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffffffffffff flags 201 index 1c
      PCI: 07:00.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 24
      PCI: 07:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30
   PCI: 00:04.0 links 1 child on link 0 PCI: 00:04.0
   PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
   PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit fffffffff flags 81202 index 24
   PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
    PCI: 08:00.0 links 0 child on link 0 NULL
    PCI: 08:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
    PCI: 08:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 14
    PCI: 08:01.0 links 0 child on link 0 NULL
    PCI: 08:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
    PCI: 08:01.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 14
    PCI: 08:02.0 links 0 child on link 0 NULL
    PCI: 08:02.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10
    PCI: 08:02.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 14
    PCI: 08:03.0 links 0 child on link 0 NULL
    PCI: 08:03.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 08:04.0 links 0 child on link 0 NULL
    PCI: 08:04.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 08:05.0 links 0 child on link 0 NULL
    PCI: 08:05.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 08:06.0 links 0 child on link 0 NULL
    PCI: 08:06.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 08:07.0 links 0 child on link 0 NULL
    PCI: 08:07.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 08:08.0 links 0 child on link 0 NULL
    PCI: 08:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 08:08.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 200 index 14
    PCI: 08:09.0 links 0 child on link 0 NULL
    PCI: 08:09.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10
    PCI: 08:09.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 14
    PCI: 08:09.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 18
    PCI: 08:09.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c
    PCI: 08:0a.0 links 0 child on link 0 NULL
    PCI: 08:0a.0 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
    PCI: 08:0a.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 08:0a.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 18
    PCI: 08:0b.0 links 0 child on link 0 NULL
    PCI: 08:0b.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
    PCI: 08:0b.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14
    PCI: 08:0c.0 links 0 child on link 0 NULL
    PCI: 08:0c.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10
   PCI: 00:08.0 links 0 child on link 0 NULL
   PCI: 00:0d.0 links 0 child on link 0 NULL
   PCI: 00:0d.1 links 0 child on link 0 NULL
   PCI: 00:1d.0 links 0 child on link 0 NULL
   PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:1d.7 links 0 child on link 0 NULL
   PCI: 00:1d.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10
   PCI: 00:1f.0 links 1 child on link 0 PCI: 00:1f.0
   PCI: 00:1f.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 40
   PCI: 00:1f.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 48
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
   PCI: 00:1f.0 resource base 0 size 4000 align 14 gran 14 limit ffffc000 flags 200 index f0
    PNP: 004e.4 links 0 child on link 0 NULL
    PNP: 004e.4 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 004e.4 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
    PNP: 004e.5 links 0 child on link 0 NULL
    PNP: 004e.5 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60
    PNP: 004e.5 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
   PCI: 00:1f.2 links 0 child on link 0 NULL
   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
   PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
   PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
   PCI: 00:1f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
   PCI: 00:1f.2 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24
   PCI: 00:1f.3 links 0 child on link 0 NULL
   PCI: 00:1f.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
   PCI: 00:1f.4 links 0 child on link 0 NULL
   PCI: 00:1f.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
  APIC_CLUSTER: 0 links 1 child on link 0 APIC_CLUSTER: 0
   APIC: 00 links 0 child on link 0 NULL
PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
PCI: 00:02.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 00:02.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
PCI: 00:03.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 02:00.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 03:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 03:01.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 03:02.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 03:02.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 03:03.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 03:03.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
PCI: 03:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
PCI: 07:00.0 24 *  [0x0 - 0x7f] io
PCI: 03:04.0 compute_resources_io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 03:04.0 1c *  [0x0 - 0xfff] io
PCI: 02:00.0 compute_resources_io: base: 1000 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 02:00.0 1c *  [0x0 - 0xfff] io
PCI: 00:03.0 compute_resources_io: base: 1000 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
PCI: 08:00.0 14 *  [0x0 - 0x1f] io
PCI: 08:01.0 14 *  [0x20 - 0x3f] io
PCI: 08:02.0 14 *  [0x40 - 0x5f] io
PCI: 00:04.0 compute_resources_io: base: 60 size: 1000 align: 12 gran: 12 limit: ffff done
PCI: 00:03.0 1c *  [0x0 - 0xfff] io
PCI: 00:04.0 1c *  [0x1000 - 0x1fff] io
PCI: 00:1f.0 40 *  [0x2000 - 0x207f] io
PCI: 00:1f.0 48 *  [0x2080 - 0x20bf] io
PCI: 00:1d.0 20 *  [0x20c0 - 0x20df] io
PCI: 00:1f.3 20 *  [0x20e0 - 0x20ff] io
PCI: 00:1f.2 20 *  [0x2400 - 0x240f] io
PCI: 00:1f.2 10 *  [0x2410 - 0x2417] io
PCI: 00:1f.2 18 *  [0x2418 - 0x241f] io
PCI: 00:1f.2 14 *  [0x2420 - 0x2423] io
PCI: 00:1f.2 1c *  [0x2424 - 0x2427] io
PCI_DOMAIN: 0000 compute_resources_io: base: 2428 size: 2428 align: 12 gran: 0 limit: ffff done
PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
PCI: 00:02.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffff
PCI: 00:02.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffff done
PCI: 00:02.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 00:02.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 00:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffff
PCI: 02:00.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 03:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 03:01.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 03:02.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 03:02.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 03:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 03:03.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
PCI: 03:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
PCI: 07:00.0 14 *  [0x0 - 0x1fffffff] prefmem
PCI: 03:04.0 compute_resources_prefmem: base: 20000000 size: 20000000 align: 29 gran: 20 limit: ffffffffffffffff done
PCI: 03:04.0 24 *  [0x0 - 0x1fffffff] prefmem
PCI: 02:00.0 compute_resources_prefmem: base: 20000000 size: 20000000 align: 29 gran: 20 limit: ffffffffffffffff done
PCI: 02:00.0 24 *  [0x0 - 0x1fffffff] prefmem
PCI: 00:03.0 compute_resources_prefmem: base: 20000000 size: 20000000 align: 29 gran: 20 limit: fffffffff done
PCI: 00:03.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 02:00.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 03:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 03:01.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 03:02.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 03:02.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 03:03.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 03:03.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
PCI: 03:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 07:00.0 1c *  [0x0 - 0x1ffffff] mem
PCI: 07:00.0 10 *  [0x2000000 - 0x2ffffff] mem
PCI: 07:00.0 30 *  [0x3000000 - 0x301ffff] mem
PCI: 03:04.0 compute_resources_mem: base: 3020000 size: 3100000 align: 25 gran: 20 limit: ffffffff done
PCI: 03:04.0 20 *  [0x0 - 0x30fffff] mem
PCI: 02:00.0 compute_resources_mem: base: 3100000 size: 3100000 align: 25 gran: 20 limit: ffffffff done
PCI: 02:00.0 20 *  [0x0 - 0x30fffff] mem
PCI: 02:00.0 10 *  [0x3100000 - 0x311ffff] mem
PCI: 00:03.0 compute_resources_mem: base: 3120000 size: 3200000 align: 25 gran: 20 limit: ffffffff done
PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffff
PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: fffffffff done
PCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
PCI: 08:08.0 14 *  [0x0 - 0xfffffff] mem
PCI: 08:0a.0 18 *  [0x10000000 - 0x1003ffff] mem
PCI: 08:00.0 10 *  [0x10040000 - 0x1005ffff] mem
PCI: 08:01.0 10 *  [0x10060000 - 0x1007ffff] mem
PCI: 08:02.0 10 *  [0x10080000 - 0x1009ffff] mem
PCI: 08:09.0 14 *  [0x100a0000 - 0x100a3fff] mem
PCI: 08:09.0 18 *  [0x100a4000 - 0x100a7fff] mem
PCI: 08:0a.0 10 *  [0x100a8000 - 0x100abfff] mem
PCI: 08:09.0 10 *  [0x100ac000 - 0x100adfff] mem
PCI: 08:0c.0 10 *  [0x100ae000 - 0x100affff] mem
PCI: 08:03.0 10 *  [0x100b0000 - 0x100b0fff] mem
PCI: 08:04.0 10 *  [0x100b1000 - 0x100b1fff] mem
PCI: 08:05.0 10 *  [0x100b2000 - 0x100b2fff] mem
PCI: 08:06.0 10 *  [0x100b3000 - 0x100b3fff] mem
PCI: 08:07.0 10 *  [0x100b4000 - 0x100b4fff] mem
PCI: 08:08.0 10 *  [0x100b5000 - 0x100b5fff] mem
PCI: 08:09.0 1c *  [0x100b6000 - 0x100b6fff] mem
PCI: 08:0a.0 14 *  [0x100b7000 - 0x100b7fff] mem
PCI: 08:0b.0 10 *  [0x100b8000 - 0x100b8fff] mem
PCI: 08:0b.0 14 *  [0x100b9000 - 0x100b9fff] mem
PCI: 00:04.0 compute_resources_mem: base: 100ba000 size: 10100000 align: 28 gran: 20 limit: ffffffff done
PCI: 00:03.0 24 *  [0x0 - 0x1fffffff] prefmem
PCI: 00:04.0 20 *  [0x20000000 - 0x300fffff] mem
PCI: 00:03.0 20 *  [0x32000000 - 0x351fffff] mem
PCI: 00:1f.0 f0 *  [0x35200000 - 0x35203fff] mem
PCI: 00:00.0 14 *  [0x35204000 - 0x35204fff] mem
PCI: 00:01.0 10 *  [0x35205000 - 0x35205fff] mem
PCI: 00:1f.4 10 *  [0x35206000 - 0x35206fff] mem
PCI: 00:1d.7 10 *  [0x35207000 - 0x352073ff] mem
PCI: 00:1f.2 24 *  [0x35207400 - 0x352077ff] mem
PCI_DOMAIN: 0000 compute_resources_mem: base: 35207800 size: 35207800 align: 29 gran: 0 limit: ffffc000 done
avoid_fixed_resources: PCI_DOMAIN: 0000
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff
avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffc000
constrain_resources: PCI_DOMAIN: 0000
constrain_resources: PCI: 00:00.0
constrain_resources: PCI: 00:00.1
constrain_resources: PCI: 00:01.0
constrain_resources: PCI: 00:02.0
constrain_resources: PCI: 00:03.0
constrain_resources: PCI: 02:00.0
constrain_resources: PCI: 03:01.0
constrain_resources: PCI: 03:02.0
constrain_resources: PCI: 03:03.0
constrain_resources: PCI: 03:04.0
constrain_resources: PCI: 07:00.0
constrain_resources: PCI: 00:04.0
constrain_resources: PCI: 08:00.0
constrain_resources: PCI: 08:01.0
constrain_resources: PCI: 08:02.0
constrain_resources: PCI: 08:03.0
constrain_resources: PCI: 08:04.0
constrain_resources: PCI: 08:05.0
constrain_resources: PCI: 08:06.0
constrain_resources: PCI: 08:07.0
constrain_resources: PCI: 08:08.0
constrain_resources: PCI: 08:09.0
constrain_resources: PCI: 08:0a.0
constrain_resources: PCI: 08:0b.0
constrain_resources: PCI: 08:0c.0
constrain_resources: PCI: 00:1d.0
constrain_resources: PCI: 00:1d.7
constrain_resources: PCI: 00:1f.0
constrain_resources: PNP: 004e.4
constrain_resources: PNP: 004e.5
constrain_resources: PCI: 00:1f.2
constrain_resources: PCI: 00:1f.3
constrain_resources: PCI: 00:1f.4
avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff
    lim->base 00001000 lim->limit 0000ffff
avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffc000
    lim->base 00000000 lim->limit febfffff
Setting resources...
PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:2428 align:12 gran:0 limit:ffff
Assigned: PCI: 00:03.0 1c *  [0x1000 - 0x1fff] io
Assigned: PCI: 00:04.0 1c *  [0x2000 - 0x2fff] io
Assigned: PCI: 00:1f.0 40 *  [0x3000 - 0x307f] io
Assigned: PCI: 00:1f.0 48 *  [0x3080 - 0x30bf] io
Assigned: PCI: 00:1d.0 20 *  [0x30c0 - 0x30df] io
Assigned: PCI: 00:1f.3 20 *  [0x30e0 - 0x30ff] io
Assigned: PCI: 00:1f.2 20 *  [0x3400 - 0x340f] io
Assigned: PCI: 00:1f.2 10 *  [0x3410 - 0x3417] io
Assigned: PCI: 00:1f.2 18 *  [0x3418 - 0x341f] io
Assigned: PCI: 00:1f.2 14 *  [0x3420 - 0x3423] io
Assigned: PCI: 00:1f.2 1c *  [0x3424 - 0x3427] io
PCI_DOMAIN: 0000 allocate_resources_io: next_base: 3428 size: 2428 align: 12 gran: 0 done
PCI: 00:02.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 00:02.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 00:03.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 02:00.0 1c *  [0x1000 - 0x1fff] io
PCI: 00:03.0 allocate_resources_io: next_base: 2000 size: 1000 align: 12 gran: 12 done
PCI: 02:00.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 03:04.0 1c *  [0x1000 - 0x1fff] io
PCI: 02:00.0 allocate_resources_io: next_base: 2000 size: 1000 align: 12 gran: 12 done
PCI: 03:01.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 03:01.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 03:02.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 03:02.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 03:03.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
PCI: 03:03.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
PCI: 03:04.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 07:00.0 24 *  [0x1000 - 0x107f] io
PCI: 03:04.0 allocate_resources_io: next_base: 1080 size: 1000 align: 12 gran: 12 done
PCI: 00:04.0 allocate_resources_io: base:2000 size:1000 align:12 gran:12 limit:ffff
Assigned: PCI: 08:00.0 14 *  [0x2000 - 0x201f] io
Assigned: PCI: 08:01.0 14 *  [0x2020 - 0x203f] io
Assigned: PCI: 08:02.0 14 *  [0x2040 - 0x205f] io
PCI: 00:04.0 allocate_resources_io: next_base: 2060 size: 1000 align: 12 gran: 12 done
PCI_DOMAIN: 0000 allocate_resources_mem: base:c0000000 size:35207800 align:29 gran:0 limit:febfffff
Assigned: PCI: 00:03.0 24 *  [0xc0000000 - 0xdfffffff] prefmem
Assigned: PCI: 00:04.0 20 *  [0xe0000000 - 0xf00fffff] mem
Assigned: PCI: 00:03.0 20 *  [0xf2000000 - 0xf51fffff] mem
Assigned: PCI: 00:1f.0 f0 *  [0xf5200000 - 0xf5203fff] mem
Assigned: PCI: 00:00.0 14 *  [0xf5204000 - 0xf5204fff] mem
Assigned: PCI: 00:01.0 10 *  [0xf5205000 - 0xf5205fff] mem
Assigned: PCI: 00:1f.4 10 *  [0xf5206000 - 0xf5206fff] mem
Assigned: PCI: 00:1d.7 10 *  [0xf5207000 - 0xf52073ff] mem
Assigned: PCI: 00:1f.2 24 *  [0xf5207400 - 0xf52077ff] mem
PCI_DOMAIN: 0000 allocate_resources_mem: next_base: f5207800 size: 35207800 align: 29 gran: 0 done
PCI: 00:02.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:02.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:02.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:02.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:03.0 allocate_resources_prefmem: base:c0000000 size:20000000 align:29 gran:20 limit:febfffff
Assigned: PCI: 02:00.0 24 *  [0xc0000000 - 0xdfffffff] prefmem
PCI: 00:03.0 allocate_resources_prefmem: next_base: e0000000 size: 20000000 align: 29 gran: 20 done
PCI: 02:00.0 allocate_resources_prefmem: base:c0000000 size:20000000 align:29 gran:20 limit:febfffff
Assigned: PCI: 03:04.0 24 *  [0xc0000000 - 0xdfffffff] prefmem
PCI: 02:00.0 allocate_resources_prefmem: next_base: e0000000 size: 20000000 align: 29 gran: 20 done
PCI: 03:01.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 03:01.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 03:02.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 03:02.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 03:03.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 03:03.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 03:04.0 allocate_resources_prefmem: base:c0000000 size:20000000 align:29 gran:20 limit:febfffff
Assigned: PCI: 07:00.0 14 *  [0xc0000000 - 0xdfffffff] prefmem
PCI: 03:04.0 allocate_resources_prefmem: next_base: e0000000 size: 20000000 align: 29 gran: 20 done
PCI: 00:03.0 allocate_resources_mem: base:f2000000 size:3200000 align:25 gran:20 limit:febfffff
Assigned: PCI: 02:00.0 20 *  [0xf2000000 - 0xf50fffff] mem
Assigned: PCI: 02:00.0 10 *  [0xf5100000 - 0xf511ffff] mem
PCI: 00:03.0 allocate_resources_mem: next_base: f5120000 size: 3200000 align: 25 gran: 20 done
PCI: 02:00.0 allocate_resources_mem: base:f2000000 size:3100000 align:25 gran:20 limit:febfffff
Assigned: PCI: 03:04.0 20 *  [0xf2000000 - 0xf50fffff] mem
PCI: 02:00.0 allocate_resources_mem: next_base: f5100000 size: 3100000 align: 25 gran: 20 done
PCI: 03:01.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 03:01.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 03:02.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 03:02.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 03:03.0 allocate_resources_mem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 03:03.0 allocate_resources_mem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 03:04.0 allocate_resources_mem: base:f2000000 size:3100000 align:25 gran:20 limit:febfffff
Assigned: PCI: 07:00.0 1c *  [0xf2000000 - 0xf3ffffff] mem
Assigned: PCI: 07:00.0 10 *  [0xf4000000 - 0xf4ffffff] mem
Assigned: PCI: 07:00.0 30 *  [0xf5000000 - 0xf501ffff] mem
PCI: 03:04.0 allocate_resources_mem: next_base: f5020000 size: 3100000 align: 25 gran: 20 done
PCI: 00:04.0 allocate_resources_prefmem: base:febfffff size:0 align:20 gran:20 limit:febfffff
PCI: 00:04.0 allocate_resources_prefmem: next_base: febfffff size: 0 align: 20 gran: 20 done
PCI: 00:04.0 allocate_resources_mem: base:e0000000 size:10100000 align:28 gran:20 limit:febfffff
Assigned: PCI: 08:08.0 14 *  [0xe0000000 - 0xefffffff] mem
Assigned: PCI: 08:0a.0 18 *  [0xf0000000 - 0xf003ffff] mem
Assigned: PCI: 08:00.0 10 *  [0xf0040000 - 0xf005ffff] mem
Assigned: PCI: 08:01.0 10 *  [0xf0060000 - 0xf007ffff] mem
Assigned: PCI: 08:02.0 10 *  [0xf0080000 - 0xf009ffff] mem
Assigned: PCI: 08:09.0 14 *  [0xf00a0000 - 0xf00a3fff] mem
Assigned: PCI: 08:09.0 18 *  [0xf00a4000 - 0xf00a7fff] mem
Assigned: PCI: 08:0a.0 10 *  [0xf00a8000 - 0xf00abfff] mem
Assigned: PCI: 08:09.0 10 *  [0xf00ac000 - 0xf00adfff] mem
Assigned: PCI: 08:0c.0 10 *  [0xf00ae000 - 0xf00affff] mem
Assigned: PCI: 08:03.0 10 *  [0xf00b0000 - 0xf00b0fff] mem
Assigned: PCI: 08:04.0 10 *  [0xf00b1000 - 0xf00b1fff] mem
Assigned: PCI: 08:05.0 10 *  [0xf00b2000 - 0xf00b2fff] mem
Assigned: PCI: 08:06.0 10 *  [0xf00b3000 - 0xf00b3fff] mem
Assigned: PCI: 08:07.0 10 *  [0xf00b4000 - 0xf00b4fff] mem
Assigned: PCI: 08:08.0 10 *  [0xf00b5000 - 0xf00b5fff] mem
Assigned: PCI: 08:09.0 1c *  [0xf00b6000 - 0xf00b6fff] mem
Assigned: PCI: 08:0a.0 14 *  [0xf00b7000 - 0xf00b7fff] mem
Assigned: PCI: 08:0b.0 10 *  [0xf00b8000 - 0xf00b8fff] mem
Assigned: PCI: 08:0b.0 14 *  [0xf00b9000 - 0xf00b9fff] mem
PCI: 00:04.0 allocate_resources_mem: next_base: f00ba000 size: 10100000 align: 28 gran: 20 done
Root Device assign_resources, bus 0 link: 0
PCI mem marker = c0000000
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
PCI: 00:00.0 14 <- [0x00f5204000 - 0x00f5204fff] size 0x00001000 gran 0x0c mem
PCI: 00:01.0 10 <- [0x00f5205000 - 0x00f5205fff] size 0x00001000 gran 0x0c mem
PCI: 00:02.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:02.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:02.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 01 mem
PCI: 00:03.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 02 io
PCI: 00:03.0 24 <- [0x00c0000000 - 0x00dfffffff] size 0x20000000 gran 0x14 bus 02 prefmem
PCI: 00:03.0 20 <- [0x00f2000000 - 0x00f51fffff] size 0x03200000 gran 0x14 bus 02 mem
PCI: 00:03.0 assign_resources, bus 2 link: 0
PCI: 02:00.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io
PCI: 02:00.0 24 <- [0x00c0000000 - 0x00dfffffff] size 0x20000000 gran 0x14 bus 03 prefmem
PCI: 02:00.0 20 <- [0x00f2000000 - 0x00f50fffff] size 0x03100000 gran 0x14 bus 03 mem
PCI: 02:00.0 10 <- [0x00f5100000 - 0x00f511ffff] size 0x00020000 gran 0x11 mem
PCI: 02:00.0 assign_resources, bus 3 link: 0
PCI: 03:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io
PCI: 03:01.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 04 prefmem
PCI: 03:01.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 04 mem
PCI: 03:02.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io
PCI: 03:02.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 05 prefmem
PCI: 03:02.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 05 mem
PCI: 03:03.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 06 io
PCI: 03:03.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 06 prefmem
PCI: 03:03.0 20 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 06 mem
PCI: 03:04.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 07 io
PCI: 03:04.0 24 <- [0x00c0000000 - 0x00dfffffff] size 0x20000000 gran 0x14 bus 07 prefmem
PCI: 03:04.0 20 <- [0x00f2000000 - 0x00f50fffff] size 0x03100000 gran 0x14 bus 07 mem
PCI: 03:04.0 assign_resources, bus 7 link: 0
PCI: 07:00.0 10 <- [0x00f4000000 - 0x00f4ffffff] size 0x01000000 gran 0x18 mem
PCI: 07:00.0 14 <- [0x00c0000000 - 0x00dfffffff] size 0x20000000 gran 0x1d prefmem64
PCI: 07:00.0 1c <- [0x00f2000000 - 0x00f3ffffff] size 0x02000000 gran 0x19 mem64
PCI: 07:00.0 24 <- [0x0000001000 - 0x000000107f] size 0x00000080 gran 0x07 io
PCI: 07:00.0 30 <- [0x00f5000000 - 0x00f501ffff] size 0x00020000 gran 0x11 romem
PCI: 03:04.0 assign_resources, bus 7 link: 0
PCI: 02:00.0 assign_resources, bus 3 link: 0
PCI: 00:03.0 assign_resources, bus 2 link: 0
PCI: 00:04.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 08 io
PCI: 00:04.0 24 <- [0x00febfffff - 0x00febffffe] size 0x00000000 gran 0x14 bus 08 prefmem
PCI: 00:04.0 20 <- [0x00e0000000 - 0x00f00fffff] size 0x10100000 gran 0x14 bus 08 mem
PCI: 00:04.0 assign_resources, bus 8 link: 0
PCI: 08:00.0 10 <- [0x00f0040000 - 0x00f005ffff] size 0x00020000 gran 0x11 mem
PCI: 08:00.0 14 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io
PCI: 08:01.0 10 <- [0x00f0060000 - 0x00f007ffff] size 0x00020000 gran 0x11 mem
PCI: 08:01.0 14 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io
PCI: 08:02.0 10 <- [0x00f0080000 - 0x00f009ffff] size 0x00020000 gran 0x11 mem
PCI: 08:02.0 14 <- [0x0000002040 - 0x000000205f] size 0x00000020 gran 0x05 io
PCI: 08:03.0 10 <- [0x00f00b0000 - 0x00f00b0fff] size 0x00001000 gran 0x0c mem
PCI: 08:04.0 10 <- [0x00f00b1000 - 0x00f00b1fff] size 0x00001000 gran 0x0c mem
PCI: 08:05.0 10 <- [0x00f00b2000 - 0x00f00b2fff] size 0x00001000 gran 0x0c mem
PCI: 08:06.0 10 <- [0x00f00b3000 - 0x00f00b3fff] size 0x00001000 gran 0x0c mem
PCI: 08:07.0 10 <- [0x00f00b4000 - 0x00f00b4fff] size 0x00001000 gran 0x0c mem
PCI: 08:08.0 10 <- [0x00f00b5000 - 0x00f00b5fff] size 0x00001000 gran 0x0c mem
PCI: 08:08.0 14 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c mem
PCI: 08:09.0 10 <- [0x00f00ac000 - 0x00f00adfff] size 0x00002000 gran 0x0d mem
PCI: 08:09.0 14 <- [0x00f00a0000 - 0x00f00a3fff] size 0x00004000 gran 0x0e mem
PCI: 08:09.0 18 <- [0x00f00a4000 - 0x00f00a7fff] size 0x00004000 gran 0x0e mem
PCI: 08:09.0 1c <- [0x00f00b6000 - 0x00f00b6fff] size 0x00001000 gran 0x0c mem
PCI: 08:0a.0 10 <- [0x00f00a8000 - 0x00f00abfff] size 0x00004000 gran 0x0e mem
PCI: 08:0a.0 14 <- [0x00f00b7000 - 0x00f00b7fff] size 0x00001000 gran 0x0c mem
PCI: 08:0a.0 18 <- [0x00f0000000 - 0x00f003ffff] size 0x00040000 gran 0x12 mem
PCI: 08:0b.0 10 <- [0x00f00b8000 - 0x00f00b8fff] size 0x00001000 gran 0x0c mem
PCI: 08:0b.0 14 <- [0x00f00b9000 - 0x00f00b9fff] size 0x00001000 gran 0x0c mem
PCI: 08:0c.0 10 <- [0x00f00ae000 - 0x00f00affff] size 0x00002000 gran 0x0d mem
PCI: 00:04.0 assign_resources, bus 8 link: 0
PCI: 00:1d.0 20 <- [0x00000030c0 - 0x00000030df] size 0x00000020 gran 0x05 io
PCI: 00:1d.7 10 <- [0x00f5207000 - 0x00f52073ff] size 0x00000400 gran 0x0a mem
PCI: 00:1f.0 40 <- [0x0000003000 - 0x000000307f] size 0x00000080 gran 0x07 io
PCI: 00:1f.0 48 <- [0x0000003080 - 0x00000030bf] size 0x00000040 gran 0x06 io
PCI: 00:1f.0 03 <- [0x00fec00000 - 0x00fec00fff] size 0x00001000 gran 0x00 mem
PCI: 00:1f.0 f0 <- [0x00f5200000 - 0x00f5203fff] size 0x00004000 gran 0x0e mem
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PNP: 004e.4 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
PNP: 004e.4 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
PNP: 004e.5 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
PNP: 004e.5 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
PCI: 00:1f.0 assign_resources, bus 0 link: 0
PCI: 00:1f.2 10 <- [0x0000003410 - 0x0000003417] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 14 <- [0x0000003420 - 0x0000003423] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 18 <- [0x0000003418 - 0x000000341f] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 1c <- [0x0000003424 - 0x0000003427] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 20 <- [0x0000003400 - 0x000000340f] size 0x00000010 gran 0x04 io
PCI: 00:1f.2 24 <- [0x00f5207400 - 0x00f52077ff] size 0x00000400 gran 0x0a mem
PCI: 00:1f.3 20 <- [0x00000030e0 - 0x00000030ff] size 0x00000020 gran 0x05 io
PCI: 00:1f.4 10 <- [0x00f5206000 - 0x00f5206fff] size 0x00001000 gran 0x0c mem
PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0
Root Device assign_resources, bus 0 link: 0
Done setting resources.
Show resources in subtree (Root Device)...After assigning values.
 Root Device links 1 child on link 0 Root Device
  PCI_DOMAIN: 0000 links 1 child on link 0 PCI_DOMAIN: 0000
  PCI_DOMAIN: 0000 resource base 1000 size 2428 align 12 gran 0 limit ffff flags 40040100 index 10000000
  PCI_DOMAIN: 0000 resource base c0000000 size 35207800 align 29 gran 0 limit febfffff flags 40040200 index 10000100
  PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
  PCI_DOMAIN: 0000 resource base c0000 size 1ff40000 align 0 gran 0 limit 0 flags e0004200 index 4
   PCI: 00:00.0 links 0 child on link 0 NULL
   PCI: 00:00.0 resource base f5204000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 14
   PCI: 00:00.1 links 0 child on link 0 NULL
   PCI: 00:01.0 links 0 child on link 0 NULL
   PCI: 00:01.0 resource base f5205000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
   PCI: 00:02.0 links 1 child on link 0 NULL
   PCI: 00:02.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:02.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24
   PCI: 00:02.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20
   PCI: 00:03.0 links 1 child on link 0 PCI: 00:03.0
   PCI: 00:03.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:03.0 resource base c0000000 size 20000000 align 29 gran 20 limit febfffff flags 60081202 index 24
   PCI: 00:03.0 resource base f2000000 size 3200000 align 25 gran 20 limit febfffff flags 60080202 index 20
    PCI: 02:00.0 links 1 child on link 0 PCI: 02:00.0
    PCI: 02:00.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
    PCI: 02:00.0 resource base c0000000 size 20000000 align 29 gran 20 limit febfffff flags 60081202 index 24
    PCI: 02:00.0 resource base f2000000 size 3100000 align 25 gran 20 limit febfffff flags 60080202 index 20
    PCI: 02:00.0 resource base f5100000 size 20000 align 17 gran 17 limit febfffff flags 60000200 index 10
     PCI: 03:01.0 links 1 child on link 0 NULL
     PCI: 03:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
     PCI: 03:01.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24
     PCI: 03:01.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20
     PCI: 03:02.0 links 1 child on link 0 NULL
     PCI: 03:02.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
     PCI: 03:02.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24
     PCI: 03:02.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20
     PCI: 03:03.0 links 1 child on link 0 NULL
     PCI: 03:03.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
     PCI: 03:03.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24
     PCI: 03:03.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60080202 index 20
     PCI: 03:04.0 links 1 child on link 0 PCI: 03:04.0
     PCI: 03:04.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
     PCI: 03:04.0 resource base c0000000 size 20000000 align 29 gran 20 limit febfffff flags 60081202 index 24
     PCI: 03:04.0 resource base f2000000 size 3100000 align 25 gran 20 limit febfffff flags 60080202 index 20
      PCI: 07:00.0 links 0 child on link 0 NULL
      PCI: 07:00.0 resource base f4000000 size 1000000 align 24 gran 24 limit febfffff flags 60000200 index 10
      PCI: 07:00.0 resource base c0000000 size 20000000 align 29 gran 29 limit febfffff flags 60001201 index 14
      PCI: 07:00.0 resource base f2000000 size 2000000 align 25 gran 25 limit febfffff flags 60000201 index 1c
      PCI: 07:00.0 resource base 1000 size 80 align 7 gran 7 limit ffff flags 60000100 index 24
      PCI: 07:00.0 resource base f5000000 size 20000 align 17 gran 17 limit febfffff flags 60002200 index 30
   PCI: 00:04.0 links 1 child on link 0 PCI: 00:04.0
   PCI: 00:04.0 resource base 2000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
   PCI: 00:04.0 resource base febfffff size 0 align 20 gran 20 limit febfffff flags 60081202 index 24
   PCI: 00:04.0 resource base e0000000 size 10100000 align 28 gran 20 limit febfffff flags 60080202 index 20
    PCI: 08:00.0 links 0 child on link 0 NULL
    PCI: 08:00.0 resource base f0040000 size 20000 align 17 gran 17 limit febfffff flags 60000200 index 10
    PCI: 08:00.0 resource base 2000 size 20 align 5 gran 5 limit ffff flags 60000100 index 14
    PCI: 08:01.0 links 0 child on link 0 NULL
    PCI: 08:01.0 resource base f0060000 size 20000 align 17 gran 17 limit febfffff flags 60000200 index 10
    PCI: 08:01.0 resource base 2020 size 20 align 5 gran 5 limit ffff flags 60000100 index 14
    PCI: 08:02.0 links 0 child on link 0 NULL
    PCI: 08:02.0 resource base f0080000 size 20000 align 17 gran 17 limit febfffff flags 60000200 index 10
    PCI: 08:02.0 resource base 2040 size 20 align 5 gran 5 limit ffff flags 60000100 index 14
    PCI: 08:03.0 links 0 child on link 0 NULL
    PCI: 08:03.0 resource base f00b0000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
    PCI: 08:04.0 links 0 child on link 0 NULL
    PCI: 08:04.0 resource base f00b1000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
    PCI: 08:05.0 links 0 child on link 0 NULL
    PCI: 08:05.0 resource base f00b2000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
    PCI: 08:06.0 links 0 child on link 0 NULL
    PCI: 08:06.0 resource base f00b3000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
    PCI: 08:07.0 links 0 child on link 0 NULL
    PCI: 08:07.0 resource base f00b4000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
    PCI: 08:08.0 links 0 child on link 0 NULL
    PCI: 08:08.0 resource base f00b5000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
    PCI: 08:08.0 resource base e0000000 size 10000000 align 28 gran 28 limit febfffff flags 60000200 index 14
    PCI: 08:09.0 links 0 child on link 0 NULL
    PCI: 08:09.0 resource base f00ac000 size 2000 align 13 gran 13 limit febfffff flags 60000200 index 10
    PCI: 08:09.0 resource base f00a0000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 14
    PCI: 08:09.0 resource base f00a4000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 18
    PCI: 08:09.0 resource base f00b6000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 1c
    PCI: 08:0a.0 links 0 child on link 0 NULL
    PCI: 08:0a.0 resource base f00a8000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index 10
    PCI: 08:0a.0 resource base f00b7000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 14
    PCI: 08:0a.0 resource base f0000000 size 40000 align 18 gran 18 limit febfffff flags 60000200 index 18
    PCI: 08:0b.0 links 0 child on link 0 NULL
    PCI: 08:0b.0 resource base f00b8000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
    PCI: 08:0b.0 resource base f00b9000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 14
    PCI: 08:0c.0 links 0 child on link 0 NULL
    PCI: 08:0c.0 resource base f00ae000 size 2000 align 13 gran 13 limit febfffff flags 60000200 index 10
   PCI: 00:08.0 links 0 child on link 0 NULL
   PCI: 00:0d.0 links 0 child on link 0 NULL
   PCI: 00:0d.1 links 0 child on link 0 NULL
   PCI: 00:1d.0 links 0 child on link 0 NULL
   PCI: 00:1d.0 resource base 30c0 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
   PCI: 00:1d.7 links 0 child on link 0 NULL
   PCI: 00:1d.7 resource base f5207000 size 400 align 10 gran 10 limit febfffff flags 60000200 index 10
   PCI: 00:1f.0 links 1 child on link 0 PCI: 00:1f.0
   PCI: 00:1f.0 resource base 3000 size 80 align 7 gran 7 limit ffff flags 60000100 index 40
   PCI: 00:1f.0 resource base 3080 size 40 align 6 gran 6 limit ffff flags 60000100 index 48
   PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
   PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
   PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags e0000200 index 3
   PCI: 00:1f.0 resource base f5200000 size 4000 align 14 gran 14 limit febfffff flags 60000200 index f0
    PNP: 004e.4 links 0 child on link 0 NULL
    PNP: 004e.4 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
    PNP: 004e.4 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
    PNP: 004e.5 links 0 child on link 0 NULL
    PNP: 004e.5 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60
    PNP: 004e.5 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
   PCI: 00:1f.2 links 0 child on link 0 NULL
   PCI: 00:1f.2 resource base 3410 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
   PCI: 00:1f.2 resource base 3420 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
   PCI: 00:1f.2 resource base 3418 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
   PCI: 00:1f.2 resource base 3424 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
   PCI: 00:1f.2 resource base 3400 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
   PCI: 00:1f.2 resource base f5207400 size 400 align 10 gran 10 limit febfffff flags 60000200 index 24
   PCI: 00:1f.3 links 0 child on link 0 NULL
   PCI: 00:1f.3 resource base 30e0 size 20 align 5 gran 5 limit ffff flags 60000100 index 20
   PCI: 00:1f.4 links 0 child on link 0 NULL
   PCI: 00:1f.4 resource base f5206000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 10
  APIC_CLUSTER: 0 links 1 child on link 0 APIC_CLUSTER: 0
   APIC: 00 links 0 child on link 0 NULL
Done allocating resources.
Enabling resources...
PCI: 00:00.0 subsystem <- 8086/2680
PCI: 00:00.0 cmd <- 06
PCI: 00:00.1 subsystem <- 8086/2680
PCI: 00:00.1 cmd <- 00
PCI: 00:01.0 subsystem <- 8086/2680
PCI: 00:01.0 cmd <- 06
PCI: 00:02.0 bridge ctrl <- 0003
PCI: 00:02.0 cmd <- 00
PCI: 00:03.0 bridge ctrl <- 000b
PCI: 00:03.0 cmd <- 07
PCI: 02:00.0 bridge ctrl <- 000b
PCI: 02:00.0 cmd <- 07
PCI: 03:01.0 bridge ctrl <- 0003
PCI: 03:01.0 cmd <- 00
PCI: 03:02.0 bridge ctrl <- 0003
PCI: 03:02.0 cmd <- 00
PCI: 03:03.0 bridge ctrl <- 0003
PCI: 03:03.0 cmd <- 00
PCI: 03:04.0 bridge ctrl <- 000b
PCI: 03:04.0 cmd <- 07
PCI: 07:00.0 cmd <- 03
PCI: 00:04.0 bridge ctrl <- 0003
PCI: 00:04.0 cmd <- 07
PCI: 08:00.0 cmd <- 03
PCI: 08:01.0 cmd <- 03
PCI: 08:02.0 cmd <- 03
PCI: 08:03.0 cmd <- 02
PCI: 08:04.0 cmd <- 02
PCI: 08:05.0 cmd <- 02
PCI: 08:06.0 cmd <- 02
PCI: 08:07.0 cmd <- 02
PCI: 08:08.0 cmd <- 02
PCI: 08:09.0 cmd <- 02
PCI: 08:0a.0 cmd <- 06
PCI: 08:0b.0 cmd <- 02
PCI: 08:0c.0 cmd <- 02
PCI: 00:1d.0 subsystem <- 8086/2680
PCI: 00:1d.0 cmd <- 01
PCI: 00:1d.7 subsystem <- 8086/2680
PCI: 00:1d.7 cmd <- 02
PCI: 00:1f.0 cmd <- 07
PCI: 00:1f.2 subsystem <- 8086/2680
PCI: 00:1f.2 cmd <- 03
PCI: 00:1f.3 subsystem <- 8086/2680
PCI: 00:1f.3 cmd <- 01
PCI: 00:1f.4 subsystem <- 8086/2680
PCI: 00:1f.4 cmd <- 02
done.
Initializing devices...
Root Device init
PCI: 00:00.0 init
PCI: 00:00.1 init
PCI: 00:01.0 init
PCI: 00:1d.0 init
PCI: 00:1d.7 init
PCI: 00:1f.0 init
set power on after power fail
NMI sources disabled.
RTC Init
PNP: 004e.4 init
PNP: 004e.5 init
PCI: 00:1f.2 init
SATA init (Legacy mode)
SATA Enabled
PCI: 00:1f.4 init
APIC_CLUSTER: 0 init
Initializing CPU #0
CPU: vendor Intel device 10650
CPU: family 06, model 15, stepping 00
Enabling cache

Setting fixed MTRRs(0-88) Type: UC
Setting fixed MTRRs(0-16) Type: WB
Setting fixed MTRRs(24-88) Type: WB
DONE fixed MTRRs
call enable_fixed_mtrr()
Setting variable MTRR 0, base:    0MB, range:  512MB, type WB
ADDRESS_MASK_HIGH=0xf
Zero-sized MTRR range @0KB
DONE variable MTRRs
Clear out the extra MTRR's
call enable_var_mtrr()
Leave x86_setup_var_mtrrs

MTRR check
Fixed MTRRs   : Enabled
Variable MTRRs: Enabled

microcode_info: sig = 0x00010650 pf=0x00000010 rev = 0x00000000

Setting up local apic... apic_id: 0x00 done.
CPU #0 initialized
All AP CPUs stopped
PCI: 07:00.0 init
PCI: 08:00.0 init
PCI: 08:01.0 init
PCI: 08:02.0 init
PCI: 08:03.0 init
PCI: 08:04.0 init
PCI: 08:05.0 init
PCI: 08:06.0 init
PCI: 08:07.0 init
PCI: 08:08.0 init
PCI: 08:09.0 init
PCI: 08:0a.0 init
PCI: 08:0b.0 init
PCI: 08:0c.0 init
Devices initialized
Show all devs...After init.
Root Device: enabled 1, 0 resources
PCI_DOMAIN: 0000: enabled 1, 4 resources
PCI: 00:00.0: enabled 1, 1 resources
PCI: 00:00.1: enabled 1, 0 resources
PCI: 00:01.0: enabled 1, 1 resources
PCI: 00:02.0: enabled 1, 3 resources
PCI: 00:03.0: enabled 1, 3 resources
PCI: 00:04.0: enabled 1, 3 resources
PCI: 00:08.0: enabled 0, 0 resources
PCI: 00:0d.0: enabled 0, 0 resources
PCI: 00:0d.1: enabled 0, 0 resources
PCI: 00:1d.0: enabled 1, 1 resources
PCI: 00:1d.7: enabled 1, 1 resources
PCI: 00:1f.0: enabled 1, 6 resources
PNP: 004e.4: enabled 1, 2 resources
PNP: 004e.5: enabled 1, 2 resources
PCI: 00:1f.2: enabled 1, 6 resources
PCI: 00:1f.3: enabled 1, 1 resources
PCI: 00:1f.4: enabled 1, 1 resources
APIC_CLUSTER: 0: enabled 1, 0 resources
APIC: 00: enabled 1, 0 resources
PCI: 02:00.0: enabled 1, 4 resources
PCI: 03:01.0: enabled 1, 3 resources
PCI: 03:02.0: enabled 1, 3 resources
PCI: 03:03.0: enabled 1, 3 resources
PCI: 03:04.0: enabled 1, 3 resources
PCI: 07:00.0: enabled 1, 5 resources
PCI: 08:00.0: enabled 1, 2 resources
PCI: 08:01.0: enabled 1, 2 resources
PCI: 08:02.0: enabled 1, 2 resources
PCI: 08:03.0: enabled 1, 1 resources
PCI: 08:04.0: enabled 1, 1 resources
PCI: 08:05.0: enabled 1, 1 resources
PCI: 08:06.0: enabled 1, 1 resources
PCI: 08:07.0: enabled 1, 1 resources
PCI: 08:08.0: enabled 1, 2 resources
PCI: 08:09.0: enabled 1, 4 resources
PCI: 08:0a.0: enabled 1, 3 resources
PCI: 08:0b.0: enabled 1, 2 resources
PCI: 08:0c.0: enabled 1, 1 resources
High Tables Base is 1fff0000.
Copying Interrupt Routing Table to 0x000f0000... done.
Copying Interrupt Routing Table to 0x1fff0000... done.
Wrote the mp table end at: 000f0410 - 000f05a0
Wrote the mp table end at: 1fff0410 - 1fff05a0
Moving GDT to 0x1fff0800...ok
Multiboot Information structure has been written.
Writing high table forward entry at 0x00000500
Wrote coreboot table at: 00000500 - 00000518  checksum d3df
New low_table_end: 0x00000518
Now going to write high coreboot table at 0x1fff0c00
rom_table_end = 0x1fff0c00
Adjust low_table_end from 0x00000518 to 0x00001000 
Adjust rom_table_end from 0x1fff0c00 to 0x20000000 
Adding high table area
Wrote coreboot table at: 1fff0c00 - 1fff0df4  checksum 8b7e
Check CBFS header at fffdffd0
magic is 4f524243
Found CBFS header at fffdffd0
Check fallback/payload
Got a payload
Segment ffe00038
data: malloc Enter, size 36, free_mem_ptr 000271a4
malloc 000271a4
New segment dstaddr 0xf0000 memsize 0x10000 srcaddr 0xffe00070 filesize 0x10000
(cleaned up) New segment addr 0xf0000 size 0x10000 offset 0xffe00070 filesize 0x10000
Segment ffe00054
Entry 000fc1cf
Loading Segment: addr: 0x00000000000f0000 memsz: 0x0000000000010000 filesz: 0x0000000000010000
lb: [0x0000000000004000, 0x000000000002a000)
Post relocation: addr: 0x00000000000f0000 memsz: 0x0000000000010000 filesz: 0x0000000000010000
it's not compressed!
[ 0x00000000000f0000, 0000000000100000, 0x0000000000100000) <- 00000000ffe00070
Loaded segments
Jumping to boot code at fc1cf
entry    = 0x000fc1cf
lb_start = 0x00004000
lb_size  = 0x00026000
adjust   = 0x1ffa0000
buffer   = 0x1ffa4000
     elf_boot_notes = 0x00018b60
adjusted_boot_notes = 0x1ffb8b60
Start bios
init ivt
init bda
init pic
init timer
tsc calibrate start=3268062738 end=3269437439 diff=1374701
CPU Mhz=800
math cp init
bios_table_addr: 0x000fd4c0 end=0x000fdcc0
Find memory size
Attempting to find coreboot table
Found coreboot table forwarder.
Now attempting to find coreboot memory map
Copying PIR from 0x1fff0000 to fd4c0
Copying MPTABLE from 0x1fff0400/1fff0410 to fd4f0
init SMBIOS tables
SMBIOS table addr=0x000fd690
Found mainboard Intel Truxton
Found CBFS header at 0xfffdffd0
Ram Size=0x1fff0000
Found 1 cpu(s)
init PNPBIOS table
Scan for VGA option rom
Attempting to init PCI bdf 07:00.0 (dev/ven 42110de)
Searching CBFS for data file pci10de,0421.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 07:00.0
Option rom sizing returned f5000000 fffe0000
Inspecting possible rom at 0xf5000000 (dv=42110de bdf=700)
Copying option rom (size 56832) from 0xf5000000 to c0000
Checking rom 0x000c0000 (sig aa55 size 111)
Running option rom at c000:0003
Searching CBFS for data file prefix vgaroms/
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Turning on vga console
Starting SeaBIOS

init keyboard
i8042_flush
i8042 flushed ff (status=ff)
i8042 flushed ff (status=ff)
i8042 flushed ff (status=ff)
i8042 flushed ff (status=ff)
i8042 flushed ff (status=ff)
i8042 flushed ff (status=ff)
i8042 flushed ff (status=ff)
i8042 flushed ff (status=ff)
i8042 flushed ff (status=ff)
i8042 flushed ff (status=ff)
i8042 flushed ff (status=ff)
i8042 flushed ff (status=ff)
i8042 flushed ff (status=ff)
i8042 flushed ff (status=ff)
i8042 flushed ff (status=ff)
i8042 flushed ff (status=ff)
i8042 timeout on flush
init lpt
Found 0 lpt ports
init serial
Found 2 serial ports
init mouse
e820 map has 5 items:
  0: 0000000000000000 - 000000000009fc00 = 1
  1: 000000000009fc00 - 00000000000a0000 = 2
  2: 00000000000f0000 - 0000000000100000 = 2
  3: 0000000000100000 - 000000001fff0000 = 1
  4: 000000001fff0000 - 0000000020000000 = 2
final bios_table_addr: 0x000fd773 (used 33%)
init boot device ordering
init floppy drives
init hard drives
ATA controller 0 at 3410/3420 (dev fa prog_if 8f)
ATA controller 1 at 3418/3424 (dev fa prog_if 8f)
powerup iobase=3410 st=0
powerup iobase=3410 st=0
ata_detect drive=0 sc=55 sn=aa dh=a0
ata_reset driveid=0
ata_reset exit status=0
Identify w0=85c0 w2=0
ata0-0: ATAPI   DVD C  DH52C2S ATAPI-7 CD-Rom/DVD-Rom
ata_detect resetresult=0000
powerup iobase=3410 st=50
powerup iobase=3410 st=0
ata_detect drive=1 sc=55 sn=aa dh=b0
send_cmd : DRQ not set (status 00)
powerup iobase=3418 st=50
powerup iobase=3418 st=50
ata_detect drive=2 sc=55 sn=aa dh=a0
ata_reset driveid=2
ata_reset exit status=50
send_cmd : read error (status=51 err=04)
Identify w0=427a w2=c837
ata1-0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63
ata1-0: WDC WD1600JS-00NCB1 ATA-7 Hard-Disk (149 GiBytes)
ata_detect resetresult=0000
powerup iobase=3418 st=50
powerup iobase=3418 st=0
ata_detect drive=3 sc=55 sn=aa dh=b0
send_cmd : DRQ not set (status 00)

Scan for option roms
Attempting to init PCI bdf 00:00.0 (dev/ven 50208086)
Searching CBFS for data file pci8086,5020.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 00:00.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:00.1 (dev/ven 50218086)
Searching CBFS for data file pci8086,5021.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 00:00.1
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:01.0 (dev/ven 50238086)
Searching CBFS for data file pci8086,5023.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 00:01.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:02.0 (dev/ven 50248086)
Searching CBFS for data file pci8086,5024.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 00:02.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 00:03.0 (dev/ven 50258086)
Searching CBFS for data file pci8086,5025.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 00:03.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 00:04.0 (dev/ven 50378086)
Searching CBFS for data file pci8086,5037.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 00:04.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 00:08.0 (dev/ven 50268086)
Searching CBFS for data file pci8086,5026.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 00:08.0
Option rom sizing returned 0 1e
Preset rom address doesn't look valid
Attempting to init PCI bdf 00:0d.0 (dev/ven 50228086)
Searching CBFS for data file pci8086,5022.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 00:0d.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1d.0 (dev/ven 50338086)
Searching CBFS for data file pci8086,5033.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 00:1d.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1d.7 (dev/ven 50358086)
Searching CBFS for data file pci8086,5035.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 00:1d.7
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1f.0 (dev/ven 50318086)
Searching CBFS for data file pci8086,5031.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 00:1f.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1f.3 (dev/ven 50328086)
Searching CBFS for data file pci8086,5032.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 00:1f.3
Option rom sizing returned 0 0
Attempting to init PCI bdf 00:1f.4 (dev/ven 50368086)
Searching CBFS for data file pci8086,5036.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 00:1f.4
Option rom sizing returned 0 0
Attempting to init PCI bdf 02:00.0 (dev/ven 850810b5)
Searching CBFS for data file pci10b5,8508.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 02:00.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 03:01.0 (dev/ven 850810b5)
Searching CBFS for data file pci10b5,8508.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 03:01.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 03:02.0 (dev/ven 850810b5)
Searching CBFS for data file pci10b5,8508.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 03:02.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 03:03.0 (dev/ven 850810b5)
Searching CBFS for data file pci10b5,8508.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 03:03.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 03:04.0 (dev/ven 850810b5)
Searching CBFS for data file pci10b5,8508.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 03:04.0
Skipping non-normal pci device (type=1)
Attempting to init PCI bdf 08:00.0 (dev/ven 50418086)
Searching CBFS for data file pci8086,5041.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 08:00.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 08:01.0 (dev/ven 50458086)
Searching CBFS for data file pci8086,5045.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 08:01.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 08:02.0 (dev/ven 50498086)
Searching CBFS for data file pci8086,5049.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 08:02.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 08:03.0 (dev/ven 503e8086)
Searching CBFS for data file pci8086,503e.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 08:03.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 08:04.0 (dev/ven 50398086)
Searching CBFS for data file pci8086,5039.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 08:04.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 08:05.0 (dev/ven 503a8086)
Searching CBFS for data file pci8086,503a.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 08:05.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 08:06.0 (dev/ven 503b8086)
Searching CBFS for data file pci8086,503b.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 08:06.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 08:07.0 (dev/ven 503c8086)
Searching CBFS for data file pci8086,503c.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 08:07.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 08:08.0 (dev/ven 503d8086)
Searching CBFS for data file pci8086,503d.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 08:08.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 08:09.0 (dev/ven 502d8086)
Searching CBFS for data file pci8086,502d.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 08:09.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 08:0a.0 (dev/ven 503f8086)
Searching CBFS for data file pci8086,503f.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 08:0a.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 08:0b.0 (dev/ven 504c8086)
Searching CBFS for data file pci8086,504c.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 08:0b.0
Option rom sizing returned 0 0
Attempting to init PCI bdf 08:0c.0 (dev/ven 50308086)
Searching CBFS for data file pci8086,5030.rom
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Attempting to map option rom on dev 08:0c.0
Option rom sizing returned 0 0
Searching CBFS for data file prefix genroms/
Found CBFS file fallback/payload
Found CBFS file fallback/coreboot_ram
Found CBFS file 
Press F12 for boot menu.

Mapping driveid 2 to 0
Jump to int19
enter handle_19:
  NULL
Booting from Floppy...
fail check_drive:379(80):
   a=00000201  b=00000000  c=00000001  d=00000000 ds=0000 es=07c0 ss=0000
  si=00000000 di=00000000 bp=00000000 sp=000072fc cs=f000 ip=c09e  f=0002
Boot failed: could not read the boot disk

enter handle_18:
  NULL
Booting from CD-Rom...
atapi_is_ready (device=0)
send_atapi_cmd : read error (status=51 err=60)
sectors=301647
589MB medium detected
Booting from 0000:7c00
ata_reset driveid=2
ata_reset exit status=50
enter handle_12:
   a=00000000  b=00000000  c=00000000  d=00000080 ds=0000 es=0000 ss=0000
  si=00008116 di=00053880 bp=00001ff0 sp=00001ff4 cs=0000 ip=8a01  f=0297
fail get_device:643(1):
   a=00004100  b=000555aa  c=00000000  d=00000081 ds=0000 es=0000 ss=0000
  si=00067fc8 di=00000081 bp=00001ff0 sp=00001ff4 cs=0000 ip=88b5  f=0246
fail get_device:643(1):
   a=00000800  b=00000000  c=00000000  d=00000081 ds=0000 es=0000 ss=0000
  si=00067fc8 di=00000081 bp=00001ff0 sp=00001ff4 cs=0000 ip=88e9  f=0246
fail handle_15XX:314(86):
   a=000000c0  b=00000000  c=00000000  d=00000001 ds=0000 es=0000 ss=0000
  si=00053908 di=00000081 bp=00001ff0 sp=00001ff4 cs=0000 ip=8ab6  f=0246
fail floppy_1300:414(80):
   a=00000000  b=00009000  c=00000000  d=00000000 ds=0000 es=0000 ss=0000
  si=002c1034 di=0009a000 bp=00001ff0 sp=00001ff4 cs=0000 ip=82c5  f=0246
fail get_device:643(1):
   a=00001500  b=00009000  c=00000000  d=00000081 ds=9000 es=9000 ss=9000
  si=002c1034 di=0009a000 bp=00001ff0 sp=00008ffe cs=9020 ip=0d07  f=0046
stub handle_16XX:272:
   a=534d0305  b=00000000  c=00003c00  d=0007bfc0 ds=9000 es=9000 ss=9000
  si=002c1034 di=00090334 bp=00001ff0 sp=00008ffe cs=9020 ip=0e77  f=0046
fail get_device:643(1):
   a=534d1500  b=00000000  c=00000000  d=00070981 ds=f000 es=9000 ss=9000
  si=002cff63 di=000900a0 bp=00001ff0 sp=00008ffe cs=9020 ip=0eaa  f=0046
enter handle_11:
   a=534d9000  b=0000e6f5  c=00000000  d=00070981 ds=9000 es=9000 ss=9000
  si=002ce6ff di=000900aa bp=00001ff0 sp=00008ffe cs=9020 ip=0f06  f=0086
fail handle_15XX:314(86):
   a=0000e980  b=0000e6f5  c=00000000  d=47534943 ds=9000 es=9000 ss=9000
  si=002ce6ff di=000900aa bp=00001ff0 sp=00008ffe cs=9020 ip=0f1e  f=0002
fail get_device:643(1):
   a=ffff0201  b=00000d00  c=00000001  d=47530081 ds=9000 es=9000 ss=9000
  si=fff0fff0 di=0009fff0 bp=

vga not working

[Arnaud Maye]

Hello Again,

Just wanted to add that at the time legacy BIOS (AMI ) initializes the 
"Club3D 8500GT", the GFX
card displays the GFX card model on the upper left corner of the screen 
as a text. In the other hand
this text is not displayed when seabios executes the vgabios.

The strange square pattern has a 720x400 resolution, this is what is 
happening as soon the vga console
is turned on.

Then for a few seconds (3-5), the monitor switches to 640x480. At this 
time the screen is black with a
few white points here and there.

Finally the monitor switches back to 720x400 with weird square patterns. 
At this time the pattern are
changing probably in sync with the linux boot.

I hope the additional infos will help.

Thank you

Arnaud

Arnaud Maye wrote:
> Hello Kevin,
>
> So the vgabios came from the manufacturer in fact. I have removed the 
> vgabios from the cbfs and
> indeed seabios seems to execute the vgabios extracted from the card.
>
> I have tried two GFX cards :
> Matrox G550 pci express 1 lane
> Club3D 8500GT Silent edition 16 lanes
>
> Both of the cards behaving same besides colors of the squares. As an 
> additional note, seabios does
> boot my Linux from the HDD as there is a lot of activity on the hard 
> disk led. It seems the faulty output
> is displaying something as we can see the output moving in sync with 
> what is supposed to be the linux
> boot.
>
> Attached is the boot log when the 8500GT card is attached. Being 
> unsure about the maximum attachment
> size in the mailing list I've been uploading video of the faulty 
> output there :
>
> http://www.gigasize.com/get.php?d=z15rwqb3zqc
>
> The G550 output look same as the 8500GT output. The only difference is 
> that most of the grey square are
> black.
>
> Any idea what I could be doing wrong Kevin?
>
> Thank you.
>
> Arnaud
>
> Kevin O'Connor wrote:
> > On Sun, Jul 26, 2009 at 01:00:52PM +0200, Arnaud Maye wrote:
> > > I've been on IRC for a GFX output issue on Friday. Actually the
> > > output is always black or full of non sense square on the screen. I
> > > have tried two graphic cards and in this respect it is fair to point
> > > the issue outside of the vgarom.
> >
> > [...]
> > > Scan for VGA option rom
> > > Attempting to init PCI bdf 07:00.0 (dev/ven 42110de)
> > > Searching CBFS for data file pci10de,0421.rom
> > > Found CBFS file fallback/payload
> > > Found CBFS file fallback/coreboot_ram
> > > Found CBFS file pci10de,0421.rom
> > > Copying data 58368@0xffe17a98 to 196608@0x000c0000
> > > Checking rom 0x000c0000 (sig aa55 size 114)
> > > Running option rom at c000:0003
> >
> > How did you obtain the vgabios?  Is this a vga adapter built-in to the
> > motherboard, or one on an external card?
> >
> > For vga adapters on external cards, one should not add the vgabios to
> > CBFS - SeaBIOS can extract the vgabios directly from the card.
> >
> > -Kevin

*
*

vga not working

[Kevin O'Connor]

On Tue, Jul 28, 2009 at 12:50:46PM +0200, Arnaud Maye wrote:
> The strange square pattern has a 720x400 resolution, this is what is
> happening as soon the vga console is turned on.

[...]
> > I have tried two GFX cards :
> > Matrox G550 pci express 1 lane
> > Club3D 8500GT Silent edition 16 lanes
> >
> > Both of the cards behaving same besides colors of the squares.

Hi Arnaud,

I don't know what would cause this.  A couple of guesses:

* coreboot isn't setting up the pci space with the correct legacy
  ranges

* seabios isn't implementing some bios feature the card is expecting

Because you're seeing this on two completely different vga cards, I'd
guess that it's something with the coreboot pci setup.  I'm not
familiar with Club3D - can you verify it isn't also using a Matrox
chip?

-Kevin

vga not working

[Arnaud Maye]

Hello Kevin,

Kevin O'Connor wrote:
> On Tue, Jul 28, 2009 at 12:50:46PM +0200, Arnaud Maye wrote:
> > The strange square pattern has a 720x400 resolution, this is what is
> > happening as soon the vga console is turned on.
>
> [...]
> > > I have tried two GFX cards :
> > > Matrox G550 pci express 1 lane
> > > Club3D 8500GT Silent edition 16 lanes
> > >
> > > Both of the cards behaving same besides colors of the squares.
>
> Hi Arnaud,
>
> I don't know what would cause this.  A couple of guesses:
> coreboot isn't setting up the pci space with the correct legacy
> ranges

We are talking about the GFX cards legacy ranges, right? I think Myles 
looked at the PCI
allocation already it seems everything is fine there.

"Re: [coreboot] non static < 0x1000 IO space can be broken |    
(EP80579) Addition"
> seabios isn't implementing some bios feature the card is expecting
>
> Because you're seeing this on two completely different vga cards, I'd
> guess that it's something with the coreboot pci setup.  I'm not
> familiar with Club3D - can you verify it isn't also using a Matrox
> chip?

The Club3D card is using a Nvidia G86 chipset. Quite a recent chipset.

http://www.hexus.net/content/item.php?item=8839

The G550 :

http://www.matrox.com/graphics/en/products/graphics_cards/g_series/g550pcie/

Both these cards are PCIe cards.
> -Kevin

As everything is not so bad, some good news. Actually besides the VGA 
(output) and Keyboard (input) my linux is booting from hard disk. I can
SSH to the hardware. I've attached our FM577 using a PMC->PCIe adapter 
just before and it is recognized. I will try a few DMAs later on.

Kevin are you able to recommend me any recent PCIe card which is known 
to be working "out of the box" under seabios? That way I will just
purchase this adapter to get up and running with the VGA. Actually I 
need to get XP to boot so I would need VGA to diagnose the windows
boot this is going to be easier.

Thank you

Kevin
*
*

vga not working

[Kevin O'Connor]

On Wed, Jul 29, 2009 at 10:31:59AM +0200, Arnaud Maye wrote:
> Kevin O'Connor wrote:
> > On Tue, Jul 28, 2009 at 12:50:46PM +0200, Arnaud Maye wrote:
> > > > I have tried two GFX cards :
> > > > Matrox G550 pci express 1 lane
> > > > Club3D 8500GT Silent edition 16 lanes
> > > >
> > > > Both of the cards behaving same besides colors of the squares.
> >
> > I don't know what would cause this.  A couple of guesses:
> > coreboot isn't setting up the pci space with the correct legacy
> > ranges
>
> We are talking about the GFX cards legacy ranges, right? I think
> Myles looked at the PCI allocation already it seems everything is
> fine there.

Setting up VGA is special in a number of ways.  I'm wondering if
something is not correct in the setup.  Again, it seems likely that
coreboot is the culprit if two completely different cards are showing
similar behavior.

[...]
> Kevin are you able to recommend me any recent PCIe card which is known  
> to be working "out of the box" under seabios? That way I will just
> purchase this adapter to get up and running with the VGA. Actually I  
> need to get XP to boot so I would need VGA to diagnose the windows
> boot this is going to be easier.

I have never tested with a PCIe VGA card.  Perhaps someone on the list
has.  However, if the issue is with coreboot, a third card will likely
exhibit the same results.

-Kevin

vga not working

[Myles Watson]

On Wed, Jul 29, 2009 at 2:31 AM, Arnaud Maye  wrote:
> coreboot isn't setting up the pci space with the correct legacy ranges
> We are talking about the GFX cards legacy ranges, right? I think Myles
> looked at the PCI
> allocation already it seems everything is fine there.

Actually I said that it wouldn't be related to the allocator because the
legacy VGA ranges are not aren't allocated there.  This is the place to
start to look for that:

Setting up VGA for PCI: 07:00.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 03:04.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 02:00.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:03.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...

1. Make sure that that's the path to your graphics card.
2. Make sure that the correct bits get set in each device so that the I/O to
the graphics card gets there.
  - The PCI_BRIDGE_CTL_VGA bit is in the device structure, so it doesn't
affect hardware
  - Many bridges need some bit set to decode those ranges

I guess I don't know how to tell where the I/O gets stopped.  If 2:00.0 is
misconfigured, but 00:03.0 and 3:04.0 are correctly configured, how would
you know?  Most of the ways I can think of to debug that are all or nothing.

I've used PCIe graphics cards with my Tyan boards, and they are initialized
correctly.  I agree with Kevin that a third card will likely have the same
problems you're seeing.

Good luck,
Myles

vga not working

[Kevin O'Connor]

On Thu, Jul 30, 2009 at 09:56:20AM -0600, Myles Watson wrote:
> On Wed, Jul 29, 2009 at 2:31 AM, Arnaud Maye  wrote:
> > We are talking about the GFX cards legacy ranges, right? I think
> > Myles looked at the PCI allocation already it seems everything is
> > fine there.
>
> Actually I said that it wouldn't be related to the allocator because the
> legacy VGA ranges are not aren't allocated there.  This is the place to
> start to look for that:

[...]
> Make sure that that's the path to your graphics card.
> Make sure that the correct bits get set in each device so that the I/O to
>
> the graphics card gets there.
> The PCI_BRIDGE_CTL_VGA bit is in the device structure, so it doesn't
>
> affect hardware
> Many bridges need some bit set to decode those ranges

In addition to making sure the legacy IO ranges are correct, you also
need to verify the legacy vga memory range (0xa0000 - 0xc0000) is
properly configured in the bridges.  Also, the chipset needs to have
this range be a pci hole - it must not have memory mapped there.

-Kevin

vga not working

[Arnaud Maye]

Hello Gents,

Thank you for your pointers. I will not be able to work on the BIOS 
until late August. We have a few
other things in //. I will investigate around this and keep you updated 
as soon am back to this project :)

Thank you

Arnaud

Kevin O'Connor wrote:
> On Thu, Jul 30, 2009 at 09:56:20AM -0600, Myles Watson wrote:
> > On Wed, Jul 29, 2009 at 2:31 AM, Arnaud Maye  wrote:
> > > We are talking about the GFX cards legacy ranges, right? I think
> > > Myles looked at the PCI allocation already it seems everything is
> > > fine there.
> >
> > Actually I said that it wouldn't be related to the allocator because the
> > legacy VGA ranges are not aren't allocated there.  This is the place to
> > start to look for that:
>
> [...]
> > Make sure that that's the path to your graphics card.
> > Make sure that the correct bits get set in each device so that the I/O to
> >
> > the graphics card gets there.
> > The PCI_BRIDGE_CTL_VGA bit is in the device structure, so it doesn't
> >
> > affect hardware
> > Many bridges need some bit set to decode those ranges
>
> In addition to making sure the legacy IO ranges are correct, you also
> need to verify the legacy vga memory range (0xa0000 - 0xc0000) is
> properly configured in the bridges.  Also, the chipset needs to have
> this range be a pci hole - it must not have memory mapped there.
>
> -Kevin

*
*

vga not working

[Arnaud Maye]

Hello Guys,

I've got the VGA to operating correctly in seabios. Actually it was as 
simple as enabling the VGA
forwarding on the pci root complex, in the northbridge. Actually during 
the coreboot boot, the VGA
output does not make much sense but as soon the OS boots, I can see the 
complete boot.

This bit can be set for one PCIe "port" or the other, actually two 
possible settings but both cannot
be enabled in the same time. So the bit to set depends where the GFX 
card is attached in fact.
Should we proceed with this "detection" to set the correct bit or can we 
assume the user connects
his card to PCIe SLOT0, in this case we hard code the correct bit 
setting for PCIe SLOT0?

So far I am doing this in the auto.c file after the RAM verification, 
and this is not the best place to do
that, I know. Where would be the best place to patch that in? In a  way 
we are only setting one bit nothing
more.

Thank you!

Arnaud

Kevin O'Connor wrote:
> On Thu, Jul 30, 2009 at 09:56:20AM -0600, Myles Watson wrote:
> > On Wed, Jul 29, 2009 at 2:31 AM, Arnaud Maye  wrote:
> > > We are talking about the GFX cards legacy ranges, right? I think
> > > Myles looked at the PCI allocation already it seems everything is
> > > fine there.
> >
> > Actually I said that it wouldn't be related to the allocator because the
> > legacy VGA ranges are not aren't allocated there.  This is the place to
> > start to look for that:
>
> [...]
> > Make sure that that's the path to your graphics card.
> > Make sure that the correct bits get set in each device so that the I/O to
> >
> > the graphics card gets there.
> > The PCI_BRIDGE_CTL_VGA bit is in the device structure, so it doesn't
> >
> > affect hardware
> > Many bridges need some bit set to decode those ranges
>
> In addition to making sure the legacy IO ranges are correct, you also
> need to verify the legacy vga memory range (0xa0000 - 0xc0000) is
> properly configured in the bridges.  Also, the chipset needs to have
> this range be a pci hole - it must not have memory mapped there.
>
> -Kevin

*
*

vga not working

[Kevin O'Connor]

On Mon, Aug 17, 2009 at 01:21:17PM +0200, Arnaud Maye wrote:
> I've got the VGA to operating correctly in seabios. Actually it was
> as simple as enabling the VGA forwarding on the pci root complex, in
> the northbridge. Actually during the coreboot boot, the VGA output
> does not make much sense but as soon the OS boots, I can see the
> complete boot.

Great!
> This bit can be set for one PCIe "port" or the other, actually two
> possible settings but both cannot be enabled in the same time. So
> the bit to set depends where the GFX card is attached in fact.
> Should we proceed with this "detection" to set the correct bit or
> can we assume the user connects his card to PCIe SLOT0, in this case
> we hard code the correct bit setting for PCIe SLOT0?
>
> So far I am doing this in the auto.c file after the RAM
> verification, and this is not the best place to do that, I
> know. Where would be the best place to patch that in? In a way we
> are only setting one bit nothing more.

As far as I know, this is supposed to be done by the option
CONFIG_CONSOLE_VGA.  (For example, see set_vga_bridge_bits() in
src/devices/device.c.)  If that option isn't setting all the bits,
then it sounds like it needs to be extended.

-Kevin

vga not working

[Arnaud Maye]

Hello Kevin,

Kevin O'Connor wrote:
> On Mon, Aug 17, 2009 at 01:21:17PM +0200, Arnaud Maye wrote:
> > I've got the VGA to operating correctly in seabios. Actually it was
> > as simple as enabling the VGA forwarding on the pci root complex, in
> > the northbridge. Actually during the coreboot boot, the VGA output
> > does not make much sense but as soon the OS boots, I can see the
> > complete boot.
>
> Great!
> > This bit can be set for one PCIe "port" or the other, actually two
> > possible settings but both cannot be enabled in the same time. So
> > the bit to set depends where the GFX card is attached in fact.
> > Should we proceed with this "detection" to set the correct bit or
> > can we assume the user connects his card to PCIe SLOT0, in this case
> > we hard code the correct bit setting for PCIe SLOT0?
> >
> > So far I am doing this in the auto.c file after the RAM
> > verification, and this is not the best place to do that, I
> > know. Where would be the best place to patch that in? In a way we
> > are only setting one bit nothing more.
>
> As far as I know, this is supposed to be done by the option
> CONFIG_CONSOLE_VGA.  (For example, see set_vga_bridge_bits() in
> src/devices/device.c.)  If that option isn't setting all the bits,
> then it sounds like it needs to be extended.

Actually this function does not set any bits to the hardware I believe. 
Just setting up some bits in the
device structure. The bit enable thing for the root complex is going to 
be 80579 specific not sure it should
be part of this file. Actually enabling these bits means write to the 
PCI configuration space.

I guess I could add a vga_enable.c part of northbridge/i3100 and call 
this function from auto.c or
something like that, not sure if that would be fine or not.

Thank you

Arnaud
> -Kevin

*
*

vga not working

[Myles Watson]

> > > This bit can be set for one PCIe "port" or the other, actually two
> > > possible settings but both cannot be enabled in the same time. So
> > > the bit to set depends where the GFX card is attached in fact.
> > > Should we proceed with this "detection" to set the correct bit or
> > > can we assume the user connects his card to PCIe SLOT0, in this case
> > > we hard code the correct bit setting for PCIe SLOT0?
> > >
> > > So far I am doing this in the auto.c file after the RAM
> > > verification, and this is not the best place to do that, I
> > > know. Where would be the best place to patch that in? In a way we
> > > are only setting one bit nothing more.
> >
> > As far as I know, this is supposed to be done by the option
> > CONFIG_CONSOLE_VGA.  (For example, see set_vga_bridge_bits() in
> > src/devices/device.c.)  If that option isn't setting all the bits,
> > then it sounds like it needs to be extended.
>
> Actually this function does not set any bits to the hardware I believe.
> Just setting up some bits in the
> device structure. The bit enable thing for the root complex is going to
> be 80579 specific not sure it should
> be part of this file. Actually enabling these bits means write to the
> PCI configuration space.
>
> I guess I could add a vga_enable.c part of northbridge/i3100 and call
> this function from auto.c or
> something like that, not sure if that would be fine or not.

The correct way to do this is to add the functionality to the chipset init
function.  It should check the bit that was set in the device structure and
write the correct thing to the PCI configuration space.

Thanks,
Myles

vga not working

[ron minnich]

On Mon, Aug 17, 2009 at 8:28 AM, Myles Watson wrote:
> The correct way to do this is to add the functionality to the chipset init
> function.  It should check the bit that was set in the device structure and
> write the correct thing to the PCI configuration space.

How about we go through this step by step, and then Arnaud gets stuck
with writing up what we figure out.

So, Arnaud, tell me more. I'm utterly ignorant of the chipset here.

As I learn more, we can fill this out and, hopefully, have something
others can use later to know what to do.

(calling from auto.c is bad form :-)

What chipset needs to have a config register setting done?
(assuming you don't know what to do from IRC already :-)

ron

vga not working

[Myles Watson]

On Mon, Aug 17, 2009 at 9:51 AM, ron minnich  wrote:
> On Mon, Aug 17, 2009 at 8:28 AM, Myles Watson wrote:
> > The correct way to do this is to add the functionality to the chipset
>
> init
> > function.  It should check the bit that was set in the device structure
>
> and
> > write the correct thing to the PCI configuration space.
>
> How about we go through this step by step, and then Arnaud gets stuck
> with writing up what we figure out.

Yes.  I'm frequently guilty of skipping steps.
> So, Arnaud, tell me more. I'm utterly ignorant of the chipset here.
>
> As I learn more, we can fill this out and, hopefully, have something
> others can use later to know what to do.
>
> (calling from auto.c is bad form :-)
>
> What chipset needs to have a config register setting done?
> (assuming you don't know what to do from IRC already :-)

Setting up VGA for PCI: 07:00.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 03:04.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 02:00.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:03.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...

For me the steps would be:
1. Make sure that the device that needs the config writes is in the above
list.

2. Add code like this:
     if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
          /* Add your code from auto.c here */
     }
to the .init function of the bridge.

For example, assuming that the i3100 PCIe port needs the configuration, I
would add the code in:

src/northbridge/intel/i3100/pciexp_porta.c

In the existing pcie_init function.

Thanks,
Myles

vga not working

[ron minnich]

On Mon, Aug 17, 2009 at 9:12 AM, Myles Watson wrote:
> For me the steps would be:
> Make sure that the device that needs the config writes is in the above
>
> list.

I am after painful detail :-)

So, what is the name of this device? src/northbridge/...
> Add code like this:
>
> if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
>           /* Add your code from auto.c here */
>      }
> to the .init function of the bridge.

Yes. And how did bridge_ctrl get set again?
> For example, assuming that the i3100 PCIe port needs the configuration, I
> would add the code in:
>
> src/northbridge/intel/i3100/pciexp_porta.c
>
> In the existing pcie_init function.

precisely, but let's drill down just a bit more, but only once we get
Arnaud into the discussion :-)

ron

vga not working

[Arnaud Maye]

Okay, so actually we are talking about the PCIe Port (PEA) peripheral in 
the ep80579. So actually
a source file for it is already in the repo as Myles pointed out earlier:

northbridge\intel\i3100\pciexp_porta.c

The PCIe portA can be either x8 (PEA) or in double x8 (PEA0 and PEA1). 
In the
truxton case PEA0 connects to PCIe SLOT0. PEA1 connects to a PCIe switch.
This switch (PEX8508) provides x1 to PCIe Slot0 to Slot1.

The BCTRL ( Bridge Control Register ) has the VGAEN bit. PEA0 or PEA1
can have VGAEN enabled but not both in fact.

So actually if a VGA peripheral is found on PEA0 (00.02.00) we set 
PEA0:BCTRL.VGAEN.
If a VGA peripheral is found on PEA1 (00.03.00) we set PEA1:BCTRL.VGAEN.

Ideally we want this to operate with the card connected where the card 
is actually connected to.

Thanks,

Arnaud

ron minnich wrote:
> On Mon, Aug 17, 2009 at 9:12 AM, Myles Watson wrote:
> > For me the steps would be:
> > Make sure that the device that needs the config writes is in the above
> >
> > list.
>
> I am after painful detail :-)
>
> So, what is the name of this device? src/northbridge/...
> > Add code like this:
> >   if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
> >        /* Add your code from auto.c here */
> >   }
> >
> > to the .init function of the bridge.
>
> Yes. And how did bridge_ctrl get set again?
> > For example, assuming that the i3100 PCIe port needs the configuration, I
> > would add the code in:
> >
> > src/northbridge/intel/i3100/pciexp_porta.c
> >
> > In the existing pcie_init function.
>
> precisely, but let's drill down just a bit more, but only once we get
> Arnaud into the discussion :-)
>
> ron

*
*

vga not working

[ron minnich]

On Mon, Aug 17, 2009 at 10:49 AM, Arnaud Maye wrote:
> Ideally we want this to operate with the card connected where the card is
> actually connected to.

And that can not be determined from hardware, right? has to be set in
a Config.lb.

ron

vga not working

[Arnaud Maye]

ron minnich wrote:
> On Mon, Aug 17, 2009 at 10:49 AM, Arnaud Maye wrote:
> > Ideally we want this to operate with the card connected where the card is
> > actually connected to.
>
> And that can not be determined from hardware, right? has to be set in
> a Config.lb.
>
> ron

Actually it should work because in devices\device.c is the 
set_vga_bridge_bits() function. This function
scans all the devices for PCI_BASE_CLASS_DISPLAY and 
PCI_CLASS_DISPLAY_OTHER. So
I guess 00.02.00 or 00.03.00 should be assigned with the 
PCI_BRIDGE_CTL_VGA as it will be the
first found.

Now in the PCIe init function, the code pointed by Myles would be 
correct. Actually the device with
PCI_BRIDGE_CTL_VGA set gets BCTRL.VGAEN flag set.

I think it should be ok, right?

Arnaud

*
*

vga not working

[Myles Watson]

On Mon, Aug 17, 2009 at 10:57 AM, ron minnich  wrote:
> On Mon, Aug 17, 2009 at 9:12 AM, Myles Watson wrote:
> > For me the steps would be:
> > Make sure that the device that needs the config writes is in the above
> >
> > list.
>
> I am after painful detail :-)

I'm much better at answering questions than brain-dumping, but I'm trying.
> > Add code like this:
> >   if (dev->link[link].bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
> >        /* Add your code from auto.c here */
> >   }
> >
> > to the .init function of the bridge.
>
> Yes. And how did bridge_ctrl get set again?

In set_vga_bridge_bits(), the code finds the VGA device and then walks back
to the root, setting the bridge_ctrl bits along the way.  When the
enable_resources() or init() function gets called, device-specific code can
then do what it needs to with that information to make it work.

Myles

vga not working

[Myles Watson]

> Actually it should work because in devices\device.c is the
> set_vga_bridge_bits() function. This function
> scans all the devices for PCI_BASE_CLASS_DISPLAY and
> PCI_CLASS_DISPLAY_OTHER. So
> I guess 00.02.00 or 00.03.00 should be assigned with the PCI_BRIDGE_CTL_VGA
> as it will be the
> first found.

Setting up VGA for PCI: 07:00.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 03:04.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 02:00.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:03.0
Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...

00:03.0 is on the list, so it will be the one assigned.
> Now in the PCIe init function, the code pointed by Myles would be correct.
> Actually the device with
> PCI_BRIDGE_CTL_VGA set gets BCTRL.VGAEN flag set.
>
> I think it should be ok, right?

I just looked in pci_device.c, and the code there sets the bits in
pci_enable_resources() instead of init().  I'm not sure why that is, but you
might want to follow that lead for consistency.

Thanks,
Myles

vga not working

[ron minnich]

I have this bad feeling that we never converged on answering the question.

Arnaud, did you see that you would want to extend the various
enable_resources functions to correctly set up the VGA control bit on
your various bridges? Or should we continue this discussion.

ron

vga not working

[ron minnich]

On Tue, Aug 18, 2009 at 11:04 PM, ron minnich wrote:
> I have this bad feeling that we never converged on answering the question.
>
> Arnaud, did you see that you would want to extend the various

i3100-specific enable_resources

Sorry, left that "i3100" part out.
> functions to correctly set up the VGA control bit on
> your various bridges? Or should we continue this discussion.

ron

vga not working

[Arnaud Maye]

Hello Ron,

Well I've made the patch, added a 13100 specific 
pci_bus_enable_resources in pciexp_porta.c and modified
the pcie_ops structure accordingly. Am not sure this should be enough. 
Actually these specific functions are never called.
pcie_init() part of the initial port is not called as well. I've placed 
a few printk_debug and I do not see them on
the log. And yeah I did buildtarget, make clean, make. Any idea what 
could go wrong here?

Actually the code in pci_device.c is setting the correct register in the 
bridges, just the value is incorrect. I am
currently checking legacy vs coreboot lspci dumps and investigate 
differences by differences. It is setting the
ISA IO/MEM forwarding bit and we do not want this to happen. If we do 
that we have to set the other
bridges as well. This is related to the 10bit address decoding.

Another thing I did see is that in fact, I do not have VGA working at 
all. The screen gets correct display at the
moment Linux loads the GFX driver. So right now checking the system 
memory mapping legacy vs coreboot
to ensure the required holes are present.

Thank you,

Arnaud

ron minnich wrote:
> On Tue, Aug 18, 2009 at 11:04 PM, ron minnich wrote:
> > I have this bad feeling that we never converged on answering the question.
> >
> > Arnaud, did you see that you would want to extend the various
>
> i3100-specific enable_resources
>
> Sorry, left that "i3100" part out.
> > functions to correctly set up the VGA control bit on
> > your various bridges? Or should we continue this discussion.
>
> ron

*
*

vga not working

[ron minnich]

On Wed, Aug 19, 2009 at 12:27 AM, Arnaud Maye wrote:

OK, there's some things to talk about in here.
> Well I've made the patch, added a 13100 specific pci_bus_enable_resources in
> pciexp_porta.c and modified
> the pcie_ops structure accordingly.

Can we see the patch?
> make clean, make. Any idea what could
> go wrong here?

hard to say without seeing code.
> Actually the code in pci_device.c is setting the correct register in the
> bridges, just the value is incorrect.

What's that mean? What is right, and what is "incorrect", and what
bridges, and what register?
> It is setting the
> ISA IO/MEM forwarding bit and we do not want this to happen.

What? where? why? How? I'm lost again.

I confess to not knowing much about this part ... so am not sure
what's happened here.

ron

vga not working

[Arnaud Maye]

ron minnich wrote:
> On Wed, Aug 19, 2009 at 12:27 AM, Arnaud Maye wrote:
>
> OK, there's some things to talk about in here.
> > Well I've made the patch, added a 13100 specific pci_bus_enable_resources in
> > pciexp_porta.c and modified
> > the pcie_ops structure accordingly.
>
> Can we see the patch?

Well this is not making a lot of sense so far, The VGA is anyway not 
working... I will provide a patch as soon I get everything to operate.
> > make clean, make. Any idea what could
> > go wrong here?
>
> hard to say without seeing code.
> > Actually the code in pci_device.c is setting the correct register in the
> > bridges, just the value is incorrect.
>
> What's that mean? What is right, and what is "incorrect", and what
> bridges, and what register?
> > It is setting the
> > ISA IO/MEM forwarding bit and we do not want this to happen.
>
> What? where? why? How? I'm lost again.

BCTRL has VGAEN and ISAEN, coreboot assign both of them to 1. The value 
0xb is wrote to register 0x3E.
As you seem to like details, 0xb is 0b1100 which means bit 3 and 2 are 
set to 1, which means VGAEEN and
ISAEN are both getting  set to 1.

The ep80579 has two x4 lanes peripherals (00:02.0 and 00:03.0) both of 
them having a register 0x3E. If you set
ISAEN on 00:02.00 you have to set ISAEN on 00:03.00 as well. This is a 
requirement provided by Intel in fact.
It makes sense as the address decoding is different as soon ISAEN is 
set. All th bridges should be set correctly.

These two peripherals can be coupled together providing x8 lanes.

Note that ISAEN is not set by the legacy BIOS, and the VGA output is 
working flawlessly. So in fact I just want
to write 0x8 instead 0xb in register 0x3E. But this I can already do, 
just not at the correct place.
> I confess to not knowing much about this part ... so am not sure
> what's happened here.
>
> ron

The description of the VGAEN bit is :

VGA Enable : Controls the routing of processor initiated transactions 
targeting VGA compatible I/O and memory
address ranges. Actually access to these ranges forward to the PCIe port 
instead the NSI ( North-South Interface ).

The PCIe port I am using is directly connected to a slot, there are no 
other bridge or switch in the way. So in this
respect the correct bit is set in the bridge.

I have checked the base address of the various memory mapped register in 
the ep80579  and none of them are
pointing a location conflicting with VGA  memory ranges.

With the GFX card connected to SLOT0, the PCIe is operating in coupled 
mode and actually configured as x8.
This is because the current coreboot port does not set PEACAPA.SIMP to 1 
in both bridge. As soon both 00:02.0
and  00:03.0 get PEACAPA.SIMP is set to 1, the two port are configured 
in x4. We can see that in
PEALNKCAP.MLW. Checking legacy BIOS settings confirm PEACAPA.SIMP should 
be 1 in both PCIe
ports.

I guess the only thing left is that coreboot does not allocate a hole 
for the VGA, two holes are required I guess,
MEM and IO. how can I check if a hole is actually reserved or not?

Any clue Ron, Myles or Kevin?

Thank you!

Arnaud

vga not working

[Myles Watson]

> The ep80579 has two x4 lanes peripherals (00:02.0 and 00:03.0) both of

You mean the i3100 here, right?
> them having a register 0x3E. If you set
> ISAEN on 00:02.00 you have to set ISAEN on 00:03.00 as well. This is a
> requirement provided by Intel in fact.
> It makes sense as the address decoding is different as soon ISAEN is
> set. All th bridges should be set correctly.
>
> These two peripherals can be coupled together providing x8 lanes.
>
> Note that ISAEN is not set by the legacy BIOS, and the VGA output is
> working flawlessly. So in fact I just want
> to write 0x8 instead 0xb in register 0x3E. But this I can already do,
> just not at the correct place.

So where have you tried?  File and function?

It looks like if that's the bit you want to set you need to have your own
enable_resources function in pciexp_porta.c.  Right now you're using the
default.
> With the GFX card connected to SLOT0, the PCIe is operating in coupled
> mode and actually configured as x8.
> This is because the current coreboot port does not set PEACAPA.SIMP to 1
> in both bridge. As soon both 00:02.0
> and  00:03.0 get PEACAPA.SIMP is set to 1, the two port are configured
> in x4. We can see that in
> PEALNKCAP.MLW. Checking legacy BIOS settings confirm PEACAPA.SIMP should
> be 1 in both PCIe
> ports.

So this should probably be done even earlier.  That's not something that is
fixed, right?  Or do you want it coupled (or not) depending on what card
gets plugged in?
> I guess the only thing left is that coreboot does not allocate a hole
> for the VGA, two holes are required I guess,
> MEM and IO. how can I check if a hole is actually reserved or not?

Look through the last resource tree in the boot log.  It should be there.

You can always add them in read_resources.

Thanks,
Myles

vga not working

[ron minnich]

On Thu, Aug 20, 2009 at 4:45 AM, Arnaud Maye wrote:
> Well this is not making a lot of sense so far, The VGA is anyway not
> working... I will provide a patch as soon I get everything to operate.

If we see the patch sooner, we can try to head off any wrong
directions you might find yourself in.

I would like to help you make best use of your efforts.

My time is pretty stretched, it is way easier for me to work from code
that from descriptions.

ron