Re: [coreboot] Intel G41 - Asrock G41M-GS: no coreboot screen output from Intel GPU on VGA
I wrote the way i had build coreboot. Tianocore is not the default payload. The default payload recently is (i checked now) SeaBIOS 1.11.2 . I have not touched anything at the payload. I just leave everything default and would like to be able to see the output of coreboot so that i can choose for example to boot from a usb-pendrive.
What should i do now to get the <everything at default coreboot> to show output on the screen?
On 2018-08-14 11:53, Jose Trujillo via coreboot wrote:
Hello h42
If you are using Tianocore you must use VESA framebuffer If Seabios use text mode
Jose
‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On August 14, 2018 2:41 PM, h42@memeware.net wrote:
I dont get anything on the screen from coreboot. The later os is displaying fine.
How i build the image: ran on a fresh git cloned (from today) 'make menuconfig', chose just the mainboard manufacturer and the model, press esc, confirmed saving, ran 'make'. I installed this image and dont get any coreboot output on the screen. When i wait long enough, i get the output from the Linux OS on the screen.
From the coreboot logfile:
coreboot-4.8-1195-gb75a08b199 [...] FMAP: Found "FLASH" version 1.1 at 0. FMAP: base = fff00000 size = 100000 #areas = 4 FMAP: area RW_MRC_CACHE found @ 10000 (65536 bytes) MRC: No data in cbmem for 'RW_MRC_CACHE'. BS: BS_DEV_ENUMERATE times (us): entry 0 run 150329 exit 16016 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... TOUUD 0x80000000 TOLUD 0x80000000 TOM 0x80000000 IGD decoded, subtracting 64M UMA and 4M GTT TSEG decoded, subtracting 8M Available memory below 4GB: 1972M Adding UMA memory area base=0x7b400000 size=0x04c00000 Adding PCIe config bar base=0xe0000000 size=0x10000000 Done reading resources. [...] [21.707417] CONFIG => [21.709411] (Primary => [21.711924] (Port => Analog , [21.715130] Framebuffer => [21.718076] (Width => 640, [21.721542] Height => 400, [21.725008] Start_X => 0, [21.728301] Start_Y => 0, [21.731594] Stride => 1, [21.734886] V_Stride => 1, [21.738179] Tiling => Linear , [21.741993] Rotation => No_Rotation, [21.746153] Offset => 0xffffffff, [21.749966] BPC => 8), [21.753085] Mode => [21.755424] (Dotclock => 148500000, [21.760192] H_Visible => 1920, [21.764524] H_Sync_Begin => 2008, [21.768857] H_Sync_End => 2052, [21.773190] H_Total => 2200, [21.777523] V_Visible => 1080, [21.781857] V_Sync_Begin => 1084, [21.786189] V_Sync_End => 1089, [21.790522] V_Total => 1125, [21.794855] H_Sync_Active_High => True, [21.799189] V_Sync_Active_High => True, [21.803521] BPC => 5)), [21.807767] Secondary => [21.810281] (Port => Disabled, [21.813487] Framebuffer => [21.816433] (Width => 1, [21.819727] Height => 1, [21.823020] Start_X => 0, [21.826313] Start_Y => 0, [21.829605] Stride => 1, [21.832899] V_Stride => 1, [21.836193] Tiling => Linear , [21.840006] Rotation => No_Rotation, [21.844166] Offset => 0x00000000, [21.847979] BPC => 8), [21.851098] Mode => [21.853438] (Dotclock => 24000000, [21.858118] H_Visible => 1, [21.862191] H_Sync_Begin => 1, [21.866263] H_Sync_End => 1, [21.870336] H_Total => 1, [21.874409] V_Visible => 1, [21.878482] V_Sync_Begin => 1, [21.882555] V_Sync_End => 1, [21.886629] V_Total => 1, [21.890702] H_Sync_Active_High => False, [21.895121] V_Sync_Active_High => False, [21.899541] BPC => 5)), [21.903787] Tertiary => [21.906300] (Port => Disabled, [21.909507] Framebuffer => [21.912453] (Width => 1, [21.915746] Height => 1, [21.919039] Start_X => 0, [21.922331] Start_Y => 0, [21.925624] Stride => 1, [21.928918] V_Stride => 1, [21.932211] Tiling => Linear , [21.936023] Rotation => No_Rotation, [21.940183] Offset => 0x00000000, [21.943996] BPC => 8), [21.947116] Mode => [21.949455] (Dotclock => 24000000, [21.954135] H_Visible => 1, [21.958207] H_Sync_Begin => 1, [21.962280] H_Sync_End => 1, [21.966353] H_Total => 1, [21.970427] V_Visible => 1, [21.974499] V_Sync_Begin => 1, [21.978572] V_Sync_End => 1, [21.982646] V_Total => 1, [21.986719] H_Sync_Active_High => False, [21.991138] V_Sync_Active_High => False, [21.995557] BPC => 5)));
PCI: 00:02.0 init finished in 307222 usecs PCI: 00:02.1 init ... PCI: 00:02.1 init finished in 2009 usecs PCI: 00:1b.0 init ... [...]
So it seems to have detected that my screen is 1920*1080. GPU + screen detection seems to be working. But i dont get any coreboot output on the screen. The output had worked fine on this screen with the OEM BIOS.
coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
Just press ESC key during booting for Seabios and if everything in the video interface is properly configured by default you should see the boot menu.
‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On August 14, 2018 4:35 PM, h42@memeware.net wrote:
I wrote the way i had build coreboot. Tianocore is not the default payload. The default payload recently is (i checked now) SeaBIOS 1.11.2 . I have not touched anything at the payload. I just leave everything default and would like to be able to see the output of coreboot so that i can choose for example to boot from a usb-pendrive.
What should i do now to get the <everything at default coreboot> to show output on the screen?
On 2018-08-14 11:53, Jose Trujillo via coreboot wrote:
Hello h42 If you are using Tianocore you must use VESA framebuffer If Seabios use text mode Jose ‐‐‐‐‐‐‐ Original Message ‐‐‐‐‐‐‐ On August 14, 2018 2:41 PM, h42@memeware.net wrote:
I dont get anything on the screen from coreboot. The later os is displaying fine. How i build the image: ran on a fresh git cloned (from today) 'make menuconfig', chose just the mainboard manufacturer and the model, press esc, confirmed saving, ran 'make'. I installed this image and dont get any coreboot output on the screen. When i wait long enough, i get the output from the Linux OS on the screen. From the coreboot logfile: coreboot-4.8-1195-gb75a08b199 [...] FMAP: Found "FLASH" version 1.1 at 0. FMAP: base = fff00000 size = 100000 #areas = 4 FMAP: area RW_MRC_CACHE found @ 10000 (65536 bytes) MRC: No data in cbmem for 'RW_MRC_CACHE'. BS: BS_DEV_ENUMERATE times (us): entry 0 run 150329 exit 16016 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... TOUUD 0x80000000 TOLUD 0x80000000 TOM 0x80000000 IGD decoded, subtracting 64M UMA and 4M GTT TSEG decoded, subtracting 8M Available memory below 4GB: 1972M Adding UMA memory area base=0x7b400000 size=0x04c00000 Adding PCIe config bar base=0xe0000000 size=0x10000000 Done reading resources. [...] [21.707417] CONFIG => [21.709411] (Primary => [21.711924] (Port => Analog , [21.715130] Framebuffer => [21.718076] (Width => 640, [21.721542] Height => 400, [21.725008] Start_X => 0, [21.728301] Start_Y => 0, [21.731594] Stride => 1, [21.734886] V_Stride => 1, [21.738179] Tiling => Linear , [21.741993] Rotation => No_Rotation, [21.746153] Offset => 0xffffffff, [21.749966] BPC => 8), [21.753085] Mode => [21.755424] (Dotclock => 148500000, [21.760192] H_Visible => 1920, [21.764524] H_Sync_Begin => 2008, [21.768857] H_Sync_End => 2052, [21.773190] H_Total => 2200, [21.777523] V_Visible => 1080, [21.781857] V_Sync_Begin => 1084, [21.786189] V_Sync_End => 1089, [21.790522] V_Total => 1125, [21.794855] H_Sync_Active_High => True, [21.799189] V_Sync_Active_High => True, [21.803521] BPC => 5)), [21.807767] Secondary => [21.810281] (Port => Disabled, [21.813487] Framebuffer => [21.816433] (Width => 1, [21.819727] Height => 1, [21.823020] Start_X => 0, [21.826313] Start_Y => 0, [21.829605] Stride => 1, [21.832899] V_Stride => 1, [21.836193] Tiling => Linear , [21.840006] Rotation => No_Rotation, [21.844166] Offset => 0x00000000, [21.847979] BPC => 8), [21.851098] Mode => [21.853438] (Dotclock => 24000000, [21.858118] H_Visible => 1, [21.862191] H_Sync_Begin => 1, [21.866263] H_Sync_End => 1, [21.870336] H_Total => 1, [21.874409] V_Visible => 1, [21.878482] V_Sync_Begin => 1, [21.882555] V_Sync_End => 1, [21.886629] V_Total => 1, [21.890702] H_Sync_Active_High => False, [21.895121] V_Sync_Active_High => False, [21.899541] BPC => 5)), [21.903787] Tertiary => [21.906300] (Port => Disabled, [21.909507] Framebuffer => [21.912453] (Width => 1, [21.915746] Height => 1, [21.919039] Start_X => 0, [21.922331] Start_Y => 0, [21.925624] Stride => 1, [21.928918] V_Stride => 1, [21.932211] Tiling => Linear , [21.936023] Rotation => No_Rotation, [21.940183] Offset => 0x00000000, [21.943996] BPC => 8), [21.947116] Mode => [21.949455] (Dotclock => 24000000, [21.954135] H_Visible => 1, [21.958207] H_Sync_Begin => 1, [21.962280] H_Sync_End => 1, [21.966353] H_Total => 1, [21.970427] V_Visible => 1, [21.974499] V_Sync_Begin => 1, [21.978572] V_Sync_End => 1, [21.982646] V_Total => 1, [21.986719] H_Sync_Active_High => False, [21.991138] V_Sync_Active_High => False, [21.995557] BPC => 5))); PCI: 00:02.0 init finished in 307222 usecs PCI: 00:02.1 init ... PCI: 00:02.1 init finished in 2009 usecs PCI: 00:1b.0 init ... [...] So it seems to have detected that my screen is 1920*1080. GPU + screen detection seems to be working. But i dont get any coreboot output on the screen. The output had worked fine on this screen with the OEM BIOS.
coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
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coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot
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h42＠memeware.net -
Jose Trujillo