IDE interface support code for AMDLX800-CS5536

[Darmawan Salihun]

Hi guys,

I'm looking for the support code for the IDE controller in CS5536 southbridge.
I checked-out Coreboot source code but only saw Flash interface
support in there.
I saw the IDE controller is switched to Flash interface support with
the "DEADBEEF"
magic number.

The board I'm working with right now use the primary IDE channel for both
HDD connectors and a CF connectors. I need to know how to initialize
the chipset
correctly for this setup. The CF connector is the primary master and
the HDD connector is primary slave.

I've checked with lspci and " cat /proc/ioports" and I found that the
legacy I/O ports
for IDE controller is working just fine. Also, the I/O ports for
IDE bus mastering (SFF-8038i) registers are allocated correctly.

Thanks,

Darmawan

[Darmawan Salihun]

> On 1/2/11, Darmawan Salihun  wrote:
> Hi guys,
>
> I'm looking for the support code for the IDE controller in CS5536
> southbridge.
> I checked-out Coreboot source code but only saw Flash interface
> support in there.
> I saw the IDE controller is switched to Flash interface support with
> the "DEADBEEF"
> magic number.
>
> The board I'm working with right now use the primary IDE channel for both
> HDD connectors and a CF connectors. I need to know how to initialize
> the chipset
> correctly for this setup. The CF connector is the primary master and
> the HDD connector is primary slave.
>
> I've checked with lspci and " cat /proc/ioports" and I found that the
> legacy I/O ports
> for IDE controller is working just fine. Also, the I/O ports for
> IDE bus mastering (SFF-8038i) registers are allocated correctly.

I mean with the current code that I tested the I/O ports allocation is
just fine.
> Thanks,
> Darmawan
>
> -= Human knowledge belongs to the world =-

[Marc Jones]

On Sat, Jan 1, 2011 at 1:38 PM, Darmawan Salihun
 wrote:
> > On 1/2/11, Darmawan Salihun  wrote:
> > Hi guys,
> >
> > I'm looking for the support code for the IDE controller in CS5536
> > southbridge.
> > I checked-out Coreboot source code but only saw Flash interface
> > support in there.
> > I saw the IDE controller is switched to Flash interface support with
> > the "DEADBEEF"
> > magic number.
> >
> > The board I'm working with right now use the primary IDE channel for both
> > HDD connectors and a CF connectors. I need to know how to initialize
> > the chipset
> > correctly for this setup. The CF connector is the primary master and
> > the HDD connector is primary slave.
> >
> > I've checked with lspci and " cat /proc/ioports" and I found that the
> > legacy I/O ports
> > for IDE controller is working just fine. Also, the I/O ports for
> > IDE bus mastering (SFF-8038i) registers are allocated correctly.
>
> I mean with the current code that I tested the I/O ports allocation is
> just fine.
> > Thanks,
> >
> > Darmawan

Hi Darmawan,

The IDE should get setup by default if the flash switch path is not selected.

I assume you have already read the registers in the databook..
http://support.amd.com/us/Embedded_TechDocs/33238G_cs5536_db.pdf

There may be more information on the embedded developer site. The
embedded guys are coreboot friendly, so they should be able to point
at the appropriate doc.

http://wwwd.amd.com/amd/devsite.nsf/home/welcome.htm?opendocument&login

Marc

[Darmawan Salihun]

Hi Mark,

On 1/5/11, Marc Jones  wrote:
> On Sat, Jan 1, 2011 at 1:38 PM, Darmawan Salihun
>  wrote:
> > > On 1/2/11, Darmawan Salihun  wrote:
> > > Hi guys,
> > >
> > > I'm looking for the support code for the IDE controller in CS5536
> > > southbridge.
> > > I checked-out Coreboot source code but only saw Flash interface
> > > support in there.
> > > I saw the IDE controller is switched to Flash interface support with
> > > the "DEADBEEF"
> > > magic number.
> > >
> > > The board I'm working with right now use the primary IDE channel for both
> > > HDD connectors and a CF connectors. I need to know how to initialize
> > > the chipset
> > > correctly for this setup. The CF connector is the primary master and
> > > the HDD connector is primary slave.
> > >
> > > I've checked with lspci and " cat /proc/ioports" and I found that the
> > > legacy I/O ports
> > > for IDE controller is working just fine. Also, the I/O ports for
> > > IDE bus mastering (SFF-8038i) registers are allocated correctly.
> >
> > I mean with the current code that I tested the I/O ports allocation is
> > just fine.
> > > Thanks,
> > >
> > > Darmawan
>
> Hi Darmawan,
>
> The IDE should get setup by default if the flash switch path is not
> selected.
>
> I assume you have already read the registers in the databook..
> http://support.amd.com/us/Embedded_TechDocs/33238G_cs5536_db.pdf

Yes, I've been reading it several times over ;-).

I have pin point the problem to be in setting the appropriate "ATA mode"
for the attached drives.
The motherboard I'm working with has a CF interface in the primary master.
While the primary slave is a 44-pin IDE connector (currently connected
to an 80GB
HDD).

I booted FreeBSD 8.0 installation disk in full debug (via USB DVD),
but it failed when it tried to set the drive controller mode via
"SET FEATURE" (ATA command). This renders the CF _and_ the HDD unusable.

I also booted to backtrack 3 i386 Linux, but it also failed even
earlier (via USB DVD),
when it tried to check for drive presence via "IDENTIFY" (ATA command).

I'm confused as to: What are the "acceptable" values for the IDE_DTC,
IDE_CAST and
IDE_ETC registers? I mean values which would enable the OS to use mass storage
device(s) on the IDE primary channel.
> There may be more information on the embedded developer site. The
> embedded guys are coreboot friendly, so they should be able to point
> at the appropriate doc.
>
> http://wwwd.amd.com/amd/devsite.nsf/home/welcome.htm?opendocument&login

I see. On to the site.

Thanks,

Darmawan