I am booting an ASUS F2A85-M motherboard with a AMD A6-5400k processor (Trinity core) using coreboot. The processor is initialized via the AGESA bootstrap protocol.

I would like to use the AGESA software in order to measure the retention time of DRAM cells (i.e. the time a DRAM cell holds its value with refresh shut off). To do this, I must (1) run my code in cache-as-RAM mode because DRAM becomes unreliable without refresh and (2) have a way to switch DRAM refresh on/off from software. (1) is accomplished by running my code in the cache-as-RAM phase of coreboot (i.e. the ROM stage). I am, however, unclear on how to accomplish (2) and I was hoping to receive some pointers/guidance on how to do this.

The AGESA protocol seems to handle memory initialization in the AmdInitPost phase, specifically in AmdMemAuto In reading this code I discovered a call with which one could disable/enable the auto-refresh feature of the DRAM. Specifically,

where NBPtr is a pointer to a data structure representing the northbridge configuration and BFDisAutoRefresh is a bit field which can be set to 1 in order to disable auto-refresh of the DRAM (see AMD BKDG, page 344 on DisAutoRefresh).

With this interface, I thought I could (1) write a value to memory (using movnti instruction to bypass the cache), (2) disable auto-refresh using MemNSetBitFieldNb, (3) wait some number of seconds, (4) enable auto-refresh using MemNSetBitFieldNb, and (5) check whether the value has persisted over the given period of time. Unfortunately, I discovered that even after waiting 3 minutes, the value in DRAM persisted (contrary to what seems to be expected by the literature). Note that I perform this procedure inside the AmdMemAuto procedure of the AGESA code once all memory initialization tasks have completed and before teardown occurs.

Worried that the processor may be caching the value, I decided to flush data at the address before disabling auto-refresh with the following interface provided by the AGESA codebase:

where 1 simply represents the number of cache lines to flush from the address Addr. This, however, proved not to solve my issue.

I am curious if anyone has dug into the AGESA vendor code and has any experience advice for how to approach the functionality I am trying to achieve.