Index: src/southbridge/intel/esb6300/Makefile.inc
===================================================================
--- src/southbridge/intel/esb6300/Makefile.inc	(revision 5965)
+++ src/southbridge/intel/esb6300/Makefile.inc	(working copy)
@@ -1,4 +1,5 @@
 driver-y += esb6300.c
+driver-y += esb6300_reset.c
 driver-y += esb6300_uhci.c
 driver-y += esb6300_lpc.c
 driver-y += esb6300_ide.c
Index: src/southbridge/intel/esb6300/esb6300_reset.c
===================================================================
--- src/southbridge/intel/esb6300/esb6300_reset.c	(revision 0)
+++ src/southbridge/intel/esb6300/esb6300_reset.c	(revision 0)
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2004 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <reset.h>
+
+void hard_reset(void)
+{
+	/* Try rebooting through port 0xcf9 */
+	outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9);
+}