> The simplest and most obvious explanation turned out to be true, theĀ register is encoded as multiples of 16MiB.
You say (in other words) the following: Coreboot prepares the whole populated 32 bit (physical layout) DRAM2 space for some OS, don't you?
TOLUD = d0000000h, and the next 256MiB are reserved for MM PCI + MM PCIe (Yonah is Y2006, so PCIe came in Y2004), so somewhere above there will be PCI configuration space (minimum 64K x 256 = 16MiB, maybe more, since some ports are PCIe), Then HSEG, after boot FLASH.
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Well, Andrey, if Nico is right, you have reduced options... Dracut stays as one of very seldom options to try, don't you agree?
Zoran