Index: coreboot-v2/src/arch/i386/lib/console.c =================================================================== --- coreboot-v2.orig/src/arch/i386/lib/console.c +++ coreboot-v2/src/arch/i386/lib/console.c @@ -13,12 +13,6 @@ static void __console_tx_byte(unsigned c #include "console_printk.c" -#if CONFIG_USE_INIT == 0 -// do_printk -#include "../../../console/vtxprintf.c" -#include "printk_init.c" -#endif - #endif /* CONFIG_USE_PRINTK_IN_CAR */ #ifndef COREBOOT_EXTRA_VERSION Index: coreboot-v2/src/console/Config.lb =================================================================== --- coreboot-v2.orig/src/console/Config.lb +++ coreboot-v2/src/console/Config.lb @@ -28,8 +28,4 @@ object console.o object vtxprintf.o object vsprintf.o -if CONFIG_USE_INIT -# if CONFIG_USE_PRINTK_IN_CAR - initobject vtxprintf.o -# end -end +initobject vtxprintf.o Index: coreboot-v2/src/lib/Config.lb =================================================================== --- coreboot-v2.orig/src/lib/Config.lb +++ coreboot-v2/src/lib/Config.lb @@ -21,12 +21,10 @@ object version.o # Force version.o to recompile every time makedefine .PHONY : version.o -if CONFIG_USE_INIT - initobject uart8250.c - initobject memset.o - initobject memcpy.o - initobject memcmp.o -end +initobject uart8250.c +initobject memset.o +initobject memcpy.o +initobject memcmp.o if CONFIG_CBFS object cbfs.o Index: coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/amd/dbm690t/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c @@ -37,6 +37,7 @@ #define SMBUS_HUB 0x71 #include +#include #include #include #include @@ -54,10 +55,6 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/amd/pistachio/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c @@ -31,6 +31,7 @@ #define DIMM1 0x51 #include +#include #include #include #include @@ -48,10 +49,6 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah/apc_auto.c +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c @@ -21,12 +21,15 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" +#include "./arch/i386/lib/printk_init.c" #if CONFIG_USE_INIT == 0 #include "lib/memcpy.c" #endif #include "arch/i386/lib/console.c" +#include "lib/uart8250.c" +#include "console/vtxprintf.c" #if 0 static void post_code(uint8_t value) { Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c @@ -24,6 +24,7 @@ #endif #include +#include #include #include #include @@ -63,9 +64,6 @@ static void post_code(uint8_t value) { #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif #include "northbridge/amd/amdk8/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb =================================================================== --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb @@ -136,7 +136,7 @@ default ROM_SIZE=524288 #FALLBACK: 512K - 4K default FALLBACK_SIZE=0x7f000 #FAILOVER: 4k -default FAILOVER_SIZE=0x01000 +default FAILOVER_SIZE=0x02000 #more 1M for pgtbl #if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time. Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c @@ -45,6 +45,7 @@ #define FAM10_SET_FIDVID_CORE_RANGE 0 #include +#include #include #include #include @@ -81,10 +82,6 @@ int do_printk(int msg_level, const char #if (USE_FAILOVER_IMAGE == 0) - #if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" - #endif - #include "northbridge/amd/amdfam10/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" Index: coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/arima/hdama/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c @@ -21,10 +21,6 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/asus/a8n_e/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/asus/a8n_e/cache_as_ram_auto.c @@ -38,6 +38,7 @@ #endif #include +#include #include #include #include @@ -54,10 +55,6 @@ /* Used by ck894_early_setup(). */ #define CK804_NUM 1 -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include #include "pc80/serial.c" #include "arch/i386/lib/console.c" Index: coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c @@ -43,6 +43,7 @@ unsigned int get_sbdn(unsigned bus); /* #define DEBUG_SMBUS 1 */ #include +#include #include #include #include @@ -56,9 +57,6 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c @@ -47,6 +47,7 @@ unsigned int get_sbdn(unsigned bus); /* #define DEBUG_SMBUS 1 */ #include +#include #include #include #include @@ -61,9 +62,6 @@ unsigned int get_sbdn(unsigned bus); #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/broadcom/blast/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/broadcom/blast/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/broadcom/blast/cache_as_ram_auto.c @@ -11,6 +11,7 @@ #endif #include +#include #include #include #include @@ -40,10 +41,6 @@ static void post_code(uint8_t value) { #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c @@ -48,6 +48,7 @@ #define DBGP_DEFAULT 7 #include +#include #include #include #include @@ -85,10 +86,6 @@ #include "cpu/x86/bist.h" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - #include "northbridge/amd/amdk8/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" Index: coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c @@ -46,6 +46,7 @@ #define DBGP_DEFAULT 7 #include +#include #include #include #include @@ -82,10 +83,6 @@ #include "cpu/x86/bist.h" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - #include "northbridge/amd/amdk8/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" Index: coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c @@ -51,6 +51,7 @@ #define DBGP_DEFAULT 7 #include +#include #include #include #include @@ -87,10 +88,6 @@ #include "cpu/x86/bist.h" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - #include "northbridge/amd/amdk8/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" Index: coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/ibm/e325/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/ibm/e325/cache_as_ram_auto.c @@ -2,6 +2,7 @@ #define __ROMCC__ #include +#include #include #include #include @@ -21,10 +22,6 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/ibm/e326/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/ibm/e326/cache_as_ram_auto.c @@ -2,6 +2,7 @@ #define __ROMCC__ #include +#include #include #include #include @@ -21,10 +22,6 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c @@ -24,6 +24,7 @@ #endif #include +#include #include #include #include @@ -52,15 +53,6 @@ #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" - // TODO: This doesn't compile at the moment. Fix later. - // #if CONFIG_USE_PRINTK_IN_CAR == 1 - // #include "lib/uart8250.c" - // #include "console/vtxprintf.c" - // #include "arch/i386/lib/printk_init.c" - // #endif -#endif #include "northbridge/amd/amdk8/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" Index: coreboot-v2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c @@ -24,6 +24,7 @@ #endif #include +#include #include #include #include @@ -52,15 +53,6 @@ #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" - // TODO: This doesn't compile at the moment. Fix later. - // #if CONFIG_USE_PRINTK_IN_CAR == 1 - // #include "lib/uart8250.c" - // #include "console/vtxprintf.c" - // #include "arch/i386/lib/printk_init.c" - // #endif -#endif #include "northbridge/amd/amdk8/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" Index: coreboot-v2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/iwill/dk8x/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/iwill/dk8x/cache_as_ram_auto.c @@ -24,6 +24,7 @@ #endif #include +#include #include #include #include @@ -52,15 +53,6 @@ #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" - // TODO: This doesn't compile at the moment. Fix later. - // #if CONFIG_USE_PRINTK_IN_CAR == 1 - // #include "lib/uart8250.c" - // #include "console/vtxprintf.c" - // #include "arch/i386/lib/printk_init.c" - // #endif -#endif #include "northbridge/amd/amdk8/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" Index: coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/kontron/986lcd-m/auto.c +++ coreboot-v2/src/mainboard/kontron/986lcd-m/auto.c @@ -23,6 +23,7 @@ #define __ROMCC__ #include +#include #include #include #include @@ -45,10 +46,6 @@ #include "northbridge/intel/i945/udelay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) #include "northbridge/intel/i945/ich7.h" Index: coreboot-v2/src/mainboard/msi/ms7135/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms7135/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/msi/ms7135/cache_as_ram_auto.c @@ -38,6 +38,7 @@ #endif #include +#include #include #include #include @@ -56,10 +57,6 @@ #define CK804_USE_NIC 1 #define CK804_USE_ACI 1 -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include #include "pc80/serial.c" #include "arch/i386/lib/console.c" Index: coreboot-v2/src/mainboard/msi/ms7260/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms7260/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/msi/ms7260/cache_as_ram_auto.c @@ -50,6 +50,7 @@ #define DBGP_DEFAULT 7 #include +#include #include #include #include @@ -84,9 +85,6 @@ #if USE_FAILOVER_IMAGE == 0 #include "cpu/x86/bist.h" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif #include "northbridge/amd/amdk8/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" Index: coreboot-v2/src/mainboard/msi/ms9185/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms9185/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/msi/ms9185/cache_as_ram_auto.c @@ -47,6 +47,7 @@ #define DEBUG_SMBUS 1 #include +#include #include #include #include @@ -75,10 +76,6 @@ static void post_code(uint8_t value) { #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" Index: coreboot-v2/src/mainboard/msi/ms9282/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/msi/ms9282/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/msi/ms9282/cache_as_ram_auto.c @@ -41,6 +41,7 @@ #define DEBUG_SMBUS 1 #include +#include #include #include #include @@ -57,10 +58,6 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/newisys/khepri/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/newisys/khepri/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/newisys/khepri/cache_as_ram_auto.c @@ -7,6 +7,7 @@ #define __ROMCC__ #include +#include #include #include #include @@ -37,10 +38,6 @@ static void post_code(uint8_t value) { #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c @@ -46,6 +46,7 @@ #define DBGP_DEFAULT 7 #include +#include #include #include #include @@ -82,10 +83,6 @@ #include "cpu/x86/bist.h" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - #include "northbridge/amd/amdk8/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" Index: coreboot-v2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/sunw/ultra40/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/sunw/ultra40/cache_as_ram_auto.c @@ -14,6 +14,7 @@ #include +#include #include #include #include @@ -32,10 +33,6 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/supermicro/h8dme/apc_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/h8dme/apc_auto.c +++ coreboot-v2/src/mainboard/supermicro/h8dme/apc_auto.c @@ -48,6 +48,9 @@ #endif #include "arch/i386/lib/console.c" +#include "lib/uart8250.c" +#include "console/vtxprintf.c" +#include "./arch/i386/lib/printk_init.c" #if 0 static void post_code(uint8_t value) { Index: coreboot-v2/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c @@ -40,6 +40,7 @@ #endif #include +#include #include #include #include @@ -75,10 +76,6 @@ #include "cpu/x86/bist.h" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "northbridge/amd/amdk8/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" Index: coreboot-v2/src/mainboard/supermicro/h8dmr/apc_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/h8dmr/apc_auto.c +++ coreboot-v2/src/mainboard/supermicro/h8dmr/apc_auto.c @@ -48,6 +48,9 @@ #endif #include "arch/i386/lib/console.c" +#include "lib/uart8250.c" +#include "console/vtxprintf.c" +#include "./arch/i386/lib/printk_init.c" #if 0 static void post_code(uint8_t value) { Index: coreboot-v2/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c @@ -44,6 +44,7 @@ #endif #include +#include #include #include #include @@ -79,10 +80,6 @@ #include "cpu/x86/bist.h" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - #include "northbridge/amd/amdk8/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" Index: coreboot-v2/src/mainboard/technexion/tim8690/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/technexion/tim8690/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/technexion/tim8690/cache_as_ram_auto.c @@ -37,6 +37,7 @@ #define SMBUS_HUB 0x71 #include +#include #include #include #include @@ -54,10 +55,6 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/tyan/s2735/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2735/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/tyan/s2735/cache_as_ram_auto.c @@ -2,6 +2,7 @@ #define __ROMCC__ #include +#include #include #include #include @@ -27,10 +28,6 @@ static void post_code(uint8_t value) { #include "southbridge/intel/i82801er/i82801er_early_smbus.c" #include "northbridge/intel/e7501/raminit.h" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/intel/e7501/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" Index: coreboot-v2/src/mainboard/tyan/s2850/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2850/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/tyan/s2850/cache_as_ram_auto.c @@ -2,6 +2,7 @@ #define __ROMCC__ #include +#include #include #include #include @@ -32,10 +33,6 @@ static void post_code(uint8_t value) { #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/tyan/s2875/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2875/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/tyan/s2875/cache_as_ram_auto.c @@ -2,6 +2,7 @@ #define __ROMCC__ #include +#include #include #include #include @@ -21,10 +22,6 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/tyan/s2880/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2880/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/tyan/s2880/cache_as_ram_auto.c @@ -2,6 +2,7 @@ #define __ROMCC__ #include +#include #include #include #include @@ -22,10 +23,6 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2881/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/tyan/s2881/cache_as_ram_auto.c @@ -8,6 +8,7 @@ #endif #include +#include #include #include #include @@ -38,10 +39,6 @@ static void post_code(uint8_t value) { #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/tyan/s2882/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2882/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/tyan/s2882/cache_as_ram_auto.c @@ -2,6 +2,7 @@ #define __ROMCC__ #include +#include #include #include #include @@ -21,10 +22,6 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/tyan/s2885/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2885/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/tyan/s2885/cache_as_ram_auto.c @@ -2,6 +2,7 @@ #define __ROMCC__ #include +#include #include #include #include @@ -32,10 +33,6 @@ static void post_code(uint8_t value) { #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/tyan/s2891/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2891/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/tyan/s2891/cache_as_ram_auto.c @@ -9,6 +9,7 @@ #endif #include +#include #include #include #include @@ -27,9 +28,6 @@ #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2892/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/tyan/s2892/cache_as_ram_auto.c @@ -2,6 +2,7 @@ #define __ROMCC__ #include +#include #include #include #include @@ -21,10 +22,6 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2895/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/tyan/s2895/cache_as_ram_auto.c @@ -12,6 +12,7 @@ #endif #include +#include #include #include #include @@ -47,10 +48,6 @@ #include "cpu/x86/bist.h" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "northbridge/amd/amdk8/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" Index: coreboot-v2/src/mainboard/tyan/s2912/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2912/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/tyan/s2912/cache_as_ram_auto.c @@ -46,6 +46,7 @@ #define DBGP_DEFAULT 7 #include +#include #include #include #include @@ -82,10 +83,6 @@ #include "cpu/x86/bist.h" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - #include "northbridge/amd/amdk8/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" Index: coreboot-v2/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c @@ -39,6 +39,7 @@ #define DBGP_DEFAULT 7 #include +#include #include #include #include @@ -78,10 +79,6 @@ static void post_code(u8 value) { #include "cpu/x86/bist.h" -#if CONFIG_USE_INIT == 0 - #include "lib/memcpy.c" -#endif - #include "northbridge/amd/amdfam10/debug.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" Index: coreboot-v2/src/mainboard/tyan/s4880/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s4880/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/tyan/s4880/cache_as_ram_auto.c @@ -2,6 +2,7 @@ #define __ROMCC__ #include +#include #include #include #include @@ -21,10 +22,6 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/mainboard/tyan/s4882/cache_as_ram_auto.c =================================================================== --- coreboot-v2.orig/src/mainboard/tyan/s4882/cache_as_ram_auto.c +++ coreboot-v2/src/mainboard/tyan/s4882/cache_as_ram_auto.c @@ -2,6 +2,7 @@ #define __ROMCC__ #include +#include #include #include #include @@ -20,10 +21,6 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#if CONFIG_USE_INIT == 0 -#include "lib/memcpy.c" -#endif - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" Index: coreboot-v2/src/northbridge/intel/i945/raminit.c =================================================================== --- coreboot-v2.orig/src/northbridge/intel/i945/raminit.c +++ coreboot-v2/src/northbridge/intel/i945/raminit.c @@ -25,8 +25,6 @@ #include "raminit.h" #include "i945.h" -#include "lib/memset.c" - #define DEBUG_RAM_SETUP /* Debugging macros. */ Index: coreboot-v2/src/pc80/serial.c =================================================================== --- coreboot-v2.orig/src/pc80/serial.c +++ coreboot-v2/src/pc80/serial.c @@ -94,9 +94,6 @@ static void uart_init(void) #else /* CONFIG_USE_PRINTK_IN_CAR == 1 */ -#if CONFIG_USE_INIT == 0 -#include "../lib/uart8250.c" -#endif extern void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs); static void uart_init(void) Index: coreboot-v2/src/arch/i386/lib/Config.lb =================================================================== --- coreboot-v2.orig/src/arch/i386/lib/Config.lb +++ coreboot-v2/src/arch/i386/lib/Config.lb @@ -9,9 +9,5 @@ object pci_ops_mmconf.c object pci_ops_auto.c object exception.c -if CONFIG_USE_INIT - if CONFIG_USE_PRINTK_IN_CAR - initobject printk_init.o - end -end +initobject printk_init.o