On 4/14/10 4:18 AM, Dustin Harrison wrote:

I've put several print_info statements in romstage.c and narrowed it down to the following line in i3100_early_lpc.c:

pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 << 7));

Further debug shows that in general I can not read a value and then use the value. If I just perfrom a read operation it executes the instruction and contiues. But if I do a read and try to use a print_info_hexXX function it just hangs.

Can you try this patch please?

Index: src/southbridge/intel/i3100/i3100_early_lpc.c
===================================================================
--- src/southbridge/intel/i3100/i3100_early_lpc.c    (revision 5413)
+++ src/southbridge/intel/i3100/i3100_early_lpc.c    (working copy)
@@ -34,13 +34,14 @@
{
     device_t dev = PCI_DEV(0x0, 0x1f, 0x0);

-    /* Temporarily enable the ACPI I/O range at 0x4000 */
-    pci_write_config32(dev, 0x40, 0x4000 | (1 << 0));
-    pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 << 7));
+#define ABASE 0x400
+    /* Temporarily enable the ACPI I/O range at ABASE */
+    pci_write_config32(dev, 0x40, ABASE | (1 << 0));
+    pci_write_config8(dev, 0x44, (1 << 7));

     /* Halt the TCO timer, preventing SMI and automatic reboot */
-    outw(inw(0x4068) | (1 << 11), 0x4068);
+    outw(inw(ABASE + 0x68) | (1 << 11), ABASE + 0x68);

     /* Disable the ACPI I/O range */
-    pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) & ~(1 << 7));
+    pci_write_config8(dev, 0x44, 0);
}

Any ideas on what to try next? Is there a recommended toolchain?

Yes, you can compile it with
$ cd coreboot/util/crossgcc
$ sh buildgcc

coreboot will automatically pick it up. You might have to delete coreboot/.xcompile in order to have coreboot pick it up.

Stefan