On Wed, Feb 22, 2017 at 9:25 AM, Zoran Stojsavljevic <zoran.stojsavljevic@gmail.com> wrote:Not possible to share with you the details of my .config, until you understand that you need to investigate this problem as well. :-)I'm not sure I understand what you are saying. You are asking for help but won't share more details? If that's the case, then good luck as I can't be much help. You telling me to investigate something doesn't make me want to continue helping in the slightest.CLI transcript follows:[user@localhost coreboot]$ pwd/home/user/projects/coreboot/coreboot [user@localhost coreboot]$ cat .config | grep FIRMWARECONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y CONFIG_HAVE_INTEL_FIRMWARE=yStill not enough information. Good luck with your problem.[user@localhost coreboot]$_______[user@localhost firmware]$ pwd/home/user/projects/coreboot/coreboot/src/southbridge/intel/ common/firmware [user@localhost firmware]$ emacs Kconfig &Beginning of the file: Kconfig?config HAVE_INTEL_FIRMWAREboolhelpChipset uses the Intel Firmware Descriptor to describe thelayout of the SPI ROM chip.if HAVE_INTEL_FIRMWAREcomment "Intel Firmware"config HAVE_IFD_BINZoranOn Wed, Feb 22, 2017 at 4:13 PM, Aaron Durbin <adurbin@google.com> wrote:On Wed, Feb 22, 2017 at 9:08 AM, Zoran Stojsavljevic <zoran.stojsavljevic@gmail.com> wrote:You mean, this one (in RED)?[user@localhost coreboot]$ cat .config | grep SPICONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 # CONFIG_TPM_ON_FAST_SPI is not set# CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS is not set CONFIG_SOC_INTEL_COMMON_SPI_FLASH_PROTECT=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not setCONFIG_SPI_FLASH=yCONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y # CONFIG_SPI_FLASH_SMM is not set# CONFIG_SPI_FLASH_NO_FAST_READ is not set# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set # CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set CONFIG_BOOT_DEVICE_SPI_FLASH=y# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set # CONFIG_DEBUG_SPI_FLASH is not set[user@localhost coreboot]$Which one (but, anyway, I think you are on the wrong mental tread, unless you explicitly prove to me that I am wrong)?Where are you setting the descriptor to use during the build? Those settings highlighted in red have nothing to do with the flash descriptor settings. Please look in src/southbridge/intel/common/firmware/Kconfig for that list. Also, without the full details of your config it's impossible to know what you are or aren't doing. ZoranOn Wed, Feb 22, 2017 at 3:39 PM, Aaron Durbin <adurbin@google.com> wrote:So this device isn't supporting SPI boot? If so, then it's notOn Wed, Feb 22, 2017 at 1:12 AM, Zoran Stojsavljevic
<zoran.stojsavljevic@gmail.com> wrote:
> Hello to community,
>
> I finally, after 3 days of additional very hard struggle, found out why I
> have (while I am in the last stage of building CBFS) nonsense while building
> APL-I Coreboot coreboot.rom?!
>
> Please, read carefully this announcement.
>
> For last three days I came to hard stop because of this failure:
>
> Just quick look into the final failure (all passed, but last stage - IFD
> failed):
>
> Compile IFDTOOL
> HOSTCC util/ifdfake/ifdfake
> DD Adding Intel Firmware Descriptor
> IFDTOOL Unlocking Management Engine
> File build/coreboot.pre is 8388608 bytes
> No Flash Descriptor found in this image
> src/southbridge/intel/common/firmware/Makefile.inc:50: recipe for target
> 'add_intel_firmware' failed
> make: *** [add_intel_firmware] Error 1
> [user@localhost coreboot]$
>
> At first, I suspect that culprit my .config file, but I have checked it
> several times (maybe > dozen), and I could NOT find any problem with it
> (except minor doubts).
>
> Then I switched to inspect -southbridge- setup, but these is none, since
> (simplified explanation/view) APL-I is SoC.
>
> The next phase was to inspect
> src/southbridge/intel/common/firmware/Makefile.inc , but there (although my
> make scripting is rusty) I could NOT find any problem...
>
> Finally, somewhere around 2:00 AM I noticed/determined the root cause of the
> problem: the util/ifdtool/ifdtool.c, line:
> if (*(uint32_t *) (image + i) == 0x0FF0A55A) {
>
> YET another INTEL IOTG PED hidden road bomb: the latest APL-I FSP:
> APL-I_FSP/ApolloLakeFspBinPkg/FspBin/ApolloLakeFsp.fd does NOT have pattern
> 0x0FF0A55A embedded in it (I have checked with HxD WIN tool).
surprise that there's no SPI descriptor. And you didn't add one it
seems.
> -->
> Then, modifying the C f-n static fdbar_t *find_fd(char *image, int size),
> finally I've got success! :-(
>
> Hello Martin,
>
> Thank you for unselfish help.
>
> Best Regards,
> Zoran Stojsavljevic
>
>
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