Thanks Marc and Kyösti for your hints.

As I'm just discovering coreboot and its multiple possibilities, please apologize if my questions seems "too simple"... ;-)

A) UART Type
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From Kconfig file in ./src/drivers/uart, the valid ID for the oxpcie is 1415:c158.
I can obtain this ID on my Startech board only when I strapped it as "native UART" (Startech documentation), that is : memory-mapped.

From Kconfig file in ./src/console, there is following sentence : "Supporting multiple different types of UARTs in one build is not supported.".
Q: Am I correct if I translate this like : "Use only memory-mapped or IO-mapped UARTs, but not both at the same time." ?


B) Memory-mapped UART required options
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From the answers received, I would say that the required options (in make menuconfig) would be:
- In "Generic Drivers": validate Oxford OXPCIe952 and de-validate "Serial Port on SuperIO".

- In "Devices": Set the device and function numbers of the PCie bridge, behind which is connected the Startech board. On Mohon Peak, it's D1-F0.
Q: What about the MMIO window base ? Is it the memory address of the UARTs, defined by the values in the BAR registers ?

- in "Console": Validate "Serial Port Console Output".
Q: What about the index of the "Serial Port console output" ? IMHO, there are only valid for IO-mapped UART. Correct ?

Q: Am I missing anything ?

Thanks in advance for the time you want to spent on it.
Regards,
Patrick

Le 06/03/2015 19:01, Marc Jones a écrit :