On Thu, Dec 4, 2008 at 10:52 AM, Marc Jones <marcj303@gmail.com> wrote:

On Thu, Dec 4, 2008 at 8:21 AM, Rudolf Marek <r.marek@assembler.cz> wrote:
>> So would it be reasonable to have the domain reserve it, since having a
>> resource for each CPU at the same place could get confusing? Do we have
>> LAPIC devices on any platforms in Coreboot, so that it could be reserved
>> there?
>
> LAPIC is in any CPU post Pentium.

I was trying to say what Rudolf clarified. There is a local APIC in
each CPU core at the addess 0xFEE00000 so we only need to reserve it
once. Logically it doesn't make sense to have it in the northbridge.
That gets back to just putting it in the domain.

That makes sense to me. I didn't want to put it in the CPU because it only needs to be reserved once. This doesn't really matter for resource allocation because the IOAPIC is at a lower address and so resource allocation will never come this high. I'd like it to be logical and complete in case something else needs to know, though.

I thought that the
IOAPIC 0xFEC00000 should in the southbridge but if the LAPIC is in
the domain then maybe the IOAPIC shoud be with it.

It makes sense to me to put it in the southbridge. Rudolf has said that different southbridges reserve different amounts of space for these, and domains are independent of southbridges.

I think that the only CPU coreboot supports that doesn't have a LAPIC
is the Geode. It has no multicore capability and sitll uses the legacy
PIC.

I should have clarified here. I was asking if any of the platforms would create a device in the dts for the LAPIC. I'm assuming that the answer is no.

Thanks,
Myles