> Do you remember from where you got these magic values? Suspect I'm going
> to need similar. Will investigate soc/amd/¨* too.

> /* QEMU-specific register */
> #define EXT_TSEG_MBYTES 0x50
> +#define SMRAMC 0x9d
> +#define C_BASE_SEG     ((0 << 2) | (1 << 1) | (0 << 0))
> +#define G_SMRAME       (1 << 3)
> +#define D_LCK          (1 << 4)
> +#define D_CLS          (1 << 5)
> +#define D_OPEN         (1 << 6)
> +#define ESMRAMC        0x9e
> +#define T_EN           (1 << 0)
> +#define TSEG_SZ_MASK   (3 << 1)
> +#define H_SMRAME       (1 << 7)

Those are northbridge specific register on how to handle the SMM windows (SMRAM). The BKDG should have something similar.
TSEG is also an interesting search parameter.

On Thu, Nov 25, 2021 at 7:39 PM awokd via coreboot <coreboot@coreboot.org> wrote:
Arthur Heymans:

> https://review.coreboot.org/c/coreboot/+/48210 and
> https://review.coreboot.org/c/coreboot/+/48262/ provided the implementation
> for PARALLEL_MP on qemu.
> Notice that modern AMD CPUs (soc/amd/¨*) also use PARALLEL_MP and can be
> used as an example for AMD AGESA platforms too.
>
> Good luck!

Thank you, going to need it! Would be nice if that AMD open source rep.
wanted to own and deliver on global (to AMD AGESA) changes like this to
"demonstrate a renewed commitment to the community" in corpospeak, but
will see what I can do.

Do you remember from where you got these magic values? Suspect I'm going
to need similar. Will investigate soc/amd/¨* too.

/* QEMU-specific register */
#define EXT_TSEG_MBYTES 0x50
+#define SMRAMC 0x9d
+#define C_BASE_SEG     ((0 << 2) | (1 << 1) | (0 << 0))
+#define G_SMRAME       (1 << 3)
+#define D_LCK          (1 << 4)
+#define D_CLS          (1 << 5)
+#define D_OPEN         (1 << 6)
+#define ESMRAMC        0x9e
+#define T_EN           (1 << 0)
+#define TSEG_SZ_MASK   (3 << 1)
+#define H_SMRAME       (1 << 7)
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