Support for Intel Core Duo and Core 2 Duo (tm) CPUs.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>

Index: src/cpu/x86/car/copy_and_run.c
===================================================================
--- src/cpu/x86/car/copy_and_run.c	(revision 3698)
+++ src/cpu/x86/car/copy_and_run.c	(working copy)
@@ -72,7 +72,7 @@
 	__asm__ volatile (
 		"cli\n\t"
 		"leal    _iseg, %edi\n\t"
-		"jmp     %edi\n\t"
+		"jmp     *%edi\n\t"
 	);
 
 }
Index: src/cpu/x86/lapic/lapic_cpu_init.c
===================================================================
--- src/cpu/x86/lapic/lapic_cpu_init.c	(revision 3698)
+++ src/cpu/x86/lapic/lapic_cpu_init.c	(working copy)
@@ -437,6 +437,10 @@
 	#define cpus_ready_for_init() do {} while(0)
 #endif
 
+#if HAVE_SMI_HANDLER
+void smm_init(void);
+#endif
+
 void initialize_cpus(struct bus *cpu_bus)
 {
 	struct device_path cpu_path;
@@ -457,14 +461,18 @@
 	cpu_path.type           = DEVICE_PATH_CPU;
 	cpu_path.u.cpu.id       = 0;
 #endif
-	
+
 	/* Find the device structure for the boot cpu */
 	info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
 
 #if CONFIG_SMP == 1
 	copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init
 #endif
-	
+
+#if HAVE_SMI_HANDLER
+	smm_init();
+#endif
+
         cpus_ready_for_init(); 
 
 #if CONFIG_SMP == 1
@@ -477,7 +485,6 @@
         /* Initialize the bootstrap processor */
         cpu_initialize();
 
-
 #if CONFIG_SMP == 1
         #if SERIAL_CPU_INIT == 1
         start_other_cpus(cpu_bus, info->cpu);
@@ -486,6 +493,5 @@
 	/* Now wait the rest of the cpus stop*/
 	wait_other_cpus_stop(cpu_bus);
 #endif
-
 }
 
Index: src/cpu/intel/model_6ex/Config.lb
===================================================================
--- src/cpu/intel/model_6ex/Config.lb	(revision 0)
+++ src/cpu/intel/model_6ex/Config.lb	(revision 0)
@@ -0,0 +1,13 @@
+uses HAVE_MOVNTI
+default HAVE_MOVNTI=1
+
+dir /cpu/x86/tsc
+dir /cpu/x86/mtrr
+dir /cpu/x86/fpu
+dir /cpu/x86/mmx
+dir /cpu/x86/sse
+dir /cpu/x86/lapic
+dir /cpu/x86/cache
+dir /cpu/intel/microcode
+dir /cpu/intel/hyperthreading
+driver model_6ex_init.o
Index: src/cpu/intel/model_6ex/model_6ex_init.c
===================================================================
--- src/cpu/intel/model_6ex/model_6ex_init.c	(revision 0)
+++ src/cpu/intel/model_6ex/model_6ex_init.c	(revision 0)
@@ -0,0 +1,94 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/hyperthreading.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+
+static const uint32_t microcode_updates[] = {
+	#include "microcode_m206e839.h"
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+static inline void strcpy(char *dst, char *src) 
+{
+	while (*src) *dst++ = *src++;
+}
+
+static void fill_processor_name(char *processor_name)
+{
+	struct cpuid_result regs;
+	char temp_processor_name[49];
+	char *processor_name_start;
+	unsigned int *name_as_ints = (unsigned int *)temp_processor_name;
+	int i;
+
+	for (i=0; i<3; i++) {
+		regs = cpuid(0x80000002 + i);
+		name_as_ints[i*4 + 0] = regs.eax;
+		name_as_ints[i*4 + 1] = regs.ebx;
+		name_as_ints[i*4 + 2] = regs.ecx;
+		name_as_ints[i*4 + 3] = regs.edx;
+	}
+
+	temp_processor_name[48] = 0;
+
+	/* Skip leading spaces */
+	processor_name_start = temp_processor_name;
+	while (*processor_name_start == ' ') 
+		processor_name_start++;
+
+	memset(processor_name, 0, 49);
+	strcpy(processor_name, processor_name_start);
+}
+
+static void model_6ex_init(device_t cpu)
+{
+	char processor_name[49];
+
+	/* Turn on caching if we haven't already */
+	x86_enable_cache();
+
+	/* Update the microcode */
+	intel_update_microcode(microcode_updates);
+
+	/* Print processor name */
+	fill_processor_name(processor_name);
+	printk_info("CPU: %s.\n", processor_name);
+
+	/* Setup MTRRs */
+	x86_setup_mtrrs(36);
+	x86_mtrr_check();
+	
+	/* Enable the local cpu apics */
+	setup_lapic();
+
+	/* Start up my cpu siblings */
+	intel_sibling_init(cpu);
+}
+
+static struct device_operations cpu_dev_ops = {
+	.init     = model_6ex_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x06e0 }, /* Intel Core Solo/Core Duo */
+	{ X86_VENDOR_INTEL, 0x06e8 }, /* Intel Core Solo/Core Duo */
+	{ 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+};
+
Index: src/cpu/intel/model_6ex/microcode_m206e839.h
===================================================================
--- src/cpu/intel/model_6ex/microcode_m206e839.h	(revision 0)
+++ src/cpu/intel/model_6ex/microcode_m206e839.h	(revision 0)
@@ -0,0 +1,291 @@
+//+++
+//       Copyright (c) <1995-2008>, Intel Corporation.
+//	All rights reserved.
+//
+//	Redistribution. Redistribution and use in binary form, without modification, are
+//	permitted provided that the following conditions are met:
+//		.Redistributions must reproduce the above copyright notice and the following
+//	disclaimer in the documentation and/or other materials provided with the
+//	distribution.
+//		.Neither the name of Intel Corporation nor the names of its suppliers may be used
+//	to endorse or promote products derived from this software without specific prior
+//	written permission.
+//		.No reverse engineering, decompilation, or disassembly of this software is
+//	permitted.
+//		."Binary form" includes any format commonly used for electronic conveyance
+//	which is a reversible, bit-exact translation of binary representation to ASCII or
+//	ISO text, for example, "uuencode."
+//
+//	DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+//	HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+//	WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+//	WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+//	PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+//	OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+//	SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+//	NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+//	LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+//	CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+//	STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+//	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+//	ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//---
+/*  Tue Apr 1 14:14:15 CST 2008  */
+/*  1624-m206e839.inc  */
+0x00000001,	0x00000039,	0x11152005,	0x000006e8,
+0x00e9d6a3,	0x00000001,	0x00000020,	0x00000fd0,
+0x00001000,	0x00000000,	0x00000000,	0x00000000,
+0xc9226026,	0x31d04cc5,	0xeb5e9216,	0x81b9b739,
+0xb8187c4d,	0xdb2db5c8,	0xac304dd3,	0x56259185,
+0x5cee9dfc,	0xc4c708fc,	0xfbfebb15,	0x4657a346,
+0xd5fdfc56,	0x49ccc684,	0xfe2f1980,	0x23e44e95,
+0xaf7e0890,	0x0a306ae9,	0x0533035c,	0xf747f6c4,
+0xbb7a6356,	0x07415037,	0xb9cd0d46,	0x4dc69422,
+0x19ed8dba,	0x61955793,	0x2c69260d,	0x0e23b80f,
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+0x2b0ceb7b,	0x6fe0367e,	0xce928c01,	0x69589c6f,
+0x0c28f0f7,	0xd9ac3fa8,	0xd6a23e1d,	0x19613ebb,
+0xe455b950,	0xa58b7cf7,	0xeeab2947,	0x1e588aa8,
+0xbb634862,	0x5b6421b2,	0x6297ae0b,	0xbf63b1e9,
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+0xacdf6376,	0x759f6e7a,	0x614eb519,	0xf97894f9,
+0x69e18e24,	0x445adfa4,	0x6fc71d78,	0xb2bd1312,
+0x270e3a49,	0xdf22e530,	0x96d6bfab,	0x2d8153c4,
+0xe487add3,	0x0461fbe4,	0x6179e23b,	0x22bf0ad7,
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+0x52f17360,	0x1a381a4f,	0xde59c8b1,	0x5ad6ddd1,
+0x01440596,	0xfb7ca9db,	0xf1b1c83b,	0xe4983438,
+0xdb246883,	0x1044db5d,	0x5e4a560e,	0x8312d13a,
+0x5db5e546,	0xfcf1485e,	0x6a95f22e,	0xebdf4063,
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+0x38a4f7a0,	0xd5af72ad,	0x7e7ba9b6,	0x9a2c2f5a,
+0xe141e11c,	0x54101bf0,	0x6bd34fba,	0x2aeebd40,
+0xf3c6a02a,	0xfb45a6ea,	0x5f6cc3f9,	0x7d19ace6,
+0xc4e50923,	0xb77d6c3b,	0x28d21508,	0xa68dbda2,
+0x53519ded,	0x7d38215b,	0x6554c1d0,	0xceade8a5,
+0x861dbd69,	0x327694d4,	0x2284cab7,	0x79b7a4a9,
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+0xed66debc,	0xc081cc22,	0x13b62693,	0x1f739d44,
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+0x6d0cff83,	0x8b23bd82,	0x13251589,	0x9243024c,
+0x452e1d68,	0x22ee9797,	0xc02673e4,	0x8b9a7d37,
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+0x31eb7699,	0xeb54ddc7,	0xa2fe7da1,	0x0ee15251,
+0x614235df,	0xe9cfedbe,	0x892a4e69,	0x9da98557,
+0x335b3fdf,	0x8ea201e5,	0x0946feb6,	0xb5a786df,
+0x022cc831,	0xab624815,	0xbc424527,	0x735f92de,
+0x9936cecb,	0x0e761edf,	0x0090693e,	0xc4a0499a,
+0x6b23228b,	0x1eb11bb0,	0xfa0e532f,	0xf3908bd4,
+0x6d12934f,	0xb0af2c23,	0x8ee4af5c,	0xdc901aa7,
+0x0354b0bf,	0xd130aaa9,	0xcdd548cf,	0x63c30fa9,
+0x2ce21b9d,	0xd28af5fd,	0xd0dd7223,	0xf8037eb4,
+0x475e5121,	0x4da06882,	0x5b5f6d0f,	0x2010ee60,
+0x6b70b26e,	0x34046d99,	0x60d17b52,	0x0ceb5995,
+0xfe843bb5,	0x32bd202f,	0xd253d64e,	0xafbbc103,
+0xfe550a5c,	0xadc17fca,	0xd50e62ac,	0x04aac0c1,
+0xfdc53287,	0x2ca779e0,	0x50d3509c,	0xc6642217,
+0x15a4a216,	0x792dc831,	0x28aaeb0e,	0xd90a51b1,
+0x4aafd019,	0x7120d967,	0x600cc53d,	0xcce4712a,
+0xa51c84bc,	0xa446aea8,	0x2d0434df,	0x7cc7e1bb,
+0xc58d985e,	0x975fd3b5,	0xeabd457e,	0x63019a78,
+0x07dd4acb,	0xf5d1b481,	0x271b33e9,	0x74e6b893,
+0xe1660e8d,	0x3b3857c1,	0xae2228b4,	0xe8971978,
+0xa5e9d620,	0xc42ce628,	0x8a723c90,	0xe1cbd643,
+0xd6b31dd6,	0x10ac4693,	0x30d07574,	0x2ceb736c,
+0xc4534cfb,	0xb1576d35,	0xb7452467,	0x83d90ec1,
+0x136647f4,	0xee1225f9,	0xb018b3ab,	0xe40e1466,
+0x6c39168a,	0x209e1e98,	0x467a80da,	0x39895b4d,
+0x9830701a,	0x08bb3694,	0x944d4ca5,	0x1b345056,
+0xfcd65853,	0x02dd7e3e,	0x8c3fe8ad,	0x4a250b9f,
+0x88f396e9,	0x1c7e6763,	0x8d63d571,	0x46bc5836,
+0x3495194f,	0x612a5504,	0xa3c960aa,	0x206508d5,
+0x0e742fa5,	0x962dc01a,	0xd7c6ae91,	0x7c60637a,
+0x4dd751b0,	0xe9ec6585,	0x7a6a9d8e,	0x97cc23b2,
+0x17c7cd98,	0x6bd0197e,	0x825caffd,	0x1b682617,
+0xb7a146df,	0x6cd43071,	0x46a325ef,	0x606c23cd,
+0xf391543b,	0x0c1273e7,	0xb14311ad,	0xa56c20d6,
+0x4f2b1f6b,	0x027fdd15,	0x153e5b84,	0x230ef754,
+0xddc5231c,	0x27009a47,	0x6a1af01f,	0x3eb1712f,
+0xdd5b0538,	0x1bdd1a17,	0x94a692ee,	0x6569ea36,
+0xbbed3e8c,	0x44be3a3a,	0x322e23fc,	0xb620d922,
+0xb0e4364b,	0xa6e9a5c9,	0x74ade8ba,	0xb619ba36,
+0x1ab260b7,	0x49d93617,	0xf34f51e0,	0x86c922f8,
+0x8b62ae4c,	0x4c5d191b,	0x8af345d3,	0x7dabf68a,
+0x50630f7d,	0x9367968d,	0x9dd2ec02,	0xcbbc9de9,
+0x96ff6002,	0x22557f00,	0xdcb11cef,	0x9a433696,
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+0x26917ebb,	0x120198ea,	0x9fbc891b,	0x6024a8b3,
+0x21f187be,	0x5fc97d12,	0x8f40dd2b,	0xed5099af,
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+0x68074f27,	0xda4e4f40,	0x92355570,	0x87d9fc1b,
+0x79ba00f8,	0x80188b0a,	0x54d6c99e,	0x0c291886,
+0xae1ba6d8,	0xe1db6d71,	0x812eb8d5,	0xfe443861,
+0x4697dfe3,	0x07e2c123,	0xef211237,	0xe39cf56d,
+0x0dfe17fa,	0xea6030a6,	0xbaf85b2f,	0xb1fb1e75,
+0xb78b8e9d,	0x93d9d1bd,	0x6865386a,	0x85797883,
+0xa4136a38,	0x4c0ab699,	0x0647103e,	0x678defd1,
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+0x26c4d503,	0x01e85a02,	0xe5794f2a,	0xe59d8e11,
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+0x8b262c13,	0x5cbbc0a0,	0x1acd3e84,	0xf4fce699,
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+0xbe10054d,	0xd1123dbf,	0x0d19268f,	0x9abdf2da,
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+0xe667e664,	0xbf46632a,	0x14119b51,	0x2746bed7,
+0x37158545,	0x1e846c85,	0x1b95a555,	0xb7199a1e,
+0xa15c019c,	0xa3387c3d,	0x65ce357c,	0x4262836d,
+0x0cfe418c,	0x24ecb61e,	0x21bae0f7,	0xae0f7d05,
+0x21cb819c,	0x7c6f341c,	0xd40399ff,	0x340603e4,
+0x0c99c59f,	0xf2bfe2c8,	0x3fa6ab62,	0xfd523ff3,
+0x6729a50d,	0x748b60db,	0xd12ce998,	0xab74bee0,
+0xabd8562e,	0x486b62d0,	0xdf54ea64,	0x05706018,
+0xad5f0651,	0x03925450,	0x953c9690,	0xf671def9,
+0x12f2bc25,	0x489088ed,	0xe0821dfe,	0x86fc2ee9,
+0x5337050a,	0x73fe5693,	0xfdb68668,	0x6e3aaf10,
+0x1ff17349,	0xe0ed3f06,	0xf04c6a24,	0xc2ca002d,
+0x4413be0e,	0xf936745e,	0x2ecba010,	0x12d5d285,
+0xac3fbf57,	0x64a4bc04,	0xc8487824,	0xa98ffbcd,
+0xd09f47ed,	0xd55c8fca,	0x48f6b1ba,	0x7c91efae,
+0x996cceee,	0xe4eba045,	0x93231e6b,	0xeec78b5b,
+0x36b57bcb,	0x117e4338,	0x372b2355,	0x858d9058,
+0xcfd6a2ad,	0x0dfcf7ff,	0xb2175d06,	0xc30c0b18,
+0x082676e6,	0xa72aef65,	0x7fe69e25,	0x89e017fc,
+0x0c02475b,	0xfb6db944,	0xa22a7f67,	0x5109be81,
+0x49be8288,	0xe5912a66,	0x3e7f9c57,	0x196a17f2,
+0xc8f6d41d,	0x4a4ed74c,	0xf7068058,	0x530f85f5,
+0x5a62affb,	0x607e69cd,	0x187b3d35,	0xc0ba9105,
+0x09242e0d,	0xb9ed74d1,	0x89ee52f9,	0x304e629f,
+0xff1c5f7a,	0x541468fc,	0x889f2877,	0x009f0823,
+0x1554c91e,	0x4ede3cc6,	0xe8055158,	0x1f875bd4,
+0x7f319b05,	0xfd3b3605,	0xeede9e36,	0xfb91c6a8,
+0x13a4a1f0,	0xcfe5ea7b,	0x72e4742d,	0xfec9bfad,
+0x423111bf,	0xfc123877,	0x9d8a1696,	0xde722ee1,
+0x58581af4,	0xe6d333e3,	0x96480fd1,	0x1ec04bc8,
+0x89cd9328,	0x184a2e72,	0x61250a9a,	0x02a60896,
+0x68c4dc7f,	0x33bc2435,	0xef7ec8e4,	0xc184d4f0,
+0x2cc1046f,	0x022ddcbe,	0x44c1bdaf,	0x7a12cd23,
+0x5b378349,	0xc304a9b6,	0x3bdb987a,	0xbc33e5e1,
+0xb24473fd,	0x3e91a25e,	0xafadce24,	0x69738f5e,
+0x64410ade,	0x74dd6439,	0xe05174a6,	0xfc407a51,
+0x6330fbf3,	0xcb7c8c5a,	0x2ddded66,	0xd3165da8,
+0x023ed9e6,	0x3f2798d0,	0xe58c407c,	0x12f6c6fe,
+0x3d4e93d9,	0x1f44033b,	0x7415ece6,	0x797e18d0,
+0x1960eb38,	0x6d8802e8,	0x9aad531f,	0xacd1bea3,
+0xa437ffb9,	0xa512277d,	0x9ede1f43,	0x30b7894b,
+0x12116f70,	0xe238aa2f,	0x0bb75ff4,	0x1c5d91df,
+0x3636f6c0,	0xe0dfcfeb,	0x5389b29b,	0xa33a7562,
+0x85e4eab9,	0x09fefce5,	0x985ad1c9,	0xd93ff9ea,
+0x4c719a78,	0x4f47e619,	0x1dd726df,	0x4d6ac303,
+0x624e6340,	0x66986a42,	0xe56fa716,	0x055a5b10,
+0x2aaba4ae,	0x247363fe,	0x86dfbbca,	0xb9a66781,
+0x98e93037,	0x5d4e8c15,	0x9cc60f0f,	0x09ce687e,
+0x7948f82e,	0x329ed957,	0x413c9131,	0xd15a62c2,
+0xe19cc4d4,	0xb6435a71,	0xc891e0cb,	0x64067d28,
+0x71b59db7,	0xcd65e65b,	0x127354ee,	0x91b9d9e5,
+0x7159f111,	0x408dde9b,	0x9b50d36e,	0x93eda2f4,
+0x55429b2e,	0xa8b97a22,	0x5b625128,	0x7000e78e,
+0xbe0ffa92,	0xa3473045,	0x0990e748,	0x9f02bfd1,
+0xb4a4b632,	0xacc6e8ef,	0x83f1e4ed,	0x8c539784,
+0xedd466a9,	0x77e6ca09,	0xa453dcb5,	0x247db83a,
+0x4cd641c0,	0x4de6a12e,	0xf8599e34,	0xc825fc73,
+0x48c4ccaf,	0xfc5bba30,	0xd71618ac,	0xc87934bd,
+0xe96101d1,	0x55d1976c,	0x471c8505,	0x7a36d839,
+0x5d62a9ee,	0xf3c54a8a,	0xa2be15d9,	0x244087c9,
+0x042c8037,	0x23224689,	0x281c5d73,	0x2139ecfc,
+0xffb8bc8a,	0x834fdd11,	0x9cd5a5bd,	0xa3368319,
+0x7e5bef0c,	0x4ae2dbda,	0x86d90089,	0x6675dfce,
+0x48876262,	0xcec72538,	0x11dc5c80,	0x86a730f9,
+0x313565c9,	0xe3e5be11,	0x106d7cce,	0x752b8be2,
+0x3d00a5bc,	0xe6f70e95,	0x44447ac8,	0x600df30c,
+0x8335ac3b,	0x8816ddee,	0x700982fe,	0xee495741,
+0x48c7e81c,	0xa3d55da2,	0xb0172982,	0x70ab2158,
+0xd4460621,	0x3a9e528b,	0x59b18a7b,	0xf4dabc4c,
+0xa8454763,	0x70877bb6,	0x66005c97,	0xaf292c06,
+0x7b843db1,	0xf343b59b,	0x25cdc7b5,	0xa41da617,
+0x9e9d895e,	0xc936f475,	0x7270925a,	0x30024230,
+0x8e72f53d,	0x2b6c1b6f,	0x1a69732c,	0x7ed5aff5,
+0xfc18a2a3,	0xaf377cc1,	0xbff09a78,	0x4b4e0814,
+0x95a0b2c1,	0x270398de,	0x201fca94,	0x2a032a4f,
+0x131542b4,	0x0d7306da,	0x2d1c3496,	0xcc3c6d8d,
+0xa814ddc9,	0xa3b3a991,	0x17ee60c2,	0x852c0b8d,
+0x11e5853a,	0x762002a7,	0x92c5311d,	0x0d4bf7e1,
+0xfffec870,	0xe3d35e5b,	0xff6ecfb9,	0xdedae6ff,
+0x0111a772,	0x9808e780,	0x29c336e8,	0xe9bc05df,
+0x5bedde11,	0x945565af,	0xaff808fe,	0x87e3423d,
+0x4de6f98f,	0x93b4adef,	0xbf704fa4,	0x09120e91,
+0xd54f3692,	0xdf8eab1e,	0xfabbf59c,	0xe74318be,
+0xaab87ffc,	0x29fa791c,	0xe3915552,	0xa652cb9b,
+0xa1252e74,	0xb35b723b,	0x542aa28b,	0x12fcc5b0,
+0x3941f962,	0x82bcc6cc,	0x47b11974,	0xb821611f,
+0x78b34250,	0xf1be5659,	0x561b9e61,	0x6f3bd501,
+0x584e6f5c,	0xd54ed547,	0xacebcd21,	0x7b5ff816,
+0xb64ad233,	0x9f2f330d,	0x69fb1ece,	0xac8710dd,
+0x58dc6c60,	0x9bee6139,	0xbb10ad0e,	0xbd8cd5dd,
+0xebc0ce9d,	0xa733274f,	0x884d9b55,	0x42b08b63,
+0xafa54a74,	0x1c7ccf64,	0x93a20191,	0xaaa3132e,
+0xc69831d1,	0x54634889,	0xfbfe3efc,	0xd3cf68d4,
+0x302e3117,	0xf5693131,	0xc3ce8c6c,	0x1f03cd89,
+0x6243334c,	0xf16bc80f,	0xdca5f130,	0xcb2cd956,
+0x4c1bb421,	0xe8de533c,	0x7f86703a,	0x29aa897e,
+0xdd54acad,	0x76b2f2ae,	0x7ef82b71,	0x2e30970b,
+0xba402597,	0x9a653ab4,	0xd68fcf53,	0x2d9f0d15,
+0x7f9efd1c,	0x2363d147,	0x5327289a,	0xe89229f3,
+0xd63a535c,	0x7efe9273,	0x64f2e3a3,	0x9bdf65a7,
+0x26b6edfb,	0x1b9c7bfe,	0x5d14b3de,	0x54d575fb,
+0x6d65db4c,	0x95648b7f,	0xa8a3b8f0,	0x7cc7ad46,
+0xe20e6dbb,	0x8488a45f,	0x8ebc2932,	0xd4767316,
+0x3e8c4b8a,	0xbab7402c,	0xfc1e217e,	0xe5c5bf82,
+0x6928fe2e,	0xc88528e9,	0x4b2e4e8f,	0xdd938b86,
+0x0c964f98,	0xfc88d480,	0x35fcaf9e,	0xdd7bbe9d,
+0x197d005a,	0x4d40b3b3,	0xcf203155,	0x0d2fa621,
+0x752d2c58,	0xb12bac12,	0x1e7e8c23,	0x94215d54,
+0x9854a71c,	0x4de63c64,	0x7a012529,	0x9c171f8d,
+0x9e71def7,	0x3bd17d50,	0x11f175d9,	0xec78abf3,
+0x7b529eee,	0xd3a69fc3,	0x5b718676,	0x58214d29,
+0xa8bd2c34,	0x41ea00ab,	0xa03f64d6,	0x4ee342b0,
+0x32b1e444,	0x1c1801a4,	0xc8424702,	0x334a7e35,
+0x50cf1543,	0x3b22b495,	0x88683776,	0x8e2e0154,
+0x6155c033,	0x4e2fa6ac,	0x42ace700,	0x8d64f97c,
+0xaf9ced17,	0xb2a5cb92,	0xa558582d,	0x88705de7,
+0x9e528d59,	0x84bd45e4,	0x5cb680c0,	0xcd48fa5c,
+
Index: src/cpu/intel/model_6ex/cache_as_ram_disable.c
===================================================================
--- src/cpu/intel/model_6ex/cache_as_ram_disable.c	(revision 0)
+++ src/cpu/intel/model_6ex/cache_as_ram_disable.c	(revision 0)
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "cpu/x86/car/copy_and_run.c"
+
+void real_main(unsigned long bist);
+
+void stage1_main(unsigned long bist)
+{
+	unsigned int cpu_reset = 0;
+
+#if USE_FALLBACK_IMAGE == 1
+        /* Is this a deliberate reset by the bios */
+        if (bios_reset_detected() && last_boot_normal()) {
+                goto normal_image;
+        } else {
+        	/* This is the primary cpu how should I boot? */
+		check_cmos_failed();
+		if (do_normal_boot()) {
+        	        goto normal_image;
+	        }
+        	else {
+	                goto fallback_image;
+        	}
+	}
+ normal_image:
+        __asm__ volatile ("jmp __normal_image"
+                : /* outputs */
+                : "a" (bist) /* inputs */
+                );
+ fallback_image:
+#endif
+
+	real_main(bist);
+
+	/* No servicable parts below this line .. */
+
+        {
+        	/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
+	        unsigned v_esp;
+	        __asm__ volatile (
+        	        "movl   %%esp, %0\n\t"
+	                : "=a" (v_esp)
+	        );
+	        printk_spew("v_esp=%08x\r\n", v_esp);
+        }
+
+cpu_reset_x:
+
+        printk_spew("cpu_reset = %08x\r\n",cpu_reset);
+
+	if(cpu_reset == 0) {
+	        print_spew("Clearing initial memory region: ");
+	}
+	print_spew("No cache as ram now - ");
+
+	/* store cpu_reset to ebx */
+        __asm__ volatile (
+                "movl %0, %%ebx\n\t"
+                ::"a" (cpu_reset)
+        );
+
+	if(cpu_reset==0) {
+#define CLEAR_FIRST_1M_RAM 1
+#include "cache_as_ram_post.c"
+	} else {
+#undef CLEAR_FIRST_1M_RAM 
+#include "cache_as_ram_post.c"
+	}
+
+	__asm__ volatile (
+                /* set new esp */ /* before _RAMBASE */
+                "subl   %0, %%ebp\n\t"
+                "subl   %0, %%esp\n\t"
+                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
+	);
+
+	{
+		unsigned new_cpu_reset;
+
+		/* get back cpu_reset from ebx */
+		__asm__ volatile (
+			"movl %%ebx, %0\n\t"
+			:"=a" (new_cpu_reset)
+		);
+
+		/* Copy and execute coreboot_ram */
+		copy_and_run(new_cpu_reset);
+		/* We will not return */
+	}
+
+	print_debug("sorry. parachute did not open.\r\n");
+}
Index: src/cpu/intel/model_6ex/cache_as_ram_post.c
===================================================================
--- src/cpu/intel/model_6ex/cache_as_ram_post.c	(revision 0)
+++ src/cpu/intel/model_6ex/cache_as_ram_post.c	(revision 0)
@@ -0,0 +1,125 @@
+/*
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+        __asm__ volatile (
+
+	"movb	$0x30, %al\noutb %al, $0x80\n"
+
+	/* Disable Cache */
+	"movl	%cr0, %eax\n"
+	"orl    $(1 << 30), %eax\n"
+	"movl	%eax, %cr0\n"
+
+	"movb	$0x31, %al\noutb %al, $0x80\n"
+
+	/* Disable MTRR */
+	"movl	$MTRRdefType_MSR, %ecx\n"
+	"rdmsr\n"
+	"andl	$(~(1 << 11)), %eax\n"
+	"wrmsr\n"
+
+	"movb	$0x32, %al\noutb %al, $0x80\n"
+
+	"invd\n"
+#if 0
+	"xorl	%eax, %eax\n"
+	"xorl	%edx, %edx\n"
+	"movl	$MTRRphysBase_MSR(0), %ecx\n"
+	"wrmsr\n"
+	"movl	$MTRRphysMask_MSR(0), %ecx\n"
+	"wrmsr\n"
+	"movl	$MTRRphysBase_MSR(1), %ecx\n"
+	"wrmsr\n"
+	"movl	$MTRRphysMask_MSR(1), %ecx\n"
+	"wrmsr\n"
+#endif
+
+	"movb	$0x33, %al\noutb %al, $0x80\n"
+#ifdef CLEAR_FIRST_1M_RAM
+	"movb	$0x34, %al\noutb %al, $0x80\n"
+	/* Enable Write Combining and Speculative Reads for the first 1MB */
+	"movl	$MTRRphysBase_MSR(0), %ecx\n"
+	"movl	$(0x00000000 | MTRR_TYPE_WRCOMB), %eax\n"
+	"xorl	%edx, %edx\n"
+	"wrmsr\n"
+	"movl	$MTRRphysMask_MSR(0), %ecx\n"
+	"movl	$(~(1024*1024 -1) | (1 << 11)), %eax\n"
+	"movl	$0x0000000f, %edx\n"	// 36bit address space
+	"wrmsr\n"
+	"movb	$0x35, %al\noutb %al, $0x80\n"
+#endif
+
+	/* Enable Cache */
+	"movl	%cr0, %eax\n"
+	"andl    $~( (1 << 30) | (1 << 29) ), %eax\n"
+	"movl	%eax, %cr0\n"
+
+	"movb	$0x36, %al\noutb %al, $0x80\n"
+#ifdef CLEAR_FIRST_1M_RAM
+
+	/* Clear first 1MB of RAM */
+	"movl	$0x00000000, %edi\n"
+	"cld\n"
+	"xorl	%eax, %eax\n"
+	"movl	$((1024*1024) / 4), %ecx\n"
+	"rep stosl\n"
+	
+	"movb	$0x37, %al\noutb %al, $0x80\n"
+#endif
+
+	/* Disable Cache */
+	"movl	%cr0, %eax\n"
+	"orl    $(1 << 30), %eax\n"
+	"movl	%eax, %cr0\n"
+
+	"movb	$0x38, %al\noutb %al, $0x80\n"
+
+	/* Enable Write Back and Speculative Reads for the first 1MB */
+	"movl	$MTRRphysBase_MSR(0), %ecx\n"
+	"movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax\n"
+	"xorl	%edx, %edx\n"
+	"wrmsr\n"
+	"movl	$MTRRphysMask_MSR(0), %ecx\n"
+	"movl	$(~(1024*1024 -1) | (1 << 11)), %eax\n"
+	"movl	$0x0000000f, %edx\n"	// 36bit address space
+	"wrmsr\n"
+
+	"movb	$0x39, %al\noutb %al, $0x80\n"
+
+	/* And Enable Cache again after setting MTRRs */
+	"movl	%cr0, %eax\n"
+	"andl    $~( (1 << 30) | (1 << 29) ), %eax\n"
+	"movl	%eax, %cr0\n"
+
+	"movb	$0x3a, %al\noutb %al, $0x80\n"
+
+	/* Enable MTRR */
+	"movl	$MTRRdefType_MSR, %ecx\n"
+	"rdmsr\n"
+	"orl	$(1 << 11), %eax\n"
+	"wrmsr\n"
+
+	"movb	$0x3b, %al\noutb %al, $0x80\n"
+
+	/* Invalidate the cache again */
+	"invd\n"
+	"movb	$0x3c, %al\noutb %al, $0x80\n"
+        );
Index: src/cpu/intel/model_6ex/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_6ex/cache_as_ram.inc	(revision 0)
+++ src/cpu/intel/model_6ex/cache_as_ram.inc	(revision 0)
@@ -0,0 +1,152 @@
+/* 
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define CACHE_AS_RAM_SIZE DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE DCACHE_RAM_BASE
+#define post_code(x) intel_chip_post_macro(x)
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/mtrr.h>
+
+	/* Save the BIST result */
+	movl    %eax, %ebp
+
+cache_as_ram:
+#if USE_FALLBACK_IMAGE == 1
+
+	post_code(0x20)
+
+	/* Send INIT IPI to all excluding ourself */
+        movl	$0x000C4500, %eax
+        movl	$0xFEE00300, %esi
+        movl	%eax, (%esi)
+
+	/* Zero out all Fixed Range and Variable Range MTRRs */
+	movl	$mtrr_table, %esi
+	movl	$( (mtrr_table_end - mtrr_table) / 2), %edi
+	xorl    %eax, %eax
+	xorl    %edx, %edx
+clear_mtrrs:
+	movw    (%esi), %bx
+	movzx   %bx, %ecx
+	wrmsr
+	add	$2, %esi
+	dec	%edi
+	jnz	clear_mtrrs
+
+	/* Configure the default memory type to uncacheable */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	andl	$(~0x00000cff), %eax
+	wrmsr
+
+	/* Set cache as ram base address */
+	movl	$(MTRRphysBase_MSR(0)), %ecx
+	movl	$(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
+	xorl	%edx, %edx
+	wrmsr
+
+	/* Set cache as ram mask */
+	movl	$(MTRRphysMask_MSR(0)), %ecx
+	movl	$(~((CACHE_AS_RAM_SIZE-1)) | (1 << 11)), %eax
+	movl	$0x0000000f, %edx
+	wrmsr
+
+	/* Enable MTRR */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$(1 << 11), %eax
+	wrmsr
+
+	/* Enable L2 Cache */
+	movl	$0x11e, %ecx
+	rdmsr
+	orl	$(1 << 8), %eax
+	wrmsr
+
+	/* CR0.CD = 0, CR0.NW = 0 */
+        movl	%cr0, %eax
+	andl	$( ~( (1 << 30) | (1 << 29) ) ), %eax
+	invd
+	movl	%eax, %cr0
+
+	/* Clear the cache memory reagion */
+	movl	$CACHE_AS_RAM_BASE, %esi
+	movl	%esi, %edi
+	movl	$(CACHE_AS_RAM_SIZE / 4), %ecx
+	//movl	$0x23322332, %eax
+	xorl	%eax, %eax
+	rep	stosl
+#endif
+
+	/* Enable Cache As RAM mode by disabling cache */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0
+
+#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
+	/* Enable cache for our code in Flash because we do XIP here */
+        movl    $MTRRphysBase_MSR(1), %ecx
+        xorl    %edx, %edx
+        movl    $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+        wrmsr
+
+        movl    $MTRRphysMask_MSR(1), %ecx
+        movl    $0x0000000f, %edx
+        movl    $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
+        wrmsr
+#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
+
+        /* enable cache */
+        movl	%cr0, %eax
+	andl	$( ~( (1 << 30) | (1 << 29) ) ), %eax
+        movl	%eax, %cr0
+
+	/* Set up stack pointer */
+	movl	$(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
+	movl	%eax, %esp
+
+	/* Restore the BIST result */
+	movl	%ebp, %eax
+	movl	%esp, %ebp
+	pushl	%eax
+
+	post_code(0x23)
+
+	call	stage1_main
+
+	post_code(0x2f)
+error:
+	hlt
+	jmp	error
+
+mtrr_table:
+	/* Fixed MTRRs */
+        .word 0x250, 0x258, 0x259
+        .word 0x268, 0x269, 0x26A
+        .word 0x26B, 0x26C, 0x26D
+        .word 0x26E, 0x26F
+	/* Variable MTRRs */
+        .word 0x200, 0x201, 0x202, 0x203
+        .word 0x204, 0x205, 0x206, 0x207
+        .word 0x208, 0x209, 0x20A, 0x20B
+        .word 0x20C, 0x20D, 0x20E, 0x20F
+mtrr_table_end:
+
Index: src/cpu/intel/model_6fx/Config.lb
===================================================================
--- src/cpu/intel/model_6fx/Config.lb	(revision 0)
+++ src/cpu/intel/model_6fx/Config.lb	(revision 0)
@@ -0,0 +1,13 @@
+uses HAVE_MOVNTI
+default HAVE_MOVNTI=1
+
+dir /cpu/x86/tsc
+dir /cpu/x86/mtrr
+dir /cpu/x86/fpu
+dir /cpu/x86/mmx
+dir /cpu/x86/sse
+dir /cpu/x86/lapic
+dir /cpu/x86/cache
+dir /cpu/intel/microcode
+dir /cpu/intel/hyperthreading
+driver model_6fx_init.o
Index: src/cpu/intel/model_6fx/model_6fx_init.c
===================================================================
--- src/cpu/intel/model_6fx/model_6fx_init.c	(revision 0)
+++ src/cpu/intel/model_6fx/model_6fx_init.c	(revision 0)
@@ -0,0 +1,94 @@
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/hyperthreading.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+
+static const uint32_t microcode_updates[] = {
+	// #include "microcode_m206e839.h"
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+static inline void strcpy(char *dst, char *src) 
+{
+	while (*src) *dst++ = *src++;
+}
+
+static void fill_processor_name(char *processor_name)
+{
+	struct cpuid_result regs;
+	char temp_processor_name[49];
+	char *processor_name_start;
+	unsigned int *name_as_ints = (unsigned int *)temp_processor_name;
+	int i;
+
+	for (i=0; i<3; i++) {
+		regs = cpuid(0x80000002 + i);
+		name_as_ints[i*4 + 0] = regs.eax;
+		name_as_ints[i*4 + 1] = regs.ebx;
+		name_as_ints[i*4 + 2] = regs.ecx;
+		name_as_ints[i*4 + 3] = regs.edx;
+	}
+
+	temp_processor_name[48] = 0;
+
+	/* Skip leading spaces */
+	processor_name_start = temp_processor_name;
+	while (*processor_name_start == ' ') 
+		processor_name_start++;
+
+	memset(processor_name, 0, 49);
+	strcpy(processor_name, processor_name_start);
+}
+
+static void model_6ex_init(device_t cpu)
+{
+	char processor_name[49];
+
+	/* Turn on caching if we haven't already */
+	x86_enable_cache();
+
+	/* Update the microcode */
+	intel_update_microcode(microcode_updates);
+
+	/* Print processor name */
+	fill_processor_name(processor_name);
+	printk_info("CPU: %s.\n", processor_name);
+
+	/* Setup MTRRs */
+	x86_setup_mtrrs(36);
+	x86_mtrr_check();
+	
+	/* Enable the local cpu apics */
+	setup_lapic();
+
+	/* Start up my cpu siblings */
+	intel_sibling_init(cpu);
+}
+
+static struct device_operations cpu_dev_ops = {
+	.init     = model_6ex_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x06f0 }, /* Intel Core 2 Solo/Core Duo */
+	{ X86_VENDOR_INTEL, 0x06f6 }, /* Intel Core 2 Solo/Core Duo */
+	{ 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+};
+
Index: src/cpu/intel/model_6fx/cache_as_ram_disable.c
===================================================================
--- src/cpu/intel/model_6fx/cache_as_ram_disable.c	(revision 0)
+++ src/cpu/intel/model_6fx/cache_as_ram_disable.c	(revision 0)
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "cpu/x86/car/copy_and_run.c"
+
+void real_main(unsigned long bist);
+
+void stage1_main(unsigned long bist)
+{
+	unsigned int cpu_reset = 0;
+
+#if USE_FALLBACK_IMAGE == 1
+        /* Is this a deliberate reset by the bios */
+        if (bios_reset_detected() && last_boot_normal()) {
+                goto normal_image;
+        } else {
+        	/* This is the primary cpu how should I boot? */
+		check_cmos_failed();
+		if (do_normal_boot()) {
+        	        goto normal_image;
+	        }
+        	else {
+	                goto fallback_image;
+        	}
+	}
+ normal_image:
+        __asm__ volatile ("jmp __normal_image"
+                : /* outputs */
+                : "a" (bist) /* inputs */
+                );
+ fallback_image:
+#endif
+
+	real_main(bist);
+
+	/* No servicable parts below this line .. */
+
+        {
+        	/* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
+	        unsigned v_esp;
+	        __asm__ volatile (
+        	        "movl   %%esp, %0\n\t"
+	                : "=a" (v_esp)
+	        );
+	        printk_spew("v_esp=%08x\r\n", v_esp);
+        }
+
+cpu_reset_x:
+
+        printk_spew("cpu_reset = %08x\r\n",cpu_reset);
+
+	if(cpu_reset == 0) {
+	        print_spew("Clearing initial memory region: ");
+	}
+	print_spew("No cache as ram now - ");
+
+	/* store cpu_reset to ebx */
+        __asm__ volatile (
+                "movl %0, %%ebx\n\t"
+                ::"a" (cpu_reset)
+        );
+
+	if(cpu_reset==0) {
+#define CLEAR_FIRST_1M_RAM 1
+#include "cache_as_ram_post.c"
+	} else {
+#undef CLEAR_FIRST_1M_RAM 
+#include "cache_as_ram_post.c"
+	}
+
+	__asm__ volatile (
+                /* set new esp */ /* before _RAMBASE */
+                "subl   %0, %%ebp\n\t"
+                "subl   %0, %%esp\n\t"
+                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
+	);
+
+	{
+		unsigned new_cpu_reset;
+
+		/* get back cpu_reset from ebx */
+		__asm__ volatile (
+			"movl %%ebx, %0\n\t"
+			:"=a" (new_cpu_reset)
+		);
+
+		/* Copy and execute coreboot_ram */
+		copy_and_run(new_cpu_reset);
+		/* We will not return */
+	}
+
+	print_debug("sorry. parachute did not open.\r\n");
+}
Index: src/cpu/intel/model_6fx/cache_as_ram_post.c
===================================================================
--- src/cpu/intel/model_6fx/cache_as_ram_post.c	(revision 0)
+++ src/cpu/intel/model_6fx/cache_as_ram_post.c	(revision 0)
@@ -0,0 +1,132 @@
+/*
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+        __asm__ volatile (
+
+	"movb	$0x30, %al\noutb %al, $0x80\n"
+
+	/* Disable Cache */
+	"movl	%cr0, %eax\n"
+	"orl    $(1 << 30), %eax\n"
+	"movl	%eax, %cr0\n"
+
+	"movb	$0x31, %al\noutb %al, $0x80\n"
+
+	/* Disable MTRR */
+	"movl	$MTRRdefType_MSR, %ecx\n"
+	"rdmsr\n"
+	"andl	$(~(1 << 11)), %eax\n"
+	"wrmsr\n"
+
+	"movb	$0x32, %al\noutb %al, $0x80\n"
+
+	"invd\n"
+#if 0
+	"xorl	%eax, %eax\n"
+	"xorl	%edx, %edx\n"
+	"movl	$MTRRphysBase_MSR(0), %ecx\n"
+	"wrmsr\n"
+	"movl	$MTRRphysMask_MSR(0), %ecx\n"
+	"wrmsr\n"
+	"movl	$MTRRphysBase_MSR(1), %ecx\n"
+	"wrmsr\n"
+	"movl	$MTRRphysMask_MSR(1), %ecx\n"
+	"wrmsr\n"
+#endif
+
+	"movb	$0x33, %al\noutb %al, $0x80\n"
+#ifdef CLEAR_FIRST_1M_RAM
+	"movb	$0x34, %al\noutb %al, $0x80\n"
+	/* Enable Write Combining and Speculative Reads for the first 1MB */
+	"movl	$MTRRphysBase_MSR(0), %ecx\n"
+	"movl	$(0x00000000 | MTRR_TYPE_WRCOMB), %eax\n"
+	"xorl	%edx, %edx\n"
+	"wrmsr\n"
+	"movl	$MTRRphysMask_MSR(0), %ecx\n"
+	"movl	$(~(1024*1024 -1) | (1 << 11)), %eax\n"
+	"movl	$0x0000000f, %edx\n"	// 36bit address space
+	"wrmsr\n"
+	"movb	$0x35, %al\noutb %al, $0x80\n"
+#endif
+
+	/* Enable Cache */
+	"movl	%cr0, %eax\n"
+	"andl    $~( (1 << 30) | (1 << 29) ), %eax\n"
+	"movl	%eax, %cr0\n"
+
+	"movb	$0x36, %al\noutb %al, $0x80\n"
+#ifdef CLEAR_FIRST_1M_RAM
+
+	/* Clear first 1MB of RAM */
+	"movl	$0x00000000, %edi\n"
+	"cld\n"
+	"xorl	%eax, %eax\n"
+	"movl	$((1024*1024) / 4), %ecx\n"
+	"rep stosl\n"
+	
+	"movb	$0x37, %al\noutb %al, $0x80\n"
+#endif
+
+	/* Disable Cache */
+	"movl	%cr0, %eax\n"
+	"orl    $(1 << 30), %eax\n"
+	"movl	%eax, %cr0\n"
+
+	"movb	$0x38, %al\noutb %al, $0x80\n"
+
+	/* Enable Write Back and Speculative Reads for the first 1MB */
+	"movl	$MTRRphysBase_MSR(0), %ecx\n"
+	"movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax\n"
+	"xorl	%edx, %edx\n"
+	"wrmsr\n"
+	"movl	$MTRRphysMask_MSR(0), %ecx\n"
+	"movl	$(~(1024*1024 -1) | (1 << 11)), %eax\n"
+	"movl	$0x0000000f, %edx	// 36bit address space\n"
+	"wrmsr\n"
+
+	"movb	$0x39, %al\noutb %al, $0x80\n"
+
+	/* And Enable Cache again after setting MTRRs */
+	"movl	%cr0, %eax\n"
+	"andl    $~( (1 << 30) | (1 << 29) ), %eax\n"
+	"movl	%eax, %cr0\n"
+
+	"movb	$0x3a, %al\noutb %al, $0x80\n"
+
+	/* Enable MTRR */
+	"movl	$MTRRdefType_MSR, %ecx\n"
+	"rdmsr\n"
+	"orl	$(1 << 11), %eax\n"
+	"wrmsr\n"
+
+	"movb	$0x3b, %al\noutb %al, $0x80\n"
+
+	/* Enable prefetchers */
+	"movl	$0x01a0, %eax\n"
+	"rdmsr\n"
+	"andl	$~((1 << 9) | (1 << 19)), %eax\n"
+	"andl	$~((1 << 5) | (1 << 7)), %edx\n"
+	"wrmsr\n"
+
+	/* Invalidate the cache again */
+	"invd\n"
+	"movb	$0x3c, %al\noutb %al, $0x80\n"
+        );
Index: src/cpu/intel/model_6fx/cache_as_ram.inc
===================================================================
--- src/cpu/intel/model_6fx/cache_as_ram.inc	(revision 0)
+++ src/cpu/intel/model_6fx/cache_as_ram.inc	(revision 0)
@@ -0,0 +1,159 @@
+/* 
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#define CACHE_AS_RAM_SIZE DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE DCACHE_RAM_BASE
+#define post_code(x) intel_chip_post_macro(x)
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/amd/mtrr.h>
+
+	/* Save the BIST result */
+	movl    %eax, %ebp
+
+cache_as_ram:
+#if USE_FALLBACK_IMAGE == 1
+
+	post_code(0x20)
+
+	/* Send INIT IPI to all excluding ourself */
+        movl	$0x000C4500, %eax
+        movl	$0xFEE00300, %esi
+        movl	%eax, (%esi)
+
+	/* Disable prefetchers */
+	movl	$0x01a0, %eax
+	rdmsr
+	orl	$((1 << 9) | (1 << 19)), %eax
+	orl	$((1 << 5) | (1 << 7)), %edx
+	wrmsr
+
+	/* Zero out all Fixed Range and Variable Range MTRRs */
+	movl	$mtrr_table, %esi
+	movl	$( (mtrr_table_end - mtrr_table) / 2), %edi
+	xorl    %eax, %eax
+	xorl    %edx, %edx
+clear_mtrrs:
+	movw    (%esi), %bx
+	movzx   %bx, %ecx
+	wrmsr
+	add	$2, %esi
+	dec	%edi
+	jnz	clear_mtrrs
+
+	/* Configure the default memory type to uncacheable */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	andl	$(~0x00000cff), %eax
+	wrmsr
+
+	/* Set cache as ram base address */
+	movl	$(MTRRphysBase_MSR(0)), %ecx
+	movl	$(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
+	xorl	%edx, %edx
+	wrmsr
+
+	/* Set cache as ram mask */
+	movl	$(MTRRphysMask_MSR(0)), %ecx
+	movl	$(~((CACHE_AS_RAM_SIZE-1)) | (1 << 11)), %eax
+	movl	$0x0000000f, %edx
+	wrmsr
+
+	/* Enable MTRR */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$(1 << 11), %eax
+	wrmsr
+
+	/* Enable L2 Cache */
+	movl	$0x11e, %ecx
+	rdmsr
+	orl	$(1 << 8), %eax
+	wrmsr
+
+	/* CR0.CD = 0, CR0.NW = 0 */
+        movl	%cr0, %eax
+	andl	$( ~( (1 << 30) | (1 << 29) ) ), %eax
+	invd
+	movl	%eax, %cr0
+
+	/* Clear the cache memory reagion */
+	movl	$CACHE_AS_RAM_BASE, %esi
+	movl	%esi, %edi
+	movl	$(CACHE_AS_RAM_SIZE / 4), %ecx
+	//movl	$0x23322332, %eax
+	xorl	%eax, %eax
+	rep	stosl
+#endif
+
+	/* Enable Cache As RAM mode by disabling cache */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0
+
+#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
+	/* Enable cache for our code in Flash because we do XIP here */
+        movl    $MTRRphysBase_MSR(1), %ecx
+        xorl    %edx, %edx
+        movl    $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+        wrmsr
+
+        movl    $MTRRphysMask_MSR(1), %ecx
+        movl    $0x0000000f, %edx
+        movl    $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
+        wrmsr
+#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
+
+        /* enable cache */
+        movl	%cr0, %eax
+	andl	$( ~( (1 << 30) | (1 << 29) ) ), %eax
+        movl	%eax, %cr0
+
+	/* Set up stack pointer */
+	movl	$(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
+	movl	%eax, %esp
+
+	/* Restore the BIST result */
+	movl	%ebp, %eax
+	movl	%esp, %ebp
+	pushl	%eax
+
+	post_code(0x23)
+
+	call	stage1_main
+
+	post_code(0x2f)
+error:
+	hlt
+	jmp	error
+
+mtrr_table:
+	/* Fixed MTRRs */
+        .word 0x250, 0x258, 0x259
+        .word 0x268, 0x269, 0x26A
+        .word 0x26B, 0x26C, 0x26D
+        .word 0x26E, 0x26F
+	/* Variable MTRRs */
+        .word 0x200, 0x201, 0x202, 0x203
+        .word 0x204, 0x205, 0x206, 0x207
+        .word 0x208, 0x209, 0x20A, 0x20B
+        .word 0x20C, 0x20D, 0x20E, 0x20F
+mtrr_table_end:
+
Index: src/cpu/intel/socket_mPGA478/socket_mPGA478.c
===================================================================
--- src/cpu/intel/socket_mPGA478/socket_mPGA478.c	(revision 0)
+++ src/cpu/intel/socket_mPGA478/socket_mPGA478.c	(revision 0)
@@ -0,0 +1,7 @@
+#include <device/device.h>
+#include "chip.h"
+
+
+struct chip_operations cpu_intel_socket_mPGA478_ops = {
+	CHIP_NAME("Socket mPGA478 CPU")
+};
Index: src/cpu/intel/socket_mPGA478/Config.lb
===================================================================
--- src/cpu/intel/socket_mPGA478/Config.lb	(revision 0)
+++ src/cpu/intel/socket_mPGA478/Config.lb	(revision 0)
@@ -0,0 +1,4 @@
+config chip.h
+object socket_mPGA478.o
+dir /cpu/intel/model_69x
+dir /cpu/intel/model_6dx
Index: src/cpu/intel/socket_mPGA478/chip.h
===================================================================
--- src/cpu/intel/socket_mPGA478/chip.h	(revision 0)
+++ src/cpu/intel/socket_mPGA478/chip.h	(revision 0)
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_socket_mPGA478_ops;
+
+struct cpu_intel_socket_mPGA478_config {
+};
Index: src/cpu/intel/socket_mFCPGA478/Config.lb
===================================================================
--- src/cpu/intel/socket_mFCPGA478/Config.lb	(revision 3698)
+++ src/cpu/intel/socket_mFCPGA478/Config.lb	(working copy)
@@ -2,3 +2,5 @@
 object socket_mFCPGA478.o
 dir /cpu/intel/model_69x
 dir /cpu/intel/model_6dx
+dir /cpu/intel/model_6ex
+dir /cpu/intel/model_6fx
