Quoting Peter Stuge peter@stuge.se:
On Mon, Feb 25, 2008 at 04:31:15PM -0500, joe@smittys.pointclark.net wrote: ..
tv-out
Dis-reguard the last patch, this is the real one. A e100 kernel driver developer helped me figure out that the ethernet was an irq routing issue, fixed! It is working great now:-)))
Good news!
Yeh, over a year on this baby......
Do you have any idea about the TV out?
Yes ..ideas. I have several others that are going to work on the tv-out with me, that's why I would like to get the source posted.
Also see the comments below:
+++ src/northbridge/intel/i82830/raminit.c (revision 0)
..
+static void set_dram_timing(const struct mem_controller *ctrl) +{
- /* Set the value for DRAM Timing Register */
- /* TODO: Configure the value according to SPD values. */
- pci_write_config32(ctrl->d0, DRT, 0x00000010);
+}
+static void set_dram_buffer_strength(const struct mem_controller *ctrl) +{
- /* TODO: This needs to be set according to the DRAM tech
* (x8, x16, or x32). Argh, Intel provides no docs on this!* Currently, it needs to be pulled from the output of* lspci -xxx Rx92- */
- /* Set the value for System Memory Buffer Strength Control Registers */
- pci_write_config32(ctrl->d0, BUFF_SC, 0xFC9B491B);
+}
How about these two TODOs? In the second case I think the comment refers to running the command under the factory BIOS - in that case it would be good to clarify that.
TODO #1 - The onboard memory has CAS 3 so this is manually set for now. TODO #2 - That came from Corey's i810 code. And he is right, I couldn't find any docs on this so it just got set manually.
+static void sdram_enable(int controllers, const struct mem_controller *ctrl) +{
..
- /* 4. Mode register set. Wait two memory cycles. */
- /* TODO: Set offset according to DRT values */
- PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
- do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0);
Can this be done?
Sure it can. The addr_offset (0x1d0) is based on the memory's CAS# Latency. The onboard memory has CAS 3 so this is manually set for now. I think some of the other Intel chips already have this setup, but they are a little different than this one.
+++ targets/rca/rm4100/Config.lb (revision 0)
..
+romimage "fallback"
- option USE_FALLBACK_IMAGE = 1
- option FALLBACK_SIZE = ROM_SIZE
- option COREBOOT_EXTRA_VERSION = "_RM4100"
+# payload /etc/hosts
This last line makes no sense so I would remove it before the commit.
Sure.
//Peter
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Thanks - Joe