Hi Angel,
I hope you're doing fine!
Thanks for your answer!
Ouch, hum, okay, understood... So RAM init is more easy on already supported hardware? What would be the effort to reach at least serialICE?
Thanks in advance, Have a nice day, Best Regards, Mickaël.
________________________________________ De : Angel Pons th3fanbus@gmail.com Envoyé : mercredi 24 novembre 2021 00:50 À : Master Cc : coreboot@coreboot.org Objet : Re: [coreboot] Personal challenge | Ramp up on coreboot : Trials on aftermarket X58 motherboards.
Hi Mickaël,
On Tue, Nov 23, 2021 at 11:29 AM Master mastermkl@hotmail.fr wrote:
Hello everyone,
I hope you're doing fine
I would like to do some trials to see if I may be able to support few boards I have cause they are aftermarket withoout EFI and without firmware updates and not working as I would like them to. (https://askubuntu.com/questions/1370496/cant-boot-latests-lives-for-install-...) I really would not like to throw them...
They are X58 chipset with ICH10 with Xeon Westmere on socket 1366 and SuperIO NCT5532D. (https://www.intel.com/content/dam/doc/datasheet/x58-express-chipset-datashee...) (https://www.intel.com/content/dam/doc/datasheet/io-controller-hub-10-family-...) (https://datasheetspdf.com/pdf-file/1042365/novoTon/NCT5532D/1)
Only the ICH10 southbridge (southbridge/intel/i82801jx) is currently supported. Neither the CPU nor the X58 IOH are supported. Most of the complexity is RAM initialization, especially because Intel does not publicly document the relevant registers. It would likely take years for an experienced developer to implement RAM init in coreboot.
The NCT5532D Super I/O isn't supported either, but it's easy to add support for it using the datasheet.
I have the tooling to backup and restore the flash and already done that few time. I have built latest coreboot (4.14 using lenovo x201 config) with EDK2 firmware as payload (edk2-stable202108 NOOPT) successfully but nothing is happening after flash swap and power on.
Flashing a firmware image for a different board is a bad idea. In extreme cases, incompatible GPIO configuration can result in short-circuits. It's unlikely, though.
I have RS232 debug working at ttyS0 (at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A) From the original firmware, just after power on, even before any bip or display or keyboard light I see "Socket = 0" on serial, so the the original firmware is able to output to this serial very early.
I read quite a lot of literature about coreboot, but still, I am not sure how to pursue now.
It's hard. I can give you general ideas on how to proceed (I'm pretty sure we can get coreboot to print something over RS232), but RAM init is still a major roadblock. Once serial output is working, it's possible to use SerialICE to gather useful information to reimplement RAM init.
Thanks in advance, Have a nice day, Best Regards, Mickaël. _______________________________________________ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-leave@coreboot.org
Best regards, Angel