============= PEIM FSP v1.0 (_BDX-DE_ v0.0.3.3) ============= Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000FFEB1000, size is 0x0011F000, handle is 0x0 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389 Loading PEIM at 0x000FFEBA990 EntryPoint=0x000FFEBAA60 PcdPeim.efi Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480 Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1 Loading PEIM at 0x000FFEBEB00 EntryPoint=0x000FFEBEBD0 SetupDefault.efi Install PPI: 57B195D1-E14B-40AD-A68F-9806000C436A Loading PEIM at 0x000FFEC1F14 EntryPoint=0x000FFEC1FEC PlatformInfo.efi enable all DMI VCx :: CPU Type Socket ModelId# 56 :: CPU stepping # 3 Install PPI: 1E2ACC41-E26A-483D-AFC7-A056C34E087B Publish PlatformInfoPPI Loading PEIM at 0x000FFEC49D4 EntryPoint=0x000FFEC4AA4 MePolicyInitPei.efi Install PPI: 7AE3CEB7-2EE2-48FA-AA49-3510BC83CABF ME PEI Platform Policy PPI Installed Loading PEIM at 0x000FFEC6BCC EntryPoint=0x000FFEC6C94 HeciInit.efi Force an S5 exit path. Install PPI: E5EE2066-FAA1-4DFA-924E-B1E3A8EE30E8 Install PPI: EE0EA811-FBD9-4777-B95A-BA4F71101F74 Loading PEIM at 0x000FFECA1D4 EntryPoint=0x000FFECA29C MeUma.efi Install PPI: 8C376010-2400-4D7D-B47B-9D851DF3C9D1 ME UMA: ME UMA PPI Installed Loading PEIM at 0x000FFECD774 EntryPoint=0x000FFECD844 SpsPei.efi [SPS] Waiting for ME firmware init complete [HECI-0] VID-DID: 8086-8C3A [HECI-0] MBAR not programmed, using default 0x00000000FEDB0000 [SPS] Sending ME-BIOS Interface Version request [HECI-0] Send msg: 80010020 [HECI-0] Got msg: 80050020 [SPS] SPS ME-BIOS interface version is 1.0 Feature set is 0x2106 [SPS] HOB: features 0x2106, flow 1, boot mode 0, cores to disable 0 Loading PEIM at 0x000FFED0FFC EntryPoint=0x000FFED10DC UncoreInitPeim.efi OVERRIDING TOTAL SYSTEM CONFIGURATION WITH UPD upd->MemDdr4Platform = 0x0 tsc->DDR4Platform = 0x2 Halting the TCO Timer (Watchdog) Running on hardware Revision: 0 BIOSSIM: InitHeap() BIOSSIM: InitUSBDebug() BDX (1HA) processor detected CPU Stepping 3 Found CCMRC Version: 00500000 MRC Sync Number: 244071 RC Version: 02040000 host = FE191768 (pointer to sysHost structure) Legacy Serial Debug Enabled QPI Init starting... ******* QPI Setup Structure ******* PPINrOptIn: 0 Bus Ratio: 1 1 1 1 IO Ratio: 1 1 1 1 MMIOL Ratio: 1 1 1 1 LegacyVgaSoc: 0 MmioP2pDis: 0 IsocAzaliaVc1En: 0 DebugPrintLevel: 15 ClusterOnDieEn: 0 IBPECIEn: 1 E2EParityEn: 0 EarlySnoopEn: 1 HomeDirWOSBEn: 1 DegradePrecedence: 0 QpiLinkSpeedMode: 1 (FAST) QpiLinkSpeed: 6 QpiLinkL0pEn: 1 QpiLinkL1En: 1 QpiLinkL0rEn: 1 QpiLbEn: 0 IioUniphyDisable (per socket): 0 0 0 0 QpiLinkCreditReduce: 2 QpiConfigTxWci: 11 QpiCrcMode: 0 QpiCpuSktHotPlugEn: 0 QpiCpuSktHotPlugTopology: 0 QpiSkuMismatchCheck: 1 QpiPortDisable (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiLinkCreditReduce (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiLinkSpeed (per port): S0:6 6 S1:6 6 S2:6 6 S3:6 6 QpiProbeType (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiConfigTxWci (per port): S0:11 11 S1:11 11 S2:11 11 S3:11 11 Rsvd (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 ******* Common Setup Structure ******* mmCfgBase: 0x80000000 mmCfgSize: 0x10000000 mmiolBase: 0x90000000 mmiolSize: 0x6C000000 mmiohBase: 0x00003800-00000000 mmiohSize: 256 GB numaEn: 1 isocEn: 0 mesegEn: 0 dcaEn: 1 ******* Common Var Structure ******* resetRequired: 0 state: 0 numCpus: 0 socketPresentBitMap: 0x01 busIio: 0x00 0x00 0x00 0x00 busUncore: 0x3F 0x00 0x00 0x00 mmCfgBase: 0x80000000 ;******* Collecting Early System Information - START *******Checkpoint Code: Socket 0, 0xA1, 0x00, 0x1FFF CAPID0[5] is set. SKU Detected as DE. SocketId: 0 Physical Chop: 3 SocketId: 0 CAPID5: 0x06000965 SocketId: 0 CAPID4: 0x24080D03 SocketId: 0 CAPID3: 0x00930A20 SocketId: 0 CAPID2: 0x53B40000 SocketId: 0 CAPID1: 0x8C001787 SocketId: 0 CAPID0: 0x00188520 ; SBSP Socket: 0 SKU: 0x05 SubSKU: 0x00 Stepping: 0x03 CAPID4[sbsp]: 0x24080D03 ; Total Cbos: 06 Cbo List: 0x965 Total HA: 01 Total R3Qpi: 00 Total QpiAgent: 00 ; TotCpus: 4 CpuList: 0x0F ; busIio: 0x00 0x40 0x80 0xC0 ; busUncore: 0x3F 0x7F 0xBF 0xFF ; Reset Type: Cold Reset Link Speed: Slow Speed ;******* Collecting Early System Information - END ******* ;******* Setting up Minimum Path - START *******Checkpoint Code: Socket 0, 0xA3, 0x01, 0x0000 ; Constructing SBSP minimum path Topology Tree ; -------------------------------------------- ; Adding SBSP (CPU0) to the treeCheckpoint Code: Socket 0, 0xA3, 0x02, 0x0020 CPU0 Link Exchange UseQpiPcSts = 1 ;SBSP Minimum Path Tree ;---------------------- ;Index Socket ParentPort Hop ParentIndex ; 00 CPU0 -- 0 -- ;******* Setting up Minimum Path - END ******* ;******* Initialize MCTP - START ******* ;******* Initialize MCTP - END ******* ;******* Check for QPI Topology Degradation - START *******Checkpoint Code: Socket 0, 0xA7, 0x01, 0x1FFF ;Link Exchange Parameter ;----------------------- ;CPU0 ; Already Reduced to Supported Topology ; System will be treated 1S Configuration ;******* Check for QPI Topology Degradation - END ******* ;******* Checking QPIRC Input Structure - START ******* ; Sys configuration Type = 16 ;******* Checking QPIRC Input Structure - END ******* ;******* Allocate RTIDs - START ******* ; WB - 02 Ubox - 00 Isoc - 00 Local RTID PerCbo - 16 Extra - 30 ; Local Base - 01 Reallocation Base - 65 ; Cbo 03 RTID straddles into xRTID space ; RTIDs split into three pools of size 8, 7 and 1 ; Sufficient extra RTIDs are available to move the Second Pool into xRTID space. No loss of RTIDs for the CBo. ; RTID Allocation Table ; --------------------- ; Local ; ----- ; WB 0 1 ; UBOX 0 0 ; ISOC 1 0 ; CBO00 1 8 ; CBO00 9 8 ; CBO01 17 8 ; CBO01 25 8 ; CBO02 33 8 ; CBO02 41 8 ; CBO03 49 8 ; CBO03 65 8 ; CBO04 73 8 ; CBO04 81 8 ; CBO05 89 8 ; CBO05 97 8 ; EXTRA 0 23 ;******* Allocate RTIDs - END ******* ;******* Cacluate Resource Allocation - START *******Checkpoint Code: Socket 0, 0xA9, 0x01, 0x1FFF ;CPU Resource Allocation ;----------------------- ;CPU0 Bus: 0x00 - 0xFF IO: 0x0000 - 0xFFFF IOAPIC: 0xFEC00000 - 0xFEC3FFFF MMIOL: 0x90000000 - 0xFBFFFFFF MMIOH: 0x00003800 00000000 - 0x0000383F FFFFFFFF ;******* Cacluate Resource Allocation - END ******* ;******* Programming RTIDs and other Credits - START *******Checkpoint Code: Socket 0, 0xAA, 0x01, 0x1FFF Checkpoint Code: Socket 0, 0xAA, 0x02, 0x1FFF ;******* Programming RTIDs and other Credits - END ******* ;******* Sync Up PBSPs - START ******* ; Setting Ubox Sticky SR07 to 0x00000000 ; Setting Ubox Sticky SR03 to 0x20000007 ; Setting Ubox Sticky SR02 to 0x00000001 ; Verifying if the remote socket(s) checked-in. ;******* Sync Up PBSPs - END ******* ;******* Programming MSR for w/a - START ******* ;******* Programming MSR for w/a - END ******* ;******* Programming BGF Overrides - START ******* ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x0 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x7D ; Wait for mailbox ready ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x11 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x17D ; Wait for mailbox ready ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x0 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x27D ; Wait for mailbox ready ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x0 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x37D ; Wait for mailbox ready ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x0 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x47D ; Wait for mailbox ready ;******* Programming BGF Overrides - END ******* ;******* Full Speed Transition - START *******Checkpoint Code: Socket 0, 0xAB, 0x00, 0x1FFF ; ;Single Socket, no QPI Links to transition ; Force unused links to disabled/low power state. ; Clr PhyInitBegin on Socket 0 Link 0 : QPIREUT_PH_CTR write 0xFFFFFFDF Set force_l1 on Socket 0 Link 0 : QPIPHYPWRCTRL write 0xFFFFFFFF ; Clr PhyInitBegin on Socket 0 Link 1 : QPIREUT_PH_CTR write 0xFFFFFFDF Set force_l1 on Socket 0 Link 1 : QPIPHYPWRCTRL write 0xFFFFFFFF ;******* Full Speed Transition - END ******* ;******* Cod Activate - START ******* ;******* Cod Activate - END ******* ******* QPI Output Structure ******* OutLegacyVgaSoc: 0 OutIsocEn: 0 OutMesegEn: 0 OutIsocAzaliaVc1En: 0 OutClusterOnDieEn: 0 OutIBPECIEn: 1 OutE2EParityEn: 0 OutEarlySnoopEn: 1 OutHomeDirWOSBEn: 0 QpiCurrentLinkSpeedMode: 0 (SLOW) OutQpiLinkSpeed: 6 OutQpiLinkL0pEn: 1 OutQpiLinkL1En: 1 OutQpiLinkL0rEn: 1 OutIioUniphyDisable: 0, 0, 0, 0 OutQpiCrcMode: 0 OutClusterOnDieReduction: 0 OutPointerSeperationHA: 0 QpiInternalGlobal->BtModeEn: 0 QpiInternalGlobal->BtMode: 0 QpiInternalGlobal->BtMode2Alt: 0 QpiInternalGlobal->Sys4SClusterOnDieEn: 0 QpiInternalGlobal->SnoopFanoutEn: 0 QpiInternalGlobal->SysSnoopMode: 0 QpiInternalGlobal->IodcEn: 0Checkpoint Code: Socket 0, 0xAF, 0x00, 0x1FFF ;******* QPIRC Exit ******* QPI Init completed! Reset Requested: 2 Pipe Init starting...Pipe Init completed! Reset Requested: 2 CPU Feature Early Config starting... CAPID0[5] is set. SKU Detected as DE.CPU Feature Early Config completed! Reset Requested: 2 START_MRC_RUN ME UMA: ME UMA Size Requested: 0 ME UMA size = 0 MBytes sizeof sysHost = 449216 sizeof BDAT = 168490 sizeof memSetup = 1463 sizeof memNvram = 136303 sizeof socketNvram = 33684 sizeof memVar = 135017 sizeof Socket = 30969 sizeof ddrChannel = 7434 sizeof dimmDevice = 946 sizeof SADTable = 20 sizeof TADTable = 23 MAX_SOCKET = 4 sizeof sysHostSetup = 1696 struct sysHost.common { options: 00000007 PROMOTE_WARN_EN 1 HALT_ON_ERROR_EN 1 serialDebugMsgLvl:03 bsdBreakpoint: 00 maxAddrMem: 40000 debugPort: 80 nvramPtr: 00000000 sysHostBufferPtr:00000000 mmCfgBase: 80000000 mmCfgSize: 10000000 pchumaEn: 00 numaEn: 01 logParsing: 00 bdatEn: 00 consoleComPort: 3F8 struct sysHost.setup.mem { options: 10124FC8 TEMPHIGH_EN 0 PDWN_SR_CKE_MODE 0 OPP_SELF_REF_EN 1 MDLL_SHUT_DOWN_EN 0 PAGE_POLICY 0 MULTI_THREAD_MRC_EN 1 ADAPTIVE_PAGE_EN 1 SCRAMBLE_EN 1 MEM_FLOWS - X_OVER_EN 1 MEM_FLOWS - SENSE_AMP_EN 1 MEM_FLOWS - E_CMDCLK_EN 1 MEM_FLOWS - REC_EN_EN 1 MEM_FLOWS - RD_DQS_EN 1 MEM_FLOWS - WR_LVL_EN 1 MEM_FLOWS - WR_FLYBY_EN 1 MEM_FLOWS - WR_DQ_EN 1 MEM_FLOWS - CMDCLK_EN 1 MEM_FLOWS - RD_ADV_EN 1 MEM_FLOWS - WR_ADV_EN 1 MEM_FLOWS - RD_VREF_EN 1 MEM_FLOWS - WR_VREF_EN 1 MEM_FLOWS - RT_OPT_EN 1 MEM_FLOWS - RX_DESKEW_EN 1 MEM_FLOWS - TX_DESKEW_EN 1 MEM_FLOWS - TX_EQ_EN 1 MEM_FLOWS - IMODE_EN 1 MEM_FLOWS - EARLY_RID_EN 1 MEM_FLOWS - DQ_SWIZ_EN 1 MEM_FLOWS - LRBUF_RD_EN 1 MEM_FLOWS - LRBUF_WR_EN 1 MEM_FLOWS - RANK_MARGIN_EN 1 MEM_FLOWS - MEMINIT_EN 1 MEM_FLOWS - FNVSIMICSSIM_EN 1 MEM_FLOWS - MEMTEST_EN 1 MEM_FLOWS - NORMAL_MODE_EN 1 MEM_FLOWS - E_CTLCLK_EN 1 MEM_FLOWS_EXT - RX_CTLE_EN 1 MEM_FLOWS_EXT - PXC_EN 1 DDR_RESET_LOOP 0 NUMA_AWARE 1 DISABLE_WMM_OPP_READ 0 ECC_CHECK_EN 1 ECC_MIX_EN 0 BALANCED_4WAY_EN 0 CA_PARITY_EN 1 SPLIT_BELOW_4GB_EN 0 MARGIN_RANKS_EN 0 MEM_OVERRIDE_EN 0 DRAMDLL_OFF_PD_EN 0 MEMORY_TEST_EN 1 MEMORY_TEST_FAST_BOOT_EN 0 ATTEMPT_FAST_BOOT 0 ATTEMPT_FAST_BOOT_COLD 0 SW_MEMORY_TEST_EN 0 RMT_COLD_FAST_BOOT 0 DISPLAY_EYE_EN 0 PER_NIBBLE_EYE_EN 0 optionsExt: 1E41677F RD_VREF_EN 1 WR_VREF_EN 1 PDA_EN 1 TURNAROUND_OPT_EN 1 PER_BIT_MARGINS 1 RASmodeEx: 16 DMNDSCRB_EN 1 PTRLSCRB_EN 1 A7_MODE_EN 1 DEVTAGGING_EN 0 struct sysHost.setup.mem { bclk: 00 enforcePOR: 00 ddrFreqLimit: 00 chInter: 04 dimmTypeSupport: 02 vrefStepSize: 00 vrefAbsMaxSteps: 00 vrefOpLimitSteps:00 pdwnCkMode: 04 MemPwrSave: 05 pprType: 00 pprErrInjTest 00 ckeThrottling: 01 olttPeakBWLIMITPercent: 00 thermalThrottlingOptions: 0A CLTT_EN 1 OLTT_EN 0 MH_OUTPUT_EN 0 MH_SENSE_EN 1 DimmTempStatValue 00 dramraplen: 02 dramraplbwlimittf: 01 lrdimmModuleDelay: 00 customRefreshRate: 00 rxVrefTraining: 00 iotMemBufferRsvtn: 00 enforceThreeMonthTimeout: 01 rmtPatternLength:7FFF rmtPatternLengthExt(CMD/CTL):7FFF patrolScrubDuration:18 memTestLoops: 01 scrambleSeedLow: 0000A02B scrambleSeedHigh:0000D395 ADREn: 00 eraseArmNVDIMMS: 01 check_pm_sts: 00 check_platform_detect: 00 mcBgfThreshold: 00 normOppIntvl: 0400 SpdSmbSpeed: 00 struct ddrChannelSetup[00] { enabled: 01 numDimmSlots: 02 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[01] { enabled: 01 numDimmSlots: 02 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[02] { enabled: 00 numDimmSlots: 03 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[03] { enabled: 00 numDimmSlots: 03 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct memTiming { nCL: 00 nRP: 00 nRCD: 00 nRRD: 00 nWTR: 00 nRAS: 00 nRTP: 00 nWR: 00 nFAW: 00 nRC: 00 nCWL: 00 nCMDRate: 00 ddrFreqLimit: 00 vdd: 00 ucVolt: 00 casSup: 00 tREFI: 00 nRFC: 00 ddrFreq: 00 }; meRequestedSize: 00000000 }; serialDebugMsgLvl: 03 lowGap: 20 highGap: 01 mmiohSize: 00000100 isocEn: 00 dcaEn: 01 options (Chip): 10124FC8 CMD_CLK_TRAINING_EN 1 ALLOW2XREF_EN 1 RAS_TO_INDP_EN 0 BANK_XOR_EN 1 optionsExt (Chip): 1E41677F EARLY_CMD_CLK_TRAINING_EN 1 CMD_REF_EN 1 LRDIMM_BACKSIDE_VREF_EN 0 LRDIMM_WR_VREF_EN 1 LRDIMM_RD_VREF_EN 1 LRDIMM_RX_DQ_CENTERING 1 LRDIMM_TX_DQ_CENTERING 1 XOVER_EN 1 DRAM_RON_EN 0 RX_ODT_EN 0 RTT_WR_EN 0 MC_RON_EN 0 TX_EQ_EN 1 IMODE_EN 0 RX_CTLE_TRN_EN 1 SENSE_EN 1 ROUND_TRIP_LATENCY_EN 0 WR_CRC 0 DDR4_PLATFORM 0 0 0 RASmode: 00 RK_SPARE 0 CH_LOCKSTEP 0 CH_MIRROR 0 struct sysHost.setup.mem (Chip) { socketInter: 01 rankInter: 08 dramraplExtendedRange: 01 dramMaint: 02 dramMaintTRRMode: 01 dramMaintMode: 01 electricalThrottling: 00 altitude: 00 forceRankMult: 00 ceccWaChMask: 00 perBitDeSkew: 01 spareErrTh: 7FFF leakyBktLo: 28 leakyBktHi: 29 restoreNVDIMMS: 01 lockstepEnableX4: 00 numSparTrans: 0004 phaseShedding: 01 }; struct ddrIMCSetup[00] { enabled: 00000001 ddrVddLimit: 00 } }; //struct sysHost.setup forceColdBoot bit set Get socket PPIN N0: PPIN Hi = 0x25BEAAB, PPIN Lo = 0x51561DAB setupChanged: 1 Clearing the MRC NVRAM structure. sizeof sysNvram = 136441 bootMode = NormalBoot subBootMode = ColdBoot Dispatch Slaves -- Started Dispatch Slaves - 0ms Promote Warning Exception List -- Started Promote Warning Exception List - 0ms Initialize Throttling Early -- Started Initialize Throttling Early - 0ms Detect DIMM Configuration -- Started Checkpoint Code: Socket 0, 0xB0, 0x00, 0x0000 N0: IMC 0 SMB Clock Period = 0x1F2C Socket | Channel | DIMM | Bus Segment | SMBUS Address -------|---------|------|--------------|-------------- 0 | 0 | 0 | 0 | 0 - Not Present 0 | 0 | 1 | 0 | 1 - Not Present 0 | 1 | 0 | 0 | 2 - Present N0.C1.D0: NVDIMM:N(380)=0x0 0 | 1 | 1 | 0 | 3 - Not Present Entering no zone 1 Detect DIMM Configuration - 298ms Get Slave Data -- Started Get Slave Data - 0ms Check POR Compatibility -- Started N0.C0: Channel disabled in MemSPD: mcId = 0, mcCh = 0 primaryWidthDDR4: 1, rowBitsDDR4: 15, columnBitsDDR4: 10, bankGroupsDDR4: 4 RDIMM population Check POR Compatibility - 14ms Initialize DDR Clocks -- Started Checkpoint Code: Socket 0, 0xB1, 0x00, 0x0000 GetPORDDRFreq returns ddrfreq = 10 ratioIndex = 10 Reset requested: non-MRC MRC reset request! Current DCLK: 12 Desired DCLK: 16, req_type = 0 Entering no zone 2 Initialize DDR Clocks - 14ms mrcTask skipped; Index = 7 Send Status -- Started Send Status -- EXIT, status = 2h Total MRC time = 388ms Setting Last Boot Date = 7272 days STOP_MRC_RUN Reset Requested: 2 Pipe Exit starting...Pipe Exit completed! Reset Requested: 2 Checking for Reset Requests ... Send HostResetWarning notification to ME. ME UMA: WARNING: HostResetWarning called on non S3/4 resume flow (0) - ignored HostResetWarning notification Complete. Issue WARM RESET! BIOS done set Checkpoint Code: Socket 0, 0xAF, 0x42, 0x0000 ============= PEIM FSP v1.0 (_BDX-DE_ v0.0.3.3) ============= Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000FFEB1000, size is 0x0011F000, handle is 0x0 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389 Loading PEIM at 0x000FFEBA990 EntryPoint=0x000FFEBAA60 PcdPeim.efi Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480 Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1 Loading PEIM at 0x000FFEBEB00 EntryPoint=0x000FFEBEBD0 SetupDefault.efi Install PPI: 57B195D1-E14B-40AD-A68F-9806000C436A Loading PEIM at 0x000FFEC1F14 EntryPoint=0x000FFEC1FEC PlatformInfo.efi enable all DMI VCx :: CPU Type Socket ModelId# 56 :: CPU stepping # 3 Install PPI: 1E2ACC41-E26A-483D-AFC7-A056C34E087B Publish PlatformInfoPPI Loading PEIM at 0x000FFEC49D4 EntryPoint=0x000FFEC4AA4 MePolicyInitPei.efi Install PPI: 7AE3CEB7-2EE2-48FA-AA49-3510BC83CABF ME PEI Platform Policy PPI Installed Loading PEIM at 0x000FFEC6BCC EntryPoint=0x000FFEC6C94 HeciInit.efi Force an S5 exit path. Install PPI: E5EE2066-FAA1-4DFA-924E-B1E3A8EE30E8 Install PPI: EE0EA811-FBD9-4777-B95A-BA4F71101F74 Loading PEIM at 0x000FFECA1D4 EntryPoint=0x000FFECA29C MeUma.efi Install PPI: 8C376010-2400-4D7D-B47B-9D851DF3C9D1 ME UMA: ME UMA PPI Installed Loading PEIM at 0x000FFECD774 EntryPoint=0x000FFECD844 SpsPei.efi [SPS] Waiting for ME firmware init complete [HECI-0] VID-DID: 8086-8C3A [HECI-0] MBAR not programmed, using default 0x00000000FEDB0000 [SPS] Sending ME-BIOS Interface Version request [HECI-0] Send msg: 80010020 [HECI-0] Got msg: 80050020 [SPS] SPS ME-BIOS interface version is 1.0 Feature set is 0x2106 [SPS] HOB: features 0x2106, flow 1, boot mode 0, cores to disable 0 Loading PEIM at 0x000FFED0FFC EntryPoint=0x000FFED10DC UncoreInitPeim.efi OVERRIDING TOTAL SYSTEM CONFIGURATION WITH UPD upd->MemDdr4Platform = 0x0 tsc->DDR4Platform = 0x2 Halting the TCO Timer (Watchdog) Running on hardware Revision: 0 BIOSSIM: InitHeap() BIOSSIM: InitUSBDebug() BDX (1HA) processor detected CPU Stepping 3 Found CCMRC Version: 00500000 MRC Sync Number: 244071 RC Version: 02040000 host = FE191768 (pointer to sysHost structure) Legacy Serial Debug Enabled QPI Init starting... ******* QPI Setup Structure ******* PPINrOptIn: 0 Bus Ratio: 1 1 1 1 IO Ratio: 1 1 1 1 MMIOL Ratio: 1 1 1 1 LegacyVgaSoc: 0 MmioP2pDis: 0 IsocAzaliaVc1En: 0 DebugPrintLevel: 15 ClusterOnDieEn: 0 IBPECIEn: 1 E2EParityEn: 0 EarlySnoopEn: 1 HomeDirWOSBEn: 1 DegradePrecedence: 0 QpiLinkSpeedMode: 1 (FAST) QpiLinkSpeed: 6 QpiLinkL0pEn: 1 QpiLinkL1En: 1 QpiLinkL0rEn: 1 QpiLbEn: 0 IioUniphyDisable (per socket): 0 0 0 0 QpiLinkCreditReduce: 2 QpiConfigTxWci: 11 QpiCrcMode: 0 QpiCpuSktHotPlugEn: 0 QpiCpuSktHotPlugTopology: 0 QpiSkuMismatchCheck: 1 QpiPortDisable (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiLinkCreditReduce (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiLinkSpeed (per port): S0:6 6 S1:6 6 S2:6 6 S3:6 6 QpiProbeType (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiConfigTxWci (per port): S0:11 11 S1:11 11 S2:11 11 S3:11 11 Rsvd (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 ******* Common Setup Structure ******* mmCfgBase: 0x80000000 mmCfgSize: 0x10000000 mmiolBase: 0x90000000 mmiolSize: 0x6C000000 mmiohBase: 0x00003800-00000000 mmiohSize: 256 GB numaEn: 1 isocEn: 0 mesegEn: 0 dcaEn: 1 ******* Common Var Structure ******* resetRequired: 0 state: 0 numCpus: 0 socketPresentBitMap: 0x01 busIio: 0x00 0x00 0x00 0x00 busUncore: 0xFF 0x00 0x00 0x00 mmCfgBase: 0x80000000 ;******* Collecting Early System Information - START *******Checkpoint Code: Socket 0, 0xA1, 0x00, 0x1FFF CAPID0[5] is set. SKU Detected as DE. SocketId: 0 Physical Chop: 3 SocketId: 0 CAPID5: 0x06000965 SocketId: 0 CAPID4: 0x24080D03 SocketId: 0 CAPID3: 0x00930A20 SocketId: 0 CAPID2: 0x53B40000 SocketId: 0 CAPID1: 0x8C001787 SocketId: 0 CAPID0: 0x00188520 ; SBSP Socket: 0 SKU: 0x05 SubSKU: 0x00 Stepping: 0x03 CAPID4[sbsp]: 0x24080D03 ; Total Cbos: 06 Cbo List: 0x965 Total HA: 01 Total R3Qpi: 00 Total QpiAgent: 00 ; TotCpus: 1 CpuList: 0x01 ; busIio: 0x00 ; busUncore: 0xFF ; Reset Type: Warm Reset Link Speed: Slow Speed ;******* Collecting Early System Information - END ******* ;******* Setting up Minimum Path - START *******Checkpoint Code: Socket 0, 0xA3, 0x01, 0x0000 ; Constructing SBSP minimum path Topology Tree ; -------------------------------------------- ; Adding SBSP (CPU0) to the treeCheckpoint Code: Socket 0, 0xA3, 0x02, 0x0020 CPU0 Link Exchange UseQpiPcSts = 1 ;SBSP Minimum Path Tree ;---------------------- ;Index Socket ParentPort Hop ParentIndex ; 00 CPU0 -- 0 -- ;******* Setting up Minimum Path - END ******* ;******* Initialize MCTP - START ******* ;******* Initialize MCTP - END ******* ;******* Check for QPI Topology Degradation - START *******Checkpoint Code: Socket 0, 0xA7, 0x01, 0x1FFF ;Link Exchange Parameter ;----------------------- ;CPU0 ; Already Reduced to Supported Topology ; System will be treated 1S Configuration ;******* Check for QPI Topology Degradation - END ******* ;******* Checking QPIRC Input Structure - START ******* ; Sys configuration Type = 16 ;******* Checking QPIRC Input Structure - END ******* ;******* Allocate RTIDs - START ******* ; WB - 02 Ubox - 00 Isoc - 00 Local RTID PerCbo - 16 Extra - 30 ; Local Base - 01 Reallocation Base - 65 ; Cbo 03 RTID straddles into xRTID space ; RTIDs split into three pools of size 8, 7 and 1 ; Sufficient extra RTIDs are available to move the Second Pool into xRTID space. No loss of RTIDs for the CBo. ; RTID Allocation Table ; --------------------- ; Local ; ----- ; WB 0 1 ; UBOX 0 0 ; ISOC 1 0 ; CBO00 1 8 ; CBO00 9 8 ; CBO01 17 8 ; CBO01 25 8 ; CBO02 33 8 ; CBO02 41 8 ; CBO03 49 8 ; CBO03 65 8 ; CBO04 73 8 ; CBO04 81 8 ; CBO05 89 8 ; CBO05 97 8 ; EXTRA 0 23 ;******* Allocate RTIDs - END ******* ;******* Cacluate Resource Allocation - START *******Checkpoint Code: Socket 0, 0xA9, 0x01, 0x1FFF ;CPU Resource Allocation ;----------------------- ;CPU0 Bus: 0x00 - 0xFF IO: 0x0000 - 0xFFFF IOAPIC: 0xFEC00000 - 0xFEC3FFFF MMIOL: 0x90000000 - 0xFBFFFFFF MMIOH: 0x00003800 00000000 - 0x0000383F FFFFFFFF ;******* Cacluate Resource Allocation - END ******* ;******* Check for QPI Topology change across reset - START ******* ;******* Check for QPI Topology change across reset - END ******* ;******* Phy/Link Updates On Warm Reset - START ******* ; Force unused links to disabled/low power state. ; Clr PhyInitBegin on Socket 0 Link 0 : QPIREUT_PH_CTR write 0xFFFFFFDF Set force_l1 on Socket 0 Link 0 : QPIPHYPWRCTRL write 0xFFFFFFFF ; Clr PhyInitBegin on Socket 0 Link 1 : QPIREUT_PH_CTR write 0xFFFFFFDF Set force_l1 on Socket 0 Link 1 : QPIPHYPWRCTRL write 0xFFFFFFFF ;******* Phy/Link Updates On Warm Reset - END ******* ;******* Sync Up PBSPs - START ******* ; Verifying if the remote socket(s) checked-in. ;******* Sync Up PBSPs - END ******* ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x0 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x91 ; Wait for mailbox ready ;******* Topology Dicovery and Optimum Route Calculation - START *******Checkpoint Code: Socket 0, 0xA7, 0x02, 0x1FFF ; Locating the Rings Present in the Topology ; No Rings Found ; Constructing Topology TreeCheckpoint Code: Socket 0, 0xA7, 0x03, 0x1FE0 ; Adjacency Table ; ---------------- ; Checking for Deadlock... ;CPU0 Topology Tree ;------------------- ;Index Socket ParentSocket ParentPort ParentIndex Hop ; 00 CPU0 -- -- -- 0 ; ; Calculating Route for CPU0 Checkpoint Code: Socket 0, 0xA7, 0x04, 0x0020 ;CPU 0 Routing Table ;------------------- ;DestSocket Port ;******* Topology Dicovery and Optimum Route Calculation - END ******* ;******* Program Optimum Route Table Settings - START *******Checkpoint Code: Socket 0, 0xA8, 0xFF, 0x1FFF ;******* Program Optimum Route Table Settings - END ******* ;******* Program Final IO SAD Setting - START *******Checkpoint Code: Socket 0, 0xA9, 0x02, 0x1FFF Checkpoint Code: Socket 0, 0xA9, 0x02, 0x1FFF Checkpoint Code: Socket 0, 0xA9, 0x03, 0x0027 ;******* Program Final IO SAD Setting - END ******* ;******* Program Misc. QPI Parameters - START *******Checkpoint Code: Socket 0, 0xAA, 0x05, 0x1FFF Lock QPI DFX. ;******* Program Misc. QPI Parameters - END ******* ;******* Program Home Agent Credits - START *******Checkpoint Code: Socket 0, 0xAA, 0x03, 0x1FFF ;******* Program Home Agent Credits - END ******* ;******* Program Home tracker and Route Back Table - START *******Checkpoint Code: Socket 0, 0xAA, 0x04, 0x1FFF ;******* Program Home tracker and Route Back Table - END ******* ;******* Program System Coherency Registers - START *******Checkpoint Code: Socket 0, 0xAE, 0x00, 0x1FFF ;******* Program System Coherency Registers - END ******* ;******* Check for S3 Resume - START ******* ;******* Check for S3 Resume - END ******* ;******* Collect Previous Boot Error - START ******* ;******* Collect Previous Boot Error - END ******* ******* QPI Output Structure ******* OutLegacyVgaSoc: 0 OutIsocEn: 0 OutMesegEn: 0 OutIsocAzaliaVc1En: 0 OutClusterOnDieEn: 0 OutIBPECIEn: 1 OutE2EParityEn: 0 OutEarlySnoopEn: 1 OutHomeDirWOSBEn: 0 QpiCurrentLinkSpeedMode: 0 (SLOW) OutQpiLinkSpeed: 6 OutQpiLinkL0pEn: 1 OutQpiLinkL1En: 1 OutQpiLinkL0rEn: 1 OutIioUniphyDisable: 0, 0, 0, 0 OutQpiCrcMode: 0 OutClusterOnDieReduction: 0 OutPointerSeperationHA: 0 QpiInternalGlobal->BtModeEn: 0 QpiInternalGlobal->BtMode: 0 QpiInternalGlobal->BtMode2Alt: 0 QpiInternalGlobal->Sys4SClusterOnDieEn: 0 QpiInternalGlobal->SnoopFanoutEn: 0 QpiInternalGlobal->SysSnoopMode: 0 QpiInternalGlobal->IodcEn: 0Checkpoint Code: Socket 0, 0xAF, 0x00, 0x1FFF ;******* QPIRC Exit ******* QPI Init completed! Reset Requested: 0 Pipe Init starting...Pipe Init completed! Reset Requested: 0 CPU Feature Early Config starting... CAPID0[5] is set. SKU Detected as DE.CPU Feature Early Config completed! Reset Requested: 0 PrevBootErrors - CBO mcbank: 18 - not present; skipping... PrevBootErrors - CBO mcbank: 20 - not present; skipping... PrevBootErrors - CBO mcbank: 21 - not present; skipping... PrevBootErrors - Valid MCA UC entries: 0 START_MRC_RUN ME UMA: ME UMA Size Requested: 0 ME UMA size = 0 MBytes sizeof sysHost = 449216 sizeof BDAT = 168490 sizeof memSetup = 1463 sizeof memNvram = 136303 sizeof socketNvram = 33684 sizeof memVar = 135017 sizeof Socket = 30969 sizeof ddrChannel = 7434 sizeof dimmDevice = 946 sizeof SADTable = 20 sizeof TADTable = 23 MAX_SOCKET = 4 sizeof sysHostSetup = 1696 struct sysHost.common { options: 00000007 PROMOTE_WARN_EN 1 HALT_ON_ERROR_EN 1 serialDebugMsgLvl:03 bsdBreakpoint: 00 maxAddrMem: 40000 debugPort: 80 nvramPtr: 00000000 sysHostBufferPtr:00000000 mmCfgBase: 80000000 mmCfgSize: 10000000 pchumaEn: 00 numaEn: 01 logParsing: 00 bdatEn: 00 consoleComPort: 3F8 struct sysHost.setup.mem { options: 10124FC8 TEMPHIGH_EN 0 PDWN_SR_CKE_MODE 0 OPP_SELF_REF_EN 1 MDLL_SHUT_DOWN_EN 0 PAGE_POLICY 0 MULTI_THREAD_MRC_EN 1 ADAPTIVE_PAGE_EN 1 SCRAMBLE_EN 1 MEM_FLOWS - X_OVER_EN 1 MEM_FLOWS - SENSE_AMP_EN 1 MEM_FLOWS - E_CMDCLK_EN 1 MEM_FLOWS - REC_EN_EN 1 MEM_FLOWS - RD_DQS_EN 1 MEM_FLOWS - WR_LVL_EN 1 MEM_FLOWS - WR_FLYBY_EN 1 MEM_FLOWS - WR_DQ_EN 1 MEM_FLOWS - CMDCLK_EN 1 MEM_FLOWS - RD_ADV_EN 1 MEM_FLOWS - WR_ADV_EN 1 MEM_FLOWS - RD_VREF_EN 1 MEM_FLOWS - WR_VREF_EN 1 MEM_FLOWS - RT_OPT_EN 1 MEM_FLOWS - RX_DESKEW_EN 1 MEM_FLOWS - TX_DESKEW_EN 1 MEM_FLOWS - TX_EQ_EN 1 MEM_FLOWS - IMODE_EN 1 MEM_FLOWS - EARLY_RID_EN 1 MEM_FLOWS - DQ_SWIZ_EN 1 MEM_FLOWS - LRBUF_RD_EN 1 MEM_FLOWS - LRBUF_WR_EN 1 MEM_FLOWS - RANK_MARGIN_EN 1 MEM_FLOWS - MEMINIT_EN 1 MEM_FLOWS - FNVSIMICSSIM_EN 1 MEM_FLOWS - MEMTEST_EN 1 MEM_FLOWS - NORMAL_MODE_EN 1 MEM_FLOWS - E_CTLCLK_EN 1 MEM_FLOWS_EXT - RX_CTLE_EN 1 MEM_FLOWS_EXT - PXC_EN 1 DDR_RESET_LOOP 0 NUMA_AWARE 1 DISABLE_WMM_OPP_READ 0 ECC_CHECK_EN 1 ECC_MIX_EN 0 BALANCED_4WAY_EN 0 CA_PARITY_EN 1 SPLIT_BELOW_4GB_EN 0 MARGIN_RANKS_EN 0 MEM_OVERRIDE_EN 0 DRAMDLL_OFF_PD_EN 0 MEMORY_TEST_EN 1 MEMORY_TEST_FAST_BOOT_EN 0 ATTEMPT_FAST_BOOT 0 ATTEMPT_FAST_BOOT_COLD 0 SW_MEMORY_TEST_EN 0 RMT_COLD_FAST_BOOT 0 DISPLAY_EYE_EN 0 PER_NIBBLE_EYE_EN 0 optionsExt: 1E41677F RD_VREF_EN 1 WR_VREF_EN 1 PDA_EN 1 TURNAROUND_OPT_EN 1 PER_BIT_MARGINS 1 RASmodeEx: 16 DMNDSCRB_EN 1 PTRLSCRB_EN 1 A7_MODE_EN 1 DEVTAGGING_EN 0 struct sysHost.setup.mem { bclk: 00 enforcePOR: 00 ddrFreqLimit: 00 chInter: 04 dimmTypeSupport: 02 vrefStepSize: 00 vrefAbsMaxSteps: 00 vrefOpLimitSteps:00 pdwnCkMode: 04 MemPwrSave: 05 pprType: 00 pprErrInjTest 00 ckeThrottling: 01 olttPeakBWLIMITPercent: 00 thermalThrottlingOptions: 0A CLTT_EN 1 OLTT_EN 0 MH_OUTPUT_EN 0 MH_SENSE_EN 1 DimmTempStatValue 00 dramraplen: 02 dramraplbwlimittf: 01 lrdimmModuleDelay: 00 customRefreshRate: 00 rxVrefTraining: 00 iotMemBufferRsvtn: 00 enforceThreeMonthTimeout: 01 rmtPatternLength:7FFF rmtPatternLengthExt(CMD/CTL):7FFF patrolScrubDuration:18 memTestLoops: 01 scrambleSeedLow: 0000A02B scrambleSeedHigh:0000D395 ADREn: 00 eraseArmNVDIMMS: 01 check_pm_sts: 00 check_platform_detect: 00 mcBgfThreshold: 00 normOppIntvl: 0400 SpdSmbSpeed: 00 struct ddrChannelSetup[00] { enabled: 01 numDimmSlots: 02 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[01] { enabled: 01 numDimmSlots: 02 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[02] { enabled: 00 numDimmSlots: 03 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[03] { enabled: 00 numDimmSlots: 03 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct memTiming { nCL: 00 nRP: 00 nRCD: 00 nRRD: 00 nWTR: 00 nRAS: 00 nRTP: 00 nWR: 00 nFAW: 00 nRC: 00 nCWL: 00 nCMDRate: 00 ddrFreqLimit: 00 vdd: 00 ucVolt: 00 casSup: 00 tREFI: 00 nRFC: 00 ddrFreq: 00 }; meRequestedSize: 00000000 }; serialDebugMsgLvl: 03 lowGap: 20 highGap: 01 mmiohSize: 00000100 isocEn: 00 dcaEn: 01 options (Chip): 10124FC8 CMD_CLK_TRAINING_EN 1 ALLOW2XREF_EN 1 RAS_TO_INDP_EN 0 BANK_XOR_EN 1 optionsExt (Chip): 1E41677F EARLY_CMD_CLK_TRAINING_EN 1 CMD_REF_EN 1 LRDIMM_BACKSIDE_VREF_EN 0 LRDIMM_WR_VREF_EN 1 LRDIMM_RD_VREF_EN 1 LRDIMM_RX_DQ_CENTERING 1 LRDIMM_TX_DQ_CENTERING 1 XOVER_EN 1 DRAM_RON_EN 0 RX_ODT_EN 0 RTT_WR_EN 0 MC_RON_EN 0 TX_EQ_EN 1 IMODE_EN 0 RX_CTLE_TRN_EN 1 SENSE_EN 1 ROUND_TRIP_LATENCY_EN 0 WR_CRC 0 DDR4_PLATFORM 0 0 0 RASmode: 00 RK_SPARE 0 CH_LOCKSTEP 0 CH_MIRROR 0 struct sysHost.setup.mem (Chip) { socketInter: 01 rankInter: 08 dramraplExtendedRange: 01 dramMaint: 02 dramMaintTRRMode: 01 dramMaintMode: 01 electricalThrottling: 00 altitude: 00 forceRankMult: 00 ceccWaChMask: 00 perBitDeSkew: 01 spareErrTh: 7FFF leakyBktLo: 28 leakyBktHi: 29 restoreNVDIMMS: 01 lockstepEnableX4: 00 numSparTrans: 0004 phaseShedding: 01 }; struct ddrIMCSetup[00] { enabled: 00000001 ddrVddLimit: 00 } }; //struct sysHost.setup forceColdBoot bit set Get socket PPIN N0: PPIN Hi = 0x25BEAAB, PPIN Lo = 0x51561DAB setupChanged: 1 Clearing the MRC NVRAM structure. sizeof sysNvram = 136441 bootMode = NormalBoot subBootMode = ColdBoot Dispatch Slaves -- Started Dispatch Slaves - 0ms Promote Warning Exception List -- Started Promote Warning Exception List - 0ms Initialize Throttling Early -- Started Initialize Throttling Early - 0ms Detect DIMM Configuration -- Started Checkpoint Code: Socket 0, 0xB0, 0x00, 0x0000 N0: IMC 0 SMB Clock Period = 0x2990 Socket | Channel | DIMM | Bus Segment | SMBUS Address -------|---------|------|--------------|-------------- 0 | 0 | 0 | 0 | 0 - Not Present 0 | 0 | 1 | 0 | 1 - Not Present 0 | 1 | 0 | 0 | 2 - Present N0.C1.D0: NVDIMM:N(380)=0x0 0 | 1 | 1 | 0 | 3 - Not Present Entering no zone 1 Detect DIMM Configuration - 298ms Get Slave Data -- Started Get Slave Data - 0ms Check POR Compatibility -- Started N0.C0: Channel disabled in MemSPD: mcId = 0, mcCh = 0 primaryWidthDDR4: 1, rowBitsDDR4: 15, columnBitsDDR4: 10, bankGroupsDDR4: 4 RDIMM population Check POR Compatibility - 14ms Initialize DDR Clocks -- Started Checkpoint Code: Socket 0, 0xB1, 0x00, 0x0000 GetPORDDRFreq returns ddrfreq = 10 ratioIndex = 10 Memory behind processor 0 running at DDR-2133 Entering no zone 2 Initialize DDR Clocks - 9ms mrcTask skipped; Index = 7 Send Status -- Started Send Status - 0ms Set Vdd -- Started N0: VR0 DDR Voltage: 1.20V Set Vdd - 2ms Check DIMM Ranks -- Started Checkpoint Code: Socket 0, 0xB4, 0x00, 0x0000 N0.C0.D0: dimmMtr: 0x000F000C N0.C0.D1: dimmMtr: 0x000F000C N0.C0.D2: dimmMtr: 0x000F000C N0.C1.D0: dimmMtr: 0x001E414C N0.C1.D1: dimmMtr: 0x000F0000 N0.C1.D2: dimmMtr: 0x000F0000 N0.C2.D0: dimmMtr: 0x000F000C N0.C2.D1: dimmMtr: 0x000F000C N0.C2.D2: dimmMtr: 0x000F000C N0.C3.D0: dimmMtr: 0x000F000C N0.C3.D1: dimmMtr: 0x000F000C N0.C3.D2: dimmMtr: 0x000F000C N0: Lockstep disabled, x4 DIMMs detected N0.C1.D0.R0: size 64 TechIndex 0x4, size 0x40 Entering no zone 3 Check DIMM Ranks - 45ms Send Data -- Started Send Data - 0ms Initialize Memory -- Started Initialize Memory - 0ms Gather SPD Data -- Started Checkpoint Code: Socket 0, 0xB2, 0x00, 0x0000 N0: SMB Clock Period = 2992 primaryWidthDDR4: 1, rowBitsDDR4: 15, columnBitsDDR4: 10, bankGroupsDDR4: 4 Entering no zone 4 Gather SPD Data - 25ms Configure XMP -- Started Configure XMP - 35ms Platform NVDIMM Status -- Started N0: CoreNVDIMMStatus Platform NVDIMM Status - 2ms Early Configuration -- Started Checkpoint Code: Socket 0, 0xB3, 0x00, 0x0000 Mem Timings: N0.C1: tCCD=4 N0.C1: tCCD_L=6 N0.C1: tCWL=14 N0.C1: tCL=15 N0.C1: tRP=15 N0.C1: tRCD=15 N0.C1: tRRD_S=4 N0.C1: tRRD_L=6 N0.C1: tWTR=3 N0.C1: tRAS=35 N0.C1: tRTP=8 N0.C1: tWR=16 N0.C1: tFAW=23 N0.C1: tRC=49 N0.C1: tRFC=278 N0.C1: casSup=0x7FF8 N0: xoverModeVar = 1 N0.C1: trrMode = 4 N0.C1: twoXRefresh = 0 N0.C1: t_stagger_ref = 0x3 N0.C1.D0.R0: DRAM Rtt_wr = 0, Rtt_park = 60, Rtt_nom = 60 Entering no zone 5 Early Configuration - 41ms DDRIO Initialization -- Started Checkpoint Code: Socket 0, 0xB6, 0x00, 0x0000 N0: Enable xovercal N0: Enabling xover 2:2 mode N0.C1: piDelay CMDn0 CMDn1 CMDs0 CMDs1 CTL CKE CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 13 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 18 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 22 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 23 1 1 1 1 1 1 1 X 1 1 1 1 1 1 1 1 X 1 1 1 1 1 1 1 1 24 1 1 1 1 1 1 1 X 0 1 1 1 1 1 1 1 X 0 1 1 1 1 1 1 1 25 1 1 1 1 1 1 1 X X 1 1 1 1 1 0 1 X X 1 1 1 1 1 0 1 26 0 0 1 1 1 1 1 X X 0 1 1 1 0 X 1 X X 0 1 1 1 0 X 1 27 X X 0 1 1 1 1 X X X 1 1 1 X X 1 X X X 1 1 1 X X 1 28 X X X 1 1 1 1 X X X 0 1 0 X X 1 X X X 0 1 0 X X 1 29 X X X 1 0 1 1 X X X X 1 X X X 1 X X X X 1 X X X 1 30 X X X 0 X 1 1 X X X X 0 X X X 0 X X X X 0 X X X 0 31 X X X X X 1 1 X X X X X X X X X X X X X X X X X X 32 X X X X X 0 1 X X X X X X X X X X X X X X X X X X 33 X X X X X X 0 X X X X X X X X X X X X X X X X X X breakOut set! N0.C1: Edge not found in first 0-63. Setting invert pi clk for second sweep N0.C1: InvertPiClk CLK CMDn0 CMDn1 CMDs0 CMDs1 CKE CTL 0 1 2 3 4 5 6 7 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N0.C1: piDelay CMDn0 CMDn1 CMDs0 CMDs1 CTL CKE CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 X X X X X X X X X X X X X X X X X X X X X X X X X breakOut set! N0.C1: CMDn0 CMDn1 CMDs0 CMDs1 CTL CKE CLK 0 1 2 3 4 5 6 7 8 26 27 26 30 29 32 33 22 24 26 28 30 28 26 25 30 Adding +112 to CMD, Adding +112 to CTL and reevaluating Invert Pi Clk. Adding +112 to CLK and reevaluating Invert Pi Clk. Adding +0 to TxDq and reevaluating InvertPiClk. Adding +33 to RcvEn. Adding +40 to TxDqs. Adding +32 to odd fubs. Adding +36 to TxPerBitDeskew. N0.C1: InvertPiClk CMDn0 CMDn1 CMDs0 CMDs1 CKE CTL CLK 0 1 2 3 4 5 6 7 8 n n n n n n n n n n n n n n n n N0.C1: CMDn0 CMDn1 CMDs0 CMDs1 CTL CKE CLK 0 1 2 3 4 5 6 7 8 10 43 42 46 45 16 49 22 56 26 60 30 60 26 57 30 N0: SetStartingCCC => CpuSku= 0, CtlEntries= 84 N0.C1: CTL Group 6, CTL side 1, piDelay 108 N0.C1: CTL Group 0, CTL side 1, piDelay 108 N0.C1: CTL Group 0, CTL side 0, piDelay 108 N0.C1: CTL Group 8, CTL side 1, piDelay 108 N0.C1: CTL Group 7, CTL side 1, piDelay 108 N0.C1: CTL Group 1, CTL side 1, piDelay 108 N0.C1: CTL Group 1, CTL side 0, piDelay 108 N0.C1: CTL Group 9, CTL side 1, piDelay 108 N0.C1: CTL Group 2, CTL side 1, piDelay 108 N0.C1: CTL Group 2, CTL side 0, piDelay 108 N0.C1: CTL Group 6, CTL side 0, piDelay 108 N0.C1: CTL Group 7, CTL side 0, piDelay 108 N0.C1: CTL Group 10, CTL side 1, piDelay 108 N0.C1: CTL Group 3, CTL side 1, piDelay 108 N0.C1: CTL Group 3, CTL side 0, piDelay 108 N0.C1: CTL Group 4, CTL side 0, piDelay 108 N0.C1: CTL Group 5, CTL side 0, piDelay 108 N0.C1: CTL Group 8, CTL side 0, piDelay 108 N0.C1: CTL Group 9, CTL side 0, piDelay 108 N0.C1: CTL Group 4, CTL side 1, piDelay 108 N0.C1: CTL Group 5, CTL side 1, piDelay 108 N0: SetStartingCCC => CpuSku= 0, CmdEntries= 48 N0.C1: CMD Group 0, CMD side 1, piDelay 103 N0.C1: CMD Group 3, CMD side 1, piDelay 103 N0.C1: CMD Group 4, CMD side 1, piDelay 103 N0.C1: CMD Group 1, CMD side 1, piDelay 103 N0.C1: CMD Group 1, CMD side 0, piDelay 103 N0.C1: CMD Group 0, CMD side 0, piDelay 103 N0.C1: CMD Group 3, CMD side 0, piDelay 103 N0.C1: CMD Group 4, CMD side 0, piDelay 103 N0.C1: CMD Group 2, CMD side 1, piDelay 103 N0.C1: CMD Group 2, CMD side 0, piDelay 103 N0.C1: CMD Group 5, CMD side 1, piDelay 103 N0.C1: CMD Group 5, CMD side 0, piDelay 103 N0: SetStartingCCC => CpuSku= 0, ClkEntries= 16 N0.C1: CLK 0, piDelay 128 N0.C1: CLK 2, piDelay 128 N0.C1: CLK 1, piDelay 128 N0.C1: CLK 3, piDelay 128 Reset All Channels JEDEC Init N0.C1.D0.R0: Write RC00 = 0x00 N0.C1.D0.R0: Write RC01 = 0x00 N0.C1.D0.R0: Write RC02 = 0x00 N0.C1.D0.R0: Write RC03 = 0x00 N0.C1.D0.R0: Write RC04 = 0x00 N0.C1.D0.R0: Write RC05 = 0x00 N0.C1.D0.R0: Write RC40 = 0x0F N0.C1.D0.R0: Write RC08 = 0x0B N0.C1.D0.R0: Write RC0A = 0x02 N0.C1.D0.R0: Write RC0B = 0x08 N0.C1.D0.R0: Write RC0C = 0x00 N0.C1.D0.R0: Write RC0E = 0x00 N0.C1.D0.R0: Write RC0F = 0x00 N0.C1.D0.R0: Write RC30 = 0x2C N0.C1.D0.R0: Write RC40 = 0x26 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x27 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x28 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x29 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x21 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x22 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x23 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x24 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x25 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC09 = 0x0C N0.C1.D0.R0: Write RC0D = 0x04 N0.C1: Issue ZQCL N0: Stage 1: Vref Offset Training Plot Of SumOfBits across Vref settings VR SA 0 1 2 3 4 5 6 7 8 N0.C1: 10 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 10 11 0 0 0 0 0 0 0 0 0 N0.C1: 11 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 11 11 0 0 0 0 0 0 0 0 0 N0.C1: 12 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 12 11 0 0 0 0 0 0 0 0 0 N0.C1: 13 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 13 11 0 0 0 0 0 0 0 0 0 N0.C1: 14 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 14 11 0 0 0 0 0 0 0 0 0 N0.C1: 15 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 15 11 0 0 0 0 0 0 0 0 0 N0.C1: 16 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 16 11 0 0 0 0 0 0 0 0 0 N0.C1: 17 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 17 11 0 0 0 0 0 0 0 0 0 N0.C1: 18 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 18 11 0 0 0 0 0 0 0 0 0 N0.C1: 19 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 19 11 0 0 0 0 0 0 0 0 0 N0.C1: 20 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 20 11 0 0 0 0 0 0 0 0 0 N0.C1: 21 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 21 11 0 0 0 0 0 0 0 0 0 N0.C1: 22 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 22 11 0 0 0 0 0 0 0 0 0 N0.C1: 23 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 23 11 0 0 0 0 0 0 0 0 0 N0.C1: 24 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 24 11 0 0 0 0 0 0 0 0 0 N0.C1: 25 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 25 11 0 0 0 0 0 0 0 0 0 N0.C1: 26 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 26 11 0 0 0 0 0 0 0 0 0 N0.C1: 27 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 27 11 0 0 0 0 0 0 0 0 0 N0.C1: 28 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 28 11 0 0 0 0 0 0 0 0 0 N0.C1: 29 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 29 11 0 0 0 0 0 0 0 0 0 N0.C1: 30 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 30 11 0 0 0 0 0 0 0 0 0 N0.C1: 31 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 31 11 0 0 0 0 0 0 0 0 0 N0.C1: 32 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 32 11 0 0 0 0 0 0 0 0 0 N0.C1: 33 19 -8 -8 -8 -8 -7 -8 -8 -8 -8 N0.C1: 33 11 0 0 0 0 1 0 0 0 0 N0.C1: 34 19 -8 -8 -8 -8 -7 -8 -8 -8 -8 N0.C1: 34 11 0 0 0 0 1 0 0 0 0 N0.C1: 35 19 -8 -8 -8 -8 -6 -8 -8 -8 -8 N0.C1: 35 11 0 0 0 0 2 0 0 0 0 N0.C1: 36 19 -8 -5 -7 -8 -5 -7 -7 -7 -8 N0.C1: 36 11 0 3 1 0 3 1 1 1 0 N0.C1: 37 19 -7 -4 -6 -8 -4 -7 -6 -6 -8 N0.C1: 37 11 1 4 2 0 4 1 2 2 0 N0.C1: 38 19 -3 -4 -5 -8 -4 -5 -4 -4 -6 N0.C1: 38 11 5 4 3 0 4 3 4 4 2 N0.C1: 39 19 -3 -4 -3 -3 -4 -3 -3 -2 -4 N0.C1: 39 11 5 4 5 5 4 5 5 6 4 N0.C1: 40 19 -3 -3 -2 -1 -1 -2 -1 -1 -1 N0.C1: 40 11 5 5 6 7 7 6 7 7 7 N0.C1: 41 19 -2 -2 0 0 -1 0 -1 0 0 N0.C1: 41 11 6 6 8 8 7 8 7 8 8 N0.C1: 42 19 0 0 0 0 0 0 0 0 0 N0.C1: 42 11 8 8 8 8 8 8 8 8 8 N0.C1: 43 19 0 0 0 0 0 0 0 0 0 N0.C1: 43 11 8 8 8 8 8 8 8 8 8 N0.C1: 44 19 0 0 0 0 0 0 0 0 0 N0.C1: 44 11 8 8 8 8 8 8 8 8 8 N0.C1: 45 19 0 0 0 0 0 0 0 0 0 N0.C1: 45 11 8 8 8 8 8 8 8 8 8 N0.C1: 46 19 0 0 0 0 0 0 0 0 0 N0.C1: 46 11 8 8 8 8 8 8 8 8 8 N0.C1: 47 19 0 0 0 0 0 0 0 0 0 N0.C1: 47 11 8 8 8 8 8 8 8 8 8 N0.C1: 48 19 0 0 0 0 0 0 0 0 0 N0.C1: 48 11 8 8 8 8 7 8 8 8 8 N0.C1: 49 19 0 0 0 0 0 0 0 0 0 N0.C1: 49 11 8 8 8 8 7 8 8 8 8 N0.C1: 50 19 0 0 0 0 0 0 0 0 0 N0.C1: 50 11 8 7 7 8 6 8 8 7 8 N0.C1: 51 19 0 0 0 0 0 0 0 0 0 N0.C1: 51 11 8 5 7 8 5 7 7 7 8 N0.C1: 52 19 0 0 0 0 0 0 0 0 0 N0.C1: 52 11 4 4 5 8 4 7 6 5 7 N0.C1: 53 19 0 0 0 0 0 0 0 0 0 N0.C1: 53 11 3 4 5 8 4 5 4 3 4 N0.C1: 54 19 0 0 0 0 0 0 0 0 0 N0.C1: 54 11 3 4 2 2 2 3 3 2 3 N0.C1: 55 19 0 0 0 0 0 0 0 0 0 N0.C1: 55 11 3 2 0 1 1 2 1 0 0 N0.C1: 56 19 0 0 0 0 0 0 0 0 0 N0.C1: 56 11 1 2 0 0 0 0 0 0 0 N0.C1: 57 19 0 0 0 0 0 0 0 0 0 N0.C1: 57 11 1 0 0 0 0 0 0 0 0 N0.C1: 58 19 0 0 0 0 0 0 0 0 0 N0.C1: 58 11 0 0 0 0 0 0 0 0 0 N0.C1: 59 19 0 0 0 0 0 0 0 0 0 N0.C1: 59 11 0 0 0 0 0 0 0 0 0 N0.C1: 60 19 0 0 0 0 0 0 0 0 0 N0.C1: 60 11 0 0 0 0 0 0 0 0 0 N0.C1: 61 19 0 0 0 0 0 0 0 0 0 N0.C1: 61 11 0 0 0 0 0 0 0 0 0 N0.C1: 62 19 0 0 0 0 0 0 0 0 0 N0.C1: 62 11 0 0 0 0 0 0 0 0 0 N0.C1: 63 19 0 0 0 0 0 0 0 0 0 N0.C1: 63 11 0 0 0 0 0 0 0 0 0 N0.C1: 64 19 0 0 0 0 0 0 0 0 0 N0.C1: 64 11 0 0 0 0 0 0 0 0 0 N0.C1: 65 19 0 0 0 0 0 0 0 0 0 N0.C1: 65 11 0 0 0 0 0 0 0 0 0 N0.C1: 66 19 0 0 0 0 0 0 0 0 0 N0.C1: 66 11 0 0 0 0 0 0 0 0 0 N0.C1: 67 19 0 0 0 0 0 0 0 0 0 N0.C1: 67 11 0 0 0 0 0 0 0 0 0 N0.C1: 68 19 0 0 0 0 0 0 0 0 0 N0.C1: 68 11 0 0 0 0 0 0 0 0 0 N0.C1: 69 19 0 0 0 0 0 0 0 0 0 N0.C1: 69 11 0 0 0 0 0 0 0 0 0 N0.C1: 70 19 0 0 0 0 0 0 0 0 0 N0.C1: 70 11 0 0 0 0 0 0 0 0 0 N0.C1: 71 19 0 0 0 0 0 0 0 0 0 N0.C1: 71 11 0 0 0 0 0 0 0 0 0 N0.C1: 72 19 0 0 0 0 0 0 0 0 0 N0.C1: 72 11 0 0 0 0 0 0 0 0 0 N0.C1: 73 19 0 0 0 0 0 0 0 0 0 N0.C1: 73 11 0 0 0 0 0 0 0 0 0 N0.C1: 74 19 0 0 0 0 0 0 0 0 0 N0.C1: 74 11 0 0 0 0 0 0 0 0 0 N0.C1: Vref 47 46 46 48 45 46 47 46 47 Stage 2: SampOffset Training 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 SA 01230123 01230123 01230123 01230123 01230123 01230123 01230123 01230123 01230123 N0.C1: 0 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 1 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 2 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 3 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 4 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 5 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 6 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 7 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 8 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 9 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 10 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 11 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 12 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 13 11111111 11101111 11111111 11111111 11111111 11111111 11111101 11110111 11111111 N0.C1: 14 10000100 11101001 11101011 10010111 10011001 11010111 00101101 11110110 11111110 N0.C1: 15 10000100 11000000 11101001 10000000 10001001 11010110 00000100 10010100 11000000 N0.C1: 16 10000100 00000000 01100001 00000000 00000000 10000000 00000000 00000000 00000000 N0.C1: 17 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 18 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 19 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 20 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 21 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 22 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 24 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 25 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 26 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 27 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 28 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 29 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 30 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 31 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 BitSAmp bit: 0 1 2 3 N0.C1: Nibble 0: 16 13 13 13 N0.C1: Nibble 1: 13 16 13 13 N0.C1: Nibble 2: 15 15 14 12 N0.C1: Nibble 3: 14 13 13 14 N0.C1: Nibble 4: 15 16 16 13 N0.C1: Nibble 5: 15 13 14 16 N0.C1: Nibble 6: 15 13 13 14 N0.C1: Nibble 7: 13 14 14 14 N0.C1: Nibble 8: 15 13 13 14 N0.C1: Nibble 9: 15 13 13 15 N0.C1: Nibble 10: 16 15 13 15 N0.C1: Nibble 11: 13 15 15 14 N0.C1: Nibble 12: 13 13 14 13 N0.C1: Nibble 13: 14 15 12 14 N0.C1: Nibble 14: 15 14 14 15 N0.C1: Nibble 15: 12 15 14 13 N0.C1: Nibble 16: 15 15 14 14 N0.C1: Nibble 17: 14 14 14 13 N0: SenseAmpOffset - 929ms N0.C1: Number of DIMMS in channel: 1 Entering no zone 6 DDRIO Initialization - 1778ms Pre-Training Initialization -- Started Pre-Training Initialization - 0ms Early CTL/CLK -- Started Checkpoint Code: Socket 0, 0xB7, 0x1A, 0x0000 N0.D0.R0: RecEn Pi Scanning: Summary: Early Ctl Clk Receive Enable Pi S0, Ch1, DIMM0, Rank0 ------------------------------------------------------------------------------------- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 1 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 2 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 3 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 4 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 5 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 6 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 7 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 8 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 9 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 10 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 11 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 12 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 13 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 14 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 15 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 16 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 17 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 18 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 19 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 20 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 21 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 22 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 23 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 24 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 25 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 26 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 27 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 28 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 29 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 30 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 31 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 32 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 33 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 34 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 35 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 36 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 37 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 38 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 39 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 40 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 1 41 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 42 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 43 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 44 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 45 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 46 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 47 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 48 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 49 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 50 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 51 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 52 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 53 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 54 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 55 0 0 0 1 1 1 0 0 1 0 0 0 0 1 1 0 0 1 56 0 0 0 1 1 1 0 0 1 0 0 0 0 1 1 0 0 1 57 0 0 0 1 1 1 0 0 1 0 0 0 0 1 1 0 0 1 58 0 0 0 1 1 1 0 0 1 0 0 0 0 1 1 0 0 1 59 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 60 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 61 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 62 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 63 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 64 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 65 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 66 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 67 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 68 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 69 0 0 0 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 70 0 0 0 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 71 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 72 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 73 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 74 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 75 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 76 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 77 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 78 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 79 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 80 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 81 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 82 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 83 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 84 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 85 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 86 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 87 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 88 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 89 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 90 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 91 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 92 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 93 0 0 1 1 0 1 1 0 0 0 0 1 1 0 1 1 0 0 94 0 0 1 1 0 1 1 1 0 0 0 1 1 0 1 1 0 0 95 0 0 1 1 0 0 1 0 0 0 0 1 1 0 1 1 0 0 96 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 97 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 98 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 99 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 100 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 101 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 102 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 103 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 104 0 1 1 0 0 0 1 1 0 0 0 1 1 0 1 1 1 0 105 0 1 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 0 106 0 1 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 0 107 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 108 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 109 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 110 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 111 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 112 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 113 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 114 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 115 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 116 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 117 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 118 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 119 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 120 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 121 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 122 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 123 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 124 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 125 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 126 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 127 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 ---------------------------------------------------------------------------- RE: 117 96 71 47 24 41 69 96 27 1 105 83 59 36 51 80 104 37 CP: 16 124 100 75 52 68 97 124 53 28 6 111 87 64 79 108 5 65 FE: 44 24 1 104 80 95 125 24 80 55 35 11 115 93 107 8 34 93 PW: 55 56 58 57 56 54 56 56 53 54 58 56 56 57 56 56 58 56 N0.C1.D0.R0.S00: Rec En Delay 16 N0.C1.D0.R0.S01: Rec En Delay 124 N0.C1.D0.R0.S02: Rec En Delay 100 N0.C1.D0.R0.S03: Rec En Delay 75 N0.C1.D0.R0.S04: Rec En Delay 52 N0.C1.D0.R0.S05: Rec En Delay 68 N0.C1.D0.R0.S06: Rec En Delay 97 N0.C1.D0.R0.S07: Rec En Delay 124 N0.C1.D0.R0.S08: Rec En Delay 53 N0.C1.D0.R0.S09: Rec En Delay 28 N0.C1.D0.R0.S10: Rec En Delay 6 N0.C1.D0.R0.S11: Rec En Delay 111 N0.C1.D0.R0.S12: Rec En Delay 87 N0.C1.D0.R0.S13: Rec En Delay 64 N0.C1.D0.R0.S14: Rec En Delay 79 N0.C1.D0.R0.S15: Rec En Delay 108 N0.C1.D0.R0.S16: Rec En Delay 5 N0.C1.D0.R0.S17: Rec En Delay 65 N0.C1.D0.R0: Round trip latency = 73 IO latency = 4 N0.D0.R0: Round trip latency N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 71 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 69 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 67 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 65 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 63 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 61 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 59 N0.C1.D0.R0: IO Latency = 6 zeroFlag = 0x10601, allZeros[1] = 0x3FFFF N0.C1.D0.R0.S00: Rec En Delay = 144 N0.C1.D0.R0.S09: Rec En Delay = 156 N0.C1.D0.R0.S10: Rec En Delay = 134 N0.C1.D0.R0.S16: Rec En Delay = 133 N0.C1.D0.R0: Round trip latency: Found all zeros Early CTL CLK Receive Enable Summary ------------------------ START_DATA_EARLY_CTL_CLK_REC_EN N0.C1.D0.R0.S00: Pi setting = 176 N0.C1.D0.R0.S01: Pi setting = 156 N0.C1.D0.R0.S02: Pi setting = 132 N0.C1.D0.R0.S03: Pi setting = 107 N0.C1.D0.R0.S04: Pi setting = 84 N0.C1.D0.R0.S05: Pi setting = 100 N0.C1.D0.R0.S06: Pi setting = 129 N0.C1.D0.R0.S07: Pi setting = 156 N0.C1.D0.R0.S08: Pi setting = 85 N0.C1.D0.R0.S09: Pi setting = 188 N0.C1.D0.R0.S10: Pi setting = 166 N0.C1.D0.R0.S11: Pi setting = 143 N0.C1.D0.R0.S12: Pi setting = 119 N0.C1.D0.R0.S13: Pi setting = 96 N0.C1.D0.R0.S14: Pi setting = 111 N0.C1.D0.R0.S15: Pi setting = 140 N0.C1.D0.R0.S16: Pi setting = 165 N0.C1.D0.R0.S17: Pi setting = 97 N0.C1.D0.R0: IO Latency = 6 N0.C1.D0.R0: Round Trip = 59 STOP_DATA_EARLY_CTL_CLK_REC_EN Starting Senseamp and ODT delay calculations ------------------------------------------------------------ N0.C1.S00: MaxRcven=176, New Senseamp/Odt delay=14 N0.C1.S01: MaxRcven=156, New Senseamp/Odt delay=14 N0.C1.S02: MaxRcven=132, New Senseamp/Odt delay=14 N0.C1.S03: MaxRcven=107, New Senseamp/Odt delay=14 N0.C1.S04: MaxRcven= 84, New Senseamp/Odt delay=14 N0.C1.S05: MaxRcven=100, New Senseamp/Odt delay=14 N0.C1.S06: MaxRcven=129, New Senseamp/Odt delay=14 N0.C1.S07: MaxRcven=156, New Senseamp/Odt delay=14 N0.C1.S08: MaxRcven= 85, New Senseamp/Odt delay=14 N0.C1.S09: MaxRcven=188, New Senseamp/Odt delay=14 N0.C1.S10: MaxRcven=166, New Senseamp/Odt delay=14 N0.C1.S11: MaxRcven=143, New Senseamp/Odt delay=14 N0.C1.S12: MaxRcven=119, New Senseamp/Odt delay=14 N0.C1.S13: MaxRcven= 96, New Senseamp/Odt delay=14 N0.C1.S14: MaxRcven=111, New Senseamp/Odt delay=14 N0.C1.S15: MaxRcven=140, New Senseamp/Odt delay=14 N0.C1.S16: MaxRcven=165, New Senseamp/Odt delay=14 N0.C1.S17: MaxRcven= 97, New Senseamp/Odt delay=14 START_DATA_CMD 0n 1n 2n 3n 4n 5n 0s 1s 2s 3s 4s 5s N0.C1: 103 103 103 103 103 103 103 103 103 103 103 103 START_DATA_CLK 0 1 2 3 N0.C1: 0 0 0 0 START_DATA_CTL 0n 1n 2n 3n 4n 5n 6n 7n 8n 9n 0s 1s 2s 3s 4s 5s 6s 7s 8s 9s 10s N0.C1: 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 N0.C1.D0.R0: le = -64 - re = 65 width = 129 N0.C1: Ctl group 0, left edge = -64 - right edge = 65 offset == 0 width =129 START_DATA_CMD 0n 1n 2n 3n 4n 5n 0s 1s 2s 3s 4s 5s N0.C1: 103 103 103 103 103 103 103 103 103 103 103 103 START_DATA_CLK 0 1 2 3 N0.C1: 0 0 0 0 START_DATA_CTL 0n 1n 2n 3n 4n 5n 6n 7n 8n 9n 0s 1s 2s 3s 4s 5s 6s 7s 8s 9s 10s N0.C1: 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 Entering no zone 7 Early CTL/CLK - 1500ms Early CMD/CLK -- Started Checkpoint Code: Socket 0, 0xB7, 0x0C, 0x0000 START_PARITY_CMD_CLK N0.C1: Setting cmd timing to 0 N0.C1.D0.R0: Setting RTL to 55 N0.C1.D0.R0: Write RC0E = 0x01 N0: Enabling C/A Parity N0.C1.D0.R0: PAR -> **********************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000****************************************************************************************** N0.C1.D0.R0: le = -69 - re = 62 N0.C1.D0.R0: CAS_N -> ************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************************** N0.C1.D0.R0: le = -67 - re = 60 N0.C1.D0.R0: A13 -> **************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000****************************************************************************************** N0.C1.D0.R0: le = -65 - re = 62 N0.C1.D0.R0: RAS_N -> ************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************************** N0.C1.D0.R0: le = -67 - re = 60 N0.C1.D0.R0: WE_N -> **********************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000********************************************************************************************** N0.C1.D0.R0: le = -69 - re = 58 N0.C1.D0.R0: A10 -> **********************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************************** N0.C1.D0.R0: le = -69 - re = 60 N0.C1.D0.R0: BA1 -> ************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000****************************************************************************************** N0.C1.D0.R0: le = -67 - re = 62 N0.C1.D0.R0: A0 -> ******************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************************ N0.C1.D0.R0: le = -73 - re = 56 N0.C1.D0.R0: BA0 -> **********************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000********************************************************************************************** N0.C1.D0.R0: le = -69 - re = 58 N0.C1.D0.R0: A1 -> **********************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000********************************************************************************************** N0.C1.D0.R0: le = -69 - re = 58 N0.C1.D0.R0: A3 -> **********************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000****************************************************************************************** N0.C1.D0.R0: le = -69 - re = 62 N0.C1.D0.R0: A2 -> ********************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************************ N0.C1.D0.R0: le = -71 - re = 56 N0.C1.D0.R0: A4 -> ************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000****************************************************************************************** N0.C1.D0.R0: le = -67 - re = 62 N0.C1.D0.R0: A5 -> ************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************************** N0.C1.D0.R0: le = -67 - re = 60 N0.C1.D0.R0: A6 -> ************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************************** N0.C1.D0.R0: le = -67 - re = 60 N0.C1.D0.R0: A7 -> **********************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************************ N0.C1.D0.R0: le = -69 - re = 56 N0.C1.D0.R0: A8 -> **********************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000********************************************************************************************** N0.C1.D0.R0: le = -69 - re = 58 N0.C1.D0.R0: A9 -> **********************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000********************************************************************************************** N0.C1.D0.R0: le = -69 - re = 58 N0.C1.D0.R0: A12 -> **********************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000********************************************************************************************** N0.C1.D0.R0: le = -69 - re = 58 N0.C1.D0.R0: A11 -> ************************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000********************************************************************************************** N0.C1.D0.R0: le = -67 - re = 58 N0.C1.D0.R0: BG1 -> ********************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000************************************************************************************************ N0.C1.D0.R0: le = -71 - re = 56 N0.C1.D0.R0: ACT_N -> **********************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000********************************************************************************************** N0.C1.D0.R0: le = -69 - re = 58 N0.C1.D0.R0: BG0 -> ************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000****************************************************************************************** N0.C1.D0.R0: le = -67 - re = 62 N0.C1.D0.R0: Write RC0E = 0x00 N0.C1: PAR: CMD Pi Group 9 clk 0: le -69 re = 62, cmdLeft = -69 cmdRight = 62 N0.C1: CAS_N: CMD Pi Group 7 clk 0: le -67 re = 60, cmdLeft = -67 cmdRight = 60 N0.C1: A13: CMD Pi Group 11 clk 0: le -65 re = 62, cmdLeft = -65 cmdRight = 62 N0.C1: RAS_N: CMD Pi Group 1 clk 0: le -67 re = 60, cmdLeft = -67 cmdRight = 60 N0.C1: WE_N: CMD Pi Group 7 clk 0: le -69 re = 58, cmdLeft = -67 cmdRight = 58 N0.C1: A10: CMD Pi Group 1 clk 0: le -69 re = 60, cmdLeft = -67 cmdRight = 60 N0.C1: BA1: CMD Pi Group 11 clk 0: le -67 re = 62, cmdLeft = -65 cmdRight = 62 N0.C1: A0: CMD Pi Group 9 clk 0: le -73 re = 56, cmdLeft = -69 cmdRight = 56 N0.C1: BA0: CMD Pi Group 4 clk 0: le -69 re = 58, cmdLeft = -69 cmdRight = 58 N0.C1: A1: CMD Pi Group 3 clk 0: le -69 re = 58, cmdLeft = -69 cmdRight = 58 N0.C1: A3: CMD Pi Group 8 clk 0: le -69 re = 62, cmdLeft = -69 cmdRight = 62 N0.C1: A2: CMD Pi Group 3 clk 0: le -71 re = 56, cmdLeft = -69 cmdRight = 56 N0.C1: A4: CMD Pi Group 8 clk 0: le -67 re = 62, cmdLeft = -67 cmdRight = 62 N0.C1: A5: CMD Pi Group 2 clk 0: le -67 re = 60, cmdLeft = -67 cmdRight = 60 N0.C1: A6: CMD Pi Group 2 clk 0: le -67 re = 60, cmdLeft = -67 cmdRight = 60 N0.C1: A7: CMD Pi Group 6 clk 0: le -69 re = 56, cmdLeft = -69 cmdRight = 56 N0.C1: A8: CMD Pi Group 6 clk 0: le -69 re = 58, cmdLeft = -69 cmdRight = 56 N0.C1: A9: CMD Pi Group 0 clk 0: le -69 re = 58, cmdLeft = -69 cmdRight = 58 N0.C1: A12: CMD Pi Group 4 clk 0: le -69 re = 58, cmdLeft = -69 cmdRight = 58 N0.C1: A11: CMD Pi Group 0 clk 0: le -67 re = 58, cmdLeft = -67 cmdRight = 58 N0.C1: BG1: CMD Pi Group 10 clk 0: le -71 re = 56, cmdLeft = -71 cmdRight = 56 N0.C1: ACT_N: CMD Pi Group 5 clk 0: le -69 re = 58, cmdLeft = -69 cmdRight = 58 N0.C1: BG0: CMD Pi Group 10 clk 0: le -67 re = 62, cmdLeft = -67 cmdRight = 56 N0.C1: CS2_N: CMD Pi Group 12 clk 0: le -511 re = 511, cmdLeft = -255 cmdRight = 255 N0.C1: CS3_N: CMD Pi Group 12 clk 0: le -511 re = 511, cmdLeft = -255 cmdRight = 255 N0.C1: C2: CMD Pi Group 5 clk 0: le -511 re = 511, cmdLeft = -69 cmdRight = 58 N0.C1: CMD Pi Group 0 clk 0 cmdOffset -4 N0.C1: CMD Pi Group 1 clk 0 cmdOffset -3 N0.C1: CMD Pi Group 2 clk 0 cmdOffset -3 N0.C1: CMD Pi Group 3 clk 0 cmdOffset -6 N0.C1: CMD Pi Group 4 clk 0 cmdOffset -5 N0.C1: CMD Pi Group 5 clk 0 cmdOffset -5 N0.C1: CMD Pi Group 6 clk 0 cmdOffset -6 N0.C1: CMD Pi Group 7 clk 0 cmdOffset -4 N0.C1: CMD Pi Group 8 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 9 clk 0 cmdOffset -6 N0.C1: CMD Pi Group 10 clk 0 cmdOffset -5 N0.C1: CMD Pi Group 11 clk 0 cmdOffset -1 N0.C1: CMD Pi Group 12 clk 0 cmdOffset 0 N0.C1: CMD Pi Group 13 clk 0 cmdOffset 0 N0.C1: CMD Pi Group 14 clk 0 cmdOffset 0 N0.C1: CMD Pi Group 0: maxOffset = -4, minOffset = -4, cmdOffset = -4 N0.C1: CMD Pi Group 1: maxOffset = -3, minOffset = -3, cmdOffset = -3 N0.C1: CMD Pi Group 2: maxOffset = -3, minOffset = -3, cmdOffset = -3 N0.C1: CMD Pi Group 3: maxOffset = -6, minOffset = -6, cmdOffset = -6 N0.C1: CMD Pi Group 4: maxOffset = -5, minOffset = -5, cmdOffset = -5 N0.C1: CMD Pi Group 5: maxOffset = -5, minOffset = -5, cmdOffset = -5 N0.C1: CMD Pi Group 6: maxOffset = -6, minOffset = -6, cmdOffset = -6 N0.C1: CMD Pi Group 7: maxOffset = -4, minOffset = -4, cmdOffset = -4 N0.C1: CMD Pi Group 8: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 9: maxOffset = -6, minOffset = -6, cmdOffset = -6 N0.C1: CMD Pi Group 10: maxOffset = -5, minOffset = -5, cmdOffset = -5 N0.C1: CMD Pi Group 11: maxOffset = -1, minOffset = -1, cmdOffset = -1 N0.C1: CMD Pi Group 0: maxOffset = 0, minOffset = 0, cmdOffset = 0 N0.C1: CMD Pi Group 1: maxOffset = 0, minOffset = 0, cmdOffset = 0 N0.C1: CMD Pi Group 2: maxOffset = 0, minOffset = 0, cmdOffset = 0 N0.C1: <--CMD Pi Group 0 clk 0: cmdLeft -63 - cmdRight 62 N0.C1: <--CMD Pi Group 1 clk 0: cmdLeft -64 - cmdRight 63 N0.C1: <--CMD Pi Group 2 clk 0: cmdLeft -64 - cmdRight 63 N0.C1: <--CMD Pi Group 3 clk 0: cmdLeft -63 - cmdRight 62 N0.C1: <--CMD Pi Group 4 clk 0: cmdLeft -64 - cmdRight 63 N0.C1: <--CMD Pi Group 5 clk 0: cmdLeft -64 - cmdRight 63 N0.C1: <--CMD Pi Group 6 clk 0: cmdLeft -63 - cmdRight 62 N0.C1: <--CMD Pi Group 7 clk 0: cmdLeft -63 - cmdRight 62 N0.C1: <--CMD Pi Group 8 clk 0: cmdLeft -65 - cmdRight 64 N0.C1: <--CMD Pi Group 9 clk 0: cmdLeft -63 - cmdRight 62 N0.C1: <--CMD Pi Group 10 clk 0: cmdLeft -62 - cmdRight 61 N0.C1: <--CMD Pi Group 11 clk 0: cmdLeft -64 - cmdRight 63 N0.C1: <--CMD Pi Group 12 clk 0: cmdLeft -255 - cmdRight 255 N0.C1: <--CMD Pi Group 13 clk 0: cmdLeft -255 - cmdRight 255 N0.C1: <--CMD Pi Group 14 clk 0: cmdLeft -255 - cmdRight 255 N0.C1: <----clk 0 ckOffset 0: -(maxLeftOffset:-62 + minRightOffset:61) / 2 START_DATA_CMD 0n 1n 2n 3n 4n 5n 0s 1s 2s 3s 4s 5s N0.C1: 99 100 98 97 101 98 100 97 98 99 97 102 START_DATA_CLK 0 1 2 3 N0.C1: 0 0 0 0 START_DATA_CTL 0n 1n 2n 3n 4n 5n 6n 7n 8n 9n 0s 1s 2s 3s 4s 5s 6s 7s 8s 9s 10s N0.C1: 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 Entering no zone 8 Early CMD/CLK - 1367ms Lrdimm BS Phase RX -- Started Checkpoint Code: Socket 0, 0xB7, 0x14, 0x0000 Entering no zone 9 Lrdimm BS Phase RX - 0ms Lrdimm BS Cycle RX -- Started Checkpoint Code: Socket 0, 0xB7, 0x15, 0x0000 Entering no zone 10 Lrdimm BS Cycle RX - 0ms Lrdimm BS Delay RX -- Started Checkpoint Code: Socket 0, 0xB7, 0x16, 0x0000 Entering no zone 11 Lrdimm BS Delay RX - 0ms Receive Enable -- Started Checkpoint Code: Socket 0, 0xB7, 0x00, 0x0000 N0.D0.R0: RecEn Pi Scanning: Summary: Receive Enable Pi S0, Ch1, DIMM0, Rank0 ------------------------------------------------------------------------------------- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 1 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 2 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 3 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 4 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 5 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 6 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 7 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 8 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 9 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 10 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 11 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 12 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 13 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 14 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 15 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 16 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 17 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 18 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 19 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 20 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 21 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 22 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 23 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 24 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 25 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 26 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 27 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 28 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 29 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 30 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 31 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 32 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 33 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 34 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 35 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 36 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 37 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 38 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 39 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 0 40 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 0 41 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 0 42 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 43 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 44 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 45 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 46 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 47 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 48 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 49 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 50 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 51 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 52 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 53 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 54 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 55 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 56 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 57 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 58 0 0 0 1 1 1 0 0 1 0 0 0 0 1 1 0 0 1 59 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 60 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 61 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 62 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 63 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 64 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 65 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 66 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 67 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 68 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 69 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 70 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 71 0 0 0 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 72 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 73 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 74 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 75 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 76 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 77 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 78 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 79 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 0 0 1 80 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 0 0 1 81 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 0 0 1 82 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 83 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 84 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 85 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 86 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 87 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 88 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 89 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 90 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 91 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 92 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 93 0 0 1 1 0 1 1 0 0 0 0 1 1 0 1 1 0 0 94 0 0 1 1 0 1 1 0 0 0 0 1 1 0 1 1 0 0 95 0 0 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 96 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 97 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 98 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 99 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 100 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 101 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 102 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 103 0 1 1 0 0 0 1 1 0 0 0 1 1 0 1 1 1 0 104 0 1 1 0 0 0 1 1 0 0 0 1 1 0 1 1 0 0 105 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 1 0 106 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 107 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 108 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 109 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 110 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 111 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 112 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 113 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 114 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 115 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 116 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 117 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 118 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 119 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 120 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 121 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 122 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 123 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 124 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 125 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 126 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 127 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 ---------------------------------------------------------------------------- RE: 119 96 72 47 25 39 71 95 27 1 106 85 59 36 51 82 105 42 CP: 18 124 101 75 52 67 98 123 53 29 6 112 86 64 78 109 5 67 FE: 45 25 2 103 80 95 125 23 79 58 35 11 114 93 105 9 33 93 PW: 54 57 58 56 55 56 54 56 52 57 57 54 55 57 54 55 56 51 N0.C1.D0.R0.S00: Rec En Delay 18 N0.C1.D0.R0.S01: Rec En Delay 124 N0.C1.D0.R0.S02: Rec En Delay 101 N0.C1.D0.R0.S03: Rec En Delay 75 N0.C1.D0.R0.S04: Rec En Delay 52 N0.C1.D0.R0.S05: Rec En Delay 67 N0.C1.D0.R0.S06: Rec En Delay 98 N0.C1.D0.R0.S07: Rec En Delay 123 N0.C1.D0.R0.S08: Rec En Delay 53 N0.C1.D0.R0.S09: Rec En Delay 29 N0.C1.D0.R0.S10: Rec En Delay 6 N0.C1.D0.R0.S11: Rec En Delay 112 N0.C1.D0.R0.S12: Rec En Delay 86 N0.C1.D0.R0.S13: Rec En Delay 64 N0.C1.D0.R0.S14: Rec En Delay 78 N0.C1.D0.R0.S15: Rec En Delay 109 N0.C1.D0.R0.S16: Rec En Delay 5 N0.C1.D0.R0.S17: Rec En Delay 67 N0.C1.D0.R0: Round trip latency = 73 IO latency = 4 N0.D0.R0: Round trip latency N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 71 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 69 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 67 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 65 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 63 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 61 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 59 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 57 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 55 N0.C1.D0.R0: IO Latency = 6 zeroFlag = 0x10601, allZeros[1] = 0x3FFFF N0.C1.D0.R0.S00: Rec En Delay = 146 N0.C1.D0.R0.S09: Rec En Delay = 157 N0.C1.D0.R0.S10: Rec En Delay = 134 N0.C1.D0.R0.S16: Rec En Delay = 133 N0.C1.D0.R0: Round trip latency: Found all zeros Receive Enable Summary ------------------------ START_DATA_REC_EN_BASIC N0.C1.D0.R0.S00: Pi setting = 178 N0.C1.D0.R0.S01: Pi setting = 156 N0.C1.D0.R0.S02: Pi setting = 133 N0.C1.D0.R0.S03: Pi setting = 107 N0.C1.D0.R0.S04: Pi setting = 84 N0.C1.D0.R0.S05: Pi setting = 99 N0.C1.D0.R0.S06: Pi setting = 130 N0.C1.D0.R0.S07: Pi setting = 155 N0.C1.D0.R0.S08: Pi setting = 85 N0.C1.D0.R0.S09: Pi setting = 189 N0.C1.D0.R0.S10: Pi setting = 166 N0.C1.D0.R0.S11: Pi setting = 144 N0.C1.D0.R0.S12: Pi setting = 118 N0.C1.D0.R0.S13: Pi setting = 96 N0.C1.D0.R0.S14: Pi setting = 110 N0.C1.D0.R0.S15: Pi setting = 141 N0.C1.D0.R0.S16: Pi setting = 165 N0.C1.D0.R0.S17: Pi setting = 99 N0.C1.D0.R0: IO Latency = 6 N0.C1.D0.R0: Round Trip = 55 STOP_DATA_REC_EN_BASIC Starting Senseamp and ODT delay calculations ------------------------------------------------------------ N0.C1.S00: MaxRcven=178, New Senseamp/Odt delay=14 N0.C1.S01: MaxRcven=156, New Senseamp/Odt delay=14 N0.C1.S02: MaxRcven=133, New Senseamp/Odt delay=14 N0.C1.S03: MaxRcven=107, New Senseamp/Odt delay=14 N0.C1.S04: MaxRcven= 84, New Senseamp/Odt delay=14 N0.C1.S05: MaxRcven= 99, New Senseamp/Odt delay=14 N0.C1.S06: MaxRcven=130, New Senseamp/Odt delay=14 N0.C1.S07: MaxRcven=155, New Senseamp/Odt delay=14 N0.C1.S08: MaxRcven= 85, New Senseamp/Odt delay=14 N0.C1.S09: MaxRcven=189, New Senseamp/Odt delay=14 N0.C1.S10: MaxRcven=166, New Senseamp/Odt delay=14 N0.C1.S11: MaxRcven=144, New Senseamp/Odt delay=14 N0.C1.S12: MaxRcven=118, New Senseamp/Odt delay=14 N0.C1.S13: MaxRcven= 96, New Senseamp/Odt delay=14 N0.C1.S14: MaxRcven=110, New Senseamp/Odt delay=14 N0.C1.S15: MaxRcven=141, New Senseamp/Odt delay=14 N0.C1.S16: MaxRcven=165, New Senseamp/Odt delay=14 N0.C1.S17: MaxRcven= 99, New Senseamp/Odt delay=14 Entering no zone 12 Receive Enable - 1371ms Rx Dq/Dqs Basic -- Started Checkpoint Code: Socket 0, 0xB7, 0x03, 0x0000 N0.D0.R0: RxDqDqs Pi Scanning... Read DQ/DQS summary for socket:0 channel:1 dimm:0 rank:0 ------------------------------------------------------------------------------------- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 # # # # # # # # # # # # # # # # # # 1 # # # # # # # # # # # # # # # # # # 2 # # # # # # # # # # # # # # # # # # 3 # # # # # # # # # # # # # # # # # # 4 # # # # # # # # # # # # # # # # # # 5 # # # # # # # # # # # # # # # # # # 6 # # # # # # # # # . . # # # . # # # 7 # # # # # . # . # . . # # . . # . . 8 # # # # . . # . # . . . # . . . . . 9 # . # # . . # . . . . . . . . . . . 10 . . # # . . . . . . . . . . . . . . 11 . . # . . . . . . . . . . . . . . . 12 . . . . . . . . . . . . . . . . . . 13 . . . . . . . . . . . . . . . . . . 14 . . . . . . . . . . . . . . . . . . 15 . . . . . . . . . . . . . . . . . . 16 . . . . . . . . . . . . . . . . . . 17 . . . . . . . . . . . . . . . . . . 18 . . . . . . . . . . . . . . . . . . 19 . . . . . . . . . . . . . . . . . . 20 . . . . . . . . . . . . . . . . . . 21 . . . . . . . . . . . . . . . . . . 22 . . . . . . . . . . . . . . . . . . 23 . . . . . . . . . . . . . . . . . . 24 . . . . . . . . . . . . . . . . . . 25 . . . . . . . . . . . . . . . . . . 26 . . . . . . . . . . . . . . . . . . 27 . . . . . . . . . . . . . . . . . . 28 . . . . . . . . . . . . . . . . . . 29 . . . . . . . . . . . . . . . . . . 30 . . . . . . . . . . . . . . . . . . 31 . . . . . . . . . . . . . . . . . . 32 . . . . . . . . . . . . . . . . . . 33 . . . . . . . . . . . . . . . . . . 34 . . . . . . . . . . . . . . . . . . 35 . . . . . . . . . . . . . . . . . . 36 . . . . . . . . . . . . . . . . . . 37 . . . . . . . . . . . . . . . . . . 38 . . . . . . . . . . . . . . . . . . 39 . . . . . . . . . . . . . . . . . . 40 . . . . . . . . . . . . . . . . . . 41 . . . . . . . . . . . . . . . . . . 42 . . . . . . . . . . . . . . . . . . 43 . . . . . . . . . . . . . . . . . . 44 . . . . . . . . . . . . . . . . . . 45 . . . . . . . . . . . . . . . . . . 46 . . . . . . . . . . . . . . . . . . 47 . . . . . . . . . . . . . . . . . . 48 . . . . . . . . . . . . . . . . . . 49 . . . . . . . . . . . . . . . . . . 50 . . . . . . . . . . . . . . . . . . 51 . . . . . . . . . . . . . . . . . . 52 . . . . . . . . . . . . . . . . . . 53 . . . . . . . . . . . . . . . . . . 54 . . . . . . . . . . . . . . . . . . 55 . . . . . . . . . . . . . . . . . . 56 . . . . . . . . . . . . . . . . . . 57 . . . . . . . . . . . . . . . . . . 58 . . . . . . . . . . . . # # . . . . 59 . . . . . . . # . # . . # # . . . . 60 . . . # . . . # . # . # # # # # # # 61 . . . # # # # # . # # # # # # # # # 62 # # # # # # # # . # # # # # # # # # 63 # # # # # # # # # # # # # # # # # # 64 # # # # # # # # # # # # # # # # # # 65 # # # # # # # # # # # # # # # # # # 66 # # # # # # # # # # # # # # # # # # 67 # # # # # # # # # # # # # # # # # # 68 # # # # # # # # # # # # # # # # # # 69 # # # # # # # # # # # # # # # # # # 70 # # # # # # # # # # # # # # # # # # 71 # # # # # # # # # # # # # # # # # # ---------------------------------------------------------------------------- EE: 10 9 12 11 8 7 10 7 9 6 6 8 9 7 6 8 7 7 PP: 35 35 36 35 34 33 35 32 35 32 33 33 33 32 32 33 33 33 FE: 61 61 61 59 60 60 60 58 62 58 60 59 57 57 59 59 59 59 START_DATA_RX_DQS_BASIC N0.C1.D0.R0.S00: Pi = 35 N0.C1.D0.R0.S01: Pi = 35 N0.C1.D0.R0.S02: Pi = 36 N0.C1.D0.R0.S03: Pi = 35 N0.C1.D0.R0.S04: Pi = 34 N0.C1.D0.R0.S05: Pi = 33 N0.C1.D0.R0.S06: Pi = 35 N0.C1.D0.R0.S07: Pi = 32 N0.C1.D0.R0.S08: Pi = 35 N0.C1.D0.R0.S09: Pi = 32 N0.C1.D0.R0.S10: Pi = 33 N0.C1.D0.R0.S11: Pi = 33 N0.C1.D0.R0.S12: Pi = 33 N0.C1.D0.R0.S13: Pi = 32 N0.C1.D0.R0.S14: Pi = 32 N0.C1.D0.R0.S15: Pi = 33 N0.C1.D0.R0.S16: Pi = 33 N0.C1.D0.R0.S17: Pi = 33 STOP_DATA_RX_DQS_BASIC Entering no zone 13 Rx Dq/Dqs Basic - 755ms Lrdimm BS Fine WL -- Started Checkpoint Code: Socket 0, 0xB7, 0x17, 0x0000 Entering no zone 14 Lrdimm BS Fine WL - 0ms Lrdimm BS Coarse WL -- Started Checkpoint Code: Socket 0, 0xB7, 0x18, 0x0000 Entering no zone 15 Lrdimm BS Coarse WL - 0ms Lrdimm BS Delay TX -- Started Checkpoint Code: Socket 0, 0xB7, 0x1C, 0x0000 Entering no zone 16 Lrdimm BS Delay TX - 0ms Write Leveling -- Started Checkpoint Code: Socket 0, 0xB7, 0x01, 0x0000 N0.C1: ODT Override: 0x1 N0.D0.R0: Write Leveling Pi Scanning... Summary: Write Leveling Pi S0, Ch1, DIMM0, Rank0 --------------------------------------- 0 1 2 3 4 5 6 7 8 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 4 1 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 1 6 1 1 1 1 1 1 1 1 1 7 1 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 1 9 1 1 1 1 0 1 1 1 0 10 1 1 1 1 0 1 1 1 0 11 1 1 1 1 0 1 1 1 0 12 1 1 1 1 0 1 1 1 0 13 1 1 1 1 0 1 1 1 0 14 1 1 1 1 0 1 1 1 0 15 1 1 1 1 0 1 1 1 0 16 1 1 1 1 0 1 1 1 0 17 1 1 1 1 0 1 1 1 0 18 1 1 1 1 0 1 1 1 0 19 1 1 1 1 0 1 1 1 0 20 1 1 1 1 0 0 1 1 0 21 1 1 1 1 0 0 1 1 0 22 1 1 1 0 0 0 1 1 0 23 1 1 1 0 0 0 1 1 0 24 1 1 1 0 0 0 1 1 0 25 1 1 1 0 0 0 1 1 0 26 1 1 0 0 0 0 1 1 0 27 1 1 0 0 0 0 1 1 0 28 1 1 0 0 0 0 1 1 0 29 1 1 0 0 0 0 1 1 0 30 1 1 0 0 0 0 1 1 0 31 1 1 0 0 0 0 1 1 0 32 1 1 0 0 0 0 1 1 0 33 1 1 0 0 0 0 1 1 0 34 1 1 0 0 0 0 0 1 0 35 1 1 0 0 0 0 0 0 0 36 1 1 0 0 0 0 0 0 0 37 1 1 0 0 0 0 0 0 0 38 1 0 0 0 0 0 0 0 0 39 1 0 0 0 0 0 0 0 0 40 1 0 0 0 0 0 0 0 0 41 1 0 0 0 0 0 0 0 0 42 1 0 0 0 0 0 0 0 0 43 1 0 0 0 0 0 0 0 0 44 1 0 0 0 0 0 0 0 0 45 1 0 0 0 0 0 0 0 0 46 1 0 0 0 0 0 0 0 0 47 1 0 0 0 0 0 0 0 0 48 1 0 0 0 0 0 0 0 0 49 0 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 51 0 0 0 0 0 0 0 0 0 52 0 0 0 0 0 0 0 0 0 53 0 0 0 0 0 0 0 0 0 54 0 0 0 0 0 0 0 0 0 55 0 0 0 0 0 0 0 0 0 56 0 0 0 0 0 0 0 0 0 57 0 0 0 0 0 0 0 0 0 58 0 0 0 0 0 0 0 0 0 59 0 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 61 0 0 0 0 0 0 0 0 0 62 0 0 0 0 0 0 0 0 0 63 0 0 0 0 0 0 0 0 0 64 0 0 0 0 0 0 0 0 0 65 0 0 0 0 0 0 0 0 0 66 0 0 0 0 0 0 0 0 0 67 0 0 0 0 0 0 0 0 0 68 0 0 0 0 0 0 0 0 0 69 0 0 0 0 0 0 0 0 0 70 0 0 0 0 0 0 0 0 0 71 0 0 0 0 0 0 0 0 0 72 0 0 0 0 0 0 0 0 0 73 0 0 0 0 1 0 0 0 1 74 0 0 0 0 1 0 0 0 1 75 0 0 0 0 1 0 0 0 1 76 0 0 0 0 1 0 0 0 1 77 0 0 0 0 1 0 0 0 1 78 0 0 0 0 1 0 0 0 1 79 0 0 0 0 1 0 0 0 1 80 0 0 0 0 1 0 0 0 1 81 0 0 0 0 1 0 0 0 1 82 0 0 0 0 1 0 0 0 1 83 0 0 0 0 1 0 0 0 1 84 0 0 0 0 1 0 0 0 1 85 0 0 0 0 1 0 0 0 1 86 0 0 0 1 1 1 0 0 1 87 0 0 0 1 1 1 0 0 1 88 0 0 0 1 1 1 0 0 1 89 0 0 0 1 1 1 0 0 1 90 0 0 1 1 1 1 0 0 1 91 0 0 1 1 1 1 0 0 1 92 0 0 1 1 1 1 0 0 1 93 0 0 1 1 1 1 0 0 1 94 0 0 1 1 1 1 0 0 1 95 0 0 1 1 1 1 0 0 1 96 0 0 1 1 1 1 0 0 1 97 0 0 1 1 1 1 1 0 1 98 0 0 1 1 1 1 1 0 1 99 0 0 1 1 1 1 1 0 1 100 0 0 1 1 1 1 1 0 1 101 0 0 1 1 1 1 1 0 1 102 0 0 1 1 1 1 1 1 1 103 0 1 1 1 1 1 1 1 1 104 0 1 1 1 1 1 1 1 1 105 0 1 1 1 1 1 1 1 1 106 0 1 1 1 1 1 1 1 1 107 0 1 1 1 1 1 1 1 1 108 0 1 1 1 1 1 1 1 1 109 0 1 1 1 1 1 1 1 1 110 0 1 1 1 1 1 1 1 1 111 0 1 1 1 1 1 1 1 1 112 0 1 1 1 1 1 1 1 1 113 0 1 1 1 1 1 1 1 1 114 0 1 1 1 1 1 1 1 1 115 1 1 1 1 1 1 1 1 1 116 1 1 1 1 1 1 1 1 1 117 1 1 1 1 1 1 1 1 1 118 1 1 1 1 1 1 1 1 1 119 1 1 1 1 1 1 1 1 1 120 1 1 1 1 1 1 1 1 1 121 1 1 1 1 1 1 1 1 1 122 1 1 1 1 1 1 1 1 1 123 1 1 1 1 1 1 1 1 1 124 1 1 1 1 1 1 1 1 1 125 1 1 1 1 1 1 1 1 1 126 1 1 1 1 1 1 1 1 1 127 1 1 1 1 1 1 1 1 1 ---------------------------------------------------------------------------- RE: 179 167 154 150 137 150 161 166 137 CP: 18 6 122 118 105 117 1 4 105 FE: 177 166 154 150 137 148 162 163 137 PW: 62 63 64 64 64 62 65 61 64 START_DATA_WR_LVL_BASIC N0.C1.D0.R0.S00: WrLevel Delay = 179 N0.C1.D0.R0.S01: WrLevel Delay = 167 N0.C1.D0.R0.S02: WrLevel Delay = 154 N0.C1.D0.R0.S03: WrLevel Delay = 150 N0.C1.D0.R0.S04: WrLevel Delay = 137 N0.C1.D0.R0.S05: WrLevel Delay = 150 N0.C1.D0.R0.S06: WrLevel Delay = 161 N0.C1.D0.R0.S07: WrLevel Delay = 166 N0.C1.D0.R0.S08: WrLevel Delay = 137 STOP_DATA_WR_LVL_BASIC Entering no zone 17 Write Leveling - 608ms Write Fly By -- Started Checkpoint Code: Socket 0, 0xB7, 0x02, 0x0000 N0.D0.R0: Current DQS offset delay is -1 DClks (DQS offset index=0) N0.D0.R0: Current DQS offset delay is 0 DClks (DQS offset index=1) N0.C1.D0.R0: Write Tx DQ/DQS Flyby delay: GlobalByteOff = 0, CRAddDelay = 0 Dqs Index Dqs Offset (DClks) DqOffset (PI) Prev Pass Current Error strobePass ------------------------------------------------------------------------------------------------------------------- N0.C1.D0.R0: 0 1 0 NO 0x001FF 0x00000 N0.C1.D0.R0: 0 1 -4 NO 0x001FF 0x00000 N0.C1.D0.R0: 0 1 4 NO 0x001FF 0x00000 N0.C1.D0.R0: 0 1 -8 NO 0x001FF 0x00000 N0.C1.D0.R0: 0 1 8 NO 0x001FF 0x00000 N0.C1.D0.R0: 0 1 -12 NO 0x001FF 0x00000 N0.C1.D0.R0: 0 1 12 NO 0x001FF 0x00000 N0.C1.D0.R0: 0 1 -20 NO 0x001FF 0x00000 N0.C1.D0.R0: 0 1 20 NO 0x001FF 0x00000 N0.C1.D0.R0: 0 1 -40 NO 0x001FF 0x00000 N0.C1.D0.R0: 0 1 40 NO 0x001FF 0x00000 N0.D0.R0: Current DQS offset delay is 1 DClks (DQS offset index=2) N0.C1.D0.R0: Write Tx DQ/DQS Flyby delay: GlobalByteOff = 0, CRAddDelay = 1 Dqs Index Dqs Offset (DClks) DqOffset (PI) Prev Pass Current Error strobePass ------------------------------------------------------------------------------------------------------------------- N0.C1.D0.R0: 1 2 0 NO 0x001FF 0x00000 N0.C1.D0.R0: 1 2 -4 NO 0x001FF 0x00000 N0.C1.D0.R0: 1 2 4 NO 0x001FF 0x00000 N0.C1.D0.R0: 1 2 -8 NO 0x001FF 0x00000 N0.C1.D0.R0: 1 2 8 NO 0x001FF 0x00000 N0.C1.D0.R0: 1 2 -12 NO 0x001FF 0x00000 N0.C1.D0.R0: 1 2 12 NO 0x001FF 0x00000 N0.C1.D0.R0: 1 2 -20 NO 0x001FF 0x00000 N0.C1.D0.R0: 1 2 20 NO 0x001FF 0x00000 N0.C1.D0.R0: 1 2 -40 NO 0x001FF 0x00000 N0.C1.D0.R0: 1 2 40 NO 0x001FF 0x00000 N0.D0.R0: Current DQS offset delay is 2 DClks (DQS offset index=3) N0.C1.D0.R0: Write Tx DQ/DQS Flyby delay: GlobalByteOff = 0, CRAddDelay = 2 Dqs Index Dqs Offset (DClks) DqOffset (PI) Prev Pass Current Error strobePass ------------------------------------------------------------------------------------------------------------------- N0.C1.D0.R0: 2 3 0 NO 0x00000 0x001FF -------------------------------------------------------------------------------- N0.C1.D0.R0: Current values: GlobalByteOff = 0 DClks, CRAddDelay[1] = 2 DClks N0.C1.D0.R0: Refining TargetOffset for all byte lanes... TgtOffset ByteOff -------------------------------------------------------------------------------- N0.C1.D0.R0.S00: 2 DClks 2 DClks N0.C1.D0.R0.S01: 2 DClks 2 DClks N0.C1.D0.R0.S02: 2 DClks 2 DClks N0.C1.D0.R0.S03: 2 DClks 2 DClks N0.C1.D0.R0.S04: 2 DClks 2 DClks N0.C1.D0.R0.S05: 2 DClks 2 DClks N0.C1.D0.R0.S06: 2 DClks 2 DClks N0.C1.D0.R0.S07: 2 DClks 2 DClks N0.C1.D0.R0.S08: 2 DClks 2 DClks TxDq (PI) TxDqs (PI) PI Offset -------------------------------------------------------------------------------- N0.C1.D0.R0.S00: 211 179 0 N0.C1.D0.R0.S01: 199 167 0 N0.C1.D0.R0.S02: 186 154 0 N0.C1.D0.R0.S03: 182 150 0 N0.C1.D0.R0.S04: 169 137 0 N0.C1.D0.R0.S05: 182 150 0 N0.C1.D0.R0.S06: 193 161 0 N0.C1.D0.R0.S07: 198 166 0 N0.C1.D0.R0.S08: 169 137 0 START_DATA_WR_LVL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1: t_cwl_adj = 2 N0.C1.D0.R0: 179 167 154 150 137 150 161 166 137 Entering no zone 18 Write Fly By - 336ms Tx Dq Basic -- Started Checkpoint Code: Socket 0, 0xB7, 0x04, 0x0000 N0.D0.R0: TxDqDqs Pi Scanning... Write DQ/DQS summary for socket:0 channel:1 dimm:0 rank:0 ------------------------------------------------------------------------------------- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 # # # # # # # # # # # # # # # # # # 1 # # # # # # # # # # # # # # # # # # 2 # # # # # # # # # # # # # # # # # # 3 # # # # # # # # # # # # # # # # # # 4 # # # # # # # # # # # # # # # # # # 5 # # # # # # # # # # # # # # # # # # 6 # # # # # # # # # # # # # # # # # # 7 # # # # # # # # # # # # # # # # # # 8 # # # # # # # # # # # # # # # # # # 9 # # # # # # # # # # # # # # # # # # 10 # # # # # # # # # # # # # # # # # # 11 # # # # # # # # # # # # # # # # # # 12 # # # # # # # # # # # # # # # # # # 13 # # # # # # # # # # # # # # # # # # 14 # # # # # # # # # # # # # # # # # # 15 # # # # # # # # # # # # # # # # # # 16 # # # # # # # # # # # # # # # # # # 17 # # # # # # # # # # # # # # # # # # 18 # # # # # # # # # # # # # # # # # # 19 # # # # # # # # # # # # # # # # # # 20 # # # # # # # # # # # # # # # # # # 21 # # # # # # # # # # # # # # # # # # 22 # # # # # # # # # # # # # # # # # # 23 # # # # # # # # # # # # # # # # # # 24 # # # # # # # # # # # # # # # # # # 25 # # # # # # # # # # # # # # # # # # 26 # # # # # # # # # # # # # # # # # # 27 # # # # # # # # # # # # # # # # # # 28 # # # # # # # # # # # # # # # # # # 29 # # # # # # # # # # # # # # # # # # 30 # # # # # # # # # # # # # # # # # # 31 # # # # # # # # # # # # # # # # # # 32 # # # # # # # # # # # # # # # # # # 33 # # # # # # # # # # # # # # # # # # 34 # # # # # # # # # # # # # # # # # # 35 # # # # # # # # # # # # # # # # # # 36 # # # # # # # # # # # # # # # # # # 37 . # # # # # # # # # # # # # # # # # 38 . . . . # . . # # # # # # # # # # # 39 . . . . # . . # . # # # # # # # # # 40 . . . . . . . . . # # # # # # # # # 41 . . . . . . . . . # # # # # # # # # 42 . . . . . . . . . . # # # # # # # # 43 . . . . . . . . . . # # # # # # # # 44 . . . . . . . . . . # . # # # # . # 45 . . . . . . . . . . . . # . # . . # 46 . . . . . . . . . . . . . . . . . # 47 . . . . . . . . . . . . . . . . . . 48 . . . . . . . . . . . . . . . . . . 49 . . . . . . . . . . . . . . . . . . 50 . . . . . . . . . . . . . . . . . . 51 . . . . . . . . . . . . . . . . . . 52 . . . . . . . . . . . . . . . . . . 53 . . . . . . . . . . . . . . . . . . 54 . . . . . . . . . . . . . . . . . . 55 . . . . . . . . . . . . . . . . . . 56 . . . . . . . . . . . . . . . . . . 57 . . . . . . . . . . . . . . . . . . 58 . . . . . . . . . . . . . . . . . . 59 . . . . . . . . . . . . . . . . . . 60 . . . . . . . . . . . . . . . . . . 61 . . . . . . . . . . . . . . . . . . 62 . . . . . . . . . . . . . . . . . . 63 . . . . . . . . . . . . . . . . . . 64 . . . . . . . . . . . . . . . . . . 65 . . . . . . . . . . . . . . . . . . 66 . . . . . . . . . . . . . . . . . . 67 . . . . . . . . . . . . . . . . . . 68 . . . . . . . . . . . . . . . . . . 69 . . . . . . . . . . . . . . . . . . 70 . . . . . . . . . . . . . . . . . . 71 . . . . . . . . . . . . . . . . . . 72 . . . . . . . . . . . . . . . . . . 73 . . . . . . . . . . . . . . . . . . 74 . . . . . . . . . . . . . . . . . . 75 . . . . . . . . . . . . . . . . . . 76 . . . . . . . . . . . . . . . . . . 77 . . . . . . . . . . . . . . . . . . 78 . . . . . . . . . . . . . . . . . . 79 . . . . . . . . . . . . . . . . . . 80 . . . . . . . . . . . . . . . . . . 81 . . . . . . . . . . . . . . . . . . 82 . . . . . . . . . . . . . . . . . . 83 . . . . . . . . . . . . . . . . . . 84 . . . . . . . . . . . . . . . . . . 85 . . . . . . . . . . . . . . . . . . 86 . . . . . . . . . . . . . . . . . . 87 . . . . . . . . . . . . . . . . . . 88 . . . . . . . . . . . . . . . . . . 89 . . . . . . . . . . . . . . . . . . 90 . . . . . . . . . . . . . . . . . . 91 . . . . . . . . . . . . . . . . . . 92 . . . . . . . . . . . . . . . . . . 93 . . . . . . . . . . . . . . . . . . 94 . . . . . . . . . . . . . . . . . . 95 . . . . . . . . . . . . . . . . . . 96 # . . . . . # . . . . . . . . . . . 97 # . # # . # # . . . . . # . . . . . 98 # # # # . # # # # # . . # . . . . . 99 # # # # # # # # # # . # # . . . . . 100 # # # # # # # # # # . # # . # . . # 101 # # # # # # # # # # # # # # # # # # 102 # # # # # # # # # # # # # # # # # # 103 # # # # # # # # # # # # # # # # # # 104 # # # # # # # # # # # # # # # # # # 105 # # # # # # # # # # # # # # # # # # 106 # # # # # # # # # # # # # # # # # # 107 # # # # # # # # # # # # # # # # # # 108 # # # # # # # # # # # # # # # # # # 109 # # # # # # # # # # # # # # # # # # 110 # # # # # # # # # # # # # # # # # # 111 # # # # # # # # # # # # # # # # # # 112 # # # # # # # # # # # # # # # # # # 113 # # # # # # # # # # # # # # # # # # 114 # # # # # # # # # # # # # # # # # # 115 # # # # # # # # # # # # # # # # # # 116 # # # # # # # # # # # # # # # # # # 117 # # # # # # # # # # # # # # # # # # 118 # # # # # # # # # # # # # # # # # # 119 # # # # # # # # # # # # # # # # # # 120 # # # # # # # # # # # # # # # # # # 121 # # # # # # # # # # # # # # # # # # 122 # # # # # # # # # # # # # # # # # # 123 # # # # # # # # # # # # # # # # # # 124 # # # # # # # # # # # # # # # # # # 125 # # # # # # # # # # # # # # # # # # 126 # # # # # # # # # # # # # # # # # # 127 # # # # # # # # # # # # # # # # # # ---------------------------------------------------------------------------- EE: 184 173 160 156 145 156 167 174 144 189 180 166 164 150 164 174 178 152 PP: 213 202 189 185 174 185 195 202 173 216 207 193 189 177 190 201 206 178 FE: 242 232 218 214 203 214 224 231 202 244 235 220 214 205 217 229 234 204 START_DATA_TX_DQ_BASIC N0.C1.D0.R0.S00: TxDqDqs: Pi = 213 N0.C1.D0.R0.S01: TxDqDqs: Pi = 202 N0.C1.D0.R0.S02: TxDqDqs: Pi = 189 N0.C1.D0.R0.S03: TxDqDqs: Pi = 185 N0.C1.D0.R0.S04: TxDqDqs: Pi = 174 N0.C1.D0.R0.S05: TxDqDqs: Pi = 185 N0.C1.D0.R0.S06: TxDqDqs: Pi = 195 N0.C1.D0.R0.S07: TxDqDqs: Pi = 202 N0.C1.D0.R0.S08: TxDqDqs: Pi = 173 N0.C1.D0.R0.S09: TxDqDqs: Pi = 216 N0.C1.D0.R0.S10: TxDqDqs: Pi = 207 N0.C1.D0.R0.S11: TxDqDqs: Pi = 193 N0.C1.D0.R0.S12: TxDqDqs: Pi = 189 N0.C1.D0.R0.S13: TxDqDqs: Pi = 177 N0.C1.D0.R0.S14: TxDqDqs: Pi = 190 N0.C1.D0.R0.S15: TxDqDqs: Pi = 201 N0.C1.D0.R0.S16: TxDqDqs: Pi = 206 N0.C1.D0.R0.S17: TxDqDqs: Pi = 178 STOP_DATA_TX_DQ_BASIC Entering no zone 19 Tx Dq Basic - 1281ms PPR Flow -- Started Checkpoint Code: Socket 0, 0xB7, 0x36, 0x0000 PPR Flow - 0ms Wr Early Vref Centering -- Started Checkpoint Code: Socket 0, 0xB7, 0x32, 0x0000 Previous Settings START_DATA_TxVref 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 82 82 82 82 82 82 82 82 82 START_DATA_TX_DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 213 202 189 185 174 185 195 202 173 216 207 193 189 177 190 201 206 178 N0.C1: Cycling through ranks to check eye width for 2DPC margining W/A!! N0.C1.D0.R0: Checking for eye widths!! Current VREF offset is 0 N0.C1.D0.R0: txVrefSafe = 0x54 New Settings START_DATA_TxVref 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 84 84 84 84 84 84 84 84 84 START_DATA_TX_DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 212 201 187 183 173 184 195 201 172 216 206 191 188 177 190 200 206 177 Wr Early Vref Centering - 114ms Rd Early Vref Centering -- Started Checkpoint Code: Socket 0, 0xB7, 0x31, 0x0000 Previous Settings START_DATA_RxVref N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 START_DATA_RX_DQS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 35 35 36 35 34 33 35 32 35 32 33 33 33 32 32 33 33 33 N0.C1: Cycling through ranks to check eye width for 2DPC margining W/A!! N0.C1.D0.R0: Checking for eye widths!! Current VREF offset is 0 New Settings START_DATA_RxVref N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 START_DATA_RX_DQS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 34 32 33 32 31 32 33 31 33 30 30 30 31 29 31 30 30 29 Rd Early Vref Centering - 197ms CMD Vref Centering -- Started Checkpoint Code: Socket 0, 0xB7, 0x24, 0x0000 N0.C1.D0.R0: High = 31 - Low = -31 N0.C1: Composite High = 31 - Composite Low = -31 final_offset = 0 Reset All Channels JEDEC Init N0.C1.D0.R0: Write RC00 = 0x00 N0.C1.D0.R0: Write RC01 = 0x00 N0.C1.D0.R0: Write RC02 = 0x00 N0.C1.D0.R0: Write RC03 = 0x00 N0.C1.D0.R0: Write RC04 = 0x00 N0.C1.D0.R0: Write RC05 = 0x00 N0.C1.D0.R0: Write RC40 = 0x0F N0.C1.D0.R0: Write RC08 = 0x0B N0.C1.D0.R0: Write RC0A = 0x02 N0.C1.D0.R0: Write RC0B = 0x08 N0.C1.D0.R0: Write RC0C = 0x00 N0.C1.D0.R0: Write RC0E = 0x00 N0.C1.D0.R0: Write RC0F = 0x00 N0.C1.D0.R0: Write RC30 = 0x2C N0.C1.D0.R0: Write RC40 = 0x26 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x27 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x28 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x29 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x21 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x22 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x23 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x24 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x25 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC09 = 0x0C N0.C1.D0.R0: Write RC0D = 0x04 N0.C1: Issue ZQCL N0.C4: (compHigh + compLow)/2 = 32 START_DATA_CMD_VREF_CENTERING N0.C0: Applying offset of 0... N0.C1: Applying offset of 0... N0.C2: Applying offset of 0... N0.C3: Applying offset of 0... STOP_DATA_CMD_VREF_CENTERING CMD Vref Centering - 183ms Late Cmd/Clk -- Started Checkpoint Code: Socket 0, 0xB7, 0x05, 0x0000 START_CMD_CLK_PER_GROUP_FINAL N0: Calling GetMargins for CmdAll C1.D0.R0: Platform Group = CmdAll C1.D0.R0: Found CMD Pi group: 0 side 0 C1.D0.R0: cmdLeft[0][0] = -56 : cmdRight[0][0] = 52 C1.D0.R0: Found CMD Pi group: 0 side 1 C1.D0.R0: cmdLeft[1][0] = -56 : cmdRight[1][0] = 52 C1.D0.R0: Found CMD Pi group: 1 side 0 C1.D0.R0: cmdLeft[2][0] = -56 : cmdRight[2][0] = 52 C1.D0.R0: Found CMD Pi group: 1 side 1 C1.D0.R0: cmdLeft[3][0] = -56 : cmdRight[3][0] = 52 C1.D0.R0: Found CMD Pi group: 2 side 0 C1.D0.R0: cmdLeft[4][0] = -56 : cmdRight[4][0] = 52 C1.D0.R0: Found CMD Pi group: 2 side 1 C1.D0.R0: cmdLeft[5][0] = -56 : cmdRight[5][0] = 52 C1.D0.R0: Found CMD Pi group: 3 side 0 C1.D0.R0: cmdLeft[6][0] = -56 : cmdRight[6][0] = 52 C1.D0.R0: Found CMD Pi group: 3 side 1 C1.D0.R0: cmdLeft[7][0] = -56 : cmdRight[7][0] = 52 C1.D0.R0: Found CMD Pi group: 4 side 0 C1.D0.R0: cmdLeft[8][0] = -56 : cmdRight[8][0] = 52 C1.D0.R0: Found CMD Pi group: 4 side 1 C1.D0.R0: cmdLeft[9][0] = -56 : cmdRight[9][0] = 52 C1.D0.R0: Found CMD Pi group: 5 side 0 C1.D0.R0: cmdLeft[10][0] = -56 : cmdRight[10][0] = 52 C1.D0.R0: Found CMD Pi group: 5 side 1 C1.D0.R0: cmdLeft[11][0] = -56 : cmdRight[11][0] = 52 N0.C1: CMD Pi Group 0 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 1 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 2 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 3 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 4 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 5 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 6 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 7 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 8 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 9 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 10 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 11 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 0: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 1: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 2: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 3: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 4: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 5: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 6: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 7: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 8: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 9: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 10: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 11: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: <--CMD Pi Group 0 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 1 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 2 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 3 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 4 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 5 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 6 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 7 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 8 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 9 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 10 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 11 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <----clk 0 ckOffset 0: -(maxLeftOffset:-54 + minRightOffset:54) / 2 STOP_CMD_CLK_PER_GROUP_FINAL Reset All Channels JEDEC Init N0.C1.D0.R0: Write RC00 = 0x00 N0.C1.D0.R0: Write RC01 = 0x00 N0.C1.D0.R0: Write RC02 = 0x00 N0.C1.D0.R0: Write RC03 = 0x00 N0.C1.D0.R0: Write RC04 = 0x00 N0.C1.D0.R0: Write RC05 = 0x00 N0.C1.D0.R0: Write RC40 = 0x0F N0.C1.D0.R0: Write RC08 = 0x0B N0.C1.D0.R0: Write RC0A = 0x02 N0.C1.D0.R0: Write RC0B = 0x08 N0.C1.D0.R0: Write RC0C = 0x00 N0.C1.D0.R0: Write RC0E = 0x00 N0.C1.D0.R0: Write RC0F = 0x00 N0.C1.D0.R0: Write RC30 = 0x2C N0.C1.D0.R0: Write RC40 = 0x26 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x27 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x28 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x29 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x21 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x22 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x23 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x24 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x25 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC09 = 0x0C N0.C1.D0.R0: Write RC0D = 0x04 N0.C1: Issue ZQCL Late Cmd/Clk - 497ms Tx Eq -- Started Checkpoint Code: Socket 0, 0xB7, 0x1B, 0x0000 Printing initialized array of cached values... Tx Eq Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C1.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting 0 Params [0] 0x0 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 61 60 61 58 61 61 61 61 59 61 60 61 58 61 61 61 61 59 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 50 49 47 48 50 53 48 50 47 50 49 47 48 50 53 48 50 47 Setting 1 Params [0] 0x2 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 61 60 61 58 61 61 61 61 59 61 60 61 58 61 61 61 61 59 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 50 49 47 49 51 53 48 51 47 50 49 47 49 51 53 48 51 47 Setting 2 Params [0] 0x4 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 61 60 61 59 61 61 61 61 60 61 60 61 59 61 61 61 61 60 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 50 49 49 49 51 53 48 52 47 50 49 49 49 51 53 48 52 47 Setting 3 Params [0] 0x6 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 61 61 61 59 61 61 61 61 60 61 61 61 59 61 61 61 61 60 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 51 50 49 49 52 54 49 53 48 51 50 49 49 52 54 49 53 48 Setting 4 Params [0] 0x8 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 61 61 61 59 61 61 61 61 60 61 61 61 59 61 61 61 61 60 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 50 50 49 50 52 54 49 53 47 50 50 49 50 52 54 49 53 47 Setting 5 Params [0] 0xA Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 61 61 61 60 61 61 61 61 60 61 61 61 60 61 61 61 61 60 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 50 51 49 50 51 54 49 52 48 50 51 49 50 51 54 49 52 48 Setting 6 Params [0] 0xC Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 61 60 61 59 61 61 60 61 58 61 60 61 59 61 61 60 61 58 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 50 49 49 48 51 53 49 52 48 50 49 49 48 51 53 49 52 48 Setting 7 Params [0] 0xE Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 59 57 59 57 59 60 58 60 54 59 57 59 57 59 60 58 60 54 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 49 49 48 48 50 52 48 52 47 49 49 48 48 50 52 48 52 47 Setting 8 Params [0] 0x10 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 58 54 55 53 56 59 55 58 51 58 54 55 53 56 59 55 58 51 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 48 49 48 49 51 52 48 51 47 48 49 48 49 51 52 48 51 47 Setting 9 Params [0] 0x12 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 55 52 53 50 54 56 53 55 50 55 52 53 50 54 56 53 55 50 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 48 48 48 48 50 52 48 51 47 48 48 48 48 50 52 48 51 47 Setting 10 Params [0] 0x14 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 50 47 48 46 49 50 48 49 45 50 47 48 46 49 50 48 49 45 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 47 48 47 47 49 52 47 50 46 47 48 47 47 49 52 47 50 46 Setting 11 Params [0] 0x16 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 46 45 45 44 45 48 45 47 43 46 45 45 44 45 48 45 47 43 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 47 48 47 47 49 51 47 50 45 47 48 47 47 49 51 47 50 45 Setting 12 Params [0] 0x18 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 42 43 41 44 44 43 44 39 45 42 43 41 44 44 43 44 39 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 46 46 46 46 49 50 47 49 45 46 46 46 46 49 50 47 49 45 Setting 13 Params [0] 0x1A Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 43 43 41 44 44 43 44 40 45 43 43 41 44 44 43 44 40 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 46 48 46 46 49 51 47 49 45 46 48 46 46 49 51 47 49 45 Setting 14 Params [0] 0x1C Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 43 43 41 44 44 42 44 39 45 43 43 41 44 44 42 44 39 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 46 46 46 46 49 50 47 49 45 46 46 46 46 49 50 47 49 45 Setting 15 Params [0] 0x1E Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 43 43 41 44 44 43 45 39 45 43 43 41 44 44 43 45 39 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 48 46 46 48 50 46 49 45 45 48 46 46 48 50 46 49 45 Power TrendLine Calculation N0.C1.D0.R0.S00: minPower = 0 : maxPower = 1500 AveOfMax = 555 : maxMarginAllGroups = 610 : slope = 0 FindOptimalTradeoff for Strobe 0: N0.C1.D0.R0.S01: minPower = 0 : maxPower = 1500 AveOfMax = 555 : maxMarginAllGroups = 610 : slope = 0 FindOptimalTradeoff for Strobe 1: N0.C1.D0.R0.S02: minPower = 0 : maxPower = 1500 AveOfMax = 550 : maxMarginAllGroups = 610 : slope = 0 FindOptimalTradeoff for Strobe 2: N0.C1.D0.R0.S03: minPower = 0 : maxPower = 1500 AveOfMax = 540 : maxMarginAllGroups = 590 : slope = 0 FindOptimalTradeoff for Strobe 3: N0.C1.D0.R0.S04: minPower = 0 : maxPower = 1500 AveOfMax = 560 : maxMarginAllGroups = 610 : slope = 0 FindOptimalTradeoff for Strobe 4: N0.C1.D0.R0.S05: minPower = 0 : maxPower = 1500 AveOfMax = 575 : maxMarginAllGroups = 610 : slope = 0 FindOptimalTradeoff for Strobe 5: N0.C1.D0.R0.S06: minPower = 0 : maxPower = 1500 AveOfMax = 550 : maxMarginAllGroups = 610 : slope = 0 FindOptimalTradeoff for Strobe 6: N0.C1.D0.R0.S07: minPower = 0 : maxPower = 1500 AveOfMax = 565 : maxMarginAllGroups = 610 : slope = 0 FindOptimalTradeoff for Strobe 7: N0.C1.D0.R0.S08: minPower = 0 : maxPower = 1500 AveOfMax = 535 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 8: N0.C1.D0.R0.S09: minPower = 0 : maxPower = 1500 AveOfMax = 555 : maxMarginAllGroups = 610 : slope = 0 FindOptimalTradeoff for Strobe 9: N0.C1.D0.R0.S10: minPower = 0 : maxPower = 1500 AveOfMax = 555 : maxMarginAllGroups = 610 : slope = 0 FindOptimalTradeoff for Strobe 10: N0.C1.D0.R0.S11: minPower = 0 : maxPower = 1500 AveOfMax = 550 : maxMarginAllGroups = 610 : slope = 0 FindOptimalTradeoff for Strobe 11: N0.C1.D0.R0.S12: minPower = 0 : maxPower = 1500 AveOfMax = 540 : maxMarginAllGroups = 590 : slope = 0 FindOptimalTradeoff for Strobe 12: N0.C1.D0.R0.S13: minPower = 0 : maxPower = 1500 AveOfMax = 560 : maxMarginAllGroups = 610 : slope = 0 FindOptimalTradeoff for Strobe 13: N0.C1.D0.R0.S14: minPower = 0 : maxPower = 1500 AveOfMax = 575 : maxMarginAllGroups = 610 : slope = 0 FindOptimalTradeoff for Strobe 14: N0.C1.D0.R0.S15: minPower = 0 : maxPower = 1500 AveOfMax = 550 : maxMarginAllGroups = 610 : slope = 0 FindOptimalTradeoff for Strobe 15: N0.C1.D0.R0.S16: minPower = 0 : maxPower = 1500 AveOfMax = 565 : maxMarginAllGroups = 610 : slope = 0 FindOptimalTradeoff for Strobe 16: N0.C1.D0.R0.S17: minPower = 0 : maxPower = 1500 AveOfMax = 535 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 17: START_OPTIMAL_TRAINING_RESULTS Tx Eq Per Strobe Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C1.D0.R0: 0 8 6 6 4 8 8 4 6 0 8 6 6 4 8 8 4 6 END_OPTIMAL_TRAINING_RESULTS Reset All Channels JEDEC Init N0.C1.D0.R0: Write RC00 = 0x00 N0.C1.D0.R0: Write RC01 = 0x00 N0.C1.D0.R0: Write RC02 = 0x00 N0.C1.D0.R0: Write RC03 = 0x00 N0.C1.D0.R0: Write RC04 = 0x00 N0.C1.D0.R0: Write RC05 = 0x00 N0.C1.D0.R0: Write RC40 = 0x0F N0.C1.D0.R0: Write RC08 = 0x0B N0.C1.D0.R0: Write RC0A = 0x02 N0.C1.D0.R0: Write RC0B = 0x08 N0.C1.D0.R0: Write RC0C = 0x00 N0.C1.D0.R0: Write RC0E = 0x00 N0.C1.D0.R0: Write RC0F = 0x00 N0.C1.D0.R0: Write RC30 = 0x2C N0.C1.D0.R0: Write RC40 = 0x26 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x27 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x28 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x29 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x21 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x22 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x23 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x24 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x25 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC09 = 0x0C N0.C1.D0.R0: Write RC0D = 0x04 N0.C1: Issue ZQCL Tx Eq - 1523ms Imode -- Started Checkpoint Code: Socket 0, 0xB7, 0x1D, 0x0000 Imode - 0ms CTLE -- Started Checkpoint Code: Socket 0, 0xB7, 0x67, 0x0000 Printing initialized array of cached values... Rx Eq Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C1.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTLE C Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C1.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTLE R Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C1.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting 0 Params Rx Eq 0x0 CTLE C 0x0 CTLE R 0x0 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 96 96 95 95 96 96 96 96 96 96 96 95 95 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 46 47 43 45 47 50 45 47 46 46 47 43 45 47 50 45 47 46 Setting 1 Params Rx Eq 0x2 CTLE C 0x1 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 46 45 42 43 47 49 44 46 45 46 45 42 43 47 49 44 46 45 Setting 2 Params Rx Eq 0x2 CTLE C 0x2 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 96 96 95 94 96 96 96 96 96 96 96 95 94 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 46 45 42 44 46 47 44 46 45 46 45 42 44 46 47 44 46 45 Setting 3 Params Rx Eq 0x2 CTLE C 0x3 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 96 96 93 92 96 96 96 96 96 96 96 93 92 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 46 46 41 43 45 49 44 46 45 46 46 41 43 45 49 44 46 45 Setting 4 Params Rx Eq 0x3 CTLE C 0x1 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 46 41 44 47 48 44 47 46 45 46 41 44 47 48 44 47 46 Setting 5 Params Rx Eq 0x3 CTLE C 0x2 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 45 41 42 45 48 44 45 46 45 45 41 42 45 48 44 45 46 Setting 6 Params Rx Eq 0x3 CTLE C 0x3 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 45 41 43 45 46 43 45 44 45 45 41 43 45 46 43 45 44 Setting 7 Params Rx Eq 0x4 CTLE C 0x1 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 46 41 43 47 49 45 45 46 45 46 41 43 47 49 45 45 46 Setting 8 Params Rx Eq 0x4 CTLE C 0x2 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 45 41 42 46 47 43 45 45 45 45 41 42 46 47 43 45 45 Setting 9 Params Rx Eq 0x4 CTLE C 0x3 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 43 44 39 41 44 47 43 44 44 43 44 39 41 44 47 43 44 44 Power TrendLine Calculation N0.C1.D0.R0.S00: minPower = 0 : maxPower = 900 AveOfMax = 710 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 0: N0.C1.D0.R0.S01: minPower = 0 : maxPower = 900 AveOfMax = 715 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 1: N0.C1.D0.R0.S02: minPower = 0 : maxPower = 900 AveOfMax = 695 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 2: N0.C1.D0.R0.S03: minPower = 0 : maxPower = 900 AveOfMax = 705 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 3: N0.C1.D0.R0.S04: minPower = 0 : maxPower = 900 AveOfMax = 715 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 4: N0.C1.D0.R0.S05: minPower = 0 : maxPower = 900 AveOfMax = 730 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 5: N0.C1.D0.R0.S06: minPower = 0 : maxPower = 900 AveOfMax = 705 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 6: N0.C1.D0.R0.S07: minPower = 0 : maxPower = 900 AveOfMax = 715 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 7: N0.C1.D0.R0.S08: minPower = 0 : maxPower = 900 AveOfMax = 710 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 8: N0.C1.D0.R0.S09: minPower = 0 : maxPower = 900 AveOfMax = 710 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 9: N0.C1.D0.R0.S10: minPower = 0 : maxPower = 900 AveOfMax = 715 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 10: N0.C1.D0.R0.S11: minPower = 0 : maxPower = 900 AveOfMax = 695 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 11: N0.C1.D0.R0.S12: minPower = 0 : maxPower = 900 AveOfMax = 705 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 12: N0.C1.D0.R0.S13: minPower = 0 : maxPower = 900 AveOfMax = 715 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 13: N0.C1.D0.R0.S14: minPower = 0 : maxPower = 900 AveOfMax = 730 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 14: N0.C1.D0.R0.S15: minPower = 0 : maxPower = 900 AveOfMax = 705 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 15: N0.C1.D0.R0.S16: minPower = 0 : maxPower = 900 AveOfMax = 715 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 16: N0.C1.D0.R0.S17: minPower = 0 : maxPower = 900 AveOfMax = 710 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 17: START_OPTIMAL_TRAINING_RESULTS Rx Eq Per Strobe Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C1.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTLE C Per Strobe Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C1.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTLE R Per Strobe Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C1.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 END_OPTIMAL_TRAINING_RESULTS CTLE - 1108ms Tx Per Bit Deskew -- Started Checkpoint Code: Socket 0, 0xB7, 0x0E, 0x0000 N0: START_PER_BIT_DESKEW ============================================================================== N0: Per Bit Deskew Tx ============================================================================== PatternLength: 64 Per bit margins: TxDq 0------7 8-----15 16----23 24----31 32----39 40----47 48----55 56----63 64----71 30 ******** ******* ******** ******* ******** ******** ******** ******** ******** 29 ******** ******* ******** ******* ******** ******* ******** ******** ******** 28 ******** ******* ******** ******* * ****** * ***** * ***** * * *** ******** 27 ******* *** *** * *** * *** *** * *** * * * *** * ***** * * *** * ***** 26 ** ** * * ** * *** * * * ** ** * * *** * *** * * * * * **** 25 * * * * ** * ** * * ** ** ** * * * * * * 24 * * ** * ** * ** * * 23 * * * * * * * -20 * -21 * * -22 * * ** * ** * * -23 * * * ** * * *** * * ** * * * * -24 * * * * ** *** *** **** *** * * ** * * * ** * * -25 ** * * *** ** **** *** **** *** * * * *** * * ** ** *** -26 ** *** **** ** **** *** **** *** * * * ** * **** * * **** ** ** *** -27 **** *** **** ** **** *** **** *** ** * * **** ** **** *** **** *** **** *** -28 ******** ******** ******** ******** **** *** ******** ******** ******** ******** -29 ******** ******** ******** ******** **** *** ******** ******** ******** ******** -30 ******** ******** ******** ******** ******** ******** ******** ******** ******** N0.C1.D0.R0: TxDq - Per bit margins 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 25 26 27 26 23 27 27 28 23 27 25 28 23 24 27 31 25 28 26 25 23 28 25 28 25 27 26 28 23 24 27 31 27 29 27 25 -27 -25 -24 -27 -28 -23 -26 -22 -26 -24 -25 -25 -28 -28 -24 -22 -25 -22 -22 -24 -28 -24 -24 -20 -23 -24 -24 -24 -28 -23 -22 -21 -28 -27 -25 -28 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 24 28 26 28 26 29 27 28 23 24 26 30 26 29 26 26 24 27 25 29 26 29 25 29 25 27 27 29 25 28 27 26 23 26 26 28 -30 -26 -28 -23 -27 -27 -26 -26 -28 -28 -27 -23 -25 -23 -23 -26 -28 -24 -27 -23 -26 -26 -26 -26 -28 -27 -25 -23 -27 -22 -24 -27 -28 -24 -25 -22 N0.C1: Calculating Bit Centers N0.C1: dimm = 0, rank = 0 Per Bit Margin Center Per Bit Skew N# = Nibble, BCx = Bit Center, BSx = Bit Skew , MSL = Most Skewed Lane N# BC0-BC1-BC2-BC3 BS0-BS1-BS2-BS3 ============================================================================== 0 -1 0 1 0 0 1 2 1 1 -2 2 0 3 0 4 2 5 2 -1 1 0 1 0 2 1 2 3 -2 -2 1 4 0 0 3 6 4 0 3 2 0 0 3 2 0 5 -2 2 0 4 0 4 2 6 6 1 1 1 2 0 0 0 1 7 -2 0 2 5 0 2 4 7 8 0 1 1 -1 1 2 2 0 9 -3 1 -1 2 0 4 2 5 10 0 1 0 1 0 1 0 1 11 -2 -2 0 3 0 0 2 5 12 0 3 1 0 0 3 1 0 13 -2 1 -1 3 0 3 1 5 14 0 1 0 1 0 1 0 1 15 -1 0 1 3 0 1 2 4 16 -1 3 1 0 0 4 2 1 17 -2 1 0 3 0 3 2 5 START_DATA_TX_DQ_PER_BIT N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 19 20 21 20 22 26 24 27 8 10 9 10 12 12 15 18 59 62 61 59 61 65 63 67 56 56 56 57 58 60 62 65 45 46 46 44 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 46 50 48 51 56 57 56 57 60 60 62 65 3 6 4 3 6 9 7 11 9 10 9 10 13 14 15 17 43 47 45 44 47 50 49 52 N0: STOP_PER_BIT_DESKEW Tx Per Bit Deskew - 448ms Rx Per Bit Deskew -- Started Checkpoint Code: Socket 0, 0xB7, 0x0D, 0x0000 N0: START_PER_BIT_DESKEW ============================================================================== N0: Per Bit Deskew Rx P ============================================================================== PatternLength: 64 Per bit margins: Rx DqsP 0------7 8-----15 16----23 24----31 32----39 40----47 48----55 56----63 64----71 30 ******** ******** ******** ****** * *** * ******** ******** ******** ******** 29 ******** ******** **** ** ** * * * * ** ***** **** *** ** *** * ******** 28 **** *** ** *** * *** ** * * * ** ***** **** * * * * ******** 27 **** *** * * * * *** * * * * * *** * **** ** 26 *** * * * * * * * * * * *** ** 25 ** * * *** * 24 * * * * -21 * * -22 * ** * * ** -23 ** * * ** * ** * ** * ** * ** -24 ** ** * *** ** ** * * *** * * *** *** ** * * * * ** -25 ** ** * * *** *** **** *** *** * * *** * * *** ** * * *** * ** -26 ** *** * * *** *** **** *** *** *** **** * ** *** **** * ****** *** *** -27 ** *** ******** ******** ******** ******** * * *** ******** ******** ******** -28 ** **** ******** ******** ******** ******** *** **** ******** ******** ******** -29 *** **** ******** ******** ******** ******** ******** ******** ******** ******** -30 *** **** ******** ******** ******** ******** ******** ******** ******** ******** N0.C1.D0.R0: RxDqsP - Per bit margins 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 27 26 25 25 29 26 27 24 28 27 29 27 28 27 29 26 29 27 27 26 30 30 28 26 29 27 30 28 30 29 31 26 31 30 30 30 -24 -24 -29 -31 -23 -23 -26 -28 -23 -27 -25 -27 -24 -24 -24 -27 -21 -24 -25 -27 -21 -22 -25 -25 -22 -25 -24 -27 -22 -23 -24 -27 -23 -26 -24 -27 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 31 31 31 29 28 28 30 28 27 28 28 24 28 26 27 26 30 29 29 26 29 28 30 28 29 29 30 28 27 25 25 24 28 28 26 24 -23 -23 -24 -26 -25 -28 -27 -29 -27 -26 -25 -28 -23 -24 -24 -27 -23 -23 -26 -26 -24 -27 -24 -26 -25 -25 -23 -26 -24 -26 -26 -27 -22 -22 -26 -27 N0.C1: Calculating Bit Centers N0.C1: dimm = 0, rank = 0 Per Bit Margin Center Per Bit Skew N# = Nibble, BCx = Bit Center, BSx = Bit Skew , MSL = Most Skewed Lane N# BC0-BC1-BC2-BC3 BS0-BS1-BS2-BS3 MSL ============================================================================== 0 1 1 -2 -3 4 4 1 0 1 3 1 0 -2 5 3 2 0 2 2 0 2 0 2 0 2 0 3 2 1 2 0 2 1 2 0 4 4 1 1 0 4 1 1 0 5 4 4 1 0 4 4 1 0 6 3 1 3 0 3 1 3 0 7 4 3 3 0 4 3 3 0 8 4 2 3 1 3 1 2 0 9 4 4 3 1 3 3 2 0 10 1 0 1 0 1 0 1 0 11 0 1 1 -2 2 3 3 0 12 2 1 1 0 2 1 1 0 13 3 3 1 0 3 3 1 0 14 2 0 3 1 2 0 3 1 15 2 2 3 1 1 1 2 0 16 1 0 0 -1 2 1 1 0 17 3 3 0 -1 4 4 1 0 START_DATA_RX_DQS_P_PER_BIT N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 4 4 1 0 5 3 2 0 2 0 2 0 2 1 2 0 4 1 1 0 4 4 1 0 3 1 3 0 4 3 3 0 3 1 2 0 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 3 3 2 0 1 0 1 0 2 3 3 0 2 1 1 0 3 3 1 0 2 0 3 1 1 1 2 0 2 1 1 0 4 4 1 0 N0: STOP_PER_BIT_DESKEW N0: START_PER_BIT_DESKEW ============================================================================== N0: Per Bit Deskew Rx N ============================================================================== PatternLength: 64 Per bit margins: Rx DqsN 0------7 8-----15 16----23 24----31 32----39 40----47 48----55 56----63 64----71 30 ******** ******** ******** ******** ******** ******** ******** ******** ******** 29 ******** ******** ******** ******** ******** ******** ******** ******** ******** 28 ******** ******** ******** ******** ******** ******** ******** ******** ******** 27 **** *** ******** ******** ******** ******* ** ***** ******** ******** ******** 26 **** *** ******** ******** ******** *** *** ** ** * ******** ** ***** **** ** 25 *** *** ******* ******** ** ***** ** * * * * **** *** * *** * *** ** 24 *** ** * * * * ** ** ** *** * ** * * *** ** * * * ** * 23 *** * ** * * * * * * * * * * * 22 * * * * * * * 21 * * * 20 * -25 * * * * ** -26 * * * * ** * * * * ** -27 ** ** * * * ** * * * *** * * * * * ** -28 ** ** * *** ** ** * * ** * * **** * ** * * ** * * * * ** -29 ** *** * * *** *** **** ******* *** **** * * *** *** **** * ***** * ****** -30 ** **** * ****** *** **** ******** ******** *** **** *** **** ******** ******** N0.C1.D0.R0: RxDqsN - Per bit margins 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 26 23 23 23 28 25 24 22 26 24 25 24 25 24 25 24 25 25 23 21 25 25 24 21 24 23 26 24 24 22 25 20 28 26 24 24 -25 -27 -31 -31 -26 -27 -29 -30 -26 -31 -29 -30 -27 -28 -28 -30 -25 -28 -29 -31 -25 -26 -29 -29 -25 -29 -28 -29 -27 -28 -29 -30 -26 -29 -28 -30 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 27 26 26 23 26 25 28 26 25 27 27 24 25 23 24 22 26 25 24 22 26 24 27 25 24 25 26 23 26 25 24 23 27 27 25 23 -27 -26 -27 -28 -26 -30 -29 -31 -29 -28 -28 -30 -28 -29 -28 -31 -27 -28 -29 -29 -27 -30 -27 -29 -29 -29 -28 -30 -27 -30 -29 -29 -25 -25 -29 -29 N0.C1: Calculating Bit Centers N0.C1: dimm = 0, rank = 0 Per Bit Margin Center Per Bit Skew N# = Nibble, BCx = Bit Center, BSx = Bit Skew , MSL = Most Skewed Lane N# BC0-BC1-BC2-BC3 BS0-BS1-BS2-BS3 MSL ============================================================================== 0 0 -2 -4 -4 4 2 0 0 1 1 -1 -2 -4 5 3 2 0 2 0 -3 -2 -3 3 0 1 0 3 -1 -2 -1 -3 2 1 2 0 4 0 -1 -3 -5 5 4 2 0 5 0 0 -2 -4 4 4 2 0 6 0 -3 -1 -2 3 0 2 1 7 -1 -3 -2 -5 4 2 3 0 8 1 -1 -2 -3 4 2 1 0 9 0 0 0 -2 2 2 2 0 10 0 -2 0 -2 2 0 2 0 11 -2 0 0 -3 1 3 3 0 12 -1 -3 -2 -4 3 1 2 0 13 0 -1 -2 -3 3 2 1 0 14 0 -3 0 -2 3 0 3 1 15 -2 -2 -1 -3 1 1 2 0 16 0 -2 -2 -3 3 1 1 0 17 1 1 -2 -3 4 4 1 0 START_DATA_RX_DQS_N_PER_BIT N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 4 2 0 0 5 3 2 0 3 0 1 0 2 1 2 0 5 4 2 0 4 4 2 0 3 0 2 1 4 2 3 0 4 2 1 0 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 2 2 2 0 2 0 2 0 1 3 3 0 3 1 2 0 3 2 1 0 3 0 3 1 1 1 2 0 3 1 1 0 4 4 1 0 N0: STOP_PER_BIT_DESKEW Rx Per Bit Deskew - 863ms Wr Vref Centering (LRDIMM) -- Started Checkpoint Code: Socket 0, 0xB7, 0x1E, 0x0000 Wr Vref Centering (LRDIMM) - 0ms Rd Vref Centering (LRDIMM) -- Started Checkpoint Code: Socket 0, 0xB7, 0x33, 0x0000 Rd Vref Centering (LRDIMM) - 0ms Wr Dq Centering (LRDIMM) -- Started Checkpoint Code: Socket 0, 0xB7, 0x34, 0x0000 Wr Dq Centering (LRDIMM) - 0ms Rd Dq Centering (LRDIMM) -- Started Checkpoint Code: Socket 0, 0xB7, 0x35, 0x0000 Rd Dq Centering (LRDIMM) - 0ms Wr Vref Centering -- Started Checkpoint Code: Socket 0, 0xB7, 0x09, 0x0000 N0: Timing offsets to test N0: tOffset 0 1 2 N0.C1.D0.R0: -4 4 0 N0: Get vref margins at 3 timing points START_TX_VREF_CENTER N0: vref Margins - 0 + N0.C1.D0.R0.S00: -31 : 30, -31 : 30, -31 : 30 N0.C1.D0.R0.S01: -31 : 30, -31 : 30, -31 : 30 N0.C1.D0.R0.S02: -31 : 30, -31 : 30, -31 : 30 N0.C1.D0.R0.S03: -31 : 30, -31 : 30, -31 : 30 N0.C1.D0.R0.S04: -31 : 30, -31 : 30, -31 : 30 N0.C1.D0.R0.S05: -31 : 30, -31 : 30, -31 : 30 N0.C1.D0.R0.S06: -31 : 30, -31 : 30, -31 : 30 N0.C1.D0.R0.S07: -31 : 30, -31 : 30, -31 : 30 N0.C1.D0.R0.S08: -31 : 30, -31 : 30, -31 : 29 STOP_TX_VREF_CENTER vrefLo vrefHi offset N0.C1.D0.R0.S00: -31 30 0 N0.C1.D0.R0.S01: -31 30 0 N0.C1.D0.R0.S02: -31 30 0 N0.C1.D0.R0.S03: -31 30 0 N0.C1.D0.R0.S04: -31 30 0 N0.C1.D0.R0.S05: -31 30 0 N0.C1.D0.R0.S06: -31 30 0 N0.C1.D0.R0.S07: -31 30 0 N0.C1.D0.R0.S08: -31 29 -1 N0.C1.D0.R0: txVrefSafe = 0x53 Wr Vref Centering - 137ms Rd Vref Centering -- Started Checkpoint Code: Socket 0, 0xB7, 0x08, 0x0000 N0: Timing offsets to test N0: tOffset 0 1 2 N0.C1.D0.R0: -4 4 0 N0: Get vref margins at 3 timing points START_RX_VREF_CENTER N0: vref Margins - 0 + N0.C1.D0.R0.S00: -47 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S01: -48 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S02: -45 : 46, -48 : 48, -48 : 48 N0.C1.D0.R0.S03: -45 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S04: -48 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S05: -48 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S06: -48 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S07: -48 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S08: -47 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S09: -47 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S10: -48 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S11: -45 : 46, -48 : 48, -48 : 48 N0.C1.D0.R0.S12: -44 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S13: -48 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S14: -48 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S15: -48 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S16: -48 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S17: -47 : 48, -48 : 48, -48 : 48 STOP_RX_VREF_CENTER vrefLo vrefHi offset N0.C1.S00: -47 48 0 N0.C1.S01: -48 48 0 N0.C1.S02: -47 47 0 N0.C1.S03: -47 48 0 N0.C1.S04: -48 48 0 N0.C1.S05: -48 48 0 N0.C1.S06: -48 48 0 N0.C1.S07: -48 48 0 N0.C1.S08: -47 48 0 N0.C1.S09: -47 48 0 N0.C1.S10: -48 48 0 N0.C1.S11: -47 47 0 N0.C1.S12: -46 48 1 N0.C1.S13: -48 48 0 N0.C1.S14: -48 48 0 N0.C1.S15: -48 48 0 N0.C1.S16: -48 48 0 N0.C1.S17: -47 48 0 Rd Vref Centering - 213ms Tx Dq Adv -- Started Checkpoint Code: Socket 0, 0xB7, 0x07, 0x0000 N0: Get eye width N0.C1.D0.R0: High = 24 - Low = -23 N0.C1: Composite High = 24 - Composite Low = -23 N0: Low: -23 High: 24 N0: Offset = 0 N0: Eye width = 47 N0: Get eye height N0.C1.D0.R0: High = 30 - Low = -31 N0.C1: Composite High = 30 - Composite Low = -31 N0.C1.D0.R0: txVrefSafe = 0x53 N0: Low: -31 High: 30 N0: Eye height = 61 N0: numerator: 0 N0: denominator: 240400 N0: vrefRatio: 770, vrefRatioSpec: 1200 N0: Max offset from timing center: 0 N0: Timing Limited N0: GetMultiVref: patternLength = 64, stepSize = 7, numPoints = 7 margin = 0, vIndex = 3, Running 7 times pattern length START_DATA_TX_DQ_ADV N0.C1.D0.R0.S12: Truncated: -1 -> 0 N0.C1.D0.R0.S14: Truncated: 0 -> -1 N0.C1.D0.R0.S16: Truncated: 0 -> -1 Results for N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------- Vref offset: 21 Left: -16 -16 -16 -17 -19 -17 -17 -19 -18 -16 -15 -17 -17 -18 -18 -18 -18 -18 Right: 16 14 15 15 16 17 16 15 16 15 14 14 14 17 17 17 16 14 Vref offset: 14 Left: -20 -19 -19 -20 -21 -20 -20 -22 -20 -19 -19 -19 -19 -20 -21 -20 -21 -20 Right: 20 18 19 19 20 21 19 18 21 19 19 18 18 21 20 21 20 19 Vref offset: 7 Left: -23 -22 -22 -22 -24 -23 -22 -24 -23 -22 -21 -21 -22 -23 -23 -23 -24 -22 Right: 24 21 21 22 23 24 22 22 24 22 22 21 21 24 23 24 24 22 Vref offset: 0 Left: -25 -24 -24 -24 -26 -26 -24 -26 -25 -25 -25 -23 -24 -25 -26 -25 -27 -25 Right: 25 24 24 24 26 26 25 26 25 25 25 24 24 26 25 26 26 25 Vref offset: -7 Left: -25 -25 -26 -24 -26 -27 -25 -26 -25 -25 -26 -25 -25 -26 -27 -26 -27 -24 Right: 24 25 23 22 24 26 24 25 22 24 25 23 21 25 25 25 26 22 Vref offset: -14 Left: -23 -23 -24 -22 -23 -24 -23 -24 -23 -22 -23 -23 -22 -23 -25 -24 -24 -22 Right: 21 20 20 20 21 23 21 22 19 21 21 20 18 22 23 22 23 19 Vref offset: -21 Left: -20 -19 -21 -20 -21 -21 -20 -20 -20 -19 -20 -20 -20 -21 -22 -22 -21 -19 Right: 16 16 17 15 16 19 16 17 15 17 16 16 13 17 18 17 19 13 ------------------------------------------------------------------------------- Prev Pi: 211 200 187 184 172 184 195 201 171 214 204 189 186 174 188 198 205 175 New Pi: 211 200 187 184 172 184 195 201 171 214 204 189 186 174 187 198 204 175 Diff: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1 0 -1 0 STOP_DATA_TX_DQ_ADV Tx Dq Adv - 327ms Rx Dq/Dqs Adv -- Started Checkpoint Code: Socket 0, 0xB7, 0x06, 0x0000 N0: Get eye width N0.C1.D0.R0: High = 24 - Low = -25 N0.C1: Composite High = 24 - Composite Low = -25 N0: Low: -25 High: 24 N0: Offset = 0 N0: Eye width = 49 N0: Get eye height N0.C1.D0.R0: High = 48 - Low = -48 N0.C1: Composite High = 48 - Composite Low = -48 N0: Low: -48 High: 48 N0: Eye height = 60 N0: numerator: 0 N0: denominator: 257960 N0: vrefRatio: 816, vrefRatioSpec: 1333 N0: Max offset from timing center: 0 N0: Timing Limited N0: GetMultiVref: patternLength = 64, stepSize = 7, numPoints = 7 margin = 0, vIndex = 3, Running 7 times pattern length START_DATA_RX_DQSN_ADV N0.C1.D0.R0.S01: Truncated: 0 -> -1 N0.C1.D0.R0.S03: Truncated: 0 -> -1 N0.C1.D0.R0.S05: Truncated: 0 -> -1 N0.C1.D0.R0.S06: Truncated: 0 -> -1 N0.C1.D0.R0.S07: Truncated: 0 -> -1 N0.C1.D0.R0.S08: Truncated: 0 -> -2 N0.C1.D0.R0.S09: Truncated: 0 -> -1 N0.C1.D0.R0.S10: Truncated: 0 -> -1 N0.C1.D0.R0.S11: Truncated: 0 -> -1 N0.C1.D0.R0.S12: Truncated: 1 -> -1 N0.C1.D0.R0.S13: Truncated: 0 -> -1 N0.C1.D0.R0.S15: Truncated: 0 -> -1 N0.C1.D0.R0.S16: Truncated: 0 -> -1 N0.C1.D0.R0.S17: Truncated: 0 -> -1 Results for N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------- Vref offset: 21 Left: -23 -23 -22 -24 -22 -26 -25 -25 -23 -24 -24 -22 -22 -24 -26 -24 -25 -24 Right: 24 24 23 26 24 25 26 24 24 23 24 23 25 25 25 25 25 24 Vref offset: 14 Left: -25 -26 -25 -26 -25 -27 -27 -27 -25 -26 -26 -25 -24 -25 -27 -26 -27 -25 Right: 26 25 25 27 26 26 27 25 25 24 26 25 25 26 26 26 25 26 Vref offset: 7 Left: -27 -28 -27 -27 -27 -28 -28 -28 -27 -26 -27 -26 -26 -27 -28 -27 -27 -26 Right: 27 26 26 26 27 27 26 26 26 27 27 25 26 26 27 25 27 26 Vref offset: 0 Left: -25 -26 -25 -25 -26 -26 -26 -27 -27 -26 -26 -25 -25 -26 -26 -26 -26 -26 Right: 25 25 25 24 26 25 25 25 24 25 25 24 24 25 26 24 25 24 Vref offset: -7 Left: -23 -25 -23 -24 -24 -25 -24 -26 -25 -24 -24 -24 -23 -24 -25 -25 -25 -24 Right: 24 24 24 24 25 25 24 24 24 24 24 23 24 24 26 24 24 23 Vref offset: -14 Left: -22 -23 -21 -22 -22 -23 -23 -24 -24 -22 -22 -21 -20 -22 -24 -23 -24 -22 Right: 24 22 22 22 24 24 23 23 23 23 23 22 23 23 24 23 23 22 Vref offset: -21 Left: -19 -21 -19 -19 -20 -22 -21 -22 -21 -20 -20 -20 -19 -20 -22 -21 -22 -20 Right: 22 21 21 21 22 22 22 21 21 22 22 21 22 22 23 22 22 22 ------------------------------------------------------------------------------- Prev Pi: 30 29 28 29 28 30 29 28 30 26 27 26 26 27 28 27 27 26 New Pi: 30 28 28 28 28 29 28 27 28 25 26 25 25 26 28 26 26 25 Diff: 0 -1 0 -1 0 -1 -1 -1 -2 -1 -1 -1 -1 -1 0 -1 -1 -1 STOP_DATA_RX_DQSN_ADV N0: Get eye width N0.C1.D0.R0: High = 25 - Low = -24 N0.C1: Composite High = 25 - Composite Low = -24 N0: Low: -24 High: 25 N0: Offset = 0 N0: Eye width = 49 N0: Get eye height N0.C1.D0.R0: High = 48 - Low = -48 N0.C1: Composite High = 48 - Composite Low = -48 N0: Low: -48 High: 48 N0: Eye height = 60 N0: numerator: 0 N0: denominator: 257960 N0: vrefRatio: 816, vrefRatioSpec: 1333 N0: Max offset from timing center: 0 N0: Timing Limited N0: GetMultiVref: patternLength = 64, stepSize = 7, numPoints = 7 margin = 0, vIndex = 3, Running 7 times pattern length START_DATA_RX_DQSP_ADV N0.C1.D0.R0.S00: Truncated: 1 -> 0 N0.C1.D0.R0.S01: Truncated: 1 -> 0 N0.C1.D0.R0.S02: Truncated: 1 -> 0 N0.C1.D0.R0.S04: Truncated: 1 -> 0 N0.C1.D0.R0.S05: Truncated: 1 -> 0 N0.C1.D0.R0.S06: Truncated: 1 -> 0 N0.C1.D0.R0.S08: Truncated: 1 -> 0 N0.C1.D0.R0.S10: Truncated: 1 -> 0 N0.C1.D0.R0.S11: Truncated: 1 -> 0 N0.C1.D0.R0.S12: Truncated: 0 -> -1 N0.C1.D0.R0.S13: Truncated: 1 -> 0 N0.C1.D0.R0.S15: Truncated: 1 -> 0 N0.C1.D0.R0.S16: Truncated: 1 -> 0 N0.C1.D0.R0.S17: Truncated: 1 -> 0 Results for N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------- Vref offset: 21 Left: -20 -22 -21 -23 -22 -23 -23 -22 -21 -21 -22 -20 -23 -22 -24 -23 -23 -21 Right: 25 24 25 25 26 27 26 27 25 25 26 25 24 27 25 27 27 27 Vref offset: 14 Left: -23 -24 -23 -25 -25 -25 -25 -24 -23 -24 -24 -22 -25 -25 -26 -25 -25 -24 Right: 26 25 26 27 27 27 27 28 26 27 28 27 25 28 27 28 28 28 Vref offset: 7 Left: -25 -25 -25 -26 -25 -26 -26 -26 -25 -26 -26 -24 -26 -27 -27 -27 -27 -26 Right: 26 26 26 26 28 28 26 28 27 27 27 27 26 27 28 27 28 27 Vref offset: 0 Left: -24 -25 -25 -25 -27 -26 -25 -25 -25 -24 -25 -25 -26 -26 -26 -25 -26 -25 Right: 25 26 25 25 27 27 25 27 26 26 25 26 25 26 26 25 27 26 Vref offset: -7 Left: -22 -23 -23 -24 -25 -25 -24 -24 -24 -23 -23 -24 -24 -25 -25 -24 -24 -23 Right: 24 25 24 24 26 26 24 26 25 25 24 25 24 26 25 24 27 25 Vref offset: -14 Left: -21 -22 -22 -22 -24 -23 -22 -23 -22 -21 -21 -22 -23 -23 -23 -22 -23 -22 Right: 23 23 23 23 25 25 24 25 24 23 23 25 23 24 25 23 25 24 Vref offset: -21 Left: -19 -19 -19 -19 -22 -22 -20 -21 -19 -19 -19 -20 -21 -21 -21 -21 -21 -20 Right: 22 23 22 21 24 24 22 24 22 22 22 23 22 23 23 23 23 23 ------------------------------------------------------------------------------- Prev Pi: 31 32 33 32 32 32 33 31 32 28 30 30 31 30 29 30 31 28 New Pi: 31 32 33 32 32 32 33 32 32 29 30 30 30 30 29 30 31 28 Diff: 0 0 0 0 0 0 0 1 0 1 0 0 -1 0 0 0 0 0 STOP_DATA_RX_DQSP_ADV Rx Dq/Dqs Adv - 635ms Round Trip Optimization -- Started Checkpoint Code: Socket 0, 0xB7, 0x13, 0x0000 Round Trip Optimization - 0ms Display Training Results -- Started N0: START_TRAINING_REGISTER_DUMP START_DATA_XOVER CMDn0 CMDn1 CMDs0 CMDs1 CTL CKE CLK 0 1 2 3 4 5 6 7 8 N0.C1: 10 43 42 46 45 16 49 22 56 26 60 30 60 26 57 30 START_DATA_REC_EN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 178 156 133 107 84 99 130 155 85 189 166 144 118 96 110 141 165 99 N0.C1.D0.R0: IO Latency = 6, Round Trip = 55 START_DATA_RX_DQSP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 31 32 33 32 32 32 33 32 32 29 30 30 30 30 29 30 31 28 START_DATA_RX_DQSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 30 28 28 28 28 29 28 27 28 25 26 25 25 26 28 26 26 25 START_DATA_WR_LVL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1: t_cwl_adj = 2 N0.C1.D0.R0: 179 167 154 150 137 150 161 166 137 START_DATA_TX_DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 211 200 187 184 172 184 195 201 171 214 204 189 186 174 187 198 204 175 START_DATA_RX_VREF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1: 65 65 65 65 65 65 65 65 65 65 65 65 66 65 65 65 65 65 START_DATA_TxVref 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 84 84 84 84 84 84 84 84 83 START_DATA_CMD 0n 1n 2n 3n 4n 5n 0s 1s 2s 3s 4s 5s N0.C1: 97 98 96 95 99 96 98 95 96 97 95 100 START_DATA_CLK 0 1 2 3 N0.C1: 0 0 0 0 START_DATA_CTL 0n 1n 2n 3n 4n 5n 6n 7n 8n 9n 0s 1s 2s 3s 4s 5s 6s 7s 8s 9s 10s N0.C1: 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 START_DATA_MRS MR0 MR1 MR2 MR3 MR4 MR5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 738 101 E0 0 0 40 894 894 894 894 894 894 894 894 893 START_DATA_RX_DQS_P_PER_BIT N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 4 4 1 0 5 3 2 0 2 0 2 0 2 1 2 0 4 1 1 0 4 4 1 0 3 1 3 0 4 3 3 0 3 1 2 0 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 3 3 2 0 1 0 1 0 2 3 3 0 2 1 1 0 3 3 1 0 2 0 3 1 1 1 2 0 2 1 1 0 4 4 1 0 START_DATA_RX_DQS_N_PER_BIT N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 4 2 0 0 5 3 2 0 3 0 1 0 2 1 2 0 5 4 2 0 4 4 2 0 3 0 2 1 4 2 3 0 4 2 1 0 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 2 2 2 0 2 0 2 0 1 3 3 0 3 1 2 0 3 2 1 0 3 0 3 1 1 1 2 0 3 1 1 0 4 4 1 0 START_DATA_TX_DQ_PER_BIT N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 19 20 21 20 22 26 24 27 8 10 9 10 12 12 15 18 59 62 61 59 61 65 63 67 56 56 56 57 58 60 62 65 45 46 46 44 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 46 50 48 51 56 57 56 57 59 59 61 64 3 6 4 3 6 9 7 11 9 10 9 10 12 13 14 16 43 47 45 44 47 50 49 52 START_DATA_CMD_VREF_CENTERING_OFFSETS N0.C1: 32 START_SENSE_AMP_TRAINING_OFFSETS BitSAmp for Channel 1 bit: 0 1 2 3 N0.C1: Nibble 0: 16 13 13 13 N0.C1: Nibble 1: 13 16 13 13 N0.C1: Nibble 2: 15 15 14 12 N0.C1: Nibble 3: 14 13 13 14 N0.C1: Nibble 4: 15 16 16 13 N0.C1: Nibble 5: 15 13 14 16 N0.C1: Nibble 6: 15 13 13 14 N0.C1: Nibble 7: 13 14 14 14 N0.C1: Nibble 8: 15 13 13 14 N0.C1: Nibble 9: 15 13 13 15 N0.C1: Nibble 10: 16 15 13 15 N0.C1: Nibble 11: 13 15 15 14 N0.C1: Nibble 12: 13 13 14 13 N0.C1: Nibble 13: 14 15 12 14 N0.C1: Nibble 14: 15 14 14 15 N0.C1: Nibble 15: 12 15 14 13 N0.C1: Nibble 16: 15 15 14 14 N0.C1: Nibble 17: 14 14 14 13 START_POWER_TRAINING_DUMP START_DATA_TX_IMODE 0 1 2 3 4 5 6 7 8 N0.C1.D0.R0: 15 15 15 15 15 15 15 15 15 START_DATA_RX_EQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_DATA_RX_CTLE_C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_DATA_RX_CTLE_R 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_DATA_DRAM_DRVSTR N0.C1.D0.R0: 34 START_DATA_TX_RON N0.C1: -32693 START_DATA_WR_ODT N0.C1.D0.R0: 0 START_DATA_RX_ODT N0.C1: -32693 START_DATA_PARK_ODT N0.C1.D0.R0: 60 START_DATA_NOM_ODT N0.C1.D0.R0: 60 START_DATA_TX_EQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 0 8 6 6 4 8 8 4 6 0 8 6 6 4 8 8 4 6 START_SWIZZLE_TRAINING_RESULTS Pattern 0 1 2 3 4 5 N0.C1: E400FE00 E4E4E4E4 E4E4E4E4 E4E4E4E4 E4E4E4E4 E4 START_COMP_REG_DUMP Ch COMP 0 1 2 3 4 5 6 7 8 1 DrvUp 47 47 47 47 47 47 47 47 47 1 DrvDn 43 43 43 43 43 43 43 43 43 Ch COMP 0 1 2 3 4 5 6 7 8 1 ODTUp 38 38 38 38 38 38 38 38 38 1 ODTDn 36 36 36 36 36 36 36 36 36 Ch COMP 0 1 2 3 4 5 6 7 8 1 Scomp 10 10 10 10 10 10 10 10 10 Ch COMP CLK CMD_n CMD_s CTL_cke CTL_ctl 1 DrvUp 44 17 17 44 44 1 DrvDn 40 17 17 40 40 Ch COMP CLK CMD_n CMD_s CTL_cke CTL_ctl 1 Scomp 10 16 16 10 10 N0: STOP_TRAINING_REGISTER_DUMP N0: STOP_TRAINING_REGISTER_DUMP Display Training Results - 750ms Post-Training Initialization -- Started N0.C0.D0: dimmMtr: 0x001F000C N0.C0.D1: dimmMtr: 0x000F000C N0.C0.D2: dimmMtr: 0x000F000C N0.C1.D0: dimmMtr: 0x001E414C N0.C1.D1: dimmMtr: 0x000F0000 N0.C1.D2: dimmMtr: 0x000F0000 N0.C2.D0: dimmMtr: 0x001F000C N0.C2.D1: dimmMtr: 0x000F000C N0.C2.D2: dimmMtr: 0x000F000C N0.C3.D0: dimmMtr: 0x001F000C N0.C3.D1: dimmMtr: 0x000F000C N0.C3.D2: dimmMtr: 0x000F000C N0: (x10000) tck = 9375, tPDM_RD=20313, tPDM_WR=20313, tWRPRE=0, tRPRE=0, BL=80000, specMin=4 N0.C1: tRRDR = 1 N0.C1: tRRDD = 1 N0.C1: odtStretch = 0 N0.C1: tWWDR = 3, minWWDR = 3 N0.C1: odtStretch = 0 N0.C1: tWWDD = 3, minWWDD = 3 N0.C1: specMin = 4, tRWSR = 4 N0.C1: specMin = 4, tRWDR = 5 N0.C1: tRWDD = 5 N0.C1: odtStretch = 0 N0.C1: tWRDR = 1 N0.C1: odtStretch = 0 N0.C1: tWRDD = 1 N0.C1: t_rrdr = 1, t_rrdd = 1 Post-Training Initialization - 78ms Rank Margin Tool -- Started Checkpoint Code: Socket 0, 0xB7, 0x10, 0x0000 Rank Margin Tool - 0ms Fill BDAT Structure -- Started Fill BDAT Structure - 0ms Platform Restore NVDIMMs -- Started N0: PlatformRestoreNVDIMMs Platform Restore NVDIMMs - 2ms Platform Arm NVDIMMs -- Started N0: PlatformArmNVDIMMs Platform Arm NVDIMMs - 2ms Late Configuration -- Started Checkpoint Code: Socket 0, 0xB7, 0x11, 0x0000 N0: DRAM Maintenance N0.C1.D0.R0: Write RC0E = 0x0D N0: Enabling C/A Parity N0.C1.D0.R0: Write RC20 = 0x01 No Pending Reset, clearing the ADR status bit Late Configuration - 15ms Initialize Throttling -- Started Checkpoint Code: Socket 0, 0xB8, 0x00, 0x0000 Initialize Throttling N0.C1.D0: Initialize DRAM RAPL N0: Initialize DRAM Phase Shedding Initialize Throttling - 150ms Advanced MemTest -- Started Checkpoint Code: Socket 0, 0xB9, 0x00, 0x0000 Advanced MemTest - 0ms MemTest -- Started Checkpoint Code: Socket 0, 0xB9, 0x00, 0x0000 MemTest - 832ms MemInit -- Started Checkpoint Code: Socket 0, 0xBA, 0x00, 0x0000 MemInit - 423ms Check Ras Support After MemInit -- Started N0.C0.D0: dimmMtr: 0x001F000C N0.C0.D1: dimmMtr: 0x000F000C N0.C0.D2: dimmMtr: 0x000F000C N0.C1.D0: dimmMtr: 0x001E414C N0.C1.D1: dimmMtr: 0x000F0000 N0.C1.D2: dimmMtr: 0x000F0000 N0.C2.D0: dimmMtr: 0x001F000C N0.C2.D1: dimmMtr: 0x000F000C N0.C2.D2: dimmMtr: 0x000F000C N0.C3.D0: dimmMtr: 0x001F000C N0.C3.D1: dimmMtr: 0x000F000C N0.C3.D2: dimmMtr: 0x000F000C Check Ras Support After MemInit - 36ms Switch to Normal Mode -- Started Checkpoint Code: Socket 0, 0xB7, 0x12, 0x0000 N0: MboxStatus: 0 PCU_MISC_CONFIG = 0x1000000 N0: MBoxStatus: 0 PCU_MISC_CONFIG = 0x0 Switch to Normal Mode - 8ms Get NVRAM Data -- Started Get NVRAM Data - 0ms Initialize Memory Map -- Started Checkpoint Code: Socket 0, 0xBB, 0x00, 0x0000 N0.C1.D0: Memory Found! TAD setup HA 0 ----------- Memory Map Info ---------------- Socket XOR Config = Non-XOR mode Socket RAS Config = Channel Independent NUMA Config Socket Interleave Ways: 1 System Mem Size (64MB granularity): 0x40 SAD Table Rule Enable Limit Mode Ways Interleave List(right to left) ------------------------------------------------------------------- 0 1 0x60 0 1 00000000 ----------- Socket Info ---------------- ----------- Socket 0 Socket Enabled Socket max DIMM pop count = 1 Socket mem size (64MB) = 0x40 ----------- TAD Info ---------------- TAD Table (Socket 0) Rule Enable Limit Mode Ch Ways --------------------------------------- Home Agent 0 0 1 0x20 0 1 TAD Interleave List Way Target Offset ChIndex 0 1 0x0 0 1 0 0x0 0 2 0 0x0 0 3 0 0x0 0 1 1 0x60 0 1 TAD Interleave List Way Target Offset ChIndex 0 1 0x0 0 1 0 0x20 0 2 0 0x0 0 3 0 0x0 0 ----------- Channel Info ---------------- ----------- Channel 0 Channel not enabled ----------- Channel 1 Channel Enabled Channel mem size (64MB) = 0x40 ----------- RIR Info ---------------- RIR Table (Socket 0, Channel 1) ---------------------------------------------- Rule Enable Limit(Ch Space) Ways 0 1 0x40 1 Rank Interleave List Way Target Offset 0 0 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 ----------- Channel 2 Channel not enabled ----------- Channel 3 Channel not enabled ----------- Socket 1 Socket not enabled ----------- Socket 2 Socket not enabled ----------- Socket 3 Socket not enabled highMemBase: 0x40 highMemSize: 0x20 TOLM: 0x1F TOHM: 0x5F Initialize Memory Map - 168ms Set RAS Configuration -- Started Checkpoint Code: Socket 0, 0xBC, 0x00, 0x0000 Set RAS Config N0: Independent ch mode enabled N0: Patrol scrub enabled and started N0: Demand scrub enabled ECC is enabled Set RAS Configuration - 12ms Memory Late -- Started Memory Late - 0ms DIMM Information -- Started START_DIMMINFO_TABLE ====================================================================================== START_SOCKET_0_TABLE BDX V2/V3 - DE ====================================================================================== S| Channel 0 | Channel 1 | Channel 2 | Channel 3 | ====================================================================================== 0| Not installed | DIMM: Micron | Not installed | Not installed | | | DRAM: Micron | | | | | RCD: Montage | | | | | 4GB(4Gbx8 1H SR) | | | | | DDR4 RDIMM R/C-D | | | | | 2400 15-15-15 | | | | | ww12 2018 | | | | |9ASF51272PZ-2G3B1 | | | | |0x0000000000000000 | | | | | | | | -------------------------------------------------------------------------------------- 1| Not installed | Not installed | Not installed | Not installed | -------------------------------------------------------------------------------------- STOP_SOCKET_0_TABLE ====================================================================================== ====================================================================================== | Socket 0 | Socket 1 | Socket 2 | Socket 3 | System | ====================================================================================== Active Memory | 4GB | N/A | N/A | N/A | 4GB | DDR Freq | | | | | DDR4-2133 | Ch1 CL-RCD-RP-CMD |15-15-15-1n | | | | | DDR Vdd | | | | | 1.20V | ECC Checking | | | | | On | CAP Checking | | | | | On | Patrol/Demand Scrub | | | | | On/On | RAS Mode | | | | | Indep | Xover Mode | | | | | 2:2 | Paging Policy | | | | | Adapt Open | Data Scrambling | | | | | On | CCMRC Revision | | | | | 00.50.00 | RC Revision | | | | | 02.04.00 | ====================================================================================== STOP_DIMMINFO_TABLE ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Platform DIMM Configuration ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Socket : 0 Channel : 0 ddr4Size : 0 volSize : 0 perSize : 0 blkSize : 0 Channel : 1 ddr4Size : 64 volSize : 0 perSize : 0 blkSize : 0 Channel : 2 ddr4Size : 0 volSize : 0 perSize : 0 blkSize : 0 Channel : 3 ddr4Size : 0 volSize : 0 perSize : 0 blkSize : 0 DIMM Information - 353ms Total MRC time = 19183ms Setting Last Boot Date = 7272 days STOP_MRC_RUN Checkpoint Code: Socket 0, 0xBF, 0x00, 0x0000 nvram[0].ppin.hi: 0x25BEAAB, var[0].ppin.hi: 0x25BEAAB nvram[0].ppin.lo: 0x51561DAB, var[0].ppin.lo: 0x51561DAB Install EFI Memory Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE MRC: lowMemBase:0 lowMemSize:20 MRC: highMemBase:40 highMemSize:20 TSEG Unaligned Size is 0x00800000 TSEG Aligned Size is 0x00800000 Low Memory Discovered at 0x00000000 - 0x7F800000 PeiInstallPeiMemory MemoryBegin 0x7F000000, MemoryLength 0x800000 TopOfHighMem 0x180000000 High Memory Discovered at 0x100000000 - 0x180000000 Save NVRAM restore data into Hob MRC status = 00000000 UMA: Memory retrain occurred during warm reset. Force ME FW reload. ME UMA: ------------- MePlatformPolicyPpi Dump Begin ------------- Revision : 0x2 DidEnabled : 0x1 DidTimeout : 0x0 DidInitStat : 0x0 ME UMA: ------------- MePlatformPolicyPpi Dump End ---------------- ME UMA: Entered ME DRAM Init Done procedure. ME UMA: MeUmaBase read: FFF80000 ME UMA: InitStat: 3 ME UMA: ME H_GS written: 1300FFFF ME UMA: HFS read before DID ACK: 0x000F0345 ME UMA: BiosAction = 0 MeDramInitDone Complete. Checking for reset... ME UMA: MeFwsts2 = 3800E000. ME UMA: DID Ack was not received, no BIOS Action to process. Reset Requested: 0 Pipe Exit starting...Pipe Exit completed! Reset Requested: 0 Checking for Reset Requests ... None Continue with system BIOS POST ... mmCfgBase 80000000 QPI: CPU[0] bus = FF QPI: IIO[0] bus = 0 QPI: IIO[0] busbase = 0 Limit=FF QPI: IIO[0] IoBase = 0 IoLimit=FFFF QPI: IIO[0] IoApicBase = FEC00000 IoApicLimit=FEC3FFFF QPI: IIO[0] Mem32Base = 90000000 Mem32Limit=FBFFFFFF QPI: IIO[0] VtdBarAddress = FBFFC000 RcbaAddress=FBFFE000 PCI: IIO[0] NEW!PciResourceMem32Limit=FBFFBFFF QPI: CPU[1] is invalid QPI: IoApic[1] is invalid QPI: CPU[2] is invalid QPI: IoApic[2] is invalid QPI: CPU[3] is invalid QPI: IoApic[3] is invalid QPI: num of Cpus = 1 QPI: num of IIOs = 1 Node:0 BaseAddress:00000000 ElementSize:00000060 Setting pam0_hienable = 3 Setting pam1_loenable = 3 Setting pam1_hienable = 3 Setting pam2_loenable = 3 Setting pam2_hienable = 3 Setting pam3_loenable = 3 Setting pam3_hienable = 3 Setting pam4_loenable = 3 Setting pam4_hienable = 3 Setting pam5_loenable = 3 Setting pam5_hienable = 3 Setting pam6_loenable = 3 Setting pam6_hienable = 3 PeimMemoryQpiInit END Temp Stack : BaseAddress=0xFE184000 Length=0x7C000 Temp Heap : BaseAddress=0xFE108000 Length=0x27210 Total temporary memory: 1015808 bytes. temporary memory stack ever used: 482048 bytes. temporary memory heap used: 160272 bytes. Old Stack size 507904, New stack size 1048576 Heap Offset = 0x0 Stack Offset = 0x7F100000 Stack Hob: BaseAddress=0x7F000000 Length=0x100000 Loading PEIM at 0x0007F7F5198 EntryPoint=0x0007F7F5260 PeiCore.efi Reinstall PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Reinstall PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A Reinstall PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: F894643D-C449-42D1-8EA8-85BDD8C65BDE Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: FFEDAD80 Memory Discovered Notify invoked ... Loading PEIM at 0x0007F7EF188 EntryPoint=0x0007F7EF260 FspDxeIpl.efi Install PPI: EE4E5898-3914-4259-9D6E-DC7BD79403CF Install PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731 Install PPI: 1A36E4E7-FAB6-476A-8E75-695A0576FDD7 Loading PEIM at 0x0007F7E4000 EntryPoint=0x0007F7E4260 PcatSingleSegmentPciCfg2Pei.efi Install PPI: 057A449A-1FDC-4C06-BFC9-F53F6A99BB92 Loading PEIM at 0x0007F7CB000 EntryPoint=0x0007F7CB260 PlatformEarlyInit.efi PowerStateAfterG3 Default has been overridden by UPD option to 0 Install PPI: A7CED760-C71C-4E1A-ACB1-89604D5216CB Install PPI: 15344673-D365-4BE2-8513-1497CC07611D Loading PEIM at 0x0007F7B4000 EntryPoint=0x0007F7B4260 PchInitPeim.efi InstallPchInitPpi() - Start Rcba needs to be programmed before here PchMiscEarlyInit() - Start PchMiscEarlyInit() - End Install PPI: ED097352-9041-445A-80B6-B29D509E8845 Install PPI: 09EA894A-BE0D-4230-A003-EDC693B48E95 Register PPI Notify: 15344673-D365-4BE2-8513-1497CC07611D Notify: PPI Guid: 15344673-D365-4BE2-8513-1497CC07611D, Peim notify entry point: 7F7B5327 PchInitialize() - Start PchSataInit() - Start PchSataInit() - End [MPHY] Creating HOB to adjust Hsio settings from DXE, if required. [MPHY] SystemConfiguration.MeMphyDebugEnableSurvivabilityTable:0 [MPHY] SystemConfiguration.MeMphyDebugCorruptEndpoints:0 [MPHY] Suppress passing the expected ChipsetInit table to the DXE code, and further on to ME Unsupported PCH Stepping for PchDmiHsio PchInitialize() - End Install PPI: 1EDCBDF9-FFC6-4BD4-94F6-195D1DE17056 InstallPchInitPpi() - End Loading PEIM at 0x0007F7A7000 EntryPoint=0x0007F7A7260 IioDmiInitPeim.efi DEBUG:::: IioDmiInitPeiEntryPoint() Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 7F7A7515 PchDmiGen2Prog() Start PchDmiGen2Prog() End DEBUG:::: DmiVc1 = 0 ; DmiVcp = 0 ; DmiVcm = 0 Register PPI Notify: 1E2ACC41-E26A-483D-AFC7-A056C34E087B Notify: PPI Guid: 1E2ACC41-E26A-483D-AFC7-A056C34E087B, Peim notify entry point: 7F7A7E1E DEBUG:::: IioSouthComplexPeiInit() Enable/disable the SC CBDMA and GbE ports in the IIO IOSF bridge...(0,2,0,0x190) = 0x33 Loading PEIM at 0x0007F796000 EntryPoint=0x0007F796260 CpuCsrAccess.efi Install PPI: 0067835F-9A50-433A-8CBB-852078197814 Loading PEIM at 0x0007F74F000 EntryPoint=0x0007F74F280 IioInit.efi IsocEn changed because QPI config. IsocEn =0 Bifurcation of the ConfigIOU1 (Port#3) for CBM will be updated to = 4 Bifurcation of the ConfigIOU2 (Port#1) for CBM will be updated to = 1 Install PPI: DDC3080A-2740-4EC2-9AA5-A0ADEFD6FF9C Socket 0 does not support uplink port! Update iioErrPinDatReg = 7 EarlyCtlePhaseSettings for IIO[0] LbcPerIouData Addr 30604 = 0x3C46 LbcPerIouControl Addr 30600 = 0x975 LbcPerIouData Addr 30604 = 0x3C46 LbcPerIouControl Addr 30600 = 0x1175 LbcPerIouData Addr 30604 = 0x3C46 LbcPerIouControl Addr 30600 = 0x2175 LbcPerIouData Addr 30604 = 0x3C46 LbcPerIouControl Addr 30600 = 0x4175 LbcPerIouData Addr 31604 = 0x3C46 LbcPerIouControl Addr 31600 = 0x975 LbcPerIouData Addr 31604 = 0x3C46 LbcPerIouControl Addr 31600 = 0x1175 LbcPerIouData Addr 31604 = 0x3C46 LbcPerIouControl Addr 31600 = 0x2175 LbcPerIouData Addr 31604 = 0x3C46 LbcPerIouControl Addr 31600 = 0x4175 LbcPerIouData Addr 31604 = 0x3C46 LbcPerIouControl Addr 31600 = 0x8175 LbcPerIouData Addr 31604 = 0x3C46 LbcPerIouControl Addr 31600 = 0x10175 LbcPerIouData Addr 31604 = 0x3C46 LbcPerIouControl Addr 31600 = 0x20175 LbcPerIouData Addr 31604 = 0x3C46 LbcPerIouControl Addr 31600 = 0x40175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x975 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x1175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x2175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x4175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x8175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x10175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x20175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x40175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x80175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x100175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x200175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x400175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x800175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x1000175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x2000175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x4000175 Program Uniphy recipe Revision 6.00 Program RX Recipe values Start. B0 D6 F0 O30760h = 0x55 B0 D6 F1 O31760h = 0xAAAA B0 D7 F0 O38760h = 0xAAAAAAAA B0 D6 F0 O30710h = 0x208 B0 D6 F1 O31710h = 0x208208 B0 D7 F0 O38710h = 0x8208208 B0 D7 F0 O38714h = 0x8208 B0 D6 F0 O30708h = 0x410 B0 D6 F1 O31708h = 0x410410 B0 D7 F0 O38708h = 0x10410410 B0 D7 F0 O3870Ch = 0x10410 B0 D6 F0 O30704h = 0x12 B0 D6 F1 O31704h = 0x492 B0 D7 F0 O38704h = 0x492492 B0 D6 F0 O30700h = 0x24 B0 D6 F1 O31700h = 0x924 B0 D7 F0 O38700h = 0x924924 B0 D6 F0 O30730h = 0x0 B0 D6 F1 O31730h = 0x0 B0 D7 F0 O38730h = 0x0 B0 D6 F0 O30734h = 0x0 B0 D6 F1 O31734h = 0x0 B0 D7 F0 O38734h = 0x0 B0 D7 F0 O38738h = 0x0 B0 D6 F0 O30A50h = 0x3 B0 D6 F1 O31A50h = 0xF B0 D7 F0 O38A50h = 0xFF B0 D6 F0 O30A60h = 0x0 B0 D6 F1 O31A60h = 0x0 B0 D7 F0 O38A60h = 0x0 B0 D6 F1 O31A64h = 0xAA B0 D7 F0 O38A64h = 0xAAAA B0 D6 F0 O30788h = 0xAA B0 D6 F1 O31788h = 0xAAAA B0 D7 F0 O38788h = 0xAAAAAAAA B0 D6 F0 O30780h = 0xA B0 D6 F1 O31780h = 0xAA B0 D7 F0 O38780h = 0xAAAA B0 D6 F0 O30790h = 0xF B0 D6 F1 O31790h = 0xFF B0 D7 F0 O38790h = 0xFFFF B0 D6 F0 O306ECh = 0x42108 B0 D6 F1 O316ECh = 0x10842108 B0 D6 F1 O316F0h = 0x108 B0 D7 F0 O386ECh = 0x10842108 B0 D7 F0 O386F0h = 0x10842108 B0 D7 F0 O386F4h = 0x42108 B0 D6 F1 O316E0h = 0x16B5AD6B B0 D6 F1 O316E4h = 0x16B B0 D7 F0 O386E0h = 0x16B5AD6B B0 D7 F0 O386E4h = 0x16B5AD6B B0 D7 F0 O386E8h = 0x5AD6B B0 D6 F0 O307B0h = 0xFF B0 D6 F1 O317B0h = 0xFFFF B0 D7 F0 O387B0h = 0xFFFFFFFF B0 D6 F0 O30798h = 0xF B0 D6 F1 O31798h = 0xFF B0 D7 F0 O38798h = 0xFFFF B0 D6 F0 O30794h = 0x0 B0 D6 F1 O31794h = 0x0 B0 D7 F0 O38794h = 0x0 B0 D6 F0 O307A0h = 0x0 B0 D6 F1 O317A0h = 0x0 B0 D7 F0 O387A0h = 0x0 B0 D7 F0 O387A4h = 0x0 B0 D6 F0 O306C8h = 0x5 B0 D6 F1 O316C8h = 0x55 B0 D7 F0 O386C8h = 0x5555 B0 D6 F0 O306CCh = 0x3 B0 D6 F1 O316CCh = 0xF B0 D7 F0 O386CCh = 0xFF B0 D6 F7 O37650h = 0xC B0 D6 F0 O306ACh = 0xF B0 D6 F1 O316ACh = 0xFF B0 D7 F0 O386ACh = 0xFFFF B0 D6 F0 O306A0h = 0xFF B0 D6 F1 O316A0h = 0xFFFF B0 D7 F0 O386A0h = 0xFFFFFFFF B0 D6 F1 O31A38h = 0x200020 B0 D6 F1 O31A3Ch = 0x200020 B0 D7 F0 O38A38h = 0x200020 B0 D7 F0 O38A3Ch = 0x200020 B0 D7 F0 O38A40h = 0x200020 B0 D7 F0 O38A44h = 0x200020 B0 D6 F1 O31A88h = 0x5555 B0 D7 F0 O38A88h = 0x55555555 B0 D6 F0 O30A8Ch = 0x55 B0 D6 F1 O31A8Ch = 0x5555 B0 D7 F0 O38A8Ch = 0x55555555 B0 D6 F1 O31A90h = 0xBBBB B0 D7 F0 O38A90h = 0xBBBBBBBB B0 D6 F0 O30840h = 0x1EF B0 D6 F1 O31840h = 0x5AD6B B0 D7 F0 O38840h = 0x16B5AD6B B0 D7 F0 O38844h = 0x16B B0 D6 F0 O30838h = 0x16B B0 D6 F1 O31838h = 0x9CE73 B0 D7 F0 O38838h = 0x2739CE73 B0 D7 F0 O3883Ch = 0x273 B0 D6 F7 O37644h = 0x238100 B0 D6 F7 O37648h = 0x14000200 B0 D6 F7 O37628h = 0x12 B0 D6 F7 O37638h = 0x132 B0 D6 F7 O37614h = 0x202C000 B0 D6 F7 O3760Ch = 0xB B0 D6 F7 O37608h = 0x5000010 B0 D6 F7 O37608h = 0x4000010 B0 D6 F7 O37608h = 0x4000010 B0 D6 F7 O37634h = 0x24010 B0 D6 F7 O37654h = 0x1 B0 D6 F0 O30300h = 0x81300000 B0 D6 F1 O31300h = 0x81300000 B0 D6 F2 O32300h = 0x81300000 B0 D7 F0 O38300h = 0x81300000 B0 D7 F1 O39300h = 0x81300000 B0 D7 F2 O3A300h = 0x81300000 B0 D7 F3 O3B300h = 0x81300000 B0 D6 F0 O30300h = 0x81300000 B0 D6 F1 O31300h = 0x81300000 B0 D6 F2 O32300h = 0x81300000 B0 D7 F0 O38300h = 0x81300000 B0 D7 F1 O39300h = 0x81300000 B0 D7 F2 O3A300h = 0x81300000 B0 D7 F3 O3B300h = 0x81300000 B0 D6 F0 O30300h = 0x81200000 B0 D6 F1 O31300h = 0x81200000 B0 D6 F2 O32300h = 0x81200000 B0 D7 F0 O38300h = 0x81200000 B0 D7 F1 O39300h = 0x81200000 B0 D7 F2 O3A300h = 0x81200000 B0 D7 F3 O3B300h = 0x81200000 B0 D6 F0 O306B0h = 0x0 B0 D6 F1 O316B0h = 0x0 B0 D7 F0 O386B0h = 0x0 B0 D7 F0 O386B4h = 0x0 B0 D1 F0 O825Ch = 0x2777 B0 D1 F1 O925Ch = 0x2777 B0 D3 F0 O1825Ch = 0x2777 B0 D3 F1 O1925Ch = 0x2777 B0 D3 F2 O1A25Ch = 0x2777 B0 D3 F3 O1B25Ch = 0x2777 B0 D6 F0 O307C0h = 0x36 B0 D6 F1 O317C0h = 0xDB6 B0 D7 F0 O387C0h = 0xDB6DB6 B0 D6 F0 O30480h = 0xAE0449E2 B0 D6 F1 O31480h = 0xAE0449E2 B0 D7 F0 O38480h = 0xAE0449E2 B0 D6 F0 O30464h = 0x70BFE3 B0 D6 F1 O31464h = 0x70BFE3 B0 D7 F0 O38464h = 0x70BFE3 B0 D6 F1 O31464h = 0x73FFE3 B0 D7 F0 O38464h = 0x73FFE3 B0 D6 F0 O30490h = 0x4 B0 D6 F1 O31490h = 0x4 B0 D6 F2 O32490h = 0x4 B0 D7 F0 O38490h = 0x4 B0 D7 F1 O39490h = 0x4 B0 D7 F2 O3A490h = 0x4 B0 D7 F3 O3B490h = 0x4 B0 D6 F0 O304BCh = 0x29439104 B0 D6 F1 O314BCh = 0x29439105 B0 D7 F0 O384BCh = 0x29439105 B0 D6 F0 O30B04h = 0x48087185 B0 D6 F1 O31B04h = 0x48006181 B0 D7 F0 O38B04h = 0x48006181 B0 D6 F0 O303F4h = 0x8A340C10 B0 D6 F1 O313F4h = 0x8A340C10 B0 D7 F0 O383F4h = 0x8A340C10 B0 D6 F0 O3048Ch = 0x2120000 B0 D6 F1 O3148Ch = 0x2020000 B0 D7 F0 O3848Ch = 0x2020000 B0 D6 F0 O304C4h = 0x10083 B0 D6 F1 O314C4h = 0x10083 B0 D7 F0 O384C4h = 0x10083 B0 D6 F1 O3139Ch = 0x641000 B0 D6 F2 O3239Ch = 0x641000 B0 D7 F0 O3839Ch = 0x641000 B0 D7 F1 O3939Ch = 0x641000 B0 D7 F2 O3A39Ch = 0x641000 B0 D7 F3 O3B39Ch = 0x641000 B0 D6 F1 O313F0h = 0x3C002000 B0 D7 F0 O383F0h = 0x3C002000 B0 D6 F1 O313FCh = 0x2 B0 D7 F0 O383FCh = 0x2 B0 D6 F1 O313CCh = 0x1000480 B0 D6 F2 O323CCh = 0x1000480 B0 D7 F0 O383CCh = 0x1000480 B0 D7 F1 O393CCh = 0x1000480 B0 D7 F2 O3A3CCh = 0x1000480 B0 D7 F3 O3B3CCh = 0x1000480 B0 D6 F1 O31438h = 0x2057F B0 D7 F0 O38438h = 0x2057F B0 D6 F1 O31B24h = 0x10011 B0 D7 F0 O38B24h = 0x10011 Program RX Recipe values End. Gen3: Gen3PrelinkOverride(SKT=0, PORT=1a(1), Phase2=0, Phase3=11) Gen3: Gen3PrelinkOverride(SKT=0, PORT=1b(2), Phase2=0, Phase3=11) Gen3: Gen3PrelinkOverride(SKT=0, PORT=3a(7), Phase2=0, Phase3=11) Gen3: Gen3PrelinkOverride(SKT=0, PORT=3b(8), Phase2=0, Phase3=11) Gen3: Gen3PrelinkOverride(SKT=0, PORT=3c(9), Phase2=0, Phase3=11) Gen3: Gen3PrelinkOverride(SKT=0, PORT=3d(10), Phase2=0, Phase3=11) PcieLinkTrainingInit at device scanning... IIO=0, IOU2=1. IIO=0, IOU0=3. IIO=0, IOU1=4. DumpIioPcieLinkStatus()..... Skt[0], D[1]:F[0] Link Down! Skt[0], D[1]:F[1] Link Down! Skt[0], D[2]:F[0] Link up as x01 Gen1! Skt[0], D[2]:F[1] Link up as x01 Gen1! Skt[0], D[2]:F[2] Link up as x01 Gen1! Skt[0], D[2]:F[3] Link up as x01 Gen1! Skt[0], D[3]:F[0] Link up as x08 Gen2! Skt[0], D[3]:F[1] Link Down! Skt[0], D[3]:F[2] Link Down! Skt[0], D[3]:F[3] Link Down! Gen3: Gen3Override(SKT=0, PORT=1a(1), Phase2=0, Phase3=11) Socket:[0] Port:[1] GEN3 retrain reset skipped... Gen3: Gen3Override(SKT=0, PORT=1b(2), Phase2=0, Phase3=11) Gen3: Gen3Override(SKT=0, PORT=3a(7), Phase2=0, Phase3=11) Socket:[0] Port:[7] GEN3 retrain reset skipped... Gen3: Gen3Override(SKT=0, PORT=3b(8), Phase2=0, Phase3=11) Gen3: Gen3Override(SKT=0, PORT=3c(9), Phase2=0, Phase3=11) Gen3: Gen3Override(SKT=0, PORT=3d(10), Phase2=0, Phase3=11) Program WA 4986406 Skt[0], D[1]:F[0] : Link Down , WA not required! Skt[0], D[3]:F[0] : Link up in Gen1/Gen2 , Process Lanes for WA LBC Read value on lane:0 is 0x3DDF DumpIioPcieLinkStatus()..... Skt[0], D[1]:F[0] Link Down! Skt[0], D[1]:F[1] Link Down! Skt[0], D[2]:F[0] Link up as x01 Gen1! Skt[0], D[2]:F[1] Link up as x01 Gen1! Skt[0], D[2]:F[2] Link up as x01 Gen1! Skt[0], D[2]:F[3] Link up as x01 Gen1! Skt[0], D[3]:F[0] Link up as x08 Gen2! Skt[0], D[3]:F[1] Link Down! Skt[0], D[3]:F[2] Link Down! Skt[0], D[3]:F[3] Link Down! DMI IIOInitPhase1... Initialize IIO:0 PCIE port:1 Func:0... PciEarlyInit at device scanning... Initialize IIO:0 PCIE port:2 Func:0... PciEarlyInit at device scanning... Initialize IIO:0 PCIE port:2 Func:2... PciEarlyInit at device scanning... Initialize IIO:0 PCIE port:3 Func:0... PciEarlyInit at device scanning... DMI IIOInitPhase2... Enabling PCIE Dev:1 Func:0 Slot Power... (auto mode) No speed change required! IIO 0 Port 1 ASPM configured as 7 Vendor specific pcie Link Init port:2 Func0... Vendor specific pcie Link Init port:2 Func2... Enabling PCIE Dev:3 Func:0 Slot Power... (auto mode) No speed change required! IIO 0 Port 7 ASPM configured as 7 DMI IIOInitPhase3... DMI Link Retrain() DMI speed is 5Gb/s (Gen2) PciPostInit port:1 Func0... PciPostInit port:2 Func0... PciPostInit port:2 Func2... PciPostInit port:3 Func0... Initialize IIO[0] IOxAPIC... IIO[0] IOxAPIC Base=FEC01000 IIO[0] TOMMIOL_OB = FEF00000 VT-d Chipset Initialization for IIO0 ... Vt-D base address : 0x7F130935FBFFC000 VtDGenCtrlReg : 0x000080A8 VtDIsoCtrlReg : 0x00000001 Non-Iso Engine CapReg : 0x08D2078C106F0466 Non-Iso Engine ExtCapReg : 0x0000000000F020DF IIOMISCCTRL for IIO 0 = 0x42030170 Initializing NTB for SKT0 setup PPD 0 Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Calling IioClockDisables: Socket=0 IioClockDisables: Socket=0, Port=0 IioClockDisables: Data Link Active or skipped for D0 : F0 IioClockDisables: DisableBitMap=CEE0000 IioClockDisables: Socket=0, Port=1 IioClockDisables: Socket=0, Port=2 IioClockDisables: Socket=0, Port=3 IioClockDisables: Data Link Active or skipped for D2 : F0 IioClockDisables: DisableBitMap=8AA0000 IioClockDisables: Socket=0, Port=4 IioClockDisables: Data Link Active or skipped for D2 : F1 IioClockDisables: DisableBitMap=8AA0000 IioClockDisables: Socket=0, Port=5 IioClockDisables: Data Link Active or skipped for D2 : F2 IioClockDisables: DisableBitMap=8AA0000 IioClockDisables: Socket=0, Port=6 IioClockDisables: Data Link Active or skipped for D2 : F3 IioClockDisables: DisableBitMap=8AA0000 IioClockDisables: Socket=0, Port=7 IioClockDisables: Data Link Active or skipped for D3 : F0 IioClockDisables: DisableBitMap=220000 IioClockDisables: Socket=0, Port=8 IioClockDisables: Socket=0, Port=9 IioClockDisables: Socket=0, Port=10 IIO Port/Clocks Powering down: Socket=0, Disable Bit Map=80220000 IioInit Secure the Platform (TXT).. IioInit PCIe device hide.. Bus=255, Device=1, Function=1 is hidden. Bus=255, Device=2, Function=1 is hidden. Bus=255, Device=2, Function=3 is hidden. Bus=255, Device=3, Function=1 is hidden. Bus=255, Device=3, Function=2 is hidden. Bus=255, Device=3, Function=3 is hidden. Skt[0], D[1]:F[0] Link Down! Skt[0], D[2]:F[0] Link up as x01 Gen1! Skt[0], D[2]:F[2] Link up as x01 Gen1! Skt[0], D[3]:F[0] Link up as x08 Gen2! Register PPI Notify: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793 Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Loading PEIM at 0x0007F73C000 EntryPoint=0x0007F73C260 MpInit.efi Install PPI: DD29124D-7819-4F15-BB07-351E7451D71C Loading PEIM at 0x0007F72F000 EntryPoint=0x0007F72F260 HeciInitDxe.efi [HECI-0] VID-DID: 8086-8C3A Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Loading PEIM at 0x0007F71C000 EntryPoint=0x0007F71C260 PlatformLateInit.efi TempMmioBase = 90000000 TempMmioLimit = FBFFFFFF TempIoBase = 1000 TempIoLimit = FFFF XHCI (14h) = 90000000...90003000 (00003000) EHCI (1Dh) = 90003000...90003400 (00000400) EHCI2 (1Ah) = 90003400...90003800 (00000400) SATA (1Fh.2) [AHCI] = 90003800...90004800 (00001000) PCI Root Port[0] Status from UPD = 1 PCI Root Port[1] Status from UPD = 1 PCI Root Port[2] Status from UPD = 1 PCI Root Port[3] Status from UPD = 1 PCI Root Port[4] Status from UPD = 1 PCI Root Port[5] Status from UPD = 1 PCI Root Port[6] Status from UPD = 1 PCI Root Port[7] Status from UPD = 1 Cpu Type= 0x56, Cpu Stepping= 0x3 Install PPI: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5 Number of Active Cores / Threads = 6 / C :::: CapId5 = 6000965, PlatformInfo->CpuData.SkuSlices = 965 :::: CapId4 = 24080D03, PlatformInfo->CpuData.CpuPCPSInfo = 3000C Socket Present BitMap, mmCfgBase, dimmTypePresent, BoardId, CpuType 1, 80000000, 7F130E8E, 0 56 EFI_PPM_STRUCT size: 166 :: !!! PPM Revision: Major:00Minor:01Rev:0000!!!. :: Reading MSR_TURBO_POWER_LIMIT (610) =4381C2 0 :: Reading Socket = 0, CSR_TURBO_POWER_LIMIT=0 0 :: Wrote Socket = 0, CSR_PCIE_ILTR_OVRD=0 Program FAST_RAPL_NSTRIKE_PL2_DUTY_CYCLE as 100 (39) Detected Boot Mode 0 Detected 12 CPU threads Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Register PPI Notify: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793 Loading PEIM at 0x0007F6E6000 EntryPoint=0x0007F6E6260 PchInitDxe.efi PchInitEntryPoint() Start PCH Device: ------------- RCBA 0xFED1C000 PmBase 0x400 GpioBase 0x500 ------------- ------------------------ PCH Dump platform protocol Start ----------------- PCH PLATFORM POLICY Revision= 1 PCH PLATFORM POLICY BusNumber= 0 ------------------------ PCH_DEVICE_ENABLE ----------------- PCH_DEVICE_ENABLE Lan= 1 PCH_DEVICE_ENABLE Azalia= 2 PCH_DEVICE_ENABLE Sata= 1 PCH_DEVICE_ENABLE Smbus= 1 PCH_DEVICE_ENABLE PciClockRun= 1 PCH_DEVICE_ENABLE Display= 1 PCH_DEVICE_ENABLE Crid0 ------------------------ PCH_USB_CONFIG ----------------- PCH_USB_CONFIG UsbPerPortCtl= 0 PCH_USB_CONFIG Ehci1Usbr= 0 PCH_USB_CONFIG Ehci2Usbr= 0 PCH_USB_CONFIG PortSettings[0] Enabled= 1 PCH_USB_CONFIG PortSettings[0] Location= 1 PCH_USB_CONFIG PortSettings[1] Enabled= 1 PCH_USB_CONFIG PortSettings[1] Location= 1 PCH_USB_CONFIG PortSettings[2] Enabled= 1 PCH_USB_CONFIG PortSettings[2] Location= 1 PCH_USB_CONFIG PortSettings[3] Enabled= 1 PCH_USB_CONFIG PortSettings[3] Location= 1 PCH_USB_CONFIG PortSettings[4] Enabled= 1 PCH_USB_CONFIG PortSettings[4] Location= 1 PCH_USB_CONFIG PortSettings[5] Enabled= 1 PCH_USB_CONFIG PortSettings[5] Location= 1 PCH_USB_CONFIG PortSettings[6] Enabled= 1 PCH_USB_CONFIG PortSettings[6] Location= 1 PCH_USB_CONFIG PortSettings[7] Enabled= 1 PCH_USB_CONFIG PortSettings[7] Location= 1 PCH_USB_CONFIG PortSettings[8] Enabled= 1 PCH_USB_CONFIG PortSettings[8] Location= 1 PCH_USB_CONFIG PortSettings[9] Enabled= 1 PCH_USB_CONFIG PortSettings[9] Location= 1 PCH_USB_CONFIG PortSettings[10] Enabled= 1 PCH_USB_CONFIG PortSettings[10] Location= 1 PCH_USB_CONFIG PortSettings[11] Enabled= 1 PCH_USB_CONFIG PortSettings[11] Location= 1 PCH_USB_CONFIG PortSettings[12] Enabled= 1 PCH_USB_CONFIG PortSettings[12] Location= 1 PCH_USB_CONFIG PortSettings[13] Enabled= 1 PCH_USB_CONFIG PortSettings[13] Location= 1 PCH_USB_CONFIG Usb20Settings[0] Enabled= 1 PCH_USB_CONFIG Usb20Settings[1] Enabled= 0 PCH_USB_CONFIG Usb30Settings.Mode= 2 PCH_USB_CONFIG Usb30Settings.PreBootSupport= 0 XhciStreams is obsoleted, it doesn't effect any setting change since Revision 2. PCH_USB_CONFIG Usb30Settings.ManualMode= 0 PCH_USB_CONFIG Usb30Settings.XhciIdleL1= 1 PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[0]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[1]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[2]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[3]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[4]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[5]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[6]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[7]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[8]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[9]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[10]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[11]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[12]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[13]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb30PerPinEnable[0]= 0 PCH_USB_CONFIG Usb30Settings.ManualModeUsb30PerPinEnable[1]= 0 PCH_USB_CONFIG Usb30Settings.ManualModeUsb30PerPinEnable[2]= 0 PCH_USB_CONFIG Usb30Settings.ManualModeUsb30PerPinEnable[3]= 0 PCH_USB_CONFIG Usb30Settings.ManualModeUsb30PerPinEnable[4]= 0 PCH_USB_CONFIG Usb30Settings.ManualModeUsb30PerPinEnable[5]= 0 PCH_USB_CONFIG Usb20OverCurrentPins[0]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[1]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[2]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[3]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[4]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[5]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[6]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[7]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[8]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[9]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[10]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[11]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[12]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[13]= OC8 PCH_USB_CONFIG Usb30OverCurrentPins[0]= OC8 PCH_USB_CONFIG Usb30OverCurrentPins[1]= OC8 PCH_USB_CONFIG Usb30OverCurrentPins[2]= OC8 PCH_USB_CONFIG Usb30OverCurrentPins[3]= OC8 PCH_USB_CONFIG Usb30OverCurrentPins[4]= OC8 PCH_USB_CONFIG Usb30OverCurrentPins[5]= OC8 PCH_USB_CONFIG Usb20PortLength[0]= 23.8 PCH_USB_CONFIG Usb20PortLength[1]= 15.9 PCH_USB_CONFIG Usb20PortLength[2]= 23.8 PCH_USB_CONFIG Usb20PortLength[3]= 23.8 PCH_USB_CONFIG Usb20PortLength[4]= 23.8 PCH_USB_CONFIG Usb20PortLength[5]= 23.8 PCH_USB_CONFIG Usb20PortLength[6]= 23.8 PCH_USB_CONFIG Usb20PortLength[7]= 23.8 PCH_USB_CONFIG Usb20PortLength[8]= 23.8 PCH_USB_CONFIG Usb20PortLength[9]= 23.8 PCH_USB_CONFIG Usb20PortLength[10]= 23.8 PCH_USB_CONFIG Usb20PortLength[11]= 23.8 PCH_USB_CONFIG Usb20PortLength[12]= 23.8 PCH_USB_CONFIG Usb20PortLength[13]= 10.1 ------------------------ PCH_PCI_EXPRESS_CONFIG ----------------- PCH_PCI_EXPRESS_CONFIG TempRootPortBusNumMin= 2 PCH_PCI_EXPRESS_CONFIG TempRootPortBusNumMax= 2 PCH_PCI_EXPRESS_CONFIG RootPort[0] Enabled= 1 PCH_PCI_EXPRESS_CONFIG RootPort[0] Hide= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] SlotImplemented= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] HotPlug= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] PmSci= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] ExtSync= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] UnsupportedRequestReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] FatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] NoFatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] CorrectableErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] PmeInterrupt= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] SystemErrorOnFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] SystemErrorOnNonFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] SystemErrorOnCorrectableError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] AdvancedErrorReporting= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] TransmitterHalfSwing= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] FunctionNumber= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] PhysicalSlotNumber= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] CompletionTimeout= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] Aspm= 4 PCH_PCI_EXPRESS_CONFIG RootPort[1] Enabled= 1 PCH_PCI_EXPRESS_CONFIG RootPort[1] Hide= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] SlotImplemented= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] HotPlug= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] PmSci= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] ExtSync= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] UnsupportedRequestReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] FatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] NoFatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] CorrectableErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] PmeInterrupt= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] SystemErrorOnFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] SystemErrorOnNonFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] SystemErrorOnCorrectableError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] AdvancedErrorReporting= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] TransmitterHalfSwing= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] FunctionNumber= 1 PCH_PCI_EXPRESS_CONFIG RootPort[1] PhysicalSlotNumber= 1 PCH_PCI_EXPRESS_CONFIG RootPort[1] CompletionTimeout= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] Aspm= 4 PCH_PCI_EXPRESS_CONFIG RootPort[2] Enabled= 1 PCH_PCI_EXPRESS_CONFIG RootPort[2] Hide= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] SlotImplemented= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] HotPlug= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] PmSci= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] ExtSync= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] UnsupportedRequestReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] FatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] NoFatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] CorrectableErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] PmeInterrupt= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] SystemErrorOnFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] SystemErrorOnNonFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] SystemErrorOnCorrectableError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] AdvancedErrorReporting= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] TransmitterHalfSwing= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] FunctionNumber= 2 PCH_PCI_EXPRESS_CONFIG RootPort[2] PhysicalSlotNumber= 2 PCH_PCI_EXPRESS_CONFIG RootPort[2] CompletionTimeout= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] Aspm= 4 PCH_PCI_EXPRESS_CONFIG RootPort[3] Enabled= 1 PCH_PCI_EXPRESS_CONFIG RootPort[3] Hide= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] SlotImplemented= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] HotPlug= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] PmSci= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] ExtSync= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] UnsupportedRequestReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] FatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] NoFatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] CorrectableErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] PmeInterrupt= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] SystemErrorOnFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] SystemErrorOnNonFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] SystemErrorOnCorrectableError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] AdvancedErrorReporting= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] TransmitterHalfSwing= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] FunctionNumber= 3 PCH_PCI_EXPRESS_CONFIG RootPort[3] PhysicalSlotNumber= 3 PCH_PCI_EXPRESS_CONFIG RootPort[3] CompletionTimeout= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] Aspm= 4 PCH_PCI_EXPRESS_CONFIG RootPort[4] Enabled= 1 PCH_PCI_EXPRESS_CONFIG RootPort[4] Hide= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] SlotImplemented= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] HotPlug= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] PmSci= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] ExtSync= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] UnsupportedRequestReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] FatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] NoFatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] CorrectableErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] PmeInterrupt= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] SystemErrorOnFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] SystemErrorOnNonFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] SystemErrorOnCorrectableError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] AdvancedErrorReporting= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] TransmitterHalfSwing= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] FunctionNumber= 4 PCH_PCI_EXPRESS_CONFIG RootPort[4] PhysicalSlotNumber= 4 PCH_PCI_EXPRESS_CONFIG RootPort[4] CompletionTimeout= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] Aspm= 4 PCH_PCI_EXPRESS_CONFIG RootPort[5] Enabled= 1 PCH_PCI_EXPRESS_CONFIG RootPort[5] Hide= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] SlotImplemented= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] HotPlug= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] PmSci= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] ExtSync= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] UnsupportedRequestReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] FatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] NoFatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] CorrectableErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] PmeInterrupt= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] SystemErrorOnFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] SystemErrorOnNonFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] SystemErrorOnCorrectableError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] AdvancedErrorReporting= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] TransmitterHalfSwing= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] FunctionNumber= 5 PCH_PCI_EXPRESS_CONFIG RootPort[5] PhysicalSlotNumber= 5 PCH_PCI_EXPRESS_CONFIG RootPort[5] CompletionTimeout= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] Aspm= 4 PCH_PCI_EXPRESS_CONFIG RootPort[6] Enabled= 1 PCH_PCI_EXPRESS_CONFIG RootPort[6] Hide= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] SlotImplemented= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] HotPlug= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] PmSci= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] ExtSync= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] UnsupportedRequestReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] FatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] NoFatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] CorrectableErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] PmeInterrupt= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] SystemErrorOnFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] SystemErrorOnNonFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] SystemErrorOnCorrectableError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] AdvancedErrorReporting= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] TransmitterHalfSwing= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] FunctionNumber= 6 PCH_PCI_EXPRESS_CONFIG RootPort[6] PhysicalSlotNumber= 6 PCH_PCI_EXPRESS_CONFIG RootPort[6] CompletionTimeout= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] Aspm= 4 PCH_PCI_EXPRESS_CONFIG RootPort[7] Enabled= 1 PCH_PCI_EXPRESS_CONFIG RootPort[7] Hide= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] SlotImplemented= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] HotPlug= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] PmSci= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] ExtSync= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] UnsupportedRequestReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] FatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] NoFatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] CorrectableErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] PmeInterrupt= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] SystemErrorOnFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] SystemErrorOnNonFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] SystemErrorOnCorrectableError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] AdvancedErrorReporting= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] TransmitterHalfSwing= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] FunctionNumber= 7 PCH_PCI_EXPRESS_CONFIG RootPort[7] PhysicalSlotNumber= 7 PCH_PCI_EXPRESS_CONFIG RootPort[7] CompletionTimeout= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] Aspm= 4 PCH_PCI_EXPRESS_CONFIG NumOfDevAspmOverride= 26 PCH_PCI_EXPRESS_CONFIG DevAspmOverride VendorId= 8086 PCH_PCI_EXPRESS_CONFIG DevAspmOverride DeviceId= 422B PCH_PCI_EXPRESS_CONFIG DevAspmOverride RevId= FF PCH_PCI_EXPRESS_CONFIG DevAspmOverride BaseClassCode= FF PCH_PCI_EXPRESS_CONFIG DevAspmOverride SubClassCode= FF PCH_PCI_EXPRESS_CONFIG DevAspmOverride EndPointAspm= 2 PCH_PCI_EXPRESS_CONFIG PchPcieSbdePort= 0 PCH_PCI_EXPRESS_CONFIG RootPortClockGating= 1 PCH_PCI_EXPRESS_CONFIG EnableSubDecode= 0 ------------------------ PCH_SATA_CONFIG ----------------- PCH_SATA_CONFIG PortSettings[0] Enabled= 1 PCH_SATA_CONFIG PortSettings[0] HotPlug= 1 PCH_SATA_CONFIG PortSettings[0] InterlockSw= 0 PCH_SATA_CONFIG PortSettings[0] External= 0 PCH_SATA_CONFIG PortSettings[0] SpinUp= 0 PCH_SATA_CONFIG PortSettings[0] SolidStateDrive= 0 PCH_SATA_CONFIG PortSettings[0] EnableDitoConfig= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DmVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DitoVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[1] Enabled= 1 PCH_SATA_CONFIG PortSettings[1] HotPlug= 1 PCH_SATA_CONFIG PortSettings[1] InterlockSw= 0 PCH_SATA_CONFIG PortSettings[1] External= 0 PCH_SATA_CONFIG PortSettings[1] SpinUp= 0 PCH_SATA_CONFIG PortSettings[1] SolidStateDrive= 0 PCH_SATA_CONFIG PortSettings[0] EnableDitoConfig= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DmVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DitoVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[2] Enabled= 1 PCH_SATA_CONFIG PortSettings[2] HotPlug= 1 PCH_SATA_CONFIG PortSettings[2] InterlockSw= 0 PCH_SATA_CONFIG PortSettings[2] External= 0 PCH_SATA_CONFIG PortSettings[2] SpinUp= 0 PCH_SATA_CONFIG PortSettings[2] SolidStateDrive= 0 PCH_SATA_CONFIG PortSettings[0] EnableDitoConfig= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DmVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DitoVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[3] Enabled= 1 PCH_SATA_CONFIG PortSettings[3] HotPlug= 1 PCH_SATA_CONFIG PortSettings[3] InterlockSw= 0 PCH_SATA_CONFIG PortSettings[3] External= 0 PCH_SATA_CONFIG PortSettings[3] SpinUp= 0 PCH_SATA_CONFIG PortSettings[3] SolidStateDrive= 0 PCH_SATA_CONFIG PortSettings[0] EnableDitoConfig= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DmVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DitoVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[4] Enabled= 1 PCH_SATA_CONFIG PortSettings[4] HotPlug= 1 PCH_SATA_CONFIG PortSettings[4] InterlockSw= 0 PCH_SATA_CONFIG PortSettings[4] External= 0 PCH_SATA_CONFIG PortSettings[4] SpinUp= 0 PCH_SATA_CONFIG PortSettings[4] SolidStateDrive= 0 PCH_SATA_CONFIG PortSettings[0] EnableDitoConfig= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DmVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DitoVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[5] Enabled= 1 PCH_SATA_CONFIG PortSettings[5] HotPlug= 1 PCH_SATA_CONFIG PortSettings[5] InterlockSw= 0 PCH_SATA_CONFIG PortSettings[5] External= 0 PCH_SATA_CONFIG PortSettings[5] SpinUp= 0 PCH_SATA_CONFIG PortSettings[5] SolidStateDrive= 0 PCH_SATA_CONFIG PortSettings[0] EnableDitoConfig= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DmVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DitoVal= 7F0FDEA0 PCH_SATA_CONFIG RaidAlternateId= 0 PCH_SATA_CONFIG Raid0= 1 PCH_SATA_CONFIG Raid1= 1 PCH_SATA_CONFIG Raid10= 1 PCH_SATA_CONFIG Raid5= 1 PCH_SATA_CONFIG Irrt= 1 PCH_SATA_CONFIG OromUiBanner= 1 PCH_SATA_CONFIG HddUnlock= 1 PCH_SATA_CONFIG LedLocate= 1 PCH_SATA_CONFIG IrrtOnly= 1 PCH_SATA_CONFIG TestMode= 0 PCH_SATA_CONFIG SalpSupport= 1 PCH_SATA_CONFIG LegacyMode= 0 PCH_SATA_CONFIG SmartStorage= 1 PCH_SATA_CONFIG OromUiDelay= 0 PCH_SATA_CONFIG SpeedSupport= 3 ------------------------ PCH_AZALIA_CONFIG ----------------- PCH_AZALIA_CONFIG Pme= 0 PCH_AZALIA_CONFIG DS= 0 PCH_AZALIA_CONFIG DA= 0 PCH_AZALIA_CONFIG AzaliaVerbTableNum= B PCH_AZALIA_CONFIG AzaliaVerbTable Header VendorDeviceId= 10EC0272 PCH_AZALIA_CONFIG AzaliaVerbTable Header SubSystemId= 0 PCH_AZALIA_CONFIG AzaliaVerbTable Header RevisionId= 0 PCH_AZALIA_CONFIG AzaliaVerbTable Header FrontPanelSupport= 1 PCH_AZALIA_CONFIG AzaliaVerbTable Header NumberOfRearJacks= E PCH_AZALIA_CONFIG AzaliaVerbTable Header NumberOfFrontJacks= 2 PCH_AZALIA_CONFIG AzaliaVerbTable VerbTableData= 7F7208B8 PCH_AZALIA_CONFIG ResetWaitTimer= 12C ------------------------ PCH_SMBUS_CONFIG ----------------- PCH_SMBUS_CONFIG NumRsvdSmbusAddresses= 4 PCH_SMBUS_CONFIG RsvdSmbusAddressTable= 7F7208A8 ------------------------ PCH_MISC_PM_CONFIG ----------------- PCH_MISC_PM_CONFIG PowerResetStatusClear MeWakeSts= 1 PCH_MISC_PM_CONFIG PowerResetStatusClear MeHrstColdSts= 1 PCH_MISC_PM_CONFIG PowerResetStatusClear MeHrstWarmSts= 1 PCH_MISC_PM_CONFIG PowerResetStatusClear MeHostPowerDn= 0 PCH_MISC_PM_CONFIG PowerResetStatusClear WolOvrWkSts= 0 PCH_MISC_PM_CONFIG WakeConfig PmeB0S5Dis= 0 PCH_MISC_PM_CONFIG WakeConfig WolEnableOverride= 0 PCH_MISC_PM_CONFIG WakeConfig Gp27WakeFromDeepSx= 0 PCH_MISC_PM_CONFIG PchDeepSxPol= 0 PCH_MISC_PM_CONFIG PchSlpS3MinAssert= 2 PCH_MISC_PM_CONFIG PchSlpS4MinAssert= 4 PCH_MISC_PM_CONFIG PchSlpSusMinAssert= 3 PCH_MISC_PM_CONFIG PchSlpAMinAssert= 3 PCH_MISC_PM_CONFIG SlpStrchSusUp= 0 PCH_MISC_PM_CONFIG SlpLanLowDc= 1 PCH_MISC_PM_CONFIG PchPwrCycDur= 4 ------------------------ PCH_IO_APIC_CONFIG ----------------- PCH_IO_APIC_CONFIG BdfValid= 1 PCH_IO_APIC_CONFIG BusNumber= F0 PCH_IO_APIC_CONFIG DeviceNumber= 1F PCH_IO_APIC_CONFIG FunctionNumber= 7 ------------------------ PCH_DEFAULT_SVID_SID ----------------- PCH_DEFAULT_SVID_SID SubSystemVendorId= 8086 PCH_DEFAULT_SVID_SID SubSystemId= 7270 ------------------------ PCH_LOCK_DOWN_CONFIG ----------------- PCH_LOCK_DOWN_CONFIG GlobalSmi= 1 PCH_LOCK_DOWN_CONFIG BiosInterface= 1 PCH_LOCK_DOWN_CONFIG GpioLockDown= 0 PCH_LOCK_DOWN_CONFIG RtcLock= 1 PCH_LOCK_DOWN_CONFIG BiosLock= 0 PCH_LOCK_DOWN_CONFIG PchBiosLockIoTrapAddress= 0 PCH_LOCK_DOWN_CONFIG GbeFlashLockDown= 0 ------------------------ PCH_THERMAL_CONFIG ----------------- PCH_THERMAL_CONFIG ThermalAlertEnable TselLock 1 PCH_THERMAL_CONFIG ThermalAlertEnable TscLock 1 PCH_THERMAL_CONFIG ThermalAlertEnable TsmicLock= 1 PCH_THERMAL_CONFIG ThermalAlertEnable PhlcLock= 1 PCH_THERMAL_CONFIG ThermalDeviceEnable (D31:F6) 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING THERMAL_THROTTLE_LEVELS T0Level 6B centigrade degree PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING THERMAL_THROTTLE_LEVELS T1Level 6E centigrade degree PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING THERMAL_THROTTLE_LEVELS T2Level 71 centigrade degree PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING THERMAL_THROTTLE_LEVELS TTEnable 1 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING THERMAL_THROTTLE_LEVELS TTState13Enable 1 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING THERMAL_THROTTLE_LEVELS TTLock 1 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING THERMAL_THROTTLE_LEVELS SuggestedSetting 1 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING DMI_HW_WIDTH_CONTROL DmiTsawEn 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING DMI_HW_WIDTH_CONTROL TS0TW 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING DMI_HW_WIDTH_CONTROL TS1TW 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING DMI_HW_WIDTH_CONTROL TS2TW 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING DMI_HW_WIDTH_CONTROL TS3TW 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING DMI_HW_WIDTH_CONTROL SuggestedSetting 1 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P0T1M 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P0T2M 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P0T3M 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P0TDisp 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P0Tinact 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P0TDispFinit 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P1T1M 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P1T2M 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P1T3M 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P1TDisp 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P1Tinact 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P1TDispFinit 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE SuggestedSetting 1 PCH_THERMAL_CONFIG PchHotLevel = 73 ------------------------ PCH_LPC_HPET_CONFIG ----------------- PCH_LPC_HPET_CONFIG HpetConfig 1 PCH_LPC_HPET_CONFIG Hpet[0] BusNumber F0 PCH_LPC_HPET_CONFIG Hpet[0] DeviceNumber F PCH_LPC_HPET_CONFIG Hpet[0] FunctionNumber 0 PCH_LPC_HPET_CONFIG Hpet[1] BusNumber F0 PCH_LPC_HPET_CONFIG Hpet[1] DeviceNumber F PCH_LPC_HPET_CONFIG Hpet[1] FunctionNumber 0 PCH_LPC_HPET_CONFIG Hpet[2] BusNumber F0 PCH_LPC_HPET_CONFIG Hpet[2] DeviceNumber F PCH_LPC_HPET_CONFIG Hpet[2] FunctionNumber 0 PCH_LPC_HPET_CONFIG Hpet[3] BusNumber F0 PCH_LPC_HPET_CONFIG Hpet[3] DeviceNumber F PCH_LPC_HPET_CONFIG Hpet[3] FunctionNumber 0 PCH_LPC_HPET_CONFIG Hpet[4] BusNumber F0 PCH_LPC_HPET_CONFIG Hpet[4] DeviceNumber F PCH_LPC_HPET_CONFIG Hpet[4] FunctionNumber 0 PCH_LPC_HPET_CONFIG Hpet[5] BusNumber F0 PCH_LPC_HPET_CONFIG Hpet[5] DeviceNumber F PCH_LPC_HPET_CONFIG Hpet[5] FunctionNumber 0 PCH_LPC_HPET_CONFIG Hpet[6] BusNumber F0 PCH_LPC_HPET_CONFIG Hpet[6] DeviceNumber F PCH_LPC_HPET_CONFIG Hpet[6] FunctionNumber 0 PCH_LPC_HPET_CONFIG Hpet[7] BusNumber F0 PCH_LPC_HPET_CONFIG Hpet[7] DeviceNumber F PCH_LPC_HPET_CONFIG Hpet[7] FunctionNumber 0 ------------------------ PCH_LPC_SIRQ_CONFIG ----------------- PCH_LPC_SIRQ_CONFIG SirqEnable= 1 PCH_LPC_SIRQ_CONFIG SirqMode= 0 PCH_LPC_SIRQ_CONFIG StartFramePulse= 0 ------------------------ PCH_DMI_CONFIG ----------------- PCH_DMI_CONFIG DmiAspm= 1 PCH_DMI_CONFIG DmiExtSync= 0 PCH_DMI_CONFIG DmiIot= 0 ------------------------ PCH_PWR_OPT_CONFIG ----------------- PCH_PWR_OPT_CONFIG PchPwrOptDmi= 1 PCH_PWR_OPT_CONFIG PchPwrOptGbe= 1 PCH_PWR_OPT_CONFIG PchPwrOptXhci= 0 PCH_PWR_OPT_CONFIG PchPwrOptEhci= 0 PCH_PWR_OPT_CONFIG PchPwrOptSata= 0 PCH_PWR_OPT_CONFIG MemCloseStateEn= 1 PCH_PWR_OPT_CONFIG InternalObffEn= 1 PCH_PWR_OPT_CONFIG ExternalObffEn= 0 PCH_PWR_OPT_CONFIG RootPort[0] LtrEnable= 1 PCH_PWR_OPT_CONFIG RootPort[0] ObffEnable= 0 PCH_PWR_OPT_CONFIG RootPort[1] LtrEnable= 1 PCH_PWR_OPT_CONFIG RootPort[1] ObffEnable= 0 PCH_PWR_OPT_CONFIG RootPort[2] LtrEnable= 1 PCH_PWR_OPT_CONFIG RootPort[2] ObffEnable= 0 PCH_PWR_OPT_CONFIG RootPort[3] LtrEnable= 1 PCH_PWR_OPT_CONFIG RootPort[3] ObffEnable= 0 PCH_PWR_OPT_CONFIG RootPort[4] LtrEnable= 1 PCH_PWR_OPT_CONFIG RootPort[4] ObffEnable= 0 PCH_PWR_OPT_CONFIG RootPort[5] LtrEnable= 1 PCH_PWR_OPT_CONFIG RootPort[5] ObffEnable= 0 PCH_PWR_OPT_CONFIG RootPort[6] LtrEnable= 1 PCH_PWR_OPT_CONFIG RootPort[6] ObffEnable= 0 PCH_PWR_OPT_CONFIG RootPort[7] LtrEnable= 1 PCH_PWR_OPT_CONFIG RootPort[7] ObffEnable= 0 PCH_PWR_OPT_CONFIG NumOfDevLtrOverride= 0 PCH_PWR_OPT_CONFIG DevLtrOverride VendorId= 0 PCH_PWR_OPT_CONFIG DevLtrOverride DeviceId= 0 PCH_PWR_OPT_CONFIG DevLtrOverride RevId= 0 PCH_PWR_OPT_CONFIG DevLtrOverride SnoopLatency= 0 PCH_PWR_OPT_CONFIG DevLtrOverride NonSnoopLatency= 0 PCH_PWR_OPT_CONFIG LegacyDmaDisable= 0 ------------------------ PCH Dump platform protocol End ----------------- InitializePchDevice() Start ChipsetInitSettingsCheck() Start ConfigureMiscPm() Start ConfigureMiscPm() End ConfigureDmi() Start ConfigureDmi() End ConfigureMiscItems() Start ConfigureMiscItems() End ConfigureLan() Start LAN can be enabled or disabled as SPI is in Descriptor Mode. ConfigureLan() End ConfigureUsb() Start CommonUsbInit() - Start CommonUsbInit() - End ConfigureUsb() End PchInitRootPorts() Start PCI Root Port[0] Status = 1 PCI Root Port[1] Status = 1 PCI Root Port[2] Status = 1 PCI Root Port[3] Status = 1 PCI Root Port[4] Status = 1 PCI Root Port[5] Status = 1 PCI Root Port[6] Status = 1 PCI Root Port[7] Status = 1 PCI Function 1 disabled as port is not hot plug enabled and no PCIe card is detected PCI Function 2 disabled as specified in the Fuse Straps PCI Function 3 disabled as port is not hot plug enabled and no PCIe card is detected PCI Function 4 disabled as port is not hot plug enabled and no PCIe card is detected PCI Function 5 disabled as port is not hot plug enabled and no PCIe card is detected PCI Function 6 disabled as specified in the Fuse Straps PCI Function 7 disabled as specified in the Fuse Straps PCI Function 8 disabled as specified in the Fuse Straps PCH PCI Root Port Clock Gating is 1 PchInitRootPorts() End ConfigureSata() Start ConfigureSata() End ConfigureDisplay() Start ConfigureDisplay() End ConfigureClockGating() Start ConfigureClockGating() End ConfigureIoApic() Start ConfigureIoApic() End ProgramSvidSid() Start ProgramSvidSid() End Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B InitializePchDevice() End PchInitEntryPoint() End Loading PEIM at 0x0007F6D9000 EntryPoint=0x0007F6D9260 SpsDxe.efi [SPS] DXE PHASE [SPS] Getting Info from PEI [SPS] Looking for SPS HOB info from PEI [SPS] HOB: flow 1, feature set 0x2106, pwr opt boot 0, cores2disable 0 [HECI-0] VID-DID: 8086-8C3A [SPS] Sending PCH temperature reporting configuration to ME [SPS] PCH Temperatur Reporting Interval: 0x00FA [SPS] PCH Temperatur Maximum Low Power Interval: 0x03E8 [HECI-0] Send msg: 80060020 [HECI-0] Got msg: 80040020 [SPS] SiliconEnabling Mode Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B DXE IPL Entry FSP HOB is located at 0x7F100000 Install PPI: 605EA650-C65C-42E1-BA80-91A52AB618C6 FSP is waiting for NOTIFY romstage_main_continue status: 0 hob_list_ptr: 7f100000 FSP Status: 0x0 CBMEM: IMD: root @ 7efff000 254 entries. IMD: root @ 7effec00 62 entries. CBFS @ 200200 size 5ffe00 CBFS: 'Master Header Locator' located CBFS at [200200:800000) CBFS: Locating 'fallback/ramstage' CBFS: Checking offset 0 CBFS: File @ offset 0 size 20 CBFS: Unmatched 'cbfs master header' at 0 CBFS: Checking offset 80 CBFS: File @ offset 80 size 44a4 CBFS: Unmatched 'fallback/romstage' at 80 CBFS: Checking offset 45c0 CBFS: File @ offset 45c0 size 19800 CBFS: Unmatched 'cpu_microcode_blob.bin' at 45c0 CBFS: Checking offset 1de40 CBFS: File @ offset 1de40 size f868 CBFS: Found @ offset 1de40 size f868 Decompressing stage fallback/ramstage @ 0x7eeb3fc0 (1350040 bytes) Loading module at 7eeb4000 with entry 7eeb4000. filesize: 0x1ff58 memsize: 0x149958 Processing 2601 relocs. Offset value of 0x7e0b4000 coreboot-4.10-ae317695e3f03d55fbba1805ff06e004383e67c8 Sat Dec 7 08:49:16 UTC 2019 ramstage starting (log level: 8)... TEST: Entering boot_state_schedule_static_entries TEST: Entering boot_state_sched_on_entry TEST: Entering boot_state_sched_callback TEST: Entering boot_state_sched_on_exit TEST: Entering boot_state_sched_callback TEST: Entering boot_state_sched_on_entry TEST: Entering boot_state_sched_callback TEST: Entering boot_state_sched_on_entry TEST: Entering boot_state_sched_callback TEST: Entering boot_state_sched_on_exit TEST: Entering boot_state_sched_callback TEST: Entering boot_state_sched_on_exit TEST: Entering boot_state_sched_callback TEST: Entering boot_state_sched_on_entry TEST: Entering boot_state_sched_callback TEST: Entering boot_state_sched_on_entry TEST: Entering boot_state_sched_callback TEST: Entering bs_walk_state_machine TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_pre_device TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_report_time BS: BS_PRE_DEVICE times (us): entry 6302 run 5916 exit 6301 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_dev_init_chips TEST: Entering dev_initialize_chips CBFS @ 200200 size 5ffe00 CBFS: 'Master Header Locator' located CBFS at [200200:800000) CBFS: Locating 'cpu_microcode_blob.bin' CBFS: Checking offset 0 CBFS: File @ offset 0 size 20 CBFS: Unmatched 'cbfs master header' at 0 CBFS: Checking offset 80 CBFS: File @ offset 80 size 44a4 CBFS: Unmatched 'fallback/romstage' at 80 CBFS: Checking offset 45c0 CBFS: File @ offset 45c0 size 19800 CBFS: Found @ offset 45c0 size 19800 microcode: sig=0x50663 pf=0x10 revision=0x700000c CPUID: 00050663 Cores: 12 Stepping: V2 Revision ID: 05 msr(17) = 0010000000000000 msr(ce) = 20080833f3811600 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_report_time BS: BS_DEV_INIT_CHIPS times (us): entry 6301 run 68478 exit 6303 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_dev_enumerate TEST: Entering dev_enumerate Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 APIC: 00: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:19.0: enabled 1 PCI: 00:1d.0: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.5: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:03.0: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:19.0: enabled 1 PCI: 00:1d.0: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.5: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:03.0: enabled 1 TEST: Entering scan_bus Root Device scanning... root_dev_scan_bus for Root Device enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 7) CPU_CLUSTER: 0 enabled enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 6) DOMAIN: 0000 enabled TEST: Entering scan_bus DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:00.0 [8086/6f00] ops fsp_header_ptr: ffeb0094 FSP Header Version: 1 FSP Revision: 3.3 PCI: 00:00.0 [8086/6f00] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) TEST: Entering set_pci_ops TEST: Entering device_id_match PCI: 00:01.0 [8086/0000] bus ops PCI: 00:01.0 [8086/6f02] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering get_pci_bridge_ops PCI: 00:02.0 subordinate bus PCI Express PCI: 00:02.0 [8086/6f04] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering get_pci_bridge_ops PCI: 00:02.2 subordinate bus PCI Express PCI: 00:02.2 [8086/6f06] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) TEST: Entering set_pci_ops TEST: Entering device_id_match PCI: 00:03.0 [8086/0000] bus ops PCI: 00:03.0 [8086/6f08] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:05.0 [8086/6f28] ops PCI: 00:05.0 [8086/6f28] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:05.1 [8086/6f29] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:05.2 [8086/6f2a] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:05.4 [8086/6f2c] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:05.6 [8086/6f39] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:06.0 [8086/6f10] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:06.1 [8086/6f11] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:06.2 [8086/6f12] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:06.3 [8086/6f13] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:06.4 [8086/6f14] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:06.5 [8086/6f15] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:06.6 [8086/6f16] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:06.7 [8086/6f17] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:07.0 [8086/6f18] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:07.1 [8086/6f19] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:07.2 [8086/6f1a] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:07.3 [8086/6f1b] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:07.4 [8086/6f1c] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:14.0 [8086/8c31] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:16.0 [8086/8c3a] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:16.1 [8086/8c3b] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:16.2 [8086/8c3c] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:16.3 [8086/8c3d] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) PCI: Static device PCI: 00:19.0 not found, disabling it. TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:1d.0 [8086/8c26] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:1f.0 [8086/8c54] bus ops PCI: 00:1f.0 [8086/8c54] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:1f.2 [8086/8c02] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:1f.3 [8086/0000] bus ops PCI: 00:1f.3 [8086/8c22] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) PCI: Static device PCI: 00:1f.5 not found, disabling it. TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:1f.6 [8086/8c24] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev PCI: Leftover static devices: PCI: 00:19.0 PCI: 00:1f.5 PCI: Check your devicetree.cb. TEST: Entering scan_bus PCI: 00:01.0 scanning... TEST: Entering pci_scan_bridge TEST: Entering do_pci_scan_bridge do_pci_scan_bridge for PCI: 00:01.0 TEST: Entering pci_bridge_route PCI: pci_scan_bus for bus 01 TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_bridge_route scan_bus: scanning of bus PCI: 00:01.0 took 217407 usecs TEST: Entering scan_bus PCI: 00:02.0 scanning... TEST: Entering do_pci_scan_bridge do_pci_scan_bridge for PCI: 00:02.0 TEST: Entering pci_bridge_route PCI: pci_scan_bus for bus 02 TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 02:00.0 [8086/6f50] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 02:00.1 [8086/6f51] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 02:00.2 [8086/6f52] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 02:00.3 [8086/6f53] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev PCIE CLK PM is not supported by endpoint ASPM: Enabled None PCIE CLK PM is not supported by endpoint ASPM: Enabled None PCIE CLK PM is not supported by endpoint ASPM: Enabled None PCIE CLK PM is not supported by endpoint ASPM: Enabled None TEST: Entering pci_bridge_route Failed to enable LTR for dev = PCI: 02:00.0 Failed to enable LTR for dev = PCI: 02:00.1 Failed to enable LTR for dev = PCI: 02:00.2 Failed to enable LTR for dev = PCI: 02:00.3 scan_bus: scanning of bus PCI: 00:02.0 took 442865 usecs TEST: Entering scan_bus PCI: 00:02.2 scanning... TEST: Entering do_pci_scan_bridge do_pci_scan_bridge for PCI: 00:02.2 TEST: Entering pci_bridge_route PCI: pci_scan_bus for bus 03 TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 03:00.0 [8086/15ac] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 03:00.1 [8086/15ac] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled L1 Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled L1 TEST: Entering pci_bridge_route scan_bus: scanning of bus PCI: 00:02.2 took 348062 usecs TEST: Entering scan_bus PCI: 00:03.0 scanning... TEST: Entering pci_scan_bridge TEST: Entering do_pci_scan_bridge do_pci_scan_bridge for PCI: 00:03.0 TEST: Entering pci_bridge_route PCI: pci_scan_bus for bus 04 TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops PCI: 04:00.0 [10de/128b] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops PCI: 04:00.1 [10de/0e0f] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_bridge_route scan_bus: scanning of bus PCI: 00:03.0 took 282678 usecs TEST: Entering scan_bus PCI: 00:1f.0 scanning... scan_lpc_bus for PCI: 00:1f.0 scan_lpc_bus for PCI: 00:1f.0 done scan_bus: scanning of bus PCI: 00:1f.0 took 9020 usecs TEST: Entering scan_bus PCI: 00:1f.3 scanning... scan_generic_bus for PCI: 00:1f.3 scan_generic_bus for PCI: 00:1f.3 done scan_bus: scanning of bus PCI: 00:1f.3 took 9796 usecs scan_bus: scanning of bus DOMAIN: 0000 took 3043293 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 3078198 usecs done TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks FspNotify(EnumInitPhaseAfterPciEnumeration) FSP Got Notification. Notification Value : 0x00000020 FSP Post PCI Enumeration ... Install PPI: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793 Notify: PPI Guid: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793, Peim notify entry point: 7F759A3C IIO PCI callback event after PCI bus assignment.. Found the CBDMA on bus:2 Found the GbE on bus:3 Hide devices in Bus:255 IIO PCI callback event after PCI resource allocation.. BDF=2,0,0 - CB_BAR=0x0 CB BAR not initialized! CBDMA[0].version=0x33 Enable IIO[0] IOxAPIC Notify: PPI Guid: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793, Peim notify entry point: 7F71C2AA FSP Notification Handler Returns : 0x00000000 Returned from FspNotify(EnumInitPhaseAfterPciEnumeration) TEST: Entering bs_sample_time TEST: Entering bs_report_time BS: BS_DEV_ENUMERATE times (us): entry 6302 run 3174234 exit 78802 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_dev_resources TEST: Entering dev_configure TEST: Entering set_vga_bridge_bits found VGA at PCI: 04:00.0 Setting up VGA for PCI: 04:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:03.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... TEST: Entering read_resources Root Device read_resources bus 0 link: 0 TEST: Entering read_resources CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done TEST: Entering pci_domain_read_resources TEST: Entering read_resources DOMAIN: 0000 read_resources bus 0 link: 0 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 fsp_mem_base: 0x7f000000 fsp_mem_len: 0x00800000 tseg_base: 0x7f800000 tseg_len: 0x00800000 highmem_size: 0x00000000 80000000 tolm: 0x80000000 Top of system low memory: 0x80000000 FSP memory location: 0x7f000000 (size: 8M) tseg: 0x7f800000 (size: 0x00800000) Available memory above 4GB: 2048M Adding PCIe config bar base=0x80000000 size=0x10000000 TEST: Entering pci_bus_read_resources TEST: Entering pci_bridge_read_bases TEST: Entering pci_moving_config8 TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config8 TEST: Entering pci_moving_config16 TEST: Entering pci_record_bridge_resource TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config32 TEST: Entering pci_record_bridge_resource TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config16 TEST: Entering pci_record_bridge_resource TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering read_resources PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done TEST: Entering pci_bus_read_resources TEST: Entering pci_bridge_read_bases TEST: Entering pci_moving_config8 TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config8 TEST: Entering pci_moving_config16 TEST: Entering pci_record_bridge_resource TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config32 TEST: Entering pci_record_bridge_resource TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config16 TEST: Entering pci_record_bridge_resource TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering read_resources PCI: 00:02.0 read_resources bus 2 link: 0 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:02.0 read_resources bus 2 link: 0 done TEST: Entering pci_bus_read_resources TEST: Entering pci_bridge_read_bases TEST: Entering pci_moving_config8 TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config8 TEST: Entering pci_moving_config16 TEST: Entering pci_record_bridge_resource TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config32 TEST: Entering pci_record_bridge_resource TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config16 TEST: Entering pci_record_bridge_resource TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering read_resources PCI: 00:02.2 read_resources bus 3 link: 0 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:02.2 read_resources bus 3 link: 0 done TEST: Entering pci_bus_read_resources TEST: Entering pci_bridge_read_bases TEST: Entering pci_moving_config8 TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config8 TEST: Entering pci_moving_config16 TEST: Entering pci_record_bridge_resource TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config32 TEST: Entering pci_record_bridge_resource TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config16 TEST: Entering pci_record_bridge_resource TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering read_resources PCI: 00:03.0 read_resources bus 4 link: 0 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:03.0 read_resources bus 4 link: 0 done TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:05.6 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:05.6 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:05.6 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:05.6 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:05.6 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:05.6 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:05.6 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.0 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.0 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.0 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.0 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.0 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.0 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:06.0 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.1 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.1 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.1 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.1 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.1 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.1 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:06.1 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.2 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.2 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.2 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.2 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.2 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.2 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:06.2 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.3 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.3 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.3 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.3 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.3 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.3 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:06.3 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.4 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.4 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.4 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.4 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.4 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.4 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:06.4 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.5 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.5 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.5 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.5 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.5 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.5 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:06.5 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.6 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.6 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.6 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.6 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.6 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.6 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:06.6 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.7 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.7 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.7 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.7 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.7 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.7 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:06.7 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.0 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.0 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.0 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.0 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.0 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.0 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:07.0 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.1 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.1 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.1 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.1 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.1 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.1 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:07.1 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.2 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.2 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.2 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.2 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.2 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.2 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:07.2 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.3 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.3 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.3 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.3 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.3 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.3 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:07.3 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.4 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.4 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.4 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.4 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.4 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.4 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:07.4 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base 100000 size 7ef00000 align 0 gran 0 limit 0 flags e0004200 index 1 PCI: 00:00.0 resource base 7f800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 2 PCI: 00:00.0 resource base 7f000000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base 100000000 size 80000000 align 0 gran 0 limit 0 flags e0004200 index 4 PCI: 00:00.0 resource base 80000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base a0000 size 60000 align 0 gran 0 limit 0 flags f0000200 index 6 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:02.0 child on link 0 PCI: 02:00.0 PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 PCI: 02:00.1 PCI: 02:00.1 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 PCI: 02:00.2 PCI: 02:00.2 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 PCI: 02:00.3 PCI: 02:00.3 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.2 child on link 0 PCI: 03:00.0 PCI: 00:02.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 1201 index 10 PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20 PCI: 03:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30 PCI: 03:00.1 PCI: 03:00.1 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 1201 index 10 PCI: 03:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20 PCI: 03:00.1 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30 PCI: 00:03.0 child on link 0 PCI: 04:00.0 PCI: 00:03.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 04:00.0 PCI: 04:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10 PCI: 04:00.0 resource base 0 size 8000000 align 27 gran 27 limit ffffffffffffffff flags 1201 index 14 PCI: 04:00.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffffffffffff flags 1201 index 1c PCI: 04:00.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 24 PCI: 04:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30 PCI: 04:00.1 PCI: 04:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10 PCI: 00:05.0 PCI: 00:05.0 resource base fbffc000 size 2000 align 0 gran 0 limit 0 flags f0000200 index 180 PCI: 00:05.1 PCI: 00:05.2 PCI: 00:05.4 PCI: 00:05.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:05.6 PCI: 00:06.0 PCI: 00:06.1 PCI: 00:06.2 PCI: 00:06.3 PCI: 00:06.4 PCI: 00:06.5 PCI: 00:06.6 PCI: 00:06.7 PCI: 00:07.0 PCI: 00:07.1 PCI: 00:07.2 PCI: 00:07.3 PCI: 00:07.4 PCI: 00:14.0 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 PCI: 00:16.0 PCI: 00:16.0 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10 PCI: 00:16.1 PCI: 00:16.1 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10 PCI: 00:16.2 PCI: 00:16.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:16.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:16.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:16.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:16.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:16.3 PCI: 00:16.3 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:16.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:1d.0 PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 PCI: 00:1f.0 PCI: 00:1f.0 resource base feb00000 size 10000 align 0 gran 0 limit 0 flags f0000200 index feb0 PCI: 00:1f.0 resource base feb80000 size 80000 align 0 gran 0 limit 0 flags f0000200 index feb8 PCI: 00:1f.0 resource base fec00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fec0 PCI: 00:1f.0 resource base fec01000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fec1 PCI: 00:1f.0 resource base fed00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fed0 PCI: 00:1f.0 resource base fef00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fef0 PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index ff00 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:1f.0 resource base 500 size 80 align 0 gran 0 limit 0 flags c0000100 index 48 PCI: 00:1f.2 PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24 PCI: 00:1f.3 PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10 PCI: 00:1f.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:1f.6 PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff TEST: Entering largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff TEST: Entering largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff TEST: Entering largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:03.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 04:00.0 24 * [0x0 - 0x7f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:03.0 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:03.0 1c * [0x0 - 0xfff] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 20 * [0x1000 - 0x101f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:1f.3 20 * [0x1020 - 0x103f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:16.2 20 * [0x1040 - 0x104f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:16.2 10 * [0x1050 - 0x1057] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:16.2 18 * [0x1058 - 0x105f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:16.3 10 * [0x1060 - 0x1067] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 10 * [0x1068 - 0x106f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 18 * [0x1070 - 0x1077] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:16.2 14 * [0x1078 - 0x107b] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:16.2 1c * [0x107c - 0x107f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 14 * [0x1080 - 0x1083] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 1c * [0x1084 - 0x1087] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str DOMAIN: 0000 io: base: 1088 size: 1088 align: 12 gran: 0 limit: ffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff TEST: Entering largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff TEST: Entering largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff TEST: Entering largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 02:00.0 10 * [0x0 - 0x1fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 02:00.1 10 * [0x2000 - 0x3fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 02:00.2 10 * [0x4000 - 0x5fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 02:00.3 10 * [0x6000 - 0x7fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:02.0 mem: base: 8000 size: 100000 align: 20 gran: 20 limit: ffffffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 03:00.0 10 * [0x0 - 0x1fffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 03:00.1 10 * [0x200000 - 0x3fffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 03:00.0 20 * [0x400000 - 0x403fff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 03:00.1 20 * [0x404000 - 0x407fff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:02.2 prefmem: base: 408000 size: 500000 align: 21 gran: 20 limit: ffffffffffffffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:02.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 03:00.0 30 * [0x0 - 0x7ffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 03:00.1 30 * [0x80000 - 0xfffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:02.2 mem: base: 100000 size: 100000 align: 20 gran: 20 limit: ffffffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:03.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 04:00.0 14 * [0x0 - 0x7ffffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 04:00.0 1c * [0x8000000 - 0x9ffffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:03.0 prefmem: base: a000000 size: a000000 align: 27 gran: 20 limit: ffffffffffffffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:03.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 04:00.0 10 * [0x0 - 0xffffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 04:00.0 30 * [0x1000000 - 0x107ffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 04:00.1 10 * [0x1080000 - 0x1083fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:03.0 mem: base: 1084000 size: 1100000 align: 24 gran: 20 limit: ffffffff done TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:03.0 24 * [0x0 - 0x9ffffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:03.0 20 * [0xa000000 - 0xb0fffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:02.2 24 * [0xb200000 - 0xb6fffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:02.0 20 * [0xb700000 - 0xb7fffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:02.2 20 * [0xb800000 - 0xb8fffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:14.0 10 * [0xb900000 - 0xb90ffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:05.4 10 * [0xb910000 - 0xb910fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:16.3 14 * [0xb911000 - 0xb911fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:1f.6 10 * [0xb912000 - 0xb912fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 24 * [0xb913000 - 0xb9137ff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:1d.0 10 * [0xb914000 - 0xb9143ff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:1f.3 10 * [0xb915000 - 0xb9150ff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:16.0 10 * [0xb916000 - 0xb91600f] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:16.1 10 * [0xb917000 - 0xb91700f] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str DOMAIN: 0000 mem: base: b917010 size: b917010 align: 27 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_is avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource2str constrain_resources: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed) TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource2str constrain_resources: PCI: 00:00.0 01 base 00100000 limit 7effffff mem (fixed) TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource2str constrain_resources: PCI: 00:00.0 02 base 7f800000 limit 7fffffff mem (fixed) TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource2str constrain_resources: PCI: 00:00.0 05 base 80000000 limit 8fffffff mem (fixed) TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource2str constrain_resources: PCI: 00:05.0 180 base fbffc000 limit fbffdfff mem (fixed) TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_is TEST: Entering resource2str constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_is TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_is TEST: Entering resource_limit TEST: Entering resource_is Setting resources... TEST: Entering allocate_resources TEST: Entering resource2str DOMAIN: 0000 io: base:1000 size:1088 align:12 gran:0 limit:ffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:03.0 1c * [0x1000 - 0x1fff] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 20 * [0x2000 - 0x201f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:1f.3 20 * [0x2020 - 0x203f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:16.2 20 * [0x2040 - 0x204f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:16.2 10 * [0x2050 - 0x2057] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:16.2 18 * [0x2058 - 0x205f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:16.3 10 * [0x2060 - 0x2067] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 10 * [0x2068 - 0x206f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 18 * [0x2070 - 0x2077] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:16.2 14 * [0x2078 - 0x207b] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:16.2 1c * [0x207c - 0x207f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 14 * [0x2080 - 0x2083] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 1c * [0x2084 - 0x2087] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering resource2str DOMAIN: 0000 io: next_base: 2088 size: 1088 align: 12 gran: 0 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:01.0 io: base:ffff size:0 align:12 gran:12 limit:ffff TEST: Entering largest_resource TEST: Entering resource2str PCI: 00:01.0 io: next_base: ffff size: 0 align: 12 gran: 12 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:02.0 io: base:ffff size:0 align:12 gran:12 limit:ffff TEST: Entering largest_resource TEST: Entering resource2str PCI: 00:02.0 io: next_base: ffff size: 0 align: 12 gran: 12 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:02.2 io: base:ffff size:0 align:12 gran:12 limit:ffff TEST: Entering largest_resource TEST: Entering resource2str PCI: 00:02.2 io: next_base: ffff size: 0 align: 12 gran: 12 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:03.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 04:00.0 24 * [0x1000 - 0x107f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering resource2str PCI: 00:03.0 io: next_base: 1080 size: 1000 align: 12 gran: 12 done TEST: Entering allocate_resources TEST: Entering resource2str DOMAIN: 0000 mem: base:f0000000 size:b917010 align:27 gran:0 limit:fbffbfff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:03.0 24 * [0xf0000000 - 0xf9ffffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:03.0 20 * [0xfa000000 - 0xfb0fffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:02.2 24 * [0xfb200000 - 0xfb6fffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:02.0 20 * [0xfb700000 - 0xfb7fffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:02.2 20 * [0xfb800000 - 0xfb8fffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:14.0 10 * [0xfb900000 - 0xfb90ffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:05.4 10 * [0xfb910000 - 0xfb910fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:16.3 14 * [0xfb911000 - 0xfb911fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:1f.6 10 * [0xfb912000 - 0xfb912fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 24 * [0xfb913000 - 0xfb9137ff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:1d.0 10 * [0xfb914000 - 0xfb9143ff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:1f.3 10 * [0xfb915000 - 0xfb9150ff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:16.0 10 * [0xfb916000 - 0xfb91600f] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:16.1 10 * [0xfb917000 - 0xfb91700f] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering resource2str DOMAIN: 0000 mem: next_base: fb917010 size: b917010 align: 27 gran: 0 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:01.0 prefmem: base:fbffbfff size:0 align:20 gran:20 limit:fbffbfff TEST: Entering largest_resource TEST: Entering resource2str PCI: 00:01.0 prefmem: next_base: fbffbfff size: 0 align: 20 gran: 20 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:01.0 mem: base:fbffbfff size:0 align:20 gran:20 limit:fbffbfff TEST: Entering largest_resource TEST: Entering resource2str PCI: 00:01.0 mem: next_base: fbffbfff size: 0 align: 20 gran: 20 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:02.0 prefmem: base:fbffbfff size:0 align:20 gran:20 limit:fbffbfff TEST: Entering largest_resource TEST: Entering resource2str PCI: 00:02.0 prefmem: next_base: fbffbfff size: 0 align: 20 gran: 20 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:02.0 mem: base:fb700000 size:100000 align:20 gran:20 limit:fb7fffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 02:00.0 10 * [0xfb700000 - 0xfb701fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 02:00.1 10 * [0xfb702000 - 0xfb703fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 02:00.2 10 * [0xfb704000 - 0xfb705fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 02:00.3 10 * [0xfb706000 - 0xfb707fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering resource2str PCI: 00:02.0 mem: next_base: fb708000 size: 100000 align: 20 gran: 20 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:02.2 prefmem: base:fb200000 size:500000 align:21 gran:20 limit:fb6fffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 03:00.0 10 * [0xfb200000 - 0xfb3fffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 03:00.1 10 * [0xfb400000 - 0xfb5fffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 03:00.0 20 * [0xfb600000 - 0xfb603fff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 03:00.1 20 * [0xfb604000 - 0xfb607fff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering resource2str PCI: 00:02.2 prefmem: next_base: fb608000 size: 500000 align: 21 gran: 20 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:02.2 mem: base:fb800000 size:100000 align:20 gran:20 limit:fb8fffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 03:00.0 30 * [0xfb800000 - 0xfb87ffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 03:00.1 30 * [0xfb880000 - 0xfb8fffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering resource2str PCI: 00:02.2 mem: next_base: fb900000 size: 100000 align: 20 gran: 20 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:03.0 prefmem: base:f0000000 size:a000000 align:27 gran:20 limit:f9ffffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 04:00.0 14 * [0xf0000000 - 0xf7ffffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 04:00.0 1c * [0xf8000000 - 0xf9ffffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering resource2str PCI: 00:03.0 prefmem: next_base: fa000000 size: a000000 align: 27 gran: 20 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:03.0 mem: base:fa000000 size:1100000 align:24 gran:20 limit:fb0fffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 04:00.0 10 * [0xfa000000 - 0xfaffffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 04:00.0 30 * [0xfb000000 - 0xfb07ffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 04:00.1 10 * [0xfb080000 - 0xfb083fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering resource2str PCI: 00:03.0 mem: next_base: fb084000 size: 1100000 align: 24 gran: 20 done TEST: Entering assign_resources Root Device assign_resources, bus 0 link: 0 TEST: Entering assign_resources DOMAIN: 0000 assign_resources, bus 0 link: 0 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io TEST: Entering pci_set_resource PCI: 00:01.0 24 <- [0x00fbffbfff - 0x00fbffbffe] size 0x00000000 gran 0x14 bus 01 prefmem TEST: Entering pci_set_resource PCI: 00:01.0 20 <- [0x00fbffbfff - 0x00fbffbffe] size 0x00000000 gran 0x14 bus 01 mem TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:02.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io TEST: Entering pci_set_resource PCI: 00:02.0 24 <- [0x00fbffbfff - 0x00fbffbffe] size 0x00000000 gran 0x14 bus 02 prefmem TEST: Entering pci_set_resource PCI: 00:02.0 20 <- [0x00fb700000 - 0x00fb7fffff] size 0x00100000 gran 0x14 bus 02 mem TEST: Entering assign_resources PCI: 00:02.0 assign_resources, bus 2 link: 0 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 02:00.0 10 <- [0x00fb700000 - 0x00fb701fff] size 0x00002000 gran 0x0d mem64 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 02:00.1 10 <- [0x00fb702000 - 0x00fb703fff] size 0x00002000 gran 0x0d mem64 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 02:00.2 10 <- [0x00fb704000 - 0x00fb705fff] size 0x00002000 gran 0x0d mem64 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 02:00.3 10 <- [0x00fb706000 - 0x00fb707fff] size 0x00002000 gran 0x0d mem64 PCI: 00:02.0 assign_resources, bus 2 link: 0 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:02.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io TEST: Entering pci_set_resource PCI: 00:02.2 24 <- [0x00fb200000 - 0x00fb6fffff] size 0x00500000 gran 0x14 bus 03 prefmem TEST: Entering pci_set_resource PCI: 00:02.2 20 <- [0x00fb800000 - 0x00fb8fffff] size 0x00100000 gran 0x14 bus 03 mem TEST: Entering assign_resources PCI: 00:02.2 assign_resources, bus 3 link: 0 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 03:00.0 10 <- [0x00fb200000 - 0x00fb3fffff] size 0x00200000 gran 0x15 prefmem64 TEST: Entering pci_set_resource PCI: 03:00.0 20 <- [0x00fb600000 - 0x00fb603fff] size 0x00004000 gran 0x0e prefmem64 TEST: Entering pci_set_resource PCI: 03:00.0 30 <- [0x00fb800000 - 0x00fb87ffff] size 0x00080000 gran 0x13 romem TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 03:00.1 10 <- [0x00fb400000 - 0x00fb5fffff] size 0x00200000 gran 0x15 prefmem64 TEST: Entering pci_set_resource PCI: 03:00.1 20 <- [0x00fb604000 - 0x00fb607fff] size 0x00004000 gran 0x0e prefmem64 TEST: Entering pci_set_resource PCI: 03:00.1 30 <- [0x00fb880000 - 0x00fb8fffff] size 0x00080000 gran 0x13 romem PCI: 00:02.2 assign_resources, bus 3 link: 0 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:03.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 04 io TEST: Entering pci_set_resource PCI: 00:03.0 24 <- [0x00f0000000 - 0x00f9ffffff] size 0x0a000000 gran 0x14 bus 04 prefmem TEST: Entering pci_set_resource PCI: 00:03.0 20 <- [0x00fa000000 - 0x00fb0fffff] size 0x01100000 gran 0x14 bus 04 mem TEST: Entering assign_resources PCI: 00:03.0 assign_resources, bus 4 link: 0 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 04:00.0 10 <- [0x00fa000000 - 0x00faffffff] size 0x01000000 gran 0x18 mem TEST: Entering pci_set_resource PCI: 04:00.0 14 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x1b prefmem64 TEST: Entering pci_set_resource PCI: 04:00.0 1c <- [0x00f8000000 - 0x00f9ffffff] size 0x02000000 gran 0x19 prefmem64 TEST: Entering pci_set_resource PCI: 04:00.0 24 <- [0x0000001000 - 0x000000107f] size 0x00000080 gran 0x07 io TEST: Entering pci_set_resource PCI: 04:00.0 30 <- [0x00fb000000 - 0x00fb07ffff] size 0x00080000 gran 0x13 romem TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 04:00.1 10 <- [0x00fb080000 - 0x00fb083fff] size 0x00004000 gran 0x0e mem PCI: 00:03.0 assign_resources, bus 4 link: 0 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:05.4 10 <- [0x00fb910000 - 0x00fb910fff] size 0x00001000 gran 0x0c mem TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:14.0 10 <- [0x00fb900000 - 0x00fb90ffff] size 0x00010000 gran 0x10 mem64 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:16.0 10 <- [0x00fb916000 - 0x00fb91600f] size 0x00000010 gran 0x04 mem64 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:16.1 10 <- [0x00fb917000 - 0x00fb91700f] size 0x00000010 gran 0x04 mem64 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:16.2 10 <- [0x0000002050 - 0x0000002057] size 0x00000008 gran 0x03 io TEST: Entering pci_set_resource PCI: 00:16.2 14 <- [0x0000002078 - 0x000000207b] size 0x00000004 gran 0x02 io TEST: Entering pci_set_resource PCI: 00:16.2 18 <- [0x0000002058 - 0x000000205f] size 0x00000008 gran 0x03 io TEST: Entering pci_set_resource PCI: 00:16.2 1c <- [0x000000207c - 0x000000207f] size 0x00000004 gran 0x02 io TEST: Entering pci_set_resource PCI: 00:16.2 20 <- [0x0000002040 - 0x000000204f] size 0x00000010 gran 0x04 io TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:16.3 10 <- [0x0000002060 - 0x0000002067] size 0x00000008 gran 0x03 io TEST: Entering pci_set_resource PCI: 00:16.3 14 <- [0x00fb911000 - 0x00fb911fff] size 0x00001000 gran 0x0c mem TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:1d.0 10 <- [0x00fb914000 - 0x00fb9143ff] size 0x00000400 gran 0x0a mem TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:1f.2 10 <- [0x0000002068 - 0x000000206f] size 0x00000008 gran 0x03 io TEST: Entering pci_set_resource PCI: 00:1f.2 14 <- [0x0000002080 - 0x0000002083] size 0x00000004 gran 0x02 io TEST: Entering pci_set_resource PCI: 00:1f.2 18 <- [0x0000002070 - 0x0000002077] size 0x00000008 gran 0x03 io TEST: Entering pci_set_resource PCI: 00:1f.2 1c <- [0x0000002084 - 0x0000002087] size 0x00000004 gran 0x02 io TEST: Entering pci_set_resource PCI: 00:1f.2 20 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io TEST: Entering pci_set_resource PCI: 00:1f.2 24 <- [0x00fb913000 - 0x00fb9137ff] size 0x00000800 gran 0x0b mem TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:1f.3 10 <- [0x00fb915000 - 0x00fb9150ff] size 0x00000100 gran 0x08 mem64 TEST: Entering pci_set_resource PCI: 00:1f.3 20 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:1f.6 10 <- [0x00fb912000 - 0x00fb912fff] size 0x00001000 gran 0x0c mem64 DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1000 size 1088 align 12 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base f0000000 size b917010 align 27 gran 0 limit fbffbfff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base 100000 size 7ef00000 align 0 gran 0 limit 0 flags e0004200 index 1 PCI: 00:00.0 resource base 7f800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 2 PCI: 00:00.0 resource base 7f000000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base 100000000 size 80000000 align 0 gran 0 limit 0 flags e0004200 index 4 PCI: 00:00.0 resource base 80000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base a0000 size 60000 align 0 gran 0 limit 0 flags f0000200 index 6 PCI: 00:01.0 PCI: 00:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:01.0 resource base fbffbfff size 0 align 20 gran 20 limit fbffbfff flags 60081202 index 24 PCI: 00:01.0 resource base fbffbfff size 0 align 20 gran 20 limit fbffbfff flags 60080202 index 20 PCI: 00:02.0 child on link 0 PCI: 02:00.0 PCI: 00:02.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.0 resource base fbffbfff size 0 align 20 gran 20 limit fbffbfff flags 60081202 index 24 PCI: 00:02.0 resource base fb700000 size 100000 align 20 gran 20 limit fb7fffff flags 60080202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base fb700000 size 2000 align 13 gran 13 limit fb701fff flags 60000201 index 10 PCI: 02:00.1 PCI: 02:00.1 resource base fb702000 size 2000 align 13 gran 13 limit fb703fff flags 60000201 index 10 PCI: 02:00.2 PCI: 02:00.2 resource base fb704000 size 2000 align 13 gran 13 limit fb705fff flags 60000201 index 10 PCI: 02:00.3 PCI: 02:00.3 resource base fb706000 size 2000 align 13 gran 13 limit fb707fff flags 60000201 index 10 PCI: 00:02.2 child on link 0 PCI: 03:00.0 PCI: 00:02.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.2 resource base fb200000 size 500000 align 21 gran 20 limit fb6fffff flags 60081202 index 24 PCI: 00:02.2 resource base fb800000 size 100000 align 20 gran 20 limit fb8fffff flags 60080202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base fb200000 size 200000 align 21 gran 21 limit fb3fffff flags 60001201 index 10 PCI: 03:00.0 resource base fb600000 size 4000 align 14 gran 14 limit fb603fff flags 60001201 index 20 PCI: 03:00.0 resource base fb800000 size 80000 align 19 gran 19 limit fb87ffff flags 60002200 index 30 PCI: 03:00.1 PCI: 03:00.1 resource base fb400000 size 200000 align 21 gran 21 limit fb5fffff flags 60001201 index 10 PCI: 03:00.1 resource base fb604000 size 4000 align 14 gran 14 limit fb607fff flags 60001201 index 20 PCI: 03:00.1 resource base fb880000 size 80000 align 19 gran 19 limit fb8fffff flags 60002200 index 30 PCI: 00:03.0 child on link 0 PCI: 04:00.0 PCI: 00:03.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c PCI: 00:03.0 resource base f0000000 size a000000 align 27 gran 20 limit f9ffffff flags 60081202 index 24 PCI: 00:03.0 resource base fa000000 size 1100000 align 24 gran 20 limit fb0fffff flags 60080202 index 20 PCI: 04:00.0 PCI: 04:00.0 resource base fa000000 size 1000000 align 24 gran 24 limit faffffff flags 60000200 index 10 PCI: 04:00.0 resource base f0000000 size 8000000 align 27 gran 27 limit f7ffffff flags 60001201 index 14 PCI: 04:00.0 resource base f8000000 size 2000000 align 25 gran 25 limit f9ffffff flags 60001201 index 1c PCI: 04:00.0 resource base 1000 size 80 align 7 gran 7 limit 107f flags 60000100 index 24 PCI: 04:00.0 resource base fb000000 size 80000 align 19 gran 19 limit fb07ffff flags 60002200 index 30 PCI: 04:00.1 PCI: 04:00.1 resource base fb080000 size 4000 align 14 gran 14 limit fb083fff flags 60000200 index 10 PCI: 00:05.0 PCI: 00:05.0 resource base fbffc000 size 2000 align 0 gran 0 limit 0 flags f0000200 index 180 PCI: 00:05.1 PCI: 00:05.2 PCI: 00:05.4 PCI: 00:05.4 resource base fb910000 size 1000 align 12 gran 12 limit fb910fff flags 60000200 index 10 PCI: 00:05.6 PCI: 00:06.0 PCI: 00:06.1 PCI: 00:06.2 PCI: 00:06.3 PCI: 00:06.4 PCI: 00:06.5 PCI: 00:06.6 PCI: 00:06.7 PCI: 00:07.0 PCI: 00:07.1 PCI: 00:07.2 PCI: 00:07.3 PCI: 00:07.4 PCI: 00:14.0 PCI: 00:14.0 resource base fb900000 size 10000 align 16 gran 16 limit fb90ffff flags 60000201 index 10 PCI: 00:16.0 PCI: 00:16.0 resource base fb916000 size 10 align 12 gran 4 limit fb91600f flags 60000201 index 10 PCI: 00:16.1 PCI: 00:16.1 resource base fb917000 size 10 align 12 gran 4 limit fb91700f flags 60000201 index 10 PCI: 00:16.2 PCI: 00:16.2 resource base 2050 size 8 align 3 gran 3 limit 2057 flags 60000100 index 10 PCI: 00:16.2 resource base 2078 size 4 align 2 gran 2 limit 207b flags 60000100 index 14 PCI: 00:16.2 resource base 2058 size 8 align 3 gran 3 limit 205f flags 60000100 index 18 PCI: 00:16.2 resource base 207c size 4 align 2 gran 2 limit 207f flags 60000100 index 1c PCI: 00:16.2 resource base 2040 size 10 align 4 gran 4 limit 204f flags 60000100 index 20 PCI: 00:16.3 PCI: 00:16.3 resource base 2060 size 8 align 3 gran 3 limit 2067 flags 60000100 index 10 PCI: 00:16.3 resource base fb911000 size 1000 align 12 gran 12 limit fb911fff flags 60000200 index 14 PCI: 00:1d.0 PCI: 00:1d.0 resource base fb914000 size 400 align 12 gran 10 limit fb9143ff flags 60000200 index 10 PCI: 00:1f.0 PCI: 00:1f.0 resource base feb00000 size 10000 align 0 gran 0 limit 0 flags f0000200 index feb0 PCI: 00:1f.0 resource base feb80000 size 80000 align 0 gran 0 limit 0 flags f0000200 index feb8 PCI: 00:1f.0 resource base fec00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fec0 PCI: 00:1f.0 resource base fec01000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fec1 PCI: 00:1f.0 resource base fed00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fed0 PCI: 00:1f.0 resource base fef00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fef0 PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index ff00 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:1f.0 resource base 500 size 80 align 0 gran 0 limit 0 flags c0000100 index 48 PCI: 00:1f.2 PCI: 00:1f.2 resource base 2068 size 8 align 3 gran 3 limit 206f flags 60000100 index 10 PCI: 00:1f.2 resource base 2080 size 4 align 2 gran 2 limit 2083 flags 60000100 index 14 PCI: 00:1f.2 resource base 2070 size 8 align 3 gran 3 limit 2077 flags 60000100 index 18 PCI: 00:1f.2 resource base 2084 size 4 align 2 gran 2 limit 2087 flags 60000100 index 1c PCI: 00:1f.2 resource base 2000 size 20 align 5 gran 5 limit 201f flags 60000100 index 20 PCI: 00:1f.2 resource base fb913000 size 800 align 12 gran 11 limit fb9137ff flags 60000200 index 24 PCI: 00:1f.3 PCI: 00:1f.3 resource base fb915000 size 100 align 12 gran 8 limit fb9150ff flags 60000201 index 10 PCI: 00:1f.3 resource base 2020 size 20 align 5 gran 5 limit 203f flags 60000100 index 20 PCI: 00:1f.6 PCI: 00:1f.6 resource base fb912000 size 1000 align 12 gran 12 limit fb912fff flags 60000201 index 10 Done allocating resources. TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_report_time BS: BS_DEV_RESOURCES times (us): entry 6302 run 14338747 exit 6303 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_dev_enable TEST: Entering dev_enable Enabling resources... TEST: Entering enable_resources TEST: Entering enable_resources TEST: Entering enable_resources TEST: Entering pci_dev_enable_resources PCI: 00:00.0 subsystem <- 8086/6f00 TEST: Entering pci_dev_set_subsystem PCI: 00:00.0 cmd <- 400 TEST: Entering pci_bus_enable_resources PCI: 00:01.0 bridge ctrl <- 0003 TEST: Entering pci_dev_enable_resources PCI: 00:01.0 cmd <- 00 TEST: Entering pci_bus_enable_resources PCI: 00:02.0 bridge ctrl <- 0003 TEST: Entering pci_dev_enable_resources PCI: 00:02.0 cmd <- 06 TEST: Entering pci_bus_enable_resources PCI: 00:02.2 bridge ctrl <- 0003 TEST: Entering pci_dev_enable_resources PCI: 00:02.2 cmd <- 06 TEST: Entering pci_bus_enable_resources PCI: 00:03.0 bridge ctrl <- 000b TEST: Entering pci_dev_enable_resources PCI: 00:03.0 cmd <- 07 TEST: Entering pci_dev_enable_resources PCI: 00:05.1 cmd <- 04 TEST: Entering pci_dev_enable_resources PCI: 00:05.2 cmd <- 04 TEST: Entering pci_dev_enable_resources PCI: 00:05.4 cmd <- 06 TEST: Entering pci_dev_enable_resources PCI: 00:05.6 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:06.0 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:06.1 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:06.2 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:06.3 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:06.4 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:06.5 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:06.6 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:06.7 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:07.0 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:07.1 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:07.2 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:07.3 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:07.4 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:14.0 subsystem <- 8086/8c31 TEST: Entering pci_dev_set_subsystem PCI: 00:14.0 cmd <- 02 TEST: Entering pci_dev_enable_resources PCI: 00:16.0 cmd <- 06 TEST: Entering pci_dev_enable_resources PCI: 00:16.1 cmd <- 02 TEST: Entering pci_dev_enable_resources PCI: 00:16.2 cmd <- 01 TEST: Entering pci_dev_enable_resources PCI: 00:16.3 cmd <- 03 TEST: Entering pci_dev_enable_resources PCI: 00:1d.0 subsystem <- 8086/8c26 TEST: Entering pci_dev_set_subsystem PCI: 00:1d.0 cmd <- 02 TEST: Entering pci_dev_enable_resources PCI: 00:1f.2 subsystem <- 8086/8c02 TEST: Entering pci_dev_set_subsystem PCI: 00:1f.2 cmd <- 03 TEST: Entering pci_dev_enable_resources PCI: 00:1f.3 cmd <- 03 TEST: Entering pci_dev_enable_resources PCI: 00:1f.6 cmd <- 02 TEST: Entering enable_resources TEST: Entering enable_resources TEST: Entering pci_dev_enable_resources PCI: 02:00.0 cmd <- 06 TEST: Entering pci_dev_enable_resources PCI: 02:00.1 cmd <- 06 TEST: Entering pci_dev_enable_resources PCI: 02:00.2 cmd <- 06 TEST: Entering pci_dev_enable_resources PCI: 02:00.3 cmd <- 06 TEST: Entering enable_resources TEST: Entering pci_dev_enable_resources PCI: 03:00.0 cmd <- 02 TEST: Entering pci_dev_enable_resources PCI: 03:00.1 cmd <- 02 TEST: Entering enable_resources TEST: Entering pci_dev_enable_resources PCI: 04:00.0 cmd <- 03 TEST: Entering pci_dev_enable_resources PCI: 04:00.1 cmd <- 02 done. TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_report_time BS: BS_DEV_ENABLE times (us): entry 6302 run 340690 exit 6301 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_dev_init TEST: Entering dev_initialize Initializing devices... calling init_dev() TEST: Entering init_dev Root Device init ... Root Device init finished in 2135 usecs TEST: Entering init_link TEST: Entering init_dev CPU_CLUSTER: 0 init ... MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local APIC... apic_id: 0x00 done. Setting up SMI for CPU Will perform SMM setup. CPU: Intel(R) Xeon(R) CPU D-1531 @ 2.20GHz. TEST: Entering alloc_find_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev Loading module at 00030000 with entry 00030000. filesize: 0x130 memsize: 0x130 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 11 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 1 apic_id 1. done. AP: slot 5 apic_id 3. AP: slot 8 apic_id a. AP: slot 7 apic_id b. Waiting for 2nd SIPI to complete...done. AP: slot 4 apic_id 7. AP: slot 6 apic_id 4. AP: slot 9 apic_id 5. AP: slot 10 apic_id 8. AP: slot 11 apic_id 9. AP: slot 2 apic_id 2. AP: slot 3 apic_id 6. Loading module at 00038000 with entry 00038000. filesize: 0x1c0 memsize: 0x1c0 Processing 13 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call 7eec50ec(00000000) Installing SMM handler to 0x7f800000 Loading module at 7f810000 with entry 7f81002b. filesize: 0x188 memsize: 0x4190 Processing 11 relocs. Offset value of 0x7f810000 Loading module at 7f808000 with entry 7f808000. filesize: 0x1c0 memsize: 0x1c0 Processing 13 relocs. Offset value of 0x7f808000 SMM Module: placing jmp sequence at 7f807c00 rel16 0x03fd SMM Module: placing jmp sequence at 7f807800 rel16 0x07fd SMM Module: placing jmp sequence at 7f807400 rel16 0x0bfd SMM Module: placing jmp sequence at 7f807000 rel16 0x0ffd SMM Module: placing jmp sequence at 7f806c00 rel16 0x13fd SMM Module: placing jmp sequence at 7f806800 rel16 0x17fd SMM Module: placing jmp sequence at 7f806400 rel16 0x1bfd SMM Module: placing jmp sequence at 7f806000 rel16 0x1ffd SMM Module: placing jmp sequence at 7f805c00 rel16 0x23fd SMM Module: placing jmp sequence at 7f805800 rel16 0x27fd SMM Module: placing jmp sequence at 7f805400 rel16 0x2bfd SMM Module: stub loaded at 7f808000. Will call 7f81002b(00000000) Initializing Southbridge SMI... ... pmbase = 0x0400 SMI_STS: PM1 PM1_STS: TMROF New SMBASE 0x7f800000 In relocation handler: CPU 0 Relocation complete. Doing parallel SMM relocation. New SMBASE 0x7f800000 New SMBASE 0x7f7fec00 New SMBASE 0x7f7fe400 New SMBASE 0x7f7fd400 New SMBASE 0x7f7fd800 In relocation handler: CPU 10 New SMBASE=0x7f7fd800 IEDBASE=0x7fc00000 In relocation handler: CPU 11 New SMBASE=0x7f7fd400 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff800800 In relocation handler: CPU 5 New SMBASE=0x7f7fec00 IEDBASE=0x7fc00000 New SMBASE 0x7f7ff800 New SMBASE 0x7f7ff000 New SMBASE 0x7f7ff400 In relocation handler: CPU 3 New SMBASE=0x7f7ff400 IEDBASE=0x7fc00000 In relocation handler: CPU 4 New SMBASE=0x7f7ff000 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff800800 New SMBASE 0x7f7fe000 In relocation handler: CPU 8 In relocation handler: CPU 2 New SMBASE 0x7f7fe800 New SMBASE 0x7f7fdc00 In relocation handler: CPU 9 New SMBASE=0x7f7fdc00 IEDBASE=0x7fc00000 In relocation handler: CPU 6 New SMBASE=0x7f7fe800 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff800800 Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. Relocation complete. microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date Relocation complete. Writing SMRR. base = 0x7f800006, mask=0xff800800 microcode: Update skipped, already up-to-date Relocation complete. Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. Writing SMRR. base = 0x7f800006, mask=0xff800800 microcode: Update skipped, already up-to-date Relocation complete. New SMBASE=0x7f7fe000 IEDBASE=0x7fc00000 In relocation handler: CPU 7 New SMBASE=0x7f7fe400 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff800800 Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. Relocation complete. microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date Relocation complete. New SMBASE=0x7f7ff800 IEDBASE=0x7fc00000 microcode: Update skipped, already up-to-date Writing SMRR. base = 0x7f800006, mask=0xff800800 New SMBASE 0x7f7ffc00 In relocation handler: CPU 1 New SMBASE=0x7f7ffc00 IEDBASE=0x7fc00000 In relocation handler: CPU 0 Writing SMRR. base = 0x7f800006, mask=0xff800800 New SMBASE=0x7f800000 IEDBASE=0x7fc00000 Relocation complete. Writing SMRR. base = 0x7f800006, mask=0xff800800 microcode: Update skipped, already up-to-date Relocation complete. Relocation complete. microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date Initializing CPU #0 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 Init Broadwell-DE core. CPU #0 initialized Initializing CPU #1 Initializing CPU #5 Initializing CPU #2 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 CPU: vendor Intel device 50663 Initializing CPU #8 Initializing CPU #7 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 Init Broadwell-DE core. CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 Initializing CPU #3 Initializing CPU #4 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 Init Broadwell-DE core. Init Broadwell-DE core. CPU #3 initialized Initializing CPU #9 Initializing CPU #6 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 CPU: vendor Intel device 50663 Init Broadwell-DE core. CPU: family 06, model 56, stepping 03 CPU #5 initialized Init Broadwell-DE core. Initializing CPU #10 Initializing CPU #11 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 CPU #8 initialized Init Broadwell-DE core. Init Broadwell-DE core. CPU: family 06, model 56, stepping 03 CPU #9 initialized Init Broadwell-DE core. CPU #7 initialized CPU #4 initialized CPU #2 initialized Init Broadwell-DE core. Init Broadwell-DE core. CPU #10 initialized CPU #11 initialized CPU #6 initialized Init Broadwell-DE core. CPU #1 initialized bsp_do_flight_plan done after 562 msecs. Enabling SMIs. Locking SMM. CPU_CLUSTER: 0 init finished in 707324 usecs TEST: Entering init_dev TEST: Entering init_link TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_link TEST: Entering init_dev TEST: Entering init_dev PCI: 00:01.0 init ... PCI: 00:01.0 init finished in 2232 usecs TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev PCI: 00:03.0 init ... PCI: 00:03.0 init finished in 2231 usecs TEST: Entering init_dev TEST: Entering init_dev PCI: 00:05.1 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:05.1 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:05.2 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:05.2 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:05.4 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x800 TEST: if 2 false, returning PCI: 00:05.4 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:05.6 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x1101 TEST: if 2 false, returning PCI: 00:05.6 init finished in 12024 usecs TEST: Entering init_dev PCI: 00:06.0 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:06.0 init finished in 11928 usecs TEST: Entering init_dev PCI: 00:06.1 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:06.1 init finished in 11928 usecs TEST: Entering init_dev PCI: 00:06.2 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:06.2 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:06.3 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:06.3 init finished in 11928 usecs TEST: Entering init_dev PCI: 00:06.4 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:06.4 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:06.5 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:06.5 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:06.6 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:06.6 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:06.7 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:06.7 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:07.0 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:07.0 init finished in 11928 usecs TEST: Entering init_dev PCI: 00:07.1 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:07.1 init finished in 11928 usecs TEST: Entering init_dev PCI: 00:07.2 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:07.2 init finished in 11928 usecs TEST: Entering init_dev PCI: 00:07.3 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:07.3 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:07.4 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:07.4 init finished in 11928 usecs TEST: Entering init_dev PCI: 00:14.0 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0xc03 TEST: if 2 false, returning PCI: 00:14.0 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:16.0 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x780 TEST: if 2 false, returning PCI: 00:16.0 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:16.1 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x780 TEST: if 2 false, returning PCI: 00:16.1 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:16.2 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x101 TEST: if 2 false, returning PCI: 00:16.2 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:16.3 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x700 TEST: if 2 false, returning PCI: 00:16.3 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:1d.0 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0xc03 TEST: if 2 false, returning PCI: 00:1d.0 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:1f.0 init ... soc: southcluster_init Programming PIRQ[A-H] Routing Control Register PIRQ[A]: 05 PIRQ[B]: 06 PIRQ[C]: 07 PIRQ[D]: 0a PIRQ[E]: 0b PIRQ[F]: 0c PIRQ[G]: 0e PIRQ[H]: 0f PCI_CFG IRQ: Write PCI config space IRQ assignments TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:00.00 using PIN A Warning: PCI Device 0 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:14.00 using PIN D INT_PIN : 4 (PIN D) PIRQ : D INT_LINE : 0xA (IRQ 10) TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:1D.00 using PIN C INT_PIN : 3 (PIN C) PIRQ : C INT_LINE : 0x7 (IRQ 7) TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:1F.02 using PIN A INT_PIN : 1 (PIN A) PIRQ : A INT_LINE : 0x5 (IRQ 5) TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:1F.03 using PIN C INT_PIN : 3 (PIN C) PIRQ : C INT_LINE : 0x7 (IRQ 7) TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:01.00 using PIN A Warning: PCI Device 1 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:03.00 using PIN A Warning: PCI Device 3 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:02.00 using PIN A Warning: PCI Device 2 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:02.02 using PIN A Warning: PCI Device 2 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:16.00 using PIN A INT_PIN : 1 (PIN A) PIRQ : A INT_LINE : 0x5 (IRQ 5) TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:16.01 using PIN B INT_PIN : 2 (PIN B) PIRQ : B INT_LINE : 0x6 (IRQ 6) TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:16.02 using PIN A INT_PIN : 1 (PIN A) PIRQ : A INT_LINE : 0x5 (IRQ 5) TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:16.03 using PIN B INT_PIN : 2 (PIN B) PIRQ : B INT_LINE : 0x6 (IRQ 6) TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:1F.06 using PIN C INT_PIN : 3 (PIN C) PIRQ : C INT_LINE : 0x7 (IRQ 7) TEST: Entering get_pci_irq_pins PCI IRQ: Found device 2:00.00 using PIN A TEST: Entering swizzle_irq_pins With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.00h Warning: PCI Device 2 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 2:00.01 using PIN B TEST: Entering swizzle_irq_pins With INT_PIN swizzled to PIN B Attached to bridge device 0:02h.00h Warning: PCI Device 2 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 2:00.02 using PIN C TEST: Entering swizzle_irq_pins With INT_PIN swizzled to PIN C Attached to bridge device 0:02h.00h Warning: PCI Device 2 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 2:00.03 using PIN D TEST: Entering swizzle_irq_pins With INT_PIN swizzled to PIN D Attached to bridge device 0:02h.00h Warning: PCI Device 2 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 3:00.00 using PIN A TEST: Entering swizzle_irq_pins With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.02h Warning: PCI Device 2 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 3:00.01 using PIN B TEST: Entering swizzle_irq_pins With INT_PIN swizzled to PIN B Attached to bridge device 0:02h.02h Warning: PCI Device 2 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 4:00.00 using PIN A TEST: Entering swizzle_irq_pins With INT_PIN swizzled to PIN A Attached to bridge device 0:03h.00h Warning: PCI Device 3 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 4:00.01 using PIN B TEST: Entering swizzle_irq_pins With INT_PIN swizzled to PIN B Attached to bridge device 0:03h.00h Warning: PCI Device 3 does not have an IRQ entry, skipping it PCI_CFG IRQ: Finished writing PCI config space IRQ assignments PCI: 00:1f.0 init finished in 467704 usecs TEST: Entering init_dev PCI: 00:1f.2 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x106 TEST: if 2 false, returning PCI: 00:1f.2 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:1f.3 init ... PCI: 00:1f.3 init finished in 2234 usecs TEST: Entering init_dev PCI: 00:1f.6 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x1180 TEST: if 2 false, returning PCI: 00:1f.6 init finished in 12023 usecs TEST: Entering init_link TEST: Entering init_link TEST: Entering init_dev PCI: 02:00.0 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 02:00.0 init finished in 11927 usecs TEST: Entering init_dev PCI: 02:00.1 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 02:00.1 init finished in 11928 usecs TEST: Entering init_dev PCI: 02:00.2 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 02:00.2 init finished in 11928 usecs TEST: Entering init_dev PCI: 02:00.3 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 02:00.3 init finished in 11927 usecs TEST: Entering init_link TEST: Entering init_dev PCI: 03:00.0 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x200 TEST: if 2 false, returning PCI: 03:00.0 init finished in 11927 usecs TEST: Entering init_dev PCI: 03:00.1 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x200 TEST: if 2 false, returning PCI: 03:00.1 init finished in 11928 usecs TEST: Entering init_link TEST: Entering init_dev PCI: 04:00.0 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x300 TEST: Entering should_load_oprom TEST: Entering should_run_oprom TEST: calling TEST: Exiting should_run_oprom TEST: if 2:returning 1 TEST: Entering pci_rom_probe CBFS @ 200200 size 5ffe00 CBFS: 'Master Header Locator' located CBFS at [200200:800000) CBFS: Locating 'pci10de,128b.rom' CBFS: Checking offset 0 CBFS: File @ offset 0 size 20 CBFS: Unmatched 'cbfs master header' at 0 CBFS: Checking offset 80 CBFS: File @ offset 80 size 44a4 CBFS: Unmatched 'fallback/romstage' at 80 CBFS: Checking offset 45c0 CBFS: File @ offset 45c0 size 19800 CBFS: Unmatched 'cpu_microcode_blob.bin' at 45c0 CBFS: Checking offset 1de40 CBFS: File @ offset 1de40 size f868 CBFS: Unmatched 'fallback/ramstage' at 1de40 CBFS: Checking offset 2d700 CBFS: File @ offset 2d700 size 3dd CBFS: Unmatched 'config' at 2d700 CBFS: Checking offset 2db40 CBFS: File @ offset 2db40 size 2b8 CBFS: Unmatched 'revision' at 2db40 CBFS: Checking offset 2de40 CBFS: File @ offset 2de40 size 368 CBFS: Unmatched 'cmos_layout.bin' at 2de40 CBFS: Checking offset 2e200 CBFS: File @ offset 2e200 size 25ca CBFS: Unmatched 'fallback/dsdt.aml' at 2e200 CBFS: Checking offset 30840 CBFS: File @ offset 30840 size 410038 CBFS: Unmatched 'img/uefi' at 30840 CBFS: Checking offset 4408c0 CBFS: File @ offset 4408c0 size 109f0 CBFS: Unmatched 'fallback/payload' at 4408c0 CBFS: Checking offset 451300 CBFS: File @ offset 451300 size 639 CBFS: Unmatched 'payload_config' at 451300 CBFS: Checking offset 451980 CBFS: File @ offset 451980 size 100 CBFS: Unmatched 'payload_revision' at 451980 CBFS: Checking offset 451b00 CBFS: File @ offset 451b00 size 5e298 CBFS: Unmatched '' at 451b00 CBFS: Checking offset 4afdc0 CBFS: File @ offset 4afdc0 size 120000 CBFS: Unmatched 'fsp.bin' at 4afdc0 CBFS: Checking offset 5cfe00 CBFS: File @ offset 5cfe00 size 2fa18 CBFS: Unmatched '' at 5cfe00 CBFS: Checking offset 5ff840 CBFS: File @ offset 5ff840 size 580 CBFS: Unmatched 'bootblock' at 5ff840 CBFS: Checking offset 5ffe00 CBFS: 'pci10de,128b.rom' not found. Option ROM address for PCI: 04:00.0 = fb000000 PCI expansion ROM, signature 0xaa55, INIT size 0xf200, data ptr 0x0190 PCI ROM image, vendor ID 10de, device ID 128b, PCI ROM image, Class Code 030000, Code Type 00 TEST: Entering pci_rom_load Copying VGA ROM Image from fb000000 to 0xc0000, 0xf200 bytes TEST: Entering should_run_oprom TEST: should_run = 1 TEST: calling run_bios Real mode stub @00000600: 889 bytes Calling Option ROM... ... Option ROM returned. TEST: calling gfx_set_init_done VGA Option ROM was run TEST: Exiting pci_dev_init PCI: 04:00.0 init finished in 539737 usecs TEST: Entering init_dev PCI: 04:00.1 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x403 TEST: if 2 false, returning PCI: 04:00.1 init finished in 11928 usecs Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 APIC: 00: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:19.0: enabled 0 PCI: 00:1d.0: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.5: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:05.0: enabled 1 PCI: 00:05.1: enabled 1 PCI: 00:05.2: enabled 1 PCI: 00:05.4: enabled 1 PCI: 00:05.6: enabled 1 PCI: 00:06.0: enabled 1 PCI: 00:06.1: enabled 1 PCI: 00:06.2: enabled 1 PCI: 00:06.3: enabled 1 PCI: 00:06.4: enabled 1 PCI: 00:06.5: enabled 1 PCI: 00:06.6: enabled 1 PCI: 00:06.7: enabled 1 PCI: 00:07.0: enabled 1 PCI: 00:07.1: enabled 1 PCI: 00:07.2: enabled 1 PCI: 00:07.3: enabled 1 PCI: 00:07.4: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:16.3: enabled 1 PCI: 00:1f.6: enabled 1 PCI: 02:00.0: enabled 1 PCI: 02:00.1: enabled 1 PCI: 02:00.2: enabled 1 PCI: 02:00.3: enabled 1 PCI: 03:00.0: enabled 1 PCI: 03:00.1: enabled 1 PCI: 04:00.0: enabled 1 PCI: 04:00.1: enabled 1 APIC: 01: enabled 1 APIC: 02: enabled 1 APIC: 06: enabled 1 APIC: 07: enabled 1 APIC: 03: enabled 1 APIC: 04: enabled 1 APIC: 0b: enabled 1 APIC: 0a: enabled 1 APIC: 05: enabled 1 APIC: 08: enabled 1 APIC: 09: enabled 1 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_report_time BS: BS_DEV_INIT times (us): entry 6309 run 2575805 exit 6303 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_post_device TEST: Entering dev_finalize Finalize devices... TEST: Entering final_dev TEST: Entering final_link TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_link TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_link TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_link TEST: Entering final_link TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_link TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_link TEST: Entering final_dev TEST: Entering final_dev Devices finalized TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_report_time BS: BS_POST_DEVICE times (us): entry 6303 run 172245 exit 6302 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_os_resume_check TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_report_time BS: BS_OS_RESUME_CHECK times (us): entry 6302 run 6400 exit 6302 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks === FSP HOB Data Structure === FSP Hoblistptr: 0x7f100000 HOB 0x7f100000 is an EFI_HOB_TYPE_HANDOFF (type 0x1) HOB 0x7f100038 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f100038 with length0x0 Address: 7f100040 Guid: ea296d92-0b69-423c-8c2833b4e0a91268 HOB 0x7f1000d8 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f1000d8 with length0x0 Address: 7f1000e0 Guid: 9b3ada4f-ae56-4c24-8deaf03b7558ae50 HOB 0x7f100170 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f100170 with length0x0 Address: 7f100178 Guid: 1e2acc41-e26a-483d-afc7a056c34e087b HOB 0x7f100260 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f100270 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f100288 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f100520 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f100520 with length0x0 Address: 7f100528 Guid: 489d2a71-ba4a-444c-9fe2a6b7e5cd7847 HOB 0x7f100570 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_SYSTEM_MEMORY (0x0) has attributes 0x3c07 at location 0x0 with length 0xa0000 HOB 0x7f1005a0 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_MEMORY_RESERVED (0x5) has attributes 0x3c07 at location 0xa0000 with length 0x60000 HOB 0x7f1005d0 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_SYSTEM_MEMORY (0x0) has attributes 0x3c07 at location 0x100000 with length 0x7ef00000 HOB 0x7f100600 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_MEMORY_RESERVED (0x5) has attributes 0x3c07 at location 0x7f000000 with length 0x800000 HOB 0x7f100630 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_MEMORY_RESERVED (0x5) has attributes 0x3c07 at location 0x7f800000 with length 0x800000 HOB 0x7f100660 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_SYSTEM_MEMORY (0x0) has attributes 0x3c07 at location 0x0 with length 0x80000000 HOB 0x7f100690 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f100690 with length0xffff Address: 7f100698 Guid: 1de25879-6e2a-4d72-a768288ccb9fa719 HOB 0x7f10f6a8 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f10f6a8 with length0xffff Address: 7f10f6b0 Guid: 1de25879-6e2a-4d72-a768288ccb9fa719 HOB 0x7f11e6c0 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f11e6c0 with length0x0 Address: 7f11e6c8 Guid: 1de25879-6e2a-4d72-a768288ccb9fa719 HOB 0x7f121bd8 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f121bd8 with length0x0 Address: 7f121be0 Guid: 7ff396a1-ee7d-431e-ba538fca127c44c0 HOB 0x7f123158 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f123158 with length0x0 Address: 7f123160 Guid: f8870015-6994-4b98-95a2bd56da91c07f HOB 0x7f127208 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f000000 with length 0x100000 HOB 0x7f127238 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7ff000 with length 0x1000 HOB 0x7f127268 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7f5000 with length 0xa000 HOB 0x7f127298 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f127298 with length0xffff Address: 7f1272a0 Guid: bbcff46c-c8d3-4113-8985b9d4f3b3f64e HOB 0x7f12f2b0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7ef000 with length 0x6000 HOB 0x7f12f2e0 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f12f2e0 with length0x0 Address: 7f12f2e8 Guid: 98c8588c-640a-4bb4-aea03f81cde17524 HOB 0x7f12f490 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f12f490 with length0x0 Address: 7f12f498 Guid: ee4e5898-3914-4259-9d6edc7bd79403cf HOB 0x7f12f4b8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f4d0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7eb000 with length 0x4000 HOB 0x7f12f500 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7e7000 with length 0x4000 HOB 0x7f12f530 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7e4000 with length 0x3000 HOB 0x7f12f560 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7e0000 with length 0x4000 HOB 0x7f12f590 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7d5000 with length 0xb000 HOB 0x7f12f5c0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7cb000 with length 0xa000 HOB 0x7f12f5f0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f600 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f618 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f630 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f688 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f698 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f6a8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f6b8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f6c8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f6d8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f6e8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f718 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f740 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f750 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f760 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f850 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7c7000 with length 0x4000 HOB 0x7f12f880 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7bd000 with length 0xa000 HOB 0x7f12f8b0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7b4000 with length 0x9000 HOB 0x7f12f8e0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f8f8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f930 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f12f930 with length0x0 Address: 7f12f938 Guid: c1392859-1f65-446e-b3f58435fcc7d1c4 HOB 0x7f12fa60 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7b0000 with length 0x4000 HOB 0x7f12fa90 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7ab000 with length 0x5000 HOB 0x7f12fac0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7a7000 with length 0x4000 HOB 0x7f12faf0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7a3000 with length 0x4000 HOB 0x7f12fb20 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f79c000 with length 0x7000 HOB 0x7f12fb50 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f796000 with length 0x6000 HOB 0x7f12fb80 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f792000 with length 0x4000 HOB 0x7f12fbb0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f770000 with length 0x22000 HOB 0x7f12fbe0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f74f000 with length 0x21000 HOB 0x7f12fc10 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f130c50 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_MEMORY_MAPPED_IO (0x1) has attributes 0x403 at location 0xfbffc000 with length 0x2000 HOB 0x7f130c80 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f74b000 with length 0x4000 HOB 0x7f130cb0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f743000 with length 0x8000 HOB 0x7f130ce0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f73c000 with length 0x7000 HOB 0x7f130d10 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f738000 with length 0x4000 HOB 0x7f130d40 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f733000 with length 0x5000 HOB 0x7f130d70 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f72f000 with length 0x4000 HOB 0x7f130da0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f130de0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f72b000 with length 0x4000 HOB 0x7f130e10 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f723000 with length 0x8000 HOB 0x7f130e40 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f71c000 with length 0x7000 HOB 0x7f130e70 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f130eb0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f130f60 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f131168 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f70c000 with length 0x10000 HOB 0x7f131198 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f1312b8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f708000 with length 0x4000 HOB 0x7f1312e8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f6f6000 with length 0x12000 HOB 0x7f131318 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f6e6000 with length 0x10000 HOB 0x7f131348 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f131360 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f6e2000 with length 0x4000 HOB 0x7f131390 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f6dd000 with length 0x5000 HOB 0x7f1313c0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f6d9000 with length 0x4000 HOB 0x7f1313f0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f132908 is an EFI_HOB_TYPE_END_OF_HOB_LIST (type 0xffff) === End of FSP HOB Data Structure === TEST: Entering bs_sample_time TEST: Entering bs_write_tables CBFS @ 200200 size 5ffe00 CBFS: 'Master Header Locator' located CBFS at [200200:800000) CBFS: Locating 'fallback/dsdt.aml' CBFS: Checking offset 0 CBFS: File @ offset 0 size 20 CBFS: Unmatched 'cbfs master header' at 0 CBFS: Checking offset 80 CBFS: File @ offset 80 size 44a4 CBFS: Unmatched 'fallback/romstage' at 80 CBFS: Checking offset 45c0 CBFS: File @ offset 45c0 size 19800 CBFS: Unmatched 'cpu_microcode_blob.bin' at 45c0 CBFS: Checking offset 1de40 CBFS: File @ offset 1de40 size f868 CBFS: Unmatched 'fallback/ramstage' at 1de40 CBFS: Checking offset 2d700 CBFS: File @ offset 2d700 size 3dd CBFS: Unmatched 'config' at 2d700 CBFS: Checking offset 2db40 CBFS: File @ offset 2db40 size 2b8 CBFS: Unmatched 'revision' at 2db40 CBFS: Checking offset 2de40 CBFS: File @ offset 2de40 size 368 CBFS: Unmatched 'cmos_layout.bin' at 2de40 CBFS: Checking offset 2e200 CBFS: File @ offset 2e200 size 25ca CBFS: Found @ offset 2e200 size 25ca CBFS @ 200200 size 5ffe00 CBFS: 'Master Header Locator' located CBFS at [200200:800000) CBFS: Locating 'fallback/slic' CBFS: Checking offset 0 CBFS: File @ offset 0 size 20 CBFS: Unmatched 'cbfs master header' at 0 CBFS: Checking offset 80 CBFS: File @ offset 80 size 44a4 CBFS: Unmatched 'fallback/romstage' at 80 CBFS: Checking offset 45c0 CBFS: File @ offset 45c0 size 19800 CBFS: Unmatched 'cpu_microcode_blob.bin' at 45c0 CBFS: Checking offset 1de40 CBFS: File @ offset 1de40 size f868 CBFS: Unmatched 'fallback/ramstage' at 1de40 CBFS: Checking offset 2d700 CBFS: File @ offset 2d700 size 3dd CBFS: Unmatched 'config' at 2d700 CBFS: Checking offset 2db40 CBFS: File @ offset 2db40 size 2b8 CBFS: Unmatched 'revision' at 2db40 CBFS: Checking offset 2de40 CBFS: File @ offset 2de40 size 368 CBFS: Unmatched 'cmos_layout.bin' at 2de40 CBFS: Checking offset 2e200 CBFS: File @ offset 2e200 size 25ca CBFS: Unmatched 'fallback/dsdt.aml' at 2e200 CBFS: Checking offset 30840 CBFS: File @ offset 30840 size 410038 CBFS: Unmatched 'img/uefi' at 30840 CBFS: Checking offset 4408c0 CBFS: File @ offset 4408c0 size 109f0 CBFS: Unmatched 'fallback/payload' at 4408c0 CBFS: Checking offset 451300 CBFS: File @ offset 451300 size 639 CBFS: Unmatched 'payload_config' at 451300 CBFS: Checking offset 451980 CBFS: File @ offset 451980 size 100 CBFS: Unmatched 'payload_revision' at 451980 CBFS: Checking offset 451b00 CBFS: File @ offset 451b00 size 5e298 CBFS: Unmatched '' at 451b00 CBFS: Checking offset 4afdc0 CBFS: File @ offset 4afdc0 size 120000 CBFS: Unmatched 'fsp.bin' at 4afdc0 CBFS: Checking offset 5cfe00 CBFS: File @ offset 5cfe00 size 2fa18 CBFS: Unmatched '' at 5cfe00 CBFS: Checking offset 5ff840 CBFS: File @ offset 5ff840 size 580 CBFS: Unmatched 'bootblock' at 5ff840 CBFS: Checking offset 5ffe00 CBFS: 'fallback/slic' not found. ACPI: Writing ACPI tables at 7ed3d000. ACPI: * FACS ACPI: * DSDT ACPI: * FADT SCI is IRQ9 ACPI: added table 1/32, length now 40 ACPI: * SSDT Turbo is available and visible PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_probe CBFS @ 200200 size 5ffe00 CBFS: 'Master Header Locator' located CBFS at [200200:800000) CBFS: Locating 'pci10de,128b.rom' CBFS: Checking offset 0 CBFS: File @ offset 0 size 20 CBFS: Unmatched 'cbfs master header' at 0 CBFS: Checking offset 80 CBFS: File @ offset 80 size 44a4 CBFS: Unmatched 'fallback/romstage' at 80 CBFS: Checking offset 45c0 CBFS: File @ offset 45c0 size 19800 CBFS: Unmatched 'cpu_microcode_blob.bin' at 45c0 CBFS: Checking offset 1de40 CBFS: File @ offset 1de40 size f868 CBFS: Unmatched 'fallback/ramstage' at 1de40 CBFS: Checking offset 2d700 CBFS: File @ offset 2d700 size 3dd CBFS: Unmatched 'config' at 2d700 CBFS: Checking offset 2db40 CBFS: File @ offset 2db40 size 2b8 CBFS: Unmatched 'revision' at 2db40 CBFS: Checking offset 2de40 CBFS: File @ offset 2de40 size 368 CBFS: Unmatched 'cmos_layout.bin' at 2de40 CBFS: Checking offset 2e200 CBFS: File @ offset 2e200 size 25ca CBFS: Unmatched 'fallback/dsdt.aml' at 2e200 CBFS: Checking offset 30840 CBFS: File @ offset 30840 size 410038 CBFS: Unmatched 'img/uefi' at 30840 CBFS: Checking offset 4408c0 CBFS: File @ offset 4408c0 size 109f0 CBFS: Unmatched 'fallback/payload' at 4408c0 CBFS: Checking offset 451300 CBFS: File @ offset 451300 size 639 CBFS: Unmatched 'payload_config' at 451300 CBFS: Checking offset 451980 CBFS: File @ offset 451980 size 100 CBFS: Unmatched 'payload_revision' at 451980 CBFS: Checking offset 451b00 CBFS: File @ offset 451b00 size 5e298 CBFS: Unmatched '' at 451b00 CBFS: Checking offset 4afdc0 CBFS: File @ offset 4afdc0 size 120000 CBFS: Unmatched 'fsp.bin' at 4afdc0 CBFS: Checking offset 5cfe00 CBFS: File @ offset 5cfe00 size 2fa18 CBFS: Unmatched '' at 5cfe00 CBFS: Checking offset 5ff840 CBFS: File @ offset 5ff840 size 580 CBFS: Unmatched 'bootblock' at 5ff840 CBFS: Checking offset 5ffe00 CBFS: 'pci10de,128b.rom' not found. Option ROM address for PCI: 04:00.0 = fb000000 PCI expansion ROM, signature 0xbeef, INIT size 0x0000, data ptr 0xffff Incorrect expansion ROM header signature beef PCI: 04:00.0: Missing PCI Option ROM TEST: Entering pci_rom_ssdt ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * MADT IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x08 IOAPIC: Dumping registers reg 0x0000: 0x08000000 reg 0x0001: 0x00170020 reg 0x0002: 0x00170020 IOAPIC: Initializing IOAPIC at 0xfec01000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x09 IOAPIC: Dumping registers reg 0x0000: 0x09000000 reg 0x0001: 0x00170020 reg 0x0002: 0x00000000 ACPI: added table 4/32, length now 52 current = 7ed42290 TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables ACPI: * DMAR ACPI: added table 5/32, length now 56 TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables ACPI: done. ACPI tables: 21264 bytes. smbios_write_tables: 7ed3c000 SMBIOS: Unknown CPU SMBIOS tables: 424 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 7108 Writing coreboot table at 0x7ed61000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-000000007ed3bfff: RAM 4. 000000007ed3c000-000000007eeb3fff: CONFIGURATION TABLES 5. 000000007eeb4000-000000007effdfff: RAMSTAGE 6. 000000007effe000-000000007effffff: CONFIGURATION TABLES 7. 000000007f000000-000000008fffffff: RESERVED 8. 00000000fbffc000-00000000fbffdfff: RESERVED 9. 00000000feb00000-00000000feb0ffff: RESERVED 10. 00000000feb80000-00000000fedfffff: RESERVED 11. 00000000fef00000-00000000ffffffff: RESERVED 12. 0000000100000000-000000017fffffff: RAM Manufacturer: ef SF: Detected W25Q128_V with sector size 0x1000, total 0x1000000 SF size 0x1000000 does not correspond to CONFIG_ROM_SIZE 0x800000!! CBFS @ 200200 size 5ffe00 CBFS: 'Master Header Locator' located CBFS at [200200:800000) FMAP: Found "FLASH" version 1.1 at 200000. FMAP: base = ff800000 size = 800000 #areas = 3 Wrote coreboot table at: 7ed61000, 0x2dc bytes, checksum cafd coreboot table: 756 bytes. IMD ROOT 0. 7efff000 00001000 IMD SMALL 1. 7effe000 00001000 RAMSTAGE 2. 7eeb3000 0014b000 57a9e100 3. 7ed69000 00149958 COREBOOT 4. 7ed61000 00008000 ACPI 5. 7ed3d000 00024000 SMBIOS 6. 7ed3c000 00000800 IMD small region: IMD ROOT 0. 7effec00 00000400 HOB 1. 7effebe0 00000001 57a9e000 2. 7effebc0 00000018 COREBOOTFWD 3. 7effeb80 00000028 TEST: Entering dev_finalize_chips TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_report_time BS: BS_WRITE_TABLES times (us): entry 1071438 run 1980572 exit 6303 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_payload_load CBFS @ 200200 size 5ffe00 CBFS: 'Master Header Locator' located CBFS at [200200:800000) CBFS: Locating 'fallback/payload' CBFS: Checking offset 0 CBFS: File @ offset 0 size 20 CBFS: Unmatched 'cbfs master header' at 0 CBFS: Checking offset 80 CBFS: File @ offset 80 size 44a4 CBFS: Unmatched 'fallback/romstage' at 80 CBFS: Checking offset 45c0 CBFS: File @ offset 45c0 size 19800 CBFS: Unmatched 'cpu_microcode_blob.bin' at 45c0 CBFS: Checking offset 1de40 CBFS: File @ offset 1de40 size f868 CBFS: Unmatched 'fallback/ramstage' at 1de40 CBFS: Checking offset 2d700 CBFS: File @ offset 2d700 size 3dd CBFS: Unmatched 'config' at 2d700 CBFS: Checking offset 2db40 CBFS: File @ offset 2db40 size 2b8 CBFS: Unmatched 'revision' at 2db40 CBFS: Checking offset 2de40 CBFS: File @ offset 2de40 size 368 CBFS: Unmatched 'cmos_layout.bin' at 2de40 CBFS: Checking offset 2e200 CBFS: File @ offset 2e200 size 25ca CBFS: Unmatched 'fallback/dsdt.aml' at 2e200 CBFS: Checking offset 30840 CBFS: File @ offset 30840 size 410038 CBFS: Unmatched 'img/uefi' at 30840 CBFS: Checking offset 4408c0 CBFS: File @ offset 4408c0 size 109f0 CBFS: Found @ offset 4408c0 size 109f0 Checking segment from ROM address 0xffe40af8 Payload being loaded at below 1MiB without region being marked as RAM usable. Checking segment from ROM address 0xffe40b14 Loading segment from ROM address 0xffe40af8 code (compression=1) New segment dstaddr 0x000e06c0 memsize 0x1f940 srcaddr 0xffe40b30 filesize 0x109b8 Loading Segment: addr: 0x000e06c0 memsz: 0x000000000001f940 filesz: 0x00000000000109b8 using LZMA [ 0x000e06c0, 00100000, 0x00100000) <- ffe40b30 Loading segment from ROM address 0xffe40b14 Entry Point 0x000fd258 Loaded segments TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_report_time BS: BS_PAYLOAD_LOAD times (us): entry 6302 run 233481 exit 6302 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks FspNotify(EnumInitPhaseReadyToBoot) fsp_header_ptr: ffeb0094 FSP Header Version: 1 FSP Revision: 3.3 FSP Got Notification. Notification Value : 0x00000040 FSP Ready To Boot ... Install PPI: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F756453 Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F7598BD IioLateInitialize ReadyToBoot Callback OnExitBootServices.. IioInit Late Secure the Platform (TXT).. Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F72F2E6 Hiding ME Devices Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F73C929 MP ReadyToBootEvent() :: Set LOCK bit in PACKAGE_RAPL_LIMIT with value = 800781B0 :: Set LOCK bit in CSR_SAPMCTL with value = B8002026 :: Set LOCK bit in CSR_DRAM_PLANE_POWER_LIMIT with value = 80000000 :: Set LOCK bit in P_STATE_LIMITS_PCU_FUN0_REG with value = 800000FF :: Set LOCK bit in CSR_DESIRED_CORES_PCU_FUN1_REG with value = 80000000 Done Write MAILBOX_BIOS_CMD_WRITE_PCU_MISC_CONFIG, data = 2, SETUP Pl2SafetyNetEnable = 1 :: Read BIOS_MAILBOX_DATA_PCU_FUN1_REG back, data = 2 :: Debug PpmSetBiosInitDone Read Data: 00000606 Detected 12 CPU threads Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F6E73CF PciERWORegInit() Start PciERWORegInit() End ThermalLockDown() Start ThermalLockdown() - ThermalBaseB = 00000004 ThermalBaseB not set!! BDX-DE MCP PMSYNC enable = 1 InstallPchThermalLevelsProtocol() ThermalLockDown() End Locking Down TCO PchInitBeforeBoot() End ConfigureXhciAtBoot() Start ConfigureXhciAtBoot() End Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F6D9797 [HECI-0] VID-DID: 8086-8C3A [SPS] Sending HMRFPO_LOCK to ME [HECI-0] Send msg: 80040007 [HECI-0] Got msg: 80180007 Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F6D9C3E [HECI-0] VID-DID: 8086-8C3A [SPS] Sending END_OF_POST to ME [HECI-0] Send msg: 80040007 [HECI-0] Got msg: 80040007 [SPS] Disabling Global Reset capability [SPS] Disabling ME functions: 0 (HECI-1) 1 (HECI-2) 2 (IDE-R) 3 (KT) FSP Notification Handler Returns : 0x00000000 ============= PEIM FSP is Completed ============= Returned from FspNotify(EnumInitPhaseReadyToBoot) TEST: Entering bs_sample_time TEST: Entering bs_payload_boot Jumping to boot code at 000fd258(7ed61000) CPU0: stack: 7eef4000 - 7eef5000, lowest used address 7eef4adc, stack used: 1316 bytes SeaBIOS (version rel-1.12.1-0-ga5cab58-dirty-20191207_141949-adlink2-Express-KL) BUILD: gcc: (coreboot toolchain v ) 8.3.0 binutils: (GNU Binutils) 2.32 Found mainboard Intel Camelback Mountain CRB Relocating init from 0x000e1d20 to 0x7ecef560 (size 51712) Found CBFS header at 0xffa00238 multiboot: eax=7eed3ac0, ebx=7eed3a74 Found 23 PCI devices (max PCI bus is 04) Copying SMBIOS entry point from 0x7ed3c000 to 0x000f6280 Copying ACPI RSDP from 0x7ed3d000 to 0x000f6250 Using pmtimer, ioport 0x408 Scan for VGA option rom Turning on vga text mode console SeaBIOS (version rel-1.12.1-0-ga5cab58-dirty-20191207_141949-adlink2-Express-KL) XHCI init on dev 00:14.0: regs @ 0xfb900000, 21 ports, 32 slots, 32 byte contexts XHCI protocol USB 2.00, 8 ports (offset 1), def 3001 XHCI protocol USB 3.00, 6 ports (offset 16), def 1000 XHCI extcap 0xc1 @ 0xfb908040 XHCI extcap 0xc0 @ 0xfb908070 XHCI extcap 0x1 @ 0xfb90846c EHCI init on dev 00:1d.0 (regs=0xfb914020) WARNING - Timeout at i8042_flush:71! AHCI controller at 00:1f.2, iobase 0xfb913000, irq 5 Found 0 lpt ports Found 1 serial ports Searching bootorder for: /rom@img/uefi XHCI no devices found USB keyboard initialized WARNING - Timeout at ehci_wait_td:517! ehci pipe=0x7ecec300 cur=7ecd0dc0 tok=00000c00 next=7ecced40 td=0x7ecced40 status=80e80 WARNING - Timeout at ehci_waittick:178! Failure on hub port 3 detect WARNING - Timeout at ehci_wait_td:517! ehci pipe=0x7ecec300 cur=7ecd0dc0 tok=00000000 next=7eccfd40 td=0x7eccfd40 status=80e80 WARNING - Timeout at ehci_waittick:165! Failure on hub port 2 detect WARNING - Timeout at ehci_wait_td:517! ehci pipe=0x7ecec300 cur=7ecd0dc0 tok=00000000 next=7ecd0d40 td=0x7ecd0d40 status=80e80 WARNING - Timeout at ehci_waittick:165! Failure on hub port 1 detect Initialized USB HUB (1 ports used) WARNING - Timeout at ehci_waittick:165! All threads complete. Scan for option roms Press ESC for boot menu. Searching bootorder for: HALT Space available for UMB: c0000-ed000, f5aa0-f6230 Returned 188416 bytes of ZoneHigh e820 map has 10 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 000000007ed2a000 = 1 RAM 4: 000000007ed2a000 - 0000000090000000 = 2 RESERVED 5: 00000000fbffc000 - 00000000fbffe000 = 2 RESERVED 6: 00000000feb00000 - 00000000feb10000 = 2 RESERVED 7: 00000000feb80000 - 00000000fee00000 = 2 RESERVED 8: 00000000fef00000 - 0000000100000000 = 2 RESERVED 9: 0000000100000000 - 0000000180000000 = 1 RAM enter handle_19: NULL Booting from CBFS... Run img/uefi Calling addr 0x00800910 Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x00000800000, size is 0x00030000, handle is 0x800000 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389 DiscoverPeimsAndOrderWithApriori(): Found 0x5 PEI FFS files in the 0th FV Loading PEIM 9B3ADA4F-AE56-4C24-8DEA-F03B7558AE50 Loading PEIM at 0x0000080CC40 EntryPoint=0x0000080FEE3 PcdPeim.efi Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480 Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1 Install PPI: 4D8B155B-C059-4C8F-8926-06FD4331DB8A Install PPI: A60C6B59-E459-425D-9C69-0BCC9CB27D81 Register PPI Notify: 605EA650-C65C-42E1-BA80-91A52AB618C6 Loading PEIM A3610442-E69F-4DF3-82CA-2360C4031A23 Loading PEIM at 0x00000811AC0 EntryPoint=0x000008131A4 ReportStatusCodeRouterPei.efi Install PPI: 0065D394-9951-4144-82A3-0AFC8579C251 Install PPI: 229832D3-7A30-4B36-B827-F40CB7D45436 Loading PEIM 9D225237-FA01-464C-A949-BAABC02D31D0 Loading PEIM at 0x000008141C0 EntryPoint=0x00000815A22 StatusCodeHandlerPei.efi PROGRESS CODE: V03020003 I0 Loading PEIM 352C6AF8-315B-4BD6-B04F-31D4ED1EBE57 Loading PEIM at 0x000008169C0 EntryPoint=0x0000081AC91 BlSupportPeim.efi PROGRESS CODE: V03020002 I0 0. 0000000000000000 - 0000000000000FFF [10] 1. 0000000000001000 - 000000000009FFFF [01] 2. 00000000000A0000 - 00000000000FFFFF [02] 3. 0000000000100000 - 000000007ED3BFFF [01] 4. 000000007ED3C000 - 000000007EFFFFFF [10] 5. 000000007F000000 - 000000008FFFFFFF [02] 6. 00000000FBFFC000 - 00000000FBFFDFFF [02] 7. 00000000FEB00000 - 00000000FEB0FFFF [02] 8. 00000000FEB80000 - 00000000FEDFFFFF [02] 9. 00000000FEF00000 - 00000000FFFFFFFF [02] 10. 0000000100000000 - 000000017FFFFFFF [01] Low memory 0x7ED3C000 SystemLowMemTop 0x90000000 PeiMemBase: 0x7AD30000. PeiMemSize: 0x4000000. PeiInstallPeiMemory MemoryBegin 0x7AD30000, MemoryLength 0x4000000 Found one valid fv : 0x3E000000830000. Install PPI: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Notify: PPI Guid: 49EDB1C1-BF21-4761-BB12-EB0031AABB39, Peim notify entry point: 806425 The 1th FV start address is 0x00000830000, size is 0x003E0000, handle is 0x830000 Install PPI: 7408D748-FC8C-4EE6-9288-C4BEC092A410 Find CbMemTable Id 0x534D4254, base 7ED3C000, size 0x800 Find CbMemTable Id 0x41435049, base 7ED3D000, size 0x24000 Detected Acpi Table at 0x7ED3D000, length 0x24000 Detected Smbios Table at 0x7ED3C000, length 0x800 Rsdp at 0x7ED3D000 Rsdt at 0x7ED3D030, Xsdt at 0x7ED3D0E0 Found Fadt in Rsdt Found MM config address in Rsdt PmCtrl Reg 0x404 PmTimer Reg 0x408 Reset Reg 0xCF9 Reset Value 0x6 PmEvt Reg 0x400 PmGpeEn Reg 0x424 PcieBaseAddr 0x80000000 Create acpi board info guid hob PROGRESS CODE: V03020003 I0 Temp Stack : BaseAddress=0x88000 Length=0x8000 Temp Heap : BaseAddress=0x80000 Length=0x8000 Total temporary memory: 65536 bytes. temporary memory stack ever used: 32768 bytes. temporary memory heap used for HobList: 3024 bytes. temporary memory heap occupied by memory pages: 0 bytes. Memory Allocation 0x00000004 0x800000 - 0xC0FFFF Memory Allocation 0x0000000B 0xFEC80000 - 0xFECFFFFF Old Stack size 32768, New stack size 131072 Stack Hob: BaseAddress=0x7AD30000 Length=0x20000 Heap Offset = 0x7ACD0000 Stack Offset = 0x7ACC0000 Loading PEIM 52C05B14-0B98-496C-BC3B-04B50211D680 Loading PEIM at 0x0007ED24000 EntryPoint=0x0007ED2BE6A PeiCore.efi Reinstall PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Reinstall PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A Reinstall PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: F894643D-C449-42D1-8EA8-85BDD8C65BDE Loading PEIM 86D70125-BAA3-4296-A62F-602BEBBB9081 Loading PEIM at 0x0007ED1E000 EntryPoint=0x0007ED22180 DxeIpl.efi PROGRESS CODE: V03020002 I0 PROGRESS CODE: V03020003 I0 Install PPI: 1A36E4E7-FAB6-476A-8E75-695A0576FDD7 Install PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731 DiscoverPeimsAndOrderWithApriori(): Found 0x0 PEI FFS files in the 1th FV DXE IPL Entry Loading PEIM D6A2CB7F-6A18-4E2F-B43B-9920A733700A Loading PEIM at 0x0007ECF5000 EntryPoint=0x0007ECF848A DxeCore.efi PROGRESS CODE: V03021001 I0 Loading DXE CORE at 0x0007ECF5000 EntryPoint=0x0007ECF848A AddressBits=46 5LevelPaging=0 1GPage=1 Pml5=1 Pml4=128 Pdp=512 TotalPage=129 Install PPI: 605EA650-C65C-42E1-BA80-91A52AB618C6 Notify: PPI Guid: 605EA650-C65C-42E1-BA80-91A52AB618C6, Peim notify entry point: 80EFF3 HandOffToDxeCore() Stack Base: 0x7ECD5000, Stack Size: 0x20000 CoreInitializeMemoryServices: BaseAddress - 0x7AD52000 Length - 0x3CAD000 MinimalMemorySizeNeeded - 0x160000 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7ED1A2E8 ProtectUefiImageCommon - 0x7ED1A2E8 - 0x000000007ECF5000 - 0x0000000000029000 HOBLIST address in DXE = 0x7E8AA018 Memory Allocation 0x00000004 0x800000 - 0xC0FFFF Memory Allocation 0x0000000B 0xFEC80000 - 0xFECFFFFF Memory Allocation 0x00000004 0x7ECD5000 - 0x7ECF4FFF Memory Allocation 0x00000003 0x7ED24000 - 0x7ED2FFFF Memory Allocation 0x00000003 0x7ED1E000 - 0x7ED23FFF Memory Allocation 0x00000003 0x7ECF5000 - 0x7ED1DFFF Memory Allocation 0x00000003 0x7ECF5000 - 0x7ED1DFFF Memory Allocation 0x00000004 0x7ECD5000 - 0x7ECF4FFF Memory Allocation 0x00000004 0x7EA00000 - 0x7EBFFFFF Memory Allocation 0x00000007 0x7EC00000 - 0x7ECD4FFF Memory Allocation 0x00000004 0x7AD30000 - 0x7AD4FFFF Memory Allocation 0x00000004 0x7E9FF000 - 0x7E9FFFFF FV Hob 0x830000 - 0xC0FFFF InstallProtocolInterface: D8117CFE-94A6-11D4-9A3A-0090273FC14D 7ED1A8D0 InstallProtocolInterface: 8F644FA9-E850-4DB1-9CE2-0B44698E8DA4 7E8A67B0 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E8A6A98 InstallProtocolInterface: 220E73B6-6BDB-4413-8405-B974B108619A 7E8A6230 InstallProtocolInterface: EE4E5898-3914-4259-9D6E-DC7BD79403CF 7ED1A570 Loading driver 80CF7257-87AB-47F9-A3FE-D50B76D89541 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E6CD140 Loading driver at 0x0007E6A0000 EntryPoint=0x0007E6A5539 PcdDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E6CD418 ProtectUefiImageCommon - 0x7E6CD140 - 0x000000007E6A0000 - 0x0000000000007A00 InstallProtocolInterface: 11B34006-D85B-4D0A-A290-D5A571310EF7 7E6A74C0 InstallProtocolInterface: 13A3F0F6-264A-3EF0-F2E0-DEC512342F34 7E6A7420 InstallProtocolInterface: 5BE40F57-FA68-4610-BBBF-E9C5FCDAD365 7E6A73E0 InstallProtocolInterface: FD0F4478-0EFD-461D-BA2D-E58C45FD5F5E 7E6A73C0 Loading driver D93CE3D8-A7EB-4730-8C8E-CC466A9ECC3C InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E6AF340 !!!!!!!! InsertImageRecord - Section Alignment(0x40) is not 4K !!!!!!!! !!!!!!!! Image - /home/adlink2/src/edk2/Build/UefiPayloadPkgX64/DEBUG_GCC5/X64/MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe/DEBUG/ReportStatusCodeRouterRuntimeDxe.dll !!!!!!!! Loading driver at 0x0007E92A000 EntryPoint=0x0007E92C448 ReportStatusCodeRouterRuntimeDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E6AF098 ProtectUefiImageCommon - 0x7E6AF340 - 0x000000007E92A000 - 0x0000000000003BC0 InstallProtocolInterface: 86212936-0E76-41C8-A03A-2AF2FC1C39E2 7E92D860 InstallProtocolInterface: D2B2B828-0826-48A7-B3DF-983C006024F0 7E92D840 Loading driver 6C2004EF-4E0E-4BE4-B14C-340EB4AA5891 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E6AE0C0 !!!!!!!! InsertImageRecord - Section Alignment(0x40) is not 4K !!!!!!!! !!!!!!!! Image - /home/adlink2/src/edk2/Build/UefiPayloadPkgX64/DEBUG_GCC5/X64/MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe/DEBUG/StatusCodeHandlerRuntimeDxe.dll !!!!!!!! Loading driver at 0x0007E926000 EntryPoint=0x0007E927F59 StatusCodeHandlerRuntimeDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E6AE318 ProtectUefiImageCommon - 0x7E6AE0C0 - 0x000000007E926000 - 0x0000000000003400 PROGRESS CODE: V03040003 I0 Loading driver F80697E9-7FD6-4665-8646-88E33EF71DFC InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E6AB040 Loading driver at 0x0007E690000 EntryPoint=0x0007E694771 SecurityStubDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E6ABD18 ProtectUefiImageCommon - 0x7E6AB040 - 0x000000007E690000 - 0x00000000000077C0 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 94AB2F58-1438-4EF1-9152-18941A3A0E68 7E6970A8 InstallProtocolInterface: A46423E3-4617-49F1-B9FF-D1BFA9115839 7E6970A0 InstallProtocolInterface: 15853D7C-3DDF-43E0-A1CB-EBF85B8F872C 7E697080 PROGRESS CODE: V03040003 I0 Loading driver 1A1E4886-9517-440E-9FDE-3BE44CEE2136 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E6AB540 Loading driver at 0x0007E670000 EntryPoint=0x0007E67A34C CpuDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E6AB898 ProtectUefiImageCommon - 0x7E6AB540 - 0x000000007E670000 - 0x000000000000F8C0 PROGRESS CODE: V03040002 I0 Paging: added 512 pages to page table pool CurrentPagingContext: MachineType - 0x8664 PageTableBase - 0x7EA01000 Attributes - 0xC0000006 InstallProtocolInterface: 26BACCB1-6F42-11D4-BCE7-0080C73C8881 7E67F360 MemoryProtectionCpuArchProtocolNotify: ProtectUefiImageCommon - 0x7ED1A2E8 - 0x000000007ECF5000 - 0x0000000000029000 ProtectUefiImageCommon - 0x7E6CD140 - 0x000000007E6A0000 - 0x0000000000007A00 ProtectUefiImageCommon - 0x7E6AF340 - 0x000000007E92A000 - 0x0000000000003BC0 ProtectUefiImageCommon - 0x7E6AE0C0 - 0x000000007E926000 - 0x0000000000003400 ProtectUefiImageCommon - 0x7E6AB040 - 0x000000007E690000 - 0x00000000000077C0 ProtectUefiImageCommon - 0x7E6AB540 - 0x000000007E670000 - 0x000000000000F8C0 ConvertPages: failed to find range 0 - 9FFFF ConvertPages: failed to find range A0000 - BFFFF ConvertPages: failed to find range C0000 - DFFFF ConvertPages: failed to find range E0000 - FFFFF ConvertPages: failed to find range 7ED3C000 - 7F7FFFFF ConvertPages: failed to find range 7F800000 - 8FFFFFFF ConvertPages: failed to find range FBFFC000 - FBFFDFFF ConvertPages: failed to find range FEB00000 - FEB0FFFF ConvertPages: failed to find range FEB80000 - FEC7FFFF ConvertPages: failed to find range FEC80000 - FECFFFFF ConvertPages: failed to find range FED00000 - FEDFFFFF ConvertPages: failed to find range FEF00000 - FFFFFFFF ConvertPages: failed to find range 100000000 - 17FFFFFFF AP Loop Mode is 1 WakeupBufferStart = 87000, WakeupBufferSize = 239 CpuDxe: 5-Level Paging = 0 APIC MODE is 1 MpInitLib: Find 12 processors in system. Detect CPU count: 12 Does not find any HOB stored CPU BIST information! InstallProtocolInterface: 3FDDA605-A76E-4F46-AD29-12F4531B3D08 7E67F300 PROGRESS CODE: V03040003 I0 Loading driver C8339973-A563-4561-B858-D8476F9DEFC4 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E6981C0 Loading driver at 0x0007E688000 EntryPoint=0x0007E689A3D Metronome.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E698498 ProtectUefiImageCommon - 0x7E6981C0 - 0x000000007E688000 - 0x0000000000002BC0 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 26BACCB2-6F42-11D4-BCE7-0080C73C8881 7E68A890 PROGRESS CODE: V03040003 I0 Loading driver B601F8C4-43B7-4784-95B1-F4226CB40CEE InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E68F0C0 !!!!!!!! InsertImageRecord - Section Alignment(0x40) is not 4K !!!!!!!! !!!!!!!! Image - /home/adlink2/src/edk2/Build/UefiPayloadPkgX64/DEBUG_GCC5/X64/MdeModulePkg/Core/RuntimeDxe/RuntimeDxe/DEBUG/RuntimeDxe.dll !!!!!!!! Loading driver at 0x0007E922000 EntryPoint=0x0007E92416A RuntimeDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E68F418 ProtectUefiImageCommon - 0x7E68F0C0 - 0x000000007E922000 - 0x0000000000003AC0 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: B7DFB4E1-052F-449F-87BE-9818FC91B733 7E925760 PROGRESS CODE: V03040003 I0 Loading driver 4B28E4C7-FF36-4E10-93CF-A82159E777C5 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E68D040 !!!!!!!! InsertImageRecord - Section Alignment(0x40) is not 4K !!!!!!!! !!!!!!!! Image - /home/adlink2/src/edk2/Build/UefiPayloadPkgX64/DEBUG_GCC5/X64/MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe/DEBUG/ResetSystemRuntimeDxe.dll !!!!!!!! Loading driver at 0x0007E91D000 EntryPoint=0x0007E91F53F ResetSystemRuntimeDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E68FA18 ProtectUefiImageCommon - 0x7E68D040 - 0x000000007E91D000 - 0x0000000000004100 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 27CFAC88-46CC-11D4-9A38-0090273FC14D 0 InstallProtocolInterface: 9DA34AE0-EAF9-4BBF-8EC3-FD60226C44BE 7E920D08 InstallProtocolInterface: 695D7835-8D47-4C11-AB22-FA8ACCE7AE7A 7E920D48 InstallProtocolInterface: 2DF6BA0B-7092-440D-BD04-FB091EC3F3C1 7E920CC8 PROGRESS CODE: V03040003 I0 Loading driver CBD2E4D5-7068-4FF5-B462-9822B4AD8D60 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E68D440 !!!!!!!! InsertImageRecord - Section Alignment(0x40) is not 4K !!!!!!!! !!!!!!!! Image - /home/adlink2/src/edk2/Build/UefiPayloadPkgX64/DEBUG_GCC5/X64/MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe/DEBUG/VariableRuntimeDxe.dll !!!!!!!! Loading driver at 0x0007E911000 EntryPoint=0x0007E9191EE VariableRuntimeDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E68D798 ProtectUefiImageCommon - 0x7E68D440 - 0x000000007E911000 - 0x000000000000BB40 PROGRESS CODE: V03040002 I0 Variable driver will work at emulated non-volatile variable mode! Variable driver will work with auth variable format! InstallProtocolInterface: CD3D0A05-9E24-437C-A891-1EE053DB7638 7E91C640 InstallProtocolInterface: AF23B340-97B4-4685-8D4F-A3F28169B21D 7E91C420 InstallProtocolInterface: 1E5668E2-8481-11D4-BCF1-0080C73C8881 0 NOTICE - AuthVariableLibInitialize() returns Unsupported! Variable driver will continue to work without auth variable support! [Variable] Lock: BB983CCF-151D-40E1-A07B-4A17BE168292:MemoryOverwriteRequestControlLock Success [Variable] Lock: E20939BE-32D4-41BE-A150-897F85D49829:MemoryOverwriteRequestControl Success RecordSecureBootPolicyVarData GetVariable SecureBoot Status E InstallProtocolInterface: 6441F818-6362-4E44-B570-7DBA31DD2453 0 PROGRESS CODE: V03040003 I0 Loading driver A19B1FE7-C1BC-49F8-875F-54A5D542443F InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E68C140 Loading driver at 0x0007E682000 EntryPoint=0x0007E683EF2 CpuIo2Dxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E68C698 ProtectUefiImageCommon - 0x7E68C140 - 0x000000007E682000 - 0x0000000000002E80 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: AD61F191-AE5F-4C0E-B9FA-E869D288C64F 7E684BC0 PROGRESS CODE: V03040003 I0 Loading driver 9B680FCE-AD6B-4F3A-B60B-F59899003443 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E68BB40 Loading driver at 0x0007E656000 EntryPoint=0x0007E65ED45 DevicePathDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E68BE98 ProtectUefiImageCommon - 0x7E68BB40 - 0x000000007E656000 - 0x000000000000C580 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 0379BE4E-D706-437D-B037-EDB82FB772A4 7E6620C0 InstallProtocolInterface: 8B843E20-8132-4852-90CC-551A4E4A7F1C 7E6620A0 InstallProtocolInterface: 05C99A21-C70F-4AD2-8A5F-35DF3343F51E 7E662080 PROGRESS CODE: V03040003 I0 Loading driver 96B5C032-DF4C-4B6E-8232-438DCF448D0E InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E68B1C0 Loading driver at 0x0007E66D000 EntryPoint=0x0007E66EA9B NullMemoryTestDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E68B518 ProtectUefiImageCommon - 0x7E68B1C0 - 0x000000007E66D000 - 0x0000000000002C80 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 309DE7F1-7F5E-4ACE-B49C-531BE5AA95EF 7E66F940 PROGRESS CODE: V03040003 I0 Loading driver 348C4D62-BFBD-4882-9ECE-C80BB1C4783B InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E6810C0 Loading driver at 0x0007E614000 EntryPoint=0x0007E616FA5 HiiDatabase.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E681B18 ProtectUefiImageCommon - 0x7E6810C0 - 0x000000007E614000 - 0x0000000000020600 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: E9CA4775-8657-47FC-97E7-7ED65A084324 7E634128 InstallProtocolInterface: 0FD96974-23AA-4CDC-B9CB-98D17750322A 7E6341A0 InstallProtocolInterface: EF9FC172-A1B2-4693-B327-6D32FC416042 7E6341C8 InstallProtocolInterface: 587E72D7-CC50-4F79-8209-CA291FC1A10F 7E634220 InstallProtocolInterface: 0A8BADD5-03B8-4D19-B128-7B8F0EDAA596 7E634250 InstallProtocolInterface: 31A6406A-6BDF-4E46-B2A2-EBAA89C40920 7E634148 InstallProtocolInterface: 1A1241E6-8F19-41A9-BC0E-E8EF39E06546 7E634170 PROGRESS CODE: V03040003 I0 Loading driver C68DAA4E-7AB5-41E8-A91D-5954421053F3 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E6870C0 Loading driver at 0x0007E667000 EntryPoint=0x0007E668964 BlSupportDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E687A18 ProtectUefiImageCommon - 0x7E6870C0 - 0x000000007E667000 - 0x0000000000002D80 PROGRESS CODE: V03040002 I0 Install Acpi Table at 0x7ED3D000, length 0x24000 Install Smbios Table at 0x7ED3C000, length 0x800 PROGRESS CODE: V03040003 I0 Loading driver F9D88642-0737-49BC-81B5-6889CD57D9EA InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E6873C0 Loading driver at 0x0007E64C000 EntryPoint=0x0007E64F063 SmbiosDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E687718 ProtectUefiImageCommon - 0x7E6873C0 - 0x000000007E64C000 - 0x0000000000004A80 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 03583FF6-CB36-4940-947E-B9B39F4AFAF7 7E6508D0 PROGRESS CODE: V03040003 I0 Loading driver 9A5163E7-5C29-453F-825C-837A46A81E15 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E6860C0 Loading driver at 0x0007E664000 EntryPoint=0x0007E666148 SerialDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E686B18 ProtectUefiImageCommon - 0x7E6860C0 - 0x000000007E664000 - 0x0000000000002F40 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: BB25CF6F-F1D4-11D2-9A0C-0090273FC1FD 7E666B80 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E666C00 PROGRESS CODE: V03040003 I0 Loading driver 6D33944A-EC75-4855-A54D-809C75241F6C InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E686440 Loading driver at 0x0007E1CB000 EntryPoint=0x0007E1D0489 BdsDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E685B18 ProtectUefiImageCommon - 0x7E686440 - 0x000000007E1CB000 - 0x0000000000017080 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 665E3FF6-46CC-11D4-9A38-0090273FC14D 7E1E14A0 PROGRESS CODE: V03040003 I0 Loading driver 6CE6B0DE-781C-4F6C-B42D-98346C614BEC InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E6857C0 Loading driver at 0x0007E647000 EntryPoint=0x0007E649506 HpetTimerDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E685598 ProtectUefiImageCommon - 0x7E6857C0 - 0x000000007E647000 - 0x00000000000045C0 PROGRESS CODE: V03040002 I0 Init HPET Timer Driver HPET Base Address = 0xFED00000 HPET_GENERAL_CAPABILITIES_ID = 0x0429B17F8086A701 HPET_GENERAL_CONFIGURATION = 0x0000000000000000 HPET_GENERAL_INTERRUPT_STATUS = 0x0000000000000000 HPET_MAIN_COUNTER = 0x000000002D08DC5F HPET Main Counter Period = 69841279 (fs) HPET_TIMER0_CONFIGURATION = 0x00F0000000008030 HPET_TIMER0_COMPARATOR = 0x0000000000000000 HPET_TIMER0_MSI_ROUTE = 0x0000000000000000 HPET_TIMER1_CONFIGURATION = 0x00F0000000008000 HPET_TIMER1_COMPARATOR = 0x00000000FFFFFFFF HPET_TIMER1_MSI_ROUTE = 0x0000000000000000 HPET_TIMER2_CONFIGURATION = 0x00F0080000008000 HPET_TIMER2_COMPARATOR = 0x000000007F0FFE38 HPET_TIMER2_MSI_ROUTE = 0x0000000000000000 HPET_TIMER3_CONFIGURATION = 0x00F0100000008000 HPET_TIMER3_COMPARATOR = 0x00000000FFFFFFFF HPET_TIMER3_MSI_ROUTE = 0x0000000000000000 HPET_TIMER4_CONFIGURATION = 0x000000000000C000 HPET_TIMER4_COMPARATOR = 0x00000000FFFFFFFF HPET_TIMER4_MSI_ROUTE = 0x0000000000000000 HPET_TIMER5_CONFIGURATION = 0x000000000000C000 HPET_TIMER5_COMPARATOR = 0x00000000FFFFFFFF HPET_TIMER5_MSI_ROUTE = 0x0000000000000000 HPET_TIMER6_CONFIGURATION = 0x000000000000C000 HPET_TIMER6_COMPARATOR = 0x00000000FFFFFFFF HPET_TIMER6_MSI_ROUTE = 0x0000000000000000 HPET_TIMER7_CONFIGURATION = 0x000000000000C000 HPET_TIMER7_COMPARATOR = 0x00000000FFFFFFFF HPET_TIMER7_MSI_ROUTE = 0x0000000000000000 Choose 64-bit HPET timer. HPET Interrupt Mode MSI HPET Interrupt Vector = 0x40 HPET Counter Mask = 0xFFFFFFFFFFFFFFFF HPET Timer Period = 100000 HPET Timer Count = 0x0000000000022F4D HPET_TIMER0_CONFIGURATION = 0x00F000000000C034 HPET_TIMER0_COMPARATOR = 0x000000002D0F6A47 HPET_TIMER0_MSI_ROUTE = 0xFEE0000000000140 InstallProtocolInterface: 26BACCB3-6F42-11D4-BCE7-0080C73C8881 7E64B220 PROGRESS CODE: V03040003 I0 Loading driver 42857F0A-13F2-4B21-8A23-53D3F714B840 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E680040 !!!!!!!! InsertImageRecord - Section Alignment(0x40) is not 4K !!!!!!!! !!!!!!!! Image - /home/adlink2/src/edk2/Build/UefiPayloadPkgX64/DEBUG_GCC5/X64/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe/DEBUG/CapsuleRuntimeDxe.dll !!!!!!!! Loading driver at 0x0007E90E000 EntryPoint=0x0007E90FA1D CapsuleRuntimeDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E680D18 ProtectUefiImageCommon - 0x7E680040 - 0x000000007E90E000 - 0x0000000000002C00 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 5053697E-2CBC-4819-90D9-0580DEEE5754 0 PROGRESS CODE: V03040003 I0 Loading driver AD608272-D07F-4964-801E-7BD3B7888652 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E680440 !!!!!!!! InsertImageRecord - Section Alignment(0x40) is not 4K !!!!!!!! !!!!!!!! Image - /home/adlink2/src/edk2/Build/UefiPayloadPkgX64/DEBUG_GCC5/X64/MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe/DEBUG/MonotonicCounterRuntimeDxe.dll !!!!!!!! Loading driver at 0x0007E90B000 EntryPoint=0x0007E90C7F1 MonotonicCounterRuntimeDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E680998 ProtectUefiImageCommon - 0x7E680440 - 0x000000007E90B000 - 0x0000000000002B00 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 1DA97072-BDDC-4B30-99F1-72A0B56FFF2A 0 PROGRESS CODE: V03040003 I0 Loading driver 378D7B65-8DA9-4773-B6E4-A47826A833E1 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E66CCC0 !!!!!!!! InsertImageRecord - Section Alignment(0x40) is not 4K !!!!!!!! !!!!!!!! Image - /home/adlink2/src/edk2/Build/UefiPayloadPkgX64/DEBUG_GCC5/X64/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe/DEBUG/PcRtc.dll !!!!!!!! Loading driver at 0x0007E906000 EntryPoint=0x0007E909073 PcRtc.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E66C818 ProtectUefiImageCommon - 0x7E66CCC0 - 0x000000007E906000 - 0x0000000000004E40 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 27CFAC87-46CC-11D4-9A38-0090273FC14D 0 PROGRESS CODE: V03040003 I0 Loading driver EBF342FE-B1D3-4EF8-957C-8048606FF671 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E66B040 Loading driver at 0x0007E193000 EntryPoint=0x0007E1954F7 SetupBrowser.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E66BD18 ProtectUefiImageCommon - 0x7E66B040 - 0x000000007E193000 - 0x000000000001B080 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: B9D4C360-BCFB-4F9B-9298-53C136982258 7E1ADA10 InstallProtocolInterface: A770C357-B693-4E6D-A6CF-D21C728E550B 7E1ADA40 InstallProtocolInterface: 1F73B18D-4630-43C1-A1DE-6F80855D7DA4 7E1ADA20 PROGRESS CODE: V03040003 I0 Loading driver 128FB770-5E79-4176-9E51-9BB268A17DD1 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E66B5C0 Loading driver at 0x0007E606000 EntryPoint=0x0007E60DCC6 PciHostBridgeDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E66AF98 ProtectUefiImageCommon - 0x7E66B5C0 - 0x000000007E606000 - 0x000000000000D5C0 PROGRESS CODE: V03040002 I0 InitRootBridge: populated root bus 0, with room for 4 subordinate bus(es) RootBridge: PciRoot(0x0) Support/Attr: 1001F / 1001F DmaAbove4G: No NoExtConfSpace: No AllocAttr: 0 () Bus: 0 - 4 Translation=0 Io: 1000 - 2FFF Translation=0 Mem: F0000000 - FB9FFFFF Translation=0 MemAbove4G: FFFFFFFFFFFFFFFF - 0 Translation=0 PMem: FFFFFFFFFFFFFFFF - 0 Translation=0 PMemAbove4G: FFFFFFFFFFFFFFFF - 0 Translation=0 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E66A798 InstallProtocolInterface: 2F707EBB-4A1A-11D4-9A38-0090273FC14D 7E66A2F0 PROGRESS CODE: V03040003 I0 Loading driver A487A478-51EF-48AA-8794-7BEE2A0562F1 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E663040 Loading driver at 0x0007E1EF000 EntryPoint=0x0007E1F666C tftpDynamicCommand.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E663598 InstallProtocolInterface: 6A1EE763-D47A-43B4-AABE-EF1DE2AB56FC 7E1F8CB0 ProtectUefiImageCommon - 0x7E663040 - 0x000000007E1EF000 - 0x000000000000B840 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 3C7200E9-005F-4EA4-87DE-A3DFAC8A27C3 7E1F8780 PROGRESS CODE: V03040003 I0 Loading driver 0253F9FA-129A-4A8D-B12E-7DC2B6376302 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E653040 Loading driver at 0x0007E1BA000 EntryPoint=0x0007E1C47FF dpDynamicCommand.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E663798 InstallProtocolInterface: 6A1EE763-D47A-43B4-AABE-EF1DE2AB56FC 7E1C8530 ProtectUefiImageCommon - 0x7E653040 - 0x000000007E1BA000 - 0x0000000000010A40 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 3C7200E9-005F-4EA4-87DE-A3DFAC8A27C3 7E1C7B20 PROGRESS CODE: V03040003 I0 Loading driver F099D67F-71AE-4C36-B2A3-DCEB0EB2B7D8 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E6534C0 Loading driver at 0x0007E63E000 EntryPoint=0x0007E63F7F8 WatchdogTimer.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E653818 ProtectUefiImageCommon - 0x7E6534C0 - 0x000000007E63E000 - 0x0000000000002880 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 665E3FF5-46CC-11D4-9A38-0090273FC14D 7E640530 PROGRESS CODE: V03040003 I0 Loading driver E660EA85-058E-4B55-A54B-F02F83A24707 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E6521C0 Loading driver at 0x0007E169000 EntryPoint=0x0007E178623 DisplayEngine.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E652B98 ProtectUefiImageCommon - 0x7E6521C0 - 0x000000007E169000 - 0x0000000000014500 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 9BBE29E9-FDA1-41EC-AD52-452213742D2E 7E17B790 InstallProtocolInterface: 4311EDC0-6054-46D4-9E40-893EA952FCCC 7E17B7A8 PROGRESS CODE: V03040003 I0 Loading driver 93B80004-9FB3-11D4-9A3A-0090273FC14D InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E641240 Loading driver at 0x0007E154000 EntryPoint=0x0007E164B8A PciBusDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E641598 ProtectUefiImageCommon - 0x7E641240 - 0x000000007E154000 - 0x0000000000014B00 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E1685E0 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E168440 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E168070 InstallProtocolInterface: 19CB87AB-2CB9-4665-8360-DDCF6054F79D 7E168050 PROGRESS CODE: V03040003 I0 Loading driver 51CCF399-4FDF-4E55-A45B-E123F84D456A InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E63B8C0 Loading driver at 0x0007E600000 EntryPoint=0x0007E6037AB ConPlatformDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E63B818 ProtectUefiImageCommon - 0x7E63B8C0 - 0x000000007E600000 - 0x00000000000052C0 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E604E40 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E604F60 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E604F40 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E604E00 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E604F60 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E604F40 PROGRESS CODE: V03040003 I0 Loading driver 408EDCEC-CF6D-477C-A5A8-B4844E3DE281 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E63AB40 Loading driver at 0x0007E1B0000 EntryPoint=0x0007E1B6A66 ConSplitterDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E63AE98 ProtectUefiImageCommon - 0x7E63AB40 - 0x000000007E1B0000 - 0x00000000000090C0 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E1B8660 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E1B8640 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E1B85D0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E1B86E0 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E1B86C0 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E1B85B0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E1B8760 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E1B8740 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E1B8590 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E1B87E0 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E1B87C0 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E1B8570 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E1B8860 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E1B8840 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E1B8550 InstallProtocolInterface: 387477C1-69C7-11D2-8E39-00A0C969723B 7E1B8930 InstallProtocolInterface: DD9E7534-7762-4698-8C14-F58517A625AA 7E1B8960 InstallProtocolInterface: 31878C87-0B75-11D5-9A4F-0090273FC14D 7E1B89D0 InstallProtocolInterface: 8D59D32B-C655-4AE9-9B15-F25904992A43 7E1B8A28 InstallProtocolInterface: 387477C2-69C7-11D2-8E39-00A0C969723B 7E1B8C30 InstallProtocolInterface: 387477C2-69C7-11D2-8E39-00A0C969723B 7E1B8AF0 PROGRESS CODE: V03040003 I0 Loading driver CCCB0C28-4B24-11D5-9A5A-0090273FC14D InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E637740 Loading driver at 0x0007E18C000 EntryPoint=0x0007E18FDC5 GraphicsConsoleDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E637A98 ProtectUefiImageCommon - 0x7E637740 - 0x000000007E18C000 - 0x0000000000006D80 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E191300 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E191360 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E1912E0 PROGRESS CODE: V03040003 I0 Loading driver 9E863906-A40F-4875-977F-5B93FF237FC6 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E6368C0 Loading driver at 0x0007E14A000 EntryPoint=0x0007E151133 TerminalDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E636818 ProtectUefiImageCommon - 0x7E6368C0 - 0x000000007E14A000 - 0x00000000000094C0 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E152CE0 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E152E90 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E152E70 PROGRESS CODE: V03040003 I0 Loading driver 0B04B2ED-861C-42CD-A22F-C3AAFACCB896 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E635040 Loading driver at 0x0007E186000 EntryPoint=0x0007E189C51 GraphicsOutputDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E636398 ProtectUefiImageCommon - 0x7E635040 - 0x000000007E186000 - 0x0000000000005880 PROGRESS CODE: V03040002 I0 Error: Image at 0007E186000 start failed: Not Found PROGRESS CODE: V03040003 I0 Loading driver 6B38F7B4-AD98-40E9-9093-ACA2B5A253C4 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E635040 Loading driver at 0x0007E186000 EntryPoint=0x0007E189DE3 DiskIoDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E636318 ProtectUefiImageCommon - 0x7E635040 - 0x000000007E186000 - 0x0000000000005880 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E18B460 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E18B4C0 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E18B430 PROGRESS CODE: V03040003 I0 Loading driver 1FA1F39E-FEFF-4AAE-BD7B-38A070A3B609 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E635440 Loading driver at 0x0007E142000 EntryPoint=0x0007E147F0C PartitionDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E635C18 ProtectUefiImageCommon - 0x7E635440 - 0x000000007E142000 - 0x0000000000007BC0 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E1497C0 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E149820 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E1497A0 PROGRESS CODE: V03040003 I0 Loading driver CD3BAFB6-50FB-4FE8-8E4E-AB74D2C1A600 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E1EEB40 Loading driver at 0x0007E1E6000 EntryPoint=0x0007E1E79A9 EnglishDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E635818 ProtectUefiImageCommon - 0x7E1EEB40 - 0x000000007E1E6000 - 0x0000000000002C80 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 1D85CD7F-F43D-11D2-9A0C-0090273FC14D 7E1E8660 InstallProtocolInterface: A4C751FC-23AE-4C3E-92E9-4964CF63F349 7E1E8600 PROGRESS CODE: V03040003 I0 Loading driver 820C59BB-274C-43B2-83EA-DAC673035A59 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E1EE240 Loading driver at 0x0007E13E000 EntryPoint=0x0007E1409B1 SataController.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E1EE598 ProtectUefiImageCommon - 0x7E1EE240 - 0x000000007E13E000 - 0x0000000000004000 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E141D00 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E141CE0 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E141C70 PROGRESS CODE: V03040003 I0 Loading driver 19DF145A-B1D4-453F-8507-38816676D7F6 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E1EDCC0 Loading driver at 0x0007E136000 EntryPoint=0x0007E13BC7B AtaBusDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E1ED118 ProtectUefiImageCommon - 0x7E1EDCC0 - 0x000000007E136000 - 0x0000000000007C80 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E13D920 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E13D8E0 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E13D660 PROGRESS CODE: V03040003 I0 Loading driver 5E523CB4-D397-4986-87BD-A6DD8B22F455 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E1ED340 Loading driver at 0x0007E11E000 EntryPoint=0x0007E12726A AtaAtapiPassThruDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E1ED718 ProtectUefiImageCommon - 0x7E1ED340 - 0x000000007E11E000 - 0x000000000000B900 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E1295C0 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E129580 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E129280 PROGRESS CODE: V03040003 I0 Loading driver 0167CCC4-D0F7-4F21-A3EF-9E64B7CDCE8B InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E1ECCC0 Loading driver at 0x0007E130000 EntryPoint=0x0007E1339FE ScsiBus.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E1EC898 ProtectUefiImageCommon - 0x7E1ECCC0 - 0x000000007E130000 - 0x0000000000005080 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E134CC0 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E134D20 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E134CA0 PROGRESS CODE: V03040003 I0 Loading driver 0A66E322-3740-4CCE-AD62-BD172CECCA35 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E1EC3C0 Loading driver at 0x0007E108000 EntryPoint=0x0007E1112ED ScsiDisk.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E1EC718 ProtectUefiImageCommon - 0x7E1EC3C0 - 0x000000007E108000 - 0x000000000000AF40 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E112B20 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E112BF0 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E112BD0 PROGRESS CODE: V03040003 I0 Loading driver 961578FE-B6B7-44C3-AF35-6BC705CD2B1F InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E1EB140 Loading driver at 0x0007E0F0000 EntryPoint=0x0007E0F9262 Fat.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E1EBD98 ProtectUefiImageCommon - 0x7E1EB140 - 0x000000007E0F0000 - 0x000000000000B580 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E0FB100 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E0FB0E0 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E0FB070 PROGRESS CODE: V03040003 I0 Loading driver 8E325979-3FE1-4927-AAE2-8F5C4BD2AF0D InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E1EB5C0 Loading driver at 0x0007E0E4000 EntryPoint=0x0007E0EC3D8 SdMmcPciHcDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E1E5F98 ProtectUefiImageCommon - 0x7E1EB5C0 - 0x000000007E0E4000 - 0x000000000000B180 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E0EEE40 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E0EEE00 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E0EEB70 PROGRESS CODE: V03040003 I0 Loading driver 2145F72F-E6F1-4440-A828-59DC9AAB5F89 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E1E5140 Loading driver at 0x0007E0FE000 EntryPoint=0x0007E104DDB EmmcDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E1E5398 ProtectUefiImageCommon - 0x7E1E5140 - 0x000000007E0FE000 - 0x0000000000009880 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E107360 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E1074E0 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E1074C0 PROGRESS CODE: V03040003 I0 Loading driver 430AC2F7-EEC6-4093-94F7-9F825A7C1C40 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E1E5540 Loading driver at 0x0007E117000 EntryPoint=0x0007E11BFE5 SdDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E1E4B18 ProtectUefiImageCommon - 0x7E1E5540 - 0x000000007E117000 - 0x0000000000006F00 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E11D9A0 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E11D9F0 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E11D9D0 PROGRESS CODE: V03040003 I0 Loading driver 2FB92EFA-2EE0-4BAE-9EB6-7464125E1EF7 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E1E47C0 Loading driver at 0x0007E0D2000 EntryPoint=0x0007E0D8C44 UhciDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E1E4D18 ProtectUefiImageCommon - 0x7E1E47C0 - 0x000000007E0D2000 - 0x0000000000008A80 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E0DA760 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E0DA720 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E0DA6B0 PROGRESS CODE: V03040003 I0 Loading driver BDFE430E-8F2A-4DB0-9991-6F856594777E InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E1E3040 Loading driver at 0x0007E0BC000 EntryPoint=0x0007E0C3E28 EhciDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E1E3D18 ProtectUefiImageCommon - 0x7E1E3040 - 0x000000007E0BC000 - 0x000000000000A4C0 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E0C6120 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E0C6170 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E0C6150 PROGRESS CODE: V03040003 I0 Loading driver B7F50E91-A759-412C-ADE4-DCD03E7F7C28 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E1E39C0 Loading driver at 0x0007E09E000 EntryPoint=0x0007E0A98C4 XhciDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E1E3898 ProtectUefiImageCommon - 0x7E1E39C0 - 0x000000007E09E000 - 0x000000000000ED00 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E0AC9A0 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E0AC960 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E0AC8F0 PROGRESS CODE: V03040003 I0 Loading driver 240612B7-A063-11D4-9A3A-0090273FC14D InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E185040 Loading driver at 0x0007E0B1000 EntryPoint=0x0007E0B9167 UsbBusDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E1E3598 ProtectUefiImageCommon - 0x7E185040 - 0x000000007E0B1000 - 0x000000000000AFC0 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E0BBC60 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E0BBC20 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E0BBAB0 PROGRESS CODE: V03040003 I0 Loading driver 2D2E62CF-9ECF-43B7-8219-94E7FC713DFE InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E185440 Loading driver at 0x0007E0CA000 EntryPoint=0x0007E0CF872 UsbKbDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E185698 ProtectUefiImageCommon - 0x7E185440 - 0x000000007E0CA000 - 0x0000000000007C40 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E0D1900 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E0D18C0 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E0D1840 PROGRESS CODE: V03040003 I0 Loading driver 9FB4B4A7-42C0-4BCD-8540-9BCC6711F83E InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7E184B40 Loading driver at 0x0007E097000 EntryPoint=0x0007E09BF05 UsbMassStorageDxe.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E185898 ProtectUefiImageCommon - 0x7E184B40 - 0x000000007E097000 - 0x0000000000006EC0 PROGRESS CODE: V03040002 I0 InstallProtocolInterface: 18A031AB-B443-4D1A-A5C0-0C09261E9F71 7E09DAC0 InstallProtocolInterface: 107A772C-D5E1-11D4-9A46-0090273FC14D 7E09DB20 InstallProtocolInterface: 6A7A5CFF-E8D9-4F70-BADA-75AB3025CE14 7E09DAA0 PROGRESS CODE: V03040003 I0 PROGRESS CODE: V03041001 I0 [Bds] Entry... [BdsDxe] Locate Variable Lock protocol - Success [Variable] Lock: 8BE4DF61-93CA-11D2-AA0D-00E098032B8C:PlatformLangCodes Success [Variable] Lock: 8BE4DF61-93CA-11D2-AA0D-00E098032B8C:LangCodes Success [Variable] Lock: 8BE4DF61-93CA-11D2-AA0D-00E098032B8C:BootOptionSupport Success [Variable] Lock: 8BE4DF61-93CA-11D2-AA0D-00E098032B8C:HwErrRecSupport Success [Variable] Lock: 8BE4DF61-93CA-11D2-AA0D-00E098032B8C:OsIndicationsSupported Success Variable Driver Auto Update Lang, Lang:eng, PlatformLang:en Status: Success [Variable] Lock: 8BE4DF61-93CA-11D2-AA0D-00E098032B8C:PlatformRecovery0000 Success PROGRESS CODE: V03051005 I0 PROGRESS CODE: V02010000 I0 PciBus: Discovered PCI @ [00|00|00] PciBus: Discovered PPB @ [00|01|00] PciBus: Discovered PPB @ [00|02|00] PciBus: Discovered PCI @ [02|00|00] BAR[0]: Type = Mem64; Alignment = 0x1FFF; Length = 0x2000; Offset = 0x10 PciBus: Discovered PCI @ [02|00|01] BAR[0]: Type = Mem64; Alignment = 0x1FFF; Length = 0x2000; Offset = 0x10 PciBus: Discovered PCI @ [02|00|02] BAR[0]: Type = Mem64; Alignment = 0x1FFF; Length = 0x2000; Offset = 0x10 PciBus: Discovered PCI @ [02|00|03] BAR[0]: Type = Mem64; Alignment = 0x1FFF; Length = 0x2000; Offset = 0x10 PciBus: Discovered PPB @ [00|02|02] PciBus: Discovered PCI @ [03|00|00] ARI: forwarding enabled for PPB[00:02:02] ARI: CapOffset = 0x150 SR-IOV: SupportedPageSize = 0x553; SystemPageSize = 0x1; FirstVFOffset = 0x80; InitialVFs = 0x40; ReservedBusNum = 0x1; CapOffset = 0x160 BAR[0]: Type = PMem64; Alignment = 0x1FFFFF; Length = 0x200000; Offset = 0x10 BAR[3]: Type = PMem64; Alignment = 0x3FFF; Length = 0x4000; Offset = 0x20 VFBAR[0]: Type = Mem64; Alignment = 0x3FFF; Length = 0x100000; Offset = 0x184 VFBAR[2]: Type = Mem64; Alignment = 0x3FFF; Length = 0x100000; Offset = 0x190 PciBus: Discovered PCI @ [03|00|01] ARI: CapOffset = 0x150 SR-IOV: SupportedPageSize = 0x553; SystemPageSize = 0x1; FirstVFOffset = 0x80; InitialVFs = 0x40; ReservedBusNum = 0x1; CapOffset = 0x160 BAR[0]: Type = PMem64; Alignment = 0x1FFFFF; Length = 0x200000; Offset = 0x10 BAR[3]: Type = PMem64; Alignment = 0x3FFF; Length = 0x4000; Offset = 0x20 VFBAR[0]: Type = Mem64; Alignment = 0x3FFF; Length = 0x100000; Offset = 0x184 VFBAR[2]: Type = Mem64; Alignment = 0x3FFF; Length = 0x100000; Offset = 0x190 PciBus: Discovered PPB @ [00|03|00] PciBus: Discovered PCI @ [04|00|00] BAR[0]: Type = Mem32; Alignment = 0xFFFFFF; Length = 0x1000000; Offset = 0x10 BAR[1]: Type = PMem64; Alignment = 0x7FFFFFF; Length = 0x8000000; Offset = 0x14 BAR[2]: Type = PMem64; Alignment = 0x1FFFFFF; Length = 0x2000000; Offset = 0x1C BAR[3]: Type = Io32; Alignment = 0x7F; Length = 0x80; Offset = 0x24 PciBus: Discovered PCI @ [04|00|01] BAR[0]: Type = Mem32; Alignment = 0x3FFF; Length = 0x4000; Offset = 0x10 PciBus: Discovered PCI @ [00|05|00] PciBus: Discovered PCI @ [00|05|01] PciBus: Discovered PCI @ [00|05|02] PciBus: Discovered PCI @ [00|05|04] BAR[0]: Type = Mem32; Alignment = 0xFFF; Length = 0x1000; Offset = 0x10 PciBus: Discovered PCI @ [00|14|00] BAR[0]: Type = Mem64; Alignment = 0xFFFF; Length = 0x10000; Offset = 0x10 PciBus: Discovered PCI @ [00|1D|00] BAR[0]: Type = Mem32; Alignment = 0xFFF; Length = 0x400; Offset = 0x10 PciBus: Discovered PCI @ [00|1F|00] PciBus: Discovered PCI @ [00|1F|02] BAR[0]: Type = Io16; Alignment = 0x7; Length = 0x8; Offset = 0x10 BAR[1]: Type = Io16; Alignment = 0x3; Length = 0x4; Offset = 0x14 BAR[2]: Type = Io16; Alignment = 0x7; Length = 0x8; Offset = 0x18 BAR[3]: Type = Io16; Alignment = 0x3; Length = 0x4; Offset = 0x1C BAR[4]: Type = Io16; Alignment = 0x1F; Length = 0x20; Offset = 0x20 BAR[5]: Type = Mem32; Alignment = 0xFFF; Length = 0x800; Offset = 0x24 PciBus: Discovered PCI @ [00|1F|03] BAR[0]: Type = Mem64; Alignment = 0xFFF; Length = 0x100; Offset = 0x10 BAR[3]: Type = Io16; Alignment = 0x1F; Length = 0x20; Offset = 0x20 PciBus: Discovered PCI @ [00|1F|06] BAR[0]: Type = Mem64; Alignment = 0xFFF; Length = 0x1000; Offset = 0x10 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E183F18 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E183428 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E183F98 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E183828 PROGRESS CODE: V02010004 I0 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E182E98 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E182028 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E182F18 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E182428 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E182F98 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E182828 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E181E98 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E181028 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E181F18 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E181428 PROGRESS CODE: V02010004 I0 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E181F98 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E181828 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E180E98 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E180028 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E180F18 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E180428 PROGRESS CODE: V02010004 I0 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E180F98 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E180828 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E17FE98 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E17F028 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E17FF18 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E17F428 PROGRESS CODE: V02010004 I0 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E17FF98 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E17F828 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E17EE98 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E17E028 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E17EF18 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E17E428 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E17EF98 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E17E828 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E12FE98 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E12F028 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E12FF18 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E12F428 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E12FF98 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E12F828 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E12EE98 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E12E028 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E12EF18 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E12E428 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E12EF98 InstallProtocolInterface: 4CF5B200-68B8-4CA5-9EEC-B23E3F50029A 7E12E828 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 Found PCI VGA device PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 Found LPC Bridge device PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 InstallReadyToLock entering...... [Variable]END_OF_DXE is signaled Initialize variable error flag (FF) All EndOfDxe callbacks have returned successfully InstallReadyToLock end [Bds]RegisterKeyNotify: 000C/0000 80000000/00 Success [Bds]RegisterKeyNotify: 0002/0000 80000000/00 Success [Bds]RegisterKeyNotify: 0000/000D 80000000/00 Success Terminal - Mode 0, Column = 80, Row = 25 Terminal - Mode 1, Column = 80, Row = 50 Terminal - Mode 2, Column = 100, Row = 31 PROGRESS CODE: V01040001 I0 InstallProtocolInterface: 387477C1-69C7-11D2-8E39-00A0C969723B 7E1167C0 InstallProtocolInterface: DD9E7534-7762-4698-8C14-F58517A625AA 7E1168A8 InstallProtocolInterface: 387477C2-69C7-11D2-8E39-00A0C969723B 7E1167D8 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E116D98 InstallProtocolInterface: D3B36F2C-D551-11D4-9A46-0090273FC14D 0 InstallProtocolInterface: D3B36F2D-D551-11D4-9A46-0090273FC14D 0 InstallProtocolInterface: D3B36F2B-D551-11D4-9A46-0090273FC14D 0 XhcCreateUsb3Hc: Capability length 0x80 XhcCreateUsb3Hc: HcSParams1 0x15000820 XhcCreateUsb3Hc: HcSParams2 0x84000054 XhcCreateUsb3Hc: HcCParams 0x200077C1 XhcCreateUsb3Hc: DBOff 0x3000 XhcCreateUsb3Hc: RTSOff 0x2000 XhcCreateUsb3Hc: UsbLegSupOffset 0x46C XhcCreateUsb3Hc: DebugCapSupOffset 0xFFFFFFFF XhcSetBiosOwnership: called to set BIOS ownership XhcResetHC! XhcInitSched:DCBAA=0x7E047000 XhcInitSched: Created CMD ring [7E047140~7E048140) EVENT ring [7E048140~7E04A140) InstallProtocolInterface: 3E745226-9818-45B6-A2AC-D7CD0E8BA2BC 7E057038 XhcDriverBindingStart: XHCI started for controller @ 7E12CC98 PROGRESS CODE: V02020000 I0 PROGRESS CODE: V02020004 I0 InstallProtocolInterface: 240612B7-A063-11D4-9A3A-0090273FC14D 7E0440A0 PROGRESS CODE: V02020003 I0 XhcGetCapability: 21 ports, 64 bit 1 UsbRootHubInit: root hub 7E043C18 - max speed 3, 21 ports UsbBusStart: usb bus started on 7E12CC98, root hub 7E043C18 EhcCreateUsb2Hc: capability length 32 InstallProtocolInterface: 3E745226-9818-45B6-A2AC-D7CD0E8BA2BC 7E0431A0 EhcDriverBindingStart: EHCI started for controller @ 7E12CA18 PROGRESS CODE: V02020000 I0 PROGRESS CODE: V02020004 I0 InstallProtocolInterface: 240612B7-A063-11D4-9A3A-0090273FC14D 7E02E020 PROGRESS CODE: V02020003 I0 EhcGetCapability: 2 ports, 64 bit 1 UsbRootHubInit: root hub 7E02EC98 - max speed 2, 2 ports UsbEnumeratePort: port 0 state - 101, change - 01 on 7E02EC98 UsbEnumeratePort: Device Connect/Disconnect Normally UsbEnumeratePort: new device connected at port 0 EhcSetRootHubPortFeature: exit status Success EhcClearRootHubPortFeature: exit status Success UsbEnumerateNewDev: hub port 0 is reset UsbEnumerateNewDev: device is of 2 speed UsbEnumerateNewDev: device uses translator (0, 0) UsbEnumerateNewDev: device is now ADDRESSED at 1 UsbEnumerateNewDev: max packet size for EP 0 is 64 UsbBuildDescTable: device has 1 configures UsbGetOneConfig: total length is 25 UsbParseConfigDesc: config 1 has 1 interfaces UsbParseInterfaceDesc: interface 0(setting 0) has 1 endpoints EhcExecTransfer: transfer failed with 2 EhcControlTransfer: error - Device Error, transfer - 2 UsbBuildDescTable: get language ID table Unsupported UsbEnumerateNewDev: device 1 is now in CONFIGED state UsbSelectConfig: config 1 selected for device 1 UsbSelectSetting: setting 0 selected for interface 0 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E02DC18 InstallProtocolInterface: 2B2F68D6-0CD2-44CF-8E8B-BBA20B1B5B75 7E02C040 UsbConnectDriver: found a hub device UsbHubInit: hub 1 has 4 ports UsbHubInit: hub 1 initialized PROGRESS CODE: V02020006 I0 EhcClearRootHubPortFeature: exit status Success UsbBusStart: usb bus started on 7E12CA18, root hub 7E02EC98 PROGRESS CODE: V02020000 I0 PROGRESS CODE: V02020000 I0 UsbBusRecursivelyConnectWantedUsbIo: TPL before connect is 4 UsbBusRecursivelyConnectWantedUsbIo: TPL after connect is 4 PROGRESS CODE: V02010000 I0 PROGRESS CODE: VUsbEnumeratePort: port 0 state - 101, change - 01 on 7E02C018 UsbEnumeratePort: Device Connect/Disconnect Normally UsbEnumeratePort: new device connected at port 0 UsbEnumerateNewDev: hub port 0 is reset UsbEnumerateNewDev: device is of 1 speed UsbEnumerateNewDev: device uses translator (1, 1) UsbEnumerateNewDev: device is now ADDRESSED at 2 UsbEnumerateNewDev: max packet size for EP 0 is 8 UsbBuildDescTable: device has 1 configures UsbGetOneConfig: total length is 34 UsbParseConfigDesc: config 1 has 1 interfaces UsbParseInterfaceDesc: interface 0(setting 0) has 1 endpoints UsbEnumerateNewDev: device 2 is now in CONFIGED state UsbSelectConfig: config 1 selected for device 2 UsbSelectSetting: setting 0 selected for interface 0 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7E12A618 InstallProtocolInterface: 2B2F68D6-0CD2-44CF-8E8B-BBA20B1B5B75 7E02C540 UsbConnectDriver: TPL before connect is 8, 7E02C698 InstallProtocolInterface: 387477C1-69C7-11D2-8E39-00A0C969723B 7E02A0B8 InstallProtocolInterface: DD9E7534-7762-4698-8C14-F58517A625AA 7E02A0D0 InstallProtocolInterface: D3B36F2B-D551-11D4-9A46-0090273FC14D 0 UsbConnectDriver: TPL after connect is 8 02010004 I0 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02010004 I0 PROGRESS CODE: V02020000 I0 PROGRESS CODE: V02020000 I0 UsbBusRecursivelyConnectWantedUsbIo: TPL before connect is 4 UsbBusRecursivelyConnectWantedUsbIo: TPL after connect is 4 SataControllerStart start Original PCI Attributes = 0x4700 Supported PCI Attributes = 0xE700 PROGRESS CODE: V02010004 I0 Enabled PCI Attributes = 0x700 Ports Implemented(PI) = 0x3F HBA Capabilities(CAP) = 0xC730FF45 InstallProtocolInterface: A1E37052-80D9-4E65-A317-3E9A55C43EC9 7E024020 SataControllerStart end with Success ==AtaAtapiPassThru Start== Controller = 7E12C698 PROGRESS CODE: V02010004 I0 InstallProtocolInterface: 1D3DE7F0-0807-424F-AA69-11A54E19A46F 7E024140 InstallProtocolInterface: 143B7632-B81B-4CB7-ABD3-B625A5B9BFFE 7E024190 PROGRESS CODE: V02080000 I0 InstallProtocolInterface: 19DF145A-B1D4-453F-8507-38816676D7F6 7E024898 PROGRESS CODE: V02080003 I0 PROGRESS CODE: V02070000 I0 InstallProtocolInterface: 0167CCC4-D0F7-4F21-A3EF-9E64B7CDCE8B 7E0244A0 PROGRESS CODE: V02070003 I0 PROGRESS CODE: V02020000 I0 PROGRESS CODE: V02020000 I0 UsbBusRecursivelyConnectWantedUsbIo: TPL before connect is 4 UsbBusRecursivelyConnectWantedUsbIo: TPL after connect is 4 PROGRESS CODE: V02080000 I0 PROGRESS CODE: V02080003 I0 SataControllerStart start SataControllerStart error. return status = Already started PROGRESS CODE: V02070000 I0 PROGRESS CODE: V02070003 I0 PROGRESS CODE: V02020000 I0 PROGRESS CODE: V02020000 I0 UsbBusRecursivelyConnectWantedUsbIo: TPL before connect is 4 UsbBusRecursivelyConnectWantedUsbIo: TPL after connect is 4 F2 or Down to enter Boot Manager Menu. ENTER to boot directly. [Bds]OsIndication: 0000000000000000 [Bds]=============Begin Load Options Dumping ...============= Driver Options: SysPrep Options: Boot Options: Boot0000: UiApp 0x0109 Boot0001: UEFI Shell 0x0001 PlatformRecovery Options: PlatformRecovery0000: Default PlatformRecovery 0x0001 [Bds]=============End Load Options Dumping============= [Bds]BdsWait ...Zzzzzzzzzzzz... [Bds]BdsWait(3)..Zzzz... [Bds]BdsWait(2)..Zzzz... [Bds]BdsWait(1)..Zzzz... [Bds]Exit the waiting! PROGRESS CODE: V03051007 I0 [Bds]Stop Hotkey Service! [Bds]UnregisterKeyNotify: 000C/0000 Success [Bds]UnregisterKeyNotify: 0002/0000 Success [Bds]UnregisterKeyNotify: 0000/000D Success PROGRESS CODE: V03051001 I0 Memory Previous Current Next Type Pages Pages Pages ====== ======== ======== ======== 09 00000008 00000000 00000008 0A 00000004 00000000 00000004 00 00000004 00000002 00000004 06 000000C0 00000040 000000C0 05 00000080 00000028 00000080 [Bds]Booting UEFI Shell [Bds] Expand MemoryMapped(0xB,0x830000,0xC0FFFF)/FvFile(7C04A583-9E3E-4F1C-AD65-E05268D0B4D1) -> MemoryMapped(0xB,0x830000,0xC0FFFF)/FvFile(7C04A583-9E3E-4F1C-AD65-E05268D0B4D1) PROGRESS CODE: V03058000 I0 InstallProtocolInterface: 5B1B31A1-9562-11D2-8E3F-00A0C969723B 7DF1ED40 Loading driver at 0x0007DC51000 EntryPoint=0x0007DC776D7 Shell.efi InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF 7E12AA18 ProtectUefiImageCommon - 0x7DF1ED40 - 0x000000007DC51000 - 0x00000000000EE0C0 PROGRESS CODE: V03058001 I0 [HiiDatabase]: Memory allocation is required after ReadyToBoot, which may change memory map and cause S4 resume issue. [HiiDatabase]: Memory allocation is required after ReadyToBoot, which may change memory map and cause S4 resume issue. [HiiDatabase]: Memory allocation is required after ReadyToBoot, which may change memory map and cause S4 resume issue. [HiiDatabase]: Memory allocation is required after ReadyToBoot, which may change memory map and cause S4 resume issue. InstallProtocolInterface: 387477C2-69C7-11D2-8E39-00A0C969723B 7DE2A2A0 InstallProtocolInterface: 752F3136-4E16-4FDC-A22A-E5F46812F4CA 7DE29018 InstallProtocolInterface: 6302D008-7F9B-4F30-87AC-60C9FEF5DA4E 7DD35EC0 UEFI Interactive Shell v2.2 EDK II UEFI v2.70 (EDK II, 0x00010000) Mapping table map: No mapping found. Press ESC in 5 seconds to skip startup.nsh or any other key to continue.Press ESC in 4 seconds to skip startup.nsh or any other key to continue.Press ESC in 3 seconds to skip startup.nsh or any other key to continue.Press ESC in 2 seconds to skip startup.nsh or any other key to continue.Press ESC in 1 seconds to skip startup.nsh or any other key to continue. Shell> Current toggle state is 0xC2 Shell> Shell> Shell> Shell> Shell> UsbEnumeratePort: port 3 state - 101, change - 01 on 7E02C018 UsbEnumeratePort: Device Connect/Disconnect Normally UsbEnumeratePort: new device connected at port 3 UsbEnumerateNewDev: hub port 3 is reset UsbEnumerateNewDev: device is of 2 speed UsbEnumerateNewDev: device uses translator (0, 0) UsbEnumerateNewDev: device is now ADDRESSED at 3 UsbEnumerateNewDev: max packet size for EP 0 is 64 UsbBuildDescTable: device has 1 configures UsbGetOneConfig: total length is 32 UsbParseConfigDesc: config 1 has 1 interfaces UsbParseInterfaceDesc: interface 0(setting 0) has 2 endpoints UsbEnumerateNewDev: device 3 is now in CONFIGED state UsbSelectConfig: config 1 selected for device 3 UsbSelectSetting: setting 0 selected for interface 0 InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7DE15A18 InstallProtocolInterface: 2B2F68D6-0CD2-44CF-8E8B-BBA20B1B5B75 7DE150C0 UsbConnectDriver: TPL before connect is 8, 7DE14E98 UsbMassInitMedia: UsbBootGetParams (Media changed) InstallProtocolInterface: 964E5B21-6459-11D2-8E39-00A0C969723B 7DE151B8 InstallProtocolInterface: D432A67F-14DC-484B-B3BB-3F0291849327 7DE15230 InstallProtocolInterface: CE345171-BA0B-11D2-8E4F-00A0C969723B 7DE15620 BlockSize : 512 LastBlock : 1D35DFF InstallProtocolInterface: 09576E91-6D3F-11D2-8E39-00A0C969723B 7DDD0E98 InstallProtocolInterface: 964E5B21-6459-11D2-8E39-00A0C969723B 7DDD0830 InstallProtocolInterface: 8CF2F62C-BC9B-4821-808D-EC9EC421A1A0 7DDD08E8 InstallProtocolInterface: CE345171-BA0B-11D2-8E4F-00A0C969723B 7DDD01A0 BlockSize : 512 LastBlock : 1D35DDF InstallProtocolInterface: 964E5B22-6459-11D2-8E39-00A0C969723B 7DDC6030 Installed Fat filesystem on 7DDD0718 UsbConnectDriver: TPL after connect is 8 PROGRESS CODE: V02020006 I0 Shell> Shell> cls Shell> m,ap ap -r Mapping table FS0: Alias(s):HD0a0d0b:;BLK1: PciRoot(0x0)/Pci(0x1D,0x0)/USB(0x0,0x0)/USB(0x3,0x0)/HD(1,MBR,0x00000000,0x20,0x1D35DE0) BLK0: Alias(s): PciRoot(0x0)/Pci(0x1D,0x0)/USB(0x0,0x0)/USB(0x3,0x0) Shell> pci Seg Bus Dev Func --- --- --- ---- 00 00 00 00 ==> Bridge Device - Host/PCI bridge Vendor 8086 Device 6F00 Prog Interface 0 00 00 01 00 ==> Bridge Device - PCI/PCI bridge Vendor 8086 Device 6F02 Prog Interface 0 00 00 02 00 ==> Bridge Device - PCI/PCI bridge Vendor 8086 Device 6F04 Prog Interface 0 00 00 02 02 ==> Bridge Device - PCI/PCI bridge Vendor 8086 Device 6F06 Prog Interface 0 00 00 03 00 ==> Bridge Device - PCI/PCI bridge Vendor 8086 Device 6F08 Prog Interface 0 00 00 05 00 ==> Base System Peripherals - Other system peripheral Vendor 8086 Device 6F28 Prog Interface 0 00 00 05 01 ==> Base System Peripherals - Other system peripheral Vendor 8086 Device 6F29 Prog Interface 0 00 00 05 02 ==> Base System Peripherals - Other system peripheral Vendor 8086 Device 6F2A Prog Interface 0 00 00 05 04 ==> Base System Peripherals - PIC Vendor 8086 Device 6F2C Prog Interface 20 00 00 14 00 ==> Serial Bus Controllers - USB Vendor 8086 Device 8C31 Prog Interface 30 00 00 1D 00 ==> Serial Bus Controllers - USB Vendor 8086 Device 8C26 Prog Interface 20 00 00 1F 00 ==> Bridge Device - PCI/ISA bridge Vendor 8086 Device 8C54 Prog Interface 0 00 00 1F 02 ==> Mass Storage Controller - Serial ATA controller Vendor 8086 Device 8C02 Prog Interface 1 00 00 1F 03 ==> Serial Bus Controllers - System Management Bus Vendor 8086 Device 8C22 Prog Interface 0 00 00 1F 06 ==> Data Acquisition & Signal Processing Controllers - Other DAQ & SP controllers Vendor 8086 Device 8C24 Prog Interface 0 00 02 00 00 ==> Base System Peripherals - Other system peripheral Vendor 8086 Device 6F50 Prog Interface 0 00 02 00 01 ==> Base System Peripherals - Other system peripheral Vendor 8086 Device 6F51 Prog Interface 0 00 02 00 02 ==> Base System Peripherals - Other system peripheral Vendor 8086 Device 6F52 Prog Interface 0 00 02 00 03 ==> Base System Peripherals - Other system peripheral Vendor 8086 Device 6F53 Prog Interface 0 00 03 00 00 ==> Network Controller - Ethernet controller Vendor 8086 Device 15AC Prog Interface 0 00 03 00 01 ==> Network Controller - Ethernet controller Vendor 8086 Device 15AC Prog Interface 0 00 04 00 00 ==> Display Controller - VGA/8514 controller Vendor 10DE Device 128B Prog Interface 0 00 04 00 01 ==> Multimedia Device - Mixed mode device Vendor 10DE Device 0E0F Prog Interface 0 Shell> ============= PEIM FSP v1.0 (_BDX-DE_ v0.0.3.3) ============= Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000FFEB1000, size is 0x0011F000, handle is 0x0 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389 Loading PEIM at 0x000FFEBA990 EntryPoint=0x000FFEBAA60 PcdPeim.efi Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480 Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1 Loading PEIM at 0x000FFEBEB00 EntryPoint=0x000FFEBEBD0 SetupDefault.efi Install PPI: 57B195D1-E14B-40AD-A68F-9806000C436A Loading PEIM at 0x000FFEC1F14 EntryPoint=0x000FFEC1FEC PlatformInfo.efi enable all DMI VCx :: CPU Type Socket ModelId# 56 :: CPU stepping # 3 Install PPI: 1E2ACC41-E26A-483D-AFC7-A056C34E087B Publish PlatformInfoPPI Loading PEIM at 0x000FFEC49D4 EntryPoint=0x000FFEC4AA4 MePolicyInitPei.efi Install PPI: 7AE3CEB7-2EE2-48FA-AA49-3510BC83CABF ME PEI Platform Policy PPI Installed Loading PEIM at 0x000FFEC6BCC EntryPoint=0x000FFEC6C94 HeciInit.efi Force an S5 exit path. Install PPI: E5EE2066-FAA1-4DFA-924E-B1E3A8EE30E8 Install PPI: EE0EA811-FBD9-4777-B95A-BA4F71101F74 Loading PEIM at 0x000FFECA1D4 EntryPoint=0x000FFECA29C MeUma.efi Install PPI: 8C376010-2400-4D7D-B47B-9D851DF3C9D1 ME UMA: ME UMA PPI Installed Loading PEIM at 0x000FFECD774 EntryPoint=0x000FFECD844 SpsPei.efi [SPS] Waiting for ME firmware init complete [HECI-0] VID-DID: 8086-8C3A [HECI-0] MBAR not programmed, using default 0x00000000FEDB0000 [SPS] Sending ME-BIOS Interface Version request [HECI-0] Send msg: 80010020 [HECI-0] Got msg: 80050020 [SPS] SPS ME-BIOS interface version is 1.0 Feature set is 0x2106 [SPS] HOB: features 0x2106, flow 1, boot mode 0, cores to disable 0 Loading PEIM at 0x000FFED0FFC EntryPoint=0x000FFED10DC UncoreInitPeim.efi OVERRIDING TOTAL SYSTEM CONFIGURATION WITH UPD upd->MemDdr4Platform = 0x0 tsc->DDR4Platform = 0x2 Halting the TCO Timer (Watchdog) Running on hardware Revision: 0 BIOSSIM: InitHeap() BIOSSIM: InitUSBDebug() BDX (1HA) processor detected CPU Stepping 3 Found CCMRC Version: 00500000 MRC Sync Number: 244071 RC Version: 02040000 host = FE191768 (pointer to sysHost structure) Legacy Serial Debug Enabled QPI Init starting... ******* QPI Setup Structure ******* PPINrOptIn: 0 Bus Ratio: 1 1 1 1 IO Ratio: 1 1 1 1 MMIOL Ratio: 1 1 1 1 LegacyVgaSoc: 0 MmioP2pDis: 0 IsocAzaliaVc1En: 0 DebugPrintLevel: 15 ClusterOnDieEn: 0 IBPECIEn: 1 E2EParityEn: 0 EarlySnoopEn: 1 HomeDirWOSBEn: 1 DegradePrecedence: 0 QpiLinkSpeedMode: 1 (FAST) QpiLinkSpeed: 6 QpiLinkL0pEn: 1 QpiLinkL1En: 1 QpiLinkL0rEn: 1 QpiLbEn: 0 IioUniphyDisable (per socket): 0 0 0 0 QpiLinkCreditReduce: 2 QpiConfigTxWci: 11 QpiCrcMode: 0 QpiCpuSktHotPlugEn: 0 QpiCpuSktHotPlugTopology: 0 QpiSkuMismatchCheck: 1 QpiPortDisable (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiLinkCreditReduce (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiLinkSpeed (per port): S0:6 6 S1:6 6 S2:6 6 S3:6 6 QpiProbeType (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiConfigTxWci (per port): S0:11 11 S1:11 11 S2:11 11 S3:11 11 Rsvd (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 ******* Common Setup Structure ******* mmCfgBase: 0x80000000 mmCfgSize: 0x10000000 mmiolBase: 0x90000000 mmiolSize: 0x6C000000 mmiohBase: 0x00003800-00000000 mmiohSize: 256 GB numaEn: 1 isocEn: 0 mesegEn: 0 dcaEn: 1 ******* Common Var Structure ******* resetRequired: 0 state: 0 numCpus: 0 socketPresentBitMap: 0x01 busIio: 0x00 0x00 0x00 0x00 busUncore: 0x3F 0x00 0x00 0x00 mmCfgBase: 0x80000000 ;******* Collecting Early System Information - START *******Checkpoint Code: Socket 0, 0xA1, 0x00, 0x1FFF CAPID0[5] is set. SKU Detected as DE. SocketId: 0 Physical Chop: 3 SocketId: 0 CAPID5: 0x06000965 SocketId: 0 CAPID4: 0x24080D03 SocketId: 0 CAPID3: 0x00930A20 SocketId: 0 CAPID2: 0x53B40000 SocketId: 0 CAPID1: 0x8C001787 SocketId: 0 CAPID0: 0x00188520 ; SBSP Socket: 0 SKU: 0x05 SubSKU: 0x00 Stepping: 0x03 CAPID4[sbsp]: 0x24080D03 ; Total Cbos: 06 Cbo List: 0x965 Total HA: 01 Total R3Qpi: 00 Total QpiAgent: 00 ; TotCpus: 4 CpuList: 0x0F ; busIio: 0x00 0x40 0x80 0xC0 ; busUncore: 0x3F 0x7F 0xBF 0xFF ; Reset Type: Cold Reset Link Speed: Slow Speed ;******* Collecting Early System Information - END ******* ;******* Setting up Minimum Path - START *******Checkpoint Code: Socket 0, 0xA3, 0x01, 0x0000 ; Constructing SBSP minimum path Topology Tree ; -------------------------------------------- ; Adding SBSP (CPU0) to the treeCheckpoint Code: Socket 0, 0xA3, 0x02, 0x0020 CPU0 Link Exchange UseQpiPcSts = 1 ;SBSP Minimum Path Tree ;---------------------- ;Index Socket ParentPort Hop ParentIndex ; 00 CPU0 -- 0 -- ;******* Setting up Minimum Path - END ******* ;******* Initialize MCTP - START ******* ;******* Initialize MCTP - END ******* ;******* Check for QPI Topology Degradation - START *******Checkpoint Code: Socket 0, 0xA7, 0x01, 0x1FFF ;Link Exchange Parameter ;----------------------- ;CPU0 ; Already Reduced to Supported Topology ; System will be treated 1S Configuration ;******* Check for QPI Topology Degradation - END ******* ;******* Checking QPIRC Input Structure - START ******* ; Sys configuration Type = 16 ;******* Checking QPIRC Input Structure - END ******* ;******* Allocate RTIDs - START ******* ; WB - 02 Ubox - 00 Isoc - 00 Local RTID PerCbo - 16 Extra - 30 ; Local Base - 01 Reallocation Base - 65 ; Cbo 03 RTID straddles into xRTID space ; RTIDs split into three pools of size 8, 7 and 1 ; Sufficient extra RTIDs are available to move the Second Pool into xRTID space. No loss of RTIDs for the CBo. ; RTID Allocation Table ; --------------------- ; Local ; ----- ; WB 0 1 ; UBOX 0 0 ; ISOC 1 0 ; CBO00 1 8 ; CBO00 9 8 ; CBO01 17 8 ; CBO01 25 8 ; CBO02 33 8 ; CBO02 41 8 ; CBO03 49 8 ; CBO03 65 8 ; CBO04 73 8 ; CBO04 81 8 ; CBO05 89 8 ; CBO05 97 8 ; EXTRA 0 23 ;******* Allocate RTIDs - END ******* ;******* Cacluate Resource Allocation - START *******Checkpoint Code: Socket 0, 0xA9, 0x01, 0x1FFF ;CPU Resource Allocation ;----------------------- ;CPU0 Bus: 0x00 - 0xFF IO: 0x0000 - 0xFFFF IOAPIC: 0xFEC00000 - 0xFEC3FFFF MMIOL: 0x90000000 - 0xFBFFFFFF MMIOH: 0x00003800 00000000 - 0x0000383F FFFFFFFF ;******* Cacluate Resource Allocation - END ******* ;******* Programming RTIDs and other Credits - START *******Checkpoint Code: Socket 0, 0xAA, 0x01, 0x1FFF Checkpoint Code: Socket 0, 0xAA, 0x02, 0x1FFF ;******* Programming RTIDs and other Credits - END ******* ;******* Sync Up PBSPs - START ******* ; Setting Ubox Sticky SR07 to 0x00000000 ; Setting Ubox Sticky SR03 to 0x20000007 ; Setting Ubox Sticky SR02 to 0x00000001 ; Verifying if the remote socket(s) checked-in. ;******* Sync Up PBSPs - END ******* ;******* Programming MSR for w/a - START ******* ;******* Programming MSR for w/a - END ******* ;******* Programming BGF Overrides - START ******* ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x0 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x7D ; Wait for mailbox ready ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x11 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x17D ; Wait for mailbox ready ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x0 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x27D ; Wait for mailbox ready ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x0 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x37D ; Wait for mailbox ready ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x0 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x47D ; Wait for mailbox ready ;******* Programming BGF Overrides - END ******* ;******* Full Speed Transition - START *******Checkpoint Code: Socket 0, 0xAB, 0x00, 0x1FFF ; ;Single Socket, no QPI Links to transition ; Force unused links to disabled/low power state. ; Clr PhyInitBegin on Socket 0 Link 0 : QPIREUT_PH_CTR write 0xFFFFFFDF Set force_l1 on Socket 0 Link 0 : QPIPHYPWRCTRL write 0xFFFFFFFF ; Clr PhyInitBegin on Socket 0 Link 1 : QPIREUT_PH_CTR write 0xFFFFFFDF Set force_l1 on Socket 0 Link 1 : QPIPHYPWRCTRL write 0xFFFFFFFF ;******* Full Speed Transition - END ******* ;******* Cod Activate - START ******* ;******* Cod Activate - END ******* ******* QPI Output Structure ******* OutLegacyVgaSoc: 0 OutIsocEn: 0 OutMesegEn: 0 OutIsocAzaliaVc1En: 0 OutClusterOnDieEn: 0 OutIBPECIEn: 1 OutE2EParityEn: 0 OutEarlySnoopEn: 1 OutHomeDirWOSBEn: 0 QpiCurrentLinkSpeedMode: 0 (SLOW) OutQpiLinkSpeed: 6 OutQpiLinkL0pEn: 1 OutQpiLinkL1En: 1 OutQpiLinkL0rEn: 1 OutIioUniphyDisable: 0, 0, 0, 0 OutQpiCrcMode: 0 OutClusterOnDieReduction: 0 OutPointerSeperationHA: 0 QpiInternalGlobal->BtModeEn: 0 QpiInternalGlobal->BtMode: 0 QpiInternalGlobal->BtMode2Alt: 0 QpiInternalGlobal->Sys4SClusterOnDieEn: 0 QpiInternalGlobal->SnoopFanoutEn: 0 QpiInternalGlobal->SysSnoopMode: 0 QpiInternalGlobal->IodcEn: 0Checkpoint Code: Socket 0, 0xAF, 0x00, 0x1FFF ;******* QPIRC Exit ******* QPI Init completed! Reset Requested: 2 Pipe Init starting...Pipe Init completed! Reset Requested: 2 CPU Feature Early Config starting... CAPID0[5] is set. SKU Detected as DE.CPU Feature Early Config completed! Reset Requested: 2 START_MRC_RUN ME UMA: ME UMA Size Requested: 0 ME UMA size = 0 MBytes sizeof sysHost = 449216 sizeof BDAT = 168490 sizeof memSetup = 1463 sizeof memNvram = 136303 sizeof socketNvram = 33684 sizeof memVar = 135017 sizeof Socket = 30969 sizeof ddrChannel = 7434 sizeof dimmDevice = 946 sizeof SADTable = 20 sizeof TADTable = 23 MAX_SOCKET = 4 sizeof sysHostSetup = 1696 struct sysHost.common { options: 00000007 PROMOTE_WARN_EN 1 HALT_ON_ERROR_EN 1 serialDebugMsgLvl:03 bsdBreakpoint: 00 maxAddrMem: 40000 debugPort: 80 nvramPtr: 00000000 sysHostBufferPtr:00000000 mmCfgBase: 80000000 mmCfgSize: 10000000 pchumaEn: 00 numaEn: 01 logParsing: 00 bdatEn: 00 consoleComPort: 3F8 struct sysHost.setup.mem { options: 10124FC8 TEMPHIGH_EN 0 PDWN_SR_CKE_MODE 0 OPP_SELF_REF_EN 1 MDLL_SHUT_DOWN_EN 0 PAGE_POLICY 0 MULTI_THREAD_MRC_EN 1 ADAPTIVE_PAGE_EN 1 SCRAMBLE_EN 1 MEM_FLOWS - X_OVER_EN 1 MEM_FLOWS - SENSE_AMP_EN 1 MEM_FLOWS - E_CMDCLK_EN 1 MEM_FLOWS - REC_EN_EN 1 MEM_FLOWS - RD_DQS_EN 1 MEM_FLOWS - WR_LVL_EN 1 MEM_FLOWS - WR_FLYBY_EN 1 MEM_FLOWS - WR_DQ_EN 1 MEM_FLOWS - CMDCLK_EN 1 MEM_FLOWS - RD_ADV_EN 1 MEM_FLOWS - WR_ADV_EN 1 MEM_FLOWS - RD_VREF_EN 1 MEM_FLOWS - WR_VREF_EN 1 MEM_FLOWS - RT_OPT_EN 1 MEM_FLOWS - RX_DESKEW_EN 1 MEM_FLOWS - TX_DESKEW_EN 1 MEM_FLOWS - TX_EQ_EN 1 MEM_FLOWS - IMODE_EN 1 MEM_FLOWS - EARLY_RID_EN 1 MEM_FLOWS - DQ_SWIZ_EN 1 MEM_FLOWS - LRBUF_RD_EN 1 MEM_FLOWS - LRBUF_WR_EN 1 MEM_FLOWS - RANK_MARGIN_EN 1 MEM_FLOWS - MEMINIT_EN 1 MEM_FLOWS - FNVSIMICSSIM_EN 1 MEM_FLOWS - MEMTEST_EN 1 MEM_FLOWS - NORMAL_MODE_EN 1 MEM_FLOWS - E_CTLCLK_EN 1 MEM_FLOWS_EXT - RX_CTLE_EN 1 MEM_FLOWS_EXT - PXC_EN 1 DDR_RESET_LOOP 0 NUMA_AWARE 1 DISABLE_WMM_OPP_READ 0 ECC_CHECK_EN 1 ECC_MIX_EN 0 BALANCED_4WAY_EN 0 CA_PARITY_EN 1 SPLIT_BELOW_4GB_EN 0 MARGIN_RANKS_EN 0 MEM_OVERRIDE_EN 0 DRAMDLL_OFF_PD_EN 0 MEMORY_TEST_EN 1 MEMORY_TEST_FAST_BOOT_EN 0 ATTEMPT_FAST_BOOT 0 ATTEMPT_FAST_BOOT_COLD 0 SW_MEMORY_TEST_EN 0 RMT_COLD_FAST_BOOT 0 DISPLAY_EYE_EN 0 PER_NIBBLE_EYE_EN 0 optionsExt: 1E41677F RD_VREF_EN 1 WR_VREF_EN 1 PDA_EN 1 TURNAROUND_OPT_EN 1 PER_BIT_MARGINS 1 RASmodeEx: 16 DMNDSCRB_EN 1 PTRLSCRB_EN 1 A7_MODE_EN 1 DEVTAGGING_EN 0 struct sysHost.setup.mem { bclk: 00 enforcePOR: 00 ddrFreqLimit: 00 chInter: 04 dimmTypeSupport: 02 vrefStepSize: 00 vrefAbsMaxSteps: 00 vrefOpLimitSteps:00 pdwnCkMode: 04 MemPwrSave: 05 pprType: 00 pprErrInjTest 00 ckeThrottling: 01 olttPeakBWLIMITPercent: 00 thermalThrottlingOptions: 0A CLTT_EN 1 OLTT_EN 0 MH_OUTPUT_EN 0 MH_SENSE_EN 1 DimmTempStatValue 00 dramraplen: 02 dramraplbwlimittf: 01 lrdimmModuleDelay: 00 customRefreshRate: 00 rxVrefTraining: 00 iotMemBufferRsvtn: 00 enforceThreeMonthTimeout: 01 rmtPatternLength:7FFF rmtPatternLengthExt(CMD/CTL):7FFF patrolScrubDuration:18 memTestLoops: 01 scrambleSeedLow: 0000A02B scrambleSeedHigh:0000D395 ADREn: 00 eraseArmNVDIMMS: 01 check_pm_sts: 00 check_platform_detect: 00 mcBgfThreshold: 00 normOppIntvl: 0400 SpdSmbSpeed: 00 struct ddrChannelSetup[00] { enabled: 01 numDimmSlots: 02 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[01] { enabled: 01 numDimmSlots: 02 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[02] { enabled: 00 numDimmSlots: 03 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[03] { enabled: 00 numDimmSlots: 03 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct memTiming { nCL: 00 nRP: 00 nRCD: 00 nRRD: 00 nWTR: 00 nRAS: 00 nRTP: 00 nWR: 00 nFAW: 00 nRC: 00 nCWL: 00 nCMDRate: 00 ddrFreqLimit: 00 vdd: 00 ucVolt: 00 casSup: 00 tREFI: 00 nRFC: 00 ddrFreq: 00 }; meRequestedSize: 00000000 }; serialDebugMsgLvl: 03 lowGap: 20 highGap: 01 mmiohSize: 00000100 isocEn: 00 dcaEn: 01 options (Chip): 10124FC8 CMD_CLK_TRAINING_EN 1 ALLOW2XREF_EN 1 RAS_TO_INDP_EN 0 BANK_XOR_EN 1 optionsExt (Chip): 1E41677F EARLY_CMD_CLK_TRAINING_EN 1 CMD_REF_EN 1 LRDIMM_BACKSIDE_VREF_EN 0 LRDIMM_WR_VREF_EN 1 LRDIMM_RD_VREF_EN 1 LRDIMM_RX_DQ_CENTERING 1 LRDIMM_TX_DQ_CENTERING 1 XOVER_EN 1 DRAM_RON_EN 0 RX_ODT_EN 0 RTT_WR_EN 0 MC_RON_EN 0 TX_EQ_EN 1 IMODE_EN 0 RX_CTLE_TRN_EN 1 SENSE_EN 1 ROUND_TRIP_LATENCY_EN 0 WR_CRC 0 DDR4_PLATFORM 0 0 0 RASmode: 00 RK_SPARE 0 CH_LOCKSTEP 0 CH_MIRROR 0 struct sysHost.setup.mem (Chip) { socketInter: 01 rankInter: 08 dramraplExtendedRange: 01 dramMaint: 02 dramMaintTRRMode: 01 dramMaintMode: 01 electricalThrottling: 00 altitude: 00 forceRankMult: 00 ceccWaChMask: 00 perBitDeSkew: 01 spareErrTh: 7FFF leakyBktLo: 28 leakyBktHi: 29 restoreNVDIMMS: 01 lockstepEnableX4: 00 numSparTrans: 0004 phaseShedding: 01 }; struct ddrIMCSetup[00] { enabled: 00000001 ddrVddLimit: 00 } }; //struct sysHost.setup forceColdBoot bit set Get socket PPIN N0: PPIN Hi = 0x25BEAAB, PPIN Lo = 0x51561DAB setupChanged: 1 Clearing the MRC NVRAM structure. sizeof sysNvram = 136441 bootMode = NormalBoot subBootMode = ColdBoot Dispatch Slaves -- Started Dispatch Slaves - 0ms Promote Warning Exception List -- Started Promote Warning Exception List - 0ms Initialize Throttling Early -- Started Initialize Throttling Early - 0ms Detect DIMM Configuration -- Started Checkpoint Code: Socket 0, 0xB0, 0x00, 0x0000 N0: IMC 0 SMB Clock Period = 0x1F2C Socket | Channel | DIMM | Bus Segment | SMBUS Address -------|---------|------|--------------|-------------- 0 | 0 | 0 | 0 | 0 - Not Present 0 | 0 | 1 | 0 | 1 - Not Present 0 | 1 | 0 | 0 | 2 - Present N0.C1.D0: NVDIMM:N(380)=0x0 0 | 1 | 1 | 0 | 3 - Not Present Entering no zone 1 Detect DIMM Configuration - 298ms Get Slave Data -- Started Get Slave Data - 0ms Check POR Compatibility -- Started N0.C0: Channel disabled in MemSPD: mcId = 0, mcCh = 0 primaryWidthDDR4: 1, rowBitsDDR4: 15, columnBitsDDR4: 10, bankGroupsDDR4: 4 RDIMM population Check POR Compatibility - 14ms Initialize DDR Clocks -- Started Checkpoint Code: Socket 0, 0xB1, 0x00, 0x0000 GetPORDDRFreq returns ddrfreq = 10 ratioIndex = 10 Reset requested: non-MRC MRC reset request! Current DCLK: 12 Desired DCLK: 16, req_type = 0 Entering no zone 2 Initialize DDR Clocks - 14ms mrcTask skipped; Index = 7 Send Status -- Started Send Status -- EXIT, status = 2h Total MRC time = 388ms Setting Last Boot Date = 7272 days STOP_MRC_RUN Reset Requested: 2 Pipe Exit starting...Pipe Exit completed! Reset Requested: 2 Checking for Reset Requests ... Send HostResetWarning notification to ME. ME UMA: WARNING: HostResetWarning called on non S3/4 resume flow (0) - ignored HostResetWarning notification Complete. Issue WARM RESET! BIOS done set Checkpoint Code: Socket 0, 0xAF, 0x42, 0x0000 ============= PEIM FSP v1.0 (_BDX-DE_ v0.0.3.3) ============= Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A The 0th FV start address is 0x000FFEB1000, size is 0x0011F000, handle is 0x0 Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39 Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38 Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: DBE23AA9-A345-4B97-85B6-B226F1617389 Loading PEIM at 0x000FFEBA990 EntryPoint=0x000FFEBAA60 PcdPeim.efi Install PPI: 06E81C58-4AD7-44BC-8390-F10265F72480 Install PPI: 01F34D25-4DE2-23AD-3FF3-36353FF323F1 Loading PEIM at 0x000FFEBEB00 EntryPoint=0x000FFEBEBD0 SetupDefault.efi Install PPI: 57B195D1-E14B-40AD-A68F-9806000C436A Loading PEIM at 0x000FFEC1F14 EntryPoint=0x000FFEC1FEC PlatformInfo.efi enable all DMI VCx :: CPU Type Socket ModelId# 56 :: CPU stepping # 3 Install PPI: 1E2ACC41-E26A-483D-AFC7-A056C34E087B Publish PlatformInfoPPI Loading PEIM at 0x000FFEC49D4 EntryPoint=0x000FFEC4AA4 MePolicyInitPei.efi Install PPI: 7AE3CEB7-2EE2-48FA-AA49-3510BC83CABF ME PEI Platform Policy PPI Installed Loading PEIM at 0x000FFEC6BCC EntryPoint=0x000FFEC6C94 HeciInit.efi Force an S5 exit path. Install PPI: E5EE2066-FAA1-4DFA-924E-B1E3A8EE30E8 Install PPI: EE0EA811-FBD9-4777-B95A-BA4F71101F74 Loading PEIM at 0x000FFECA1D4 EntryPoint=0x000FFECA29C MeUma.efi Install PPI: 8C376010-2400-4D7D-B47B-9D851DF3C9D1 ME UMA: ME UMA PPI Installed Loading PEIM at 0x000FFECD774 EntryPoint=0x000FFECD844 SpsPei.efi [SPS] Waiting for ME firmware init complete [HECI-0] VID-DID: 8086-8C3A [HECI-0] MBAR not programmed, using default 0x00000000FEDB0000 [SPS] Sending ME-BIOS Interface Version request [HECI-0] Send msg: 80010020 [HECI-0] Got msg: 80050020 [SPS] SPS ME-BIOS interface version is 1.0 Feature set is 0x2106 [SPS] HOB: features 0x2106, flow 1, boot mode 0, cores to disable 0 Loading PEIM at 0x000FFED0FFC EntryPoint=0x000FFED10DC UncoreInitPeim.efi OVERRIDING TOTAL SYSTEM CONFIGURATION WITH UPD upd->MemDdr4Platform = 0x0 tsc->DDR4Platform = 0x2 Halting the TCO Timer (Watchdog) Running on hardware Revision: 0 BIOSSIM: InitHeap() BIOSSIM: InitUSBDebug() BDX (1HA) processor detected CPU Stepping 3 Found CCMRC Version: 00500000 MRC Sync Number: 244071 RC Version: 02040000 host = FE191768 (pointer to sysHost structure) Legacy Serial Debug Enabled QPI Init starting... ******* QPI Setup Structure ******* PPINrOptIn: 0 Bus Ratio: 1 1 1 1 IO Ratio: 1 1 1 1 MMIOL Ratio: 1 1 1 1 LegacyVgaSoc: 0 MmioP2pDis: 0 IsocAzaliaVc1En: 0 DebugPrintLevel: 15 ClusterOnDieEn: 0 IBPECIEn: 1 E2EParityEn: 0 EarlySnoopEn: 1 HomeDirWOSBEn: 1 DegradePrecedence: 0 QpiLinkSpeedMode: 1 (FAST) QpiLinkSpeed: 6 QpiLinkL0pEn: 1 QpiLinkL1En: 1 QpiLinkL0rEn: 1 QpiLbEn: 0 IioUniphyDisable (per socket): 0 0 0 0 QpiLinkCreditReduce: 2 QpiConfigTxWci: 11 QpiCrcMode: 0 QpiCpuSktHotPlugEn: 0 QpiCpuSktHotPlugTopology: 0 QpiSkuMismatchCheck: 1 QpiPortDisable (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiLinkCreditReduce (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiLinkSpeed (per port): S0:6 6 S1:6 6 S2:6 6 S3:6 6 QpiProbeType (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 QpiConfigTxWci (per port): S0:11 11 S1:11 11 S2:11 11 S3:11 11 Rsvd (per port): S0:0 0 S1:0 0 S2:0 0 S3:0 0 ******* Common Setup Structure ******* mmCfgBase: 0x80000000 mmCfgSize: 0x10000000 mmiolBase: 0x90000000 mmiolSize: 0x6C000000 mmiohBase: 0x00003800-00000000 mmiohSize: 256 GB numaEn: 1 isocEn: 0 mesegEn: 0 dcaEn: 1 ******* Common Var Structure ******* resetRequired: 0 state: 0 numCpus: 0 socketPresentBitMap: 0x01 busIio: 0x00 0x00 0x00 0x00 busUncore: 0xFF 0x00 0x00 0x00 mmCfgBase: 0x80000000 ;******* Collecting Early System Information - START *******Checkpoint Code: Socket 0, 0xA1, 0x00, 0x1FFF CAPID0[5] is set. SKU Detected as DE. SocketId: 0 Physical Chop: 3 SocketId: 0 CAPID5: 0x06000965 SocketId: 0 CAPID4: 0x24080D03 SocketId: 0 CAPID3: 0x00930A20 SocketId: 0 CAPID2: 0x53B40000 SocketId: 0 CAPID1: 0x8C001787 SocketId: 0 CAPID0: 0x00188520 ; SBSP Socket: 0 SKU: 0x05 SubSKU: 0x00 Stepping: 0x03 CAPID4[sbsp]: 0x24080D03 ; Total Cbos: 06 Cbo List: 0x965 Total HA: 01 Total R3Qpi: 00 Total QpiAgent: 00 ; TotCpus: 1 CpuList: 0x01 ; busIio: 0x00 ; busUncore: 0xFF ; Reset Type: Warm Reset Link Speed: Slow Speed ;******* Collecting Early System Information - END ******* ;******* Setting up Minimum Path - START *******Checkpoint Code: Socket 0, 0xA3, 0x01, 0x0000 ; Constructing SBSP minimum path Topology Tree ; -------------------------------------------- ; Adding SBSP (CPU0) to the treeCheckpoint Code: Socket 0, 0xA3, 0x02, 0x0020 CPU0 Link Exchange UseQpiPcSts = 1 ;SBSP Minimum Path Tree ;---------------------- ;Index Socket ParentPort Hop ParentIndex ; 00 CPU0 -- 0 -- ;******* Setting up Minimum Path - END ******* ;******* Initialize MCTP - START ******* ;******* Initialize MCTP - END ******* ;******* Check for QPI Topology Degradation - START *******Checkpoint Code: Socket 0, 0xA7, 0x01, 0x1FFF ;Link Exchange Parameter ;----------------------- ;CPU0 ; Already Reduced to Supported Topology ; System will be treated 1S Configuration ;******* Check for QPI Topology Degradation - END ******* ;******* Checking QPIRC Input Structure - START ******* ; Sys configuration Type = 16 ;******* Checking QPIRC Input Structure - END ******* ;******* Allocate RTIDs - START ******* ; WB - 02 Ubox - 00 Isoc - 00 Local RTID PerCbo - 16 Extra - 30 ; Local Base - 01 Reallocation Base - 65 ; Cbo 03 RTID straddles into xRTID space ; RTIDs split into three pools of size 8, 7 and 1 ; Sufficient extra RTIDs are available to move the Second Pool into xRTID space. No loss of RTIDs for the CBo. ; RTID Allocation Table ; --------------------- ; Local ; ----- ; WB 0 1 ; UBOX 0 0 ; ISOC 1 0 ; CBO00 1 8 ; CBO00 9 8 ; CBO01 17 8 ; CBO01 25 8 ; CBO02 33 8 ; CBO02 41 8 ; CBO03 49 8 ; CBO03 65 8 ; CBO04 73 8 ; CBO04 81 8 ; CBO05 89 8 ; CBO05 97 8 ; EXTRA 0 23 ;******* Allocate RTIDs - END ******* ;******* Cacluate Resource Allocation - START *******Checkpoint Code: Socket 0, 0xA9, 0x01, 0x1FFF ;CPU Resource Allocation ;----------------------- ;CPU0 Bus: 0x00 - 0xFF IO: 0x0000 - 0xFFFF IOAPIC: 0xFEC00000 - 0xFEC3FFFF MMIOL: 0x90000000 - 0xFBFFFFFF MMIOH: 0x00003800 00000000 - 0x0000383F FFFFFFFF ;******* Cacluate Resource Allocation - END ******* ;******* Check for QPI Topology change across reset - START ******* ;******* Check for QPI Topology change across reset - END ******* ;******* Phy/Link Updates On Warm Reset - START ******* ; Force unused links to disabled/low power state. ; Clr PhyInitBegin on Socket 0 Link 0 : QPIREUT_PH_CTR write 0xFFFFFFDF Set force_l1 on Socket 0 Link 0 : QPIPHYPWRCTRL write 0xFFFFFFFF ; Clr PhyInitBegin on Socket 0 Link 1 : QPIREUT_PH_CTR write 0xFFFFFFDF Set force_l1 on Socket 0 Link 1 : QPIPHYPWRCTRL write 0xFFFFFFFF ;******* Phy/Link Updates On Warm Reset - END ******* ;******* Sync Up PBSPs - START ******* ; Verifying if the remote socket(s) checked-in. ;******* Sync Up PBSPs - END ******* ; Wait for mailbox ready ; Send Data portion of command. Socket = 0 Data sent == 0x0 ; Send Pcode mailbox command. Socket = 0 Command sent == 0x91 ; Wait for mailbox ready ;******* Topology Dicovery and Optimum Route Calculation - START *******Checkpoint Code: Socket 0, 0xA7, 0x02, 0x1FFF ; Locating the Rings Present in the Topology ; No Rings Found ; Constructing Topology TreeCheckpoint Code: Socket 0, 0xA7, 0x03, 0x1FE0 ; Adjacency Table ; ---------------- ; Checking for Deadlock... ;CPU0 Topology Tree ;------------------- ;Index Socket ParentSocket ParentPort ParentIndex Hop ; 00 CPU0 -- -- -- 0 ; ; Calculating Route for CPU0 Checkpoint Code: Socket 0, 0xA7, 0x04, 0x0020 ;CPU 0 Routing Table ;------------------- ;DestSocket Port ;******* Topology Dicovery and Optimum Route Calculation - END ******* ;******* Program Optimum Route Table Settings - START *******Checkpoint Code: Socket 0, 0xA8, 0xFF, 0x1FFF ;******* Program Optimum Route Table Settings - END ******* ;******* Program Final IO SAD Setting - START *******Checkpoint Code: Socket 0, 0xA9, 0x02, 0x1FFF Checkpoint Code: Socket 0, 0xA9, 0x02, 0x1FFF Checkpoint Code: Socket 0, 0xA9, 0x03, 0x0027 ;******* Program Final IO SAD Setting - END ******* ;******* Program Misc. QPI Parameters - START *******Checkpoint Code: Socket 0, 0xAA, 0x05, 0x1FFF Lock QPI DFX. ;******* Program Misc. QPI Parameters - END ******* ;******* Program Home Agent Credits - START *******Checkpoint Code: Socket 0, 0xAA, 0x03, 0x1FFF ;******* Program Home Agent Credits - END ******* ;******* Program Home tracker and Route Back Table - START *******Checkpoint Code: Socket 0, 0xAA, 0x04, 0x1FFF ;******* Program Home tracker and Route Back Table - END ******* ;******* Program System Coherency Registers - START *******Checkpoint Code: Socket 0, 0xAE, 0x00, 0x1FFF ;******* Program System Coherency Registers - END ******* ;******* Check for S3 Resume - START ******* ;******* Check for S3 Resume - END ******* ;******* Collect Previous Boot Error - START ******* ;******* Collect Previous Boot Error - END ******* ******* QPI Output Structure ******* OutLegacyVgaSoc: 0 OutIsocEn: 0 OutMesegEn: 0 OutIsocAzaliaVc1En: 0 OutClusterOnDieEn: 0 OutIBPECIEn: 1 OutE2EParityEn: 0 OutEarlySnoopEn: 1 OutHomeDirWOSBEn: 0 QpiCurrentLinkSpeedMode: 0 (SLOW) OutQpiLinkSpeed: 6 OutQpiLinkL0pEn: 1 OutQpiLinkL1En: 1 OutQpiLinkL0rEn: 1 OutIioUniphyDisable: 0, 0, 0, 0 OutQpiCrcMode: 0 OutClusterOnDieReduction: 0 OutPointerSeperationHA: 0 QpiInternalGlobal->BtModeEn: 0 QpiInternalGlobal->BtMode: 0 QpiInternalGlobal->BtMode2Alt: 0 QpiInternalGlobal->Sys4SClusterOnDieEn: 0 QpiInternalGlobal->SnoopFanoutEn: 0 QpiInternalGlobal->SysSnoopMode: 0 QpiInternalGlobal->IodcEn: 0Checkpoint Code: Socket 0, 0xAF, 0x00, 0x1FFF ;******* QPIRC Exit ******* QPI Init completed! Reset Requested: 0 Pipe Init starting...Pipe Init completed! Reset Requested: 0 CPU Feature Early Config starting... CAPID0[5] is set. SKU Detected as DE.CPU Feature Early Config completed! Reset Requested: 0 PrevBootErrors - CBO mcbank: 18 - not present; skipping... PrevBootErrors - CBO mcbank: 20 - not present; skipping... PrevBootErrors - CBO mcbank: 21 - not present; skipping... PrevBootErrors - Valid MCA UC entries: 0 START_MRC_RUN ME UMA: ME UMA Size Requested: 0 ME UMA size = 0 MBytes sizeof sysHost = 449216 sizeof BDAT = 168490 sizeof memSetup = 1463 sizeof memNvram = 136303 sizeof socketNvram = 33684 sizeof memVar = 135017 sizeof Socket = 30969 sizeof ddrChannel = 7434 sizeof dimmDevice = 946 sizeof SADTable = 20 sizeof TADTable = 23 MAX_SOCKET = 4 sizeof sysHostSetup = 1696 struct sysHost.common { options: 00000007 PROMOTE_WARN_EN 1 HALT_ON_ERROR_EN 1 serialDebugMsgLvl:03 bsdBreakpoint: 00 maxAddrMem: 40000 debugPort: 80 nvramPtr: 00000000 sysHostBufferPtr:00000000 mmCfgBase: 80000000 mmCfgSize: 10000000 pchumaEn: 00 numaEn: 01 logParsing: 00 bdatEn: 00 consoleComPort: 3F8 struct sysHost.setup.mem { options: 10124FC8 TEMPHIGH_EN 0 PDWN_SR_CKE_MODE 0 OPP_SELF_REF_EN 1 MDLL_SHUT_DOWN_EN 0 PAGE_POLICY 0 MULTI_THREAD_MRC_EN 1 ADAPTIVE_PAGE_EN 1 SCRAMBLE_EN 1 MEM_FLOWS - X_OVER_EN 1 MEM_FLOWS - SENSE_AMP_EN 1 MEM_FLOWS - E_CMDCLK_EN 1 MEM_FLOWS - REC_EN_EN 1 MEM_FLOWS - RD_DQS_EN 1 MEM_FLOWS - WR_LVL_EN 1 MEM_FLOWS - WR_FLYBY_EN 1 MEM_FLOWS - WR_DQ_EN 1 MEM_FLOWS - CMDCLK_EN 1 MEM_FLOWS - RD_ADV_EN 1 MEM_FLOWS - WR_ADV_EN 1 MEM_FLOWS - RD_VREF_EN 1 MEM_FLOWS - WR_VREF_EN 1 MEM_FLOWS - RT_OPT_EN 1 MEM_FLOWS - RX_DESKEW_EN 1 MEM_FLOWS - TX_DESKEW_EN 1 MEM_FLOWS - TX_EQ_EN 1 MEM_FLOWS - IMODE_EN 1 MEM_FLOWS - EARLY_RID_EN 1 MEM_FLOWS - DQ_SWIZ_EN 1 MEM_FLOWS - LRBUF_RD_EN 1 MEM_FLOWS - LRBUF_WR_EN 1 MEM_FLOWS - RANK_MARGIN_EN 1 MEM_FLOWS - MEMINIT_EN 1 MEM_FLOWS - FNVSIMICSSIM_EN 1 MEM_FLOWS - MEMTEST_EN 1 MEM_FLOWS - NORMAL_MODE_EN 1 MEM_FLOWS - E_CTLCLK_EN 1 MEM_FLOWS_EXT - RX_CTLE_EN 1 MEM_FLOWS_EXT - PXC_EN 1 DDR_RESET_LOOP 0 NUMA_AWARE 1 DISABLE_WMM_OPP_READ 0 ECC_CHECK_EN 1 ECC_MIX_EN 0 BALANCED_4WAY_EN 0 CA_PARITY_EN 1 SPLIT_BELOW_4GB_EN 0 MARGIN_RANKS_EN 0 MEM_OVERRIDE_EN 0 DRAMDLL_OFF_PD_EN 0 MEMORY_TEST_EN 1 MEMORY_TEST_FAST_BOOT_EN 0 ATTEMPT_FAST_BOOT 0 ATTEMPT_FAST_BOOT_COLD 0 SW_MEMORY_TEST_EN 0 RMT_COLD_FAST_BOOT 0 DISPLAY_EYE_EN 0 PER_NIBBLE_EYE_EN 0 optionsExt: 1E41677F RD_VREF_EN 1 WR_VREF_EN 1 PDA_EN 1 TURNAROUND_OPT_EN 1 PER_BIT_MARGINS 1 RASmodeEx: 16 DMNDSCRB_EN 1 PTRLSCRB_EN 1 A7_MODE_EN 1 DEVTAGGING_EN 0 struct sysHost.setup.mem { bclk: 00 enforcePOR: 00 ddrFreqLimit: 00 chInter: 04 dimmTypeSupport: 02 vrefStepSize: 00 vrefAbsMaxSteps: 00 vrefOpLimitSteps:00 pdwnCkMode: 04 MemPwrSave: 05 pprType: 00 pprErrInjTest 00 ckeThrottling: 01 olttPeakBWLIMITPercent: 00 thermalThrottlingOptions: 0A CLTT_EN 1 OLTT_EN 0 MH_OUTPUT_EN 0 MH_SENSE_EN 1 DimmTempStatValue 00 dramraplen: 02 dramraplbwlimittf: 01 lrdimmModuleDelay: 00 customRefreshRate: 00 rxVrefTraining: 00 iotMemBufferRsvtn: 00 enforceThreeMonthTimeout: 01 rmtPatternLength:7FFF rmtPatternLengthExt(CMD/CTL):7FFF patrolScrubDuration:18 memTestLoops: 01 scrambleSeedLow: 0000A02B scrambleSeedHigh:0000D395 ADREn: 00 eraseArmNVDIMMS: 01 check_pm_sts: 00 check_platform_detect: 00 mcBgfThreshold: 00 normOppIntvl: 0400 SpdSmbSpeed: 00 struct ddrChannelSetup[00] { enabled: 01 numDimmSlots: 02 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[01] { enabled: 01 numDimmSlots: 02 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[02] { enabled: 00 numDimmSlots: 03 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct ddrChannelSetup[03] { enabled: 00 numDimmSlots: 03 batterybacked: 00 struct ddrDimmSetup[00] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[01] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 struct ddrDimmSetup[02] { mapOut[00]: 00 mapOut[01]: 00 mapOut[02]: 00 mapOut[03]: 00 }; NvDimmIdx: 00 }; struct memTiming { nCL: 00 nRP: 00 nRCD: 00 nRRD: 00 nWTR: 00 nRAS: 00 nRTP: 00 nWR: 00 nFAW: 00 nRC: 00 nCWL: 00 nCMDRate: 00 ddrFreqLimit: 00 vdd: 00 ucVolt: 00 casSup: 00 tREFI: 00 nRFC: 00 ddrFreq: 00 }; meRequestedSize: 00000000 }; serialDebugMsgLvl: 03 lowGap: 20 highGap: 01 mmiohSize: 00000100 isocEn: 00 dcaEn: 01 options (Chip): 10124FC8 CMD_CLK_TRAINING_EN 1 ALLOW2XREF_EN 1 RAS_TO_INDP_EN 0 BANK_XOR_EN 1 optionsExt (Chip): 1E41677F EARLY_CMD_CLK_TRAINING_EN 1 CMD_REF_EN 1 LRDIMM_BACKSIDE_VREF_EN 0 LRDIMM_WR_VREF_EN 1 LRDIMM_RD_VREF_EN 1 LRDIMM_RX_DQ_CENTERING 1 LRDIMM_TX_DQ_CENTERING 1 XOVER_EN 1 DRAM_RON_EN 0 RX_ODT_EN 0 RTT_WR_EN 0 MC_RON_EN 0 TX_EQ_EN 1 IMODE_EN 0 RX_CTLE_TRN_EN 1 SENSE_EN 1 ROUND_TRIP_LATENCY_EN 0 WR_CRC 0 DDR4_PLATFORM 0 0 0 RASmode: 00 RK_SPARE 0 CH_LOCKSTEP 0 CH_MIRROR 0 struct sysHost.setup.mem (Chip) { socketInter: 01 rankInter: 08 dramraplExtendedRange: 01 dramMaint: 02 dramMaintTRRMode: 01 dramMaintMode: 01 electricalThrottling: 00 altitude: 00 forceRankMult: 00 ceccWaChMask: 00 perBitDeSkew: 01 spareErrTh: 7FFF leakyBktLo: 28 leakyBktHi: 29 restoreNVDIMMS: 01 lockstepEnableX4: 00 numSparTrans: 0004 phaseShedding: 01 }; struct ddrIMCSetup[00] { enabled: 00000001 ddrVddLimit: 00 } }; //struct sysHost.setup forceColdBoot bit set Get socket PPIN N0: PPIN Hi = 0x25BEAAB, PPIN Lo = 0x51561DAB setupChanged: 1 Clearing the MRC NVRAM structure. sizeof sysNvram = 136441 bootMode = NormalBoot subBootMode = ColdBoot Dispatch Slaves -- Started Dispatch Slaves - 0ms Promote Warning Exception List -- Started Promote Warning Exception List - 0ms Initialize Throttling Early -- Started Initialize Throttling Early - 0ms Detect DIMM Configuration -- Started Checkpoint Code: Socket 0, 0xB0, 0x00, 0x0000 N0: IMC 0 SMB Clock Period = 0x2990 Socket | Channel | DIMM | Bus Segment | SMBUS Address -------|---------|------|--------------|-------------- 0 | 0 | 0 | 0 | 0 - Not Present 0 | 0 | 1 | 0 | 1 - Not Present 0 | 1 | 0 | 0 | 2 - Present N0.C1.D0: NVDIMM:N(380)=0x0 0 | 1 | 1 | 0 | 3 - Not Present Entering no zone 1 Detect DIMM Configuration - 298ms Get Slave Data -- Started Get Slave Data - 0ms Check POR Compatibility -- Started N0.C0: Channel disabled in MemSPD: mcId = 0, mcCh = 0 primaryWidthDDR4: 1, rowBitsDDR4: 15, columnBitsDDR4: 10, bankGroupsDDR4: 4 RDIMM population Check POR Compatibility - 14ms Initialize DDR Clocks -- Started Checkpoint Code: Socket 0, 0xB1, 0x00, 0x0000 GetPORDDRFreq returns ddrfreq = 10 ratioIndex = 10 Memory behind processor 0 running at DDR-2133 Entering no zone 2 Initialize DDR Clocks - 9ms mrcTask skipped; Index = 7 Send Status -- Started Send Status - 0ms Set Vdd -- Started N0: VR0 DDR Voltage: 1.20V Set Vdd - 2ms Check DIMM Ranks -- Started Checkpoint Code: Socket 0, 0xB4, 0x00, 0x0000 N0.C0.D0: dimmMtr: 0x000F000C N0.C0.D1: dimmMtr: 0x000F000C N0.C0.D2: dimmMtr: 0x000F000C N0.C1.D0: dimmMtr: 0x001E414C N0.C1.D1: dimmMtr: 0x000F0000 N0.C1.D2: dimmMtr: 0x000F0000 N0.C2.D0: dimmMtr: 0x000F000C N0.C2.D1: dimmMtr: 0x000F000C N0.C2.D2: dimmMtr: 0x000F000C N0.C3.D0: dimmMtr: 0x000F000C N0.C3.D1: dimmMtr: 0x000F000C N0.C3.D2: dimmMtr: 0x000F000C N0: Lockstep disabled, x4 DIMMs detected N0.C1.D0.R0: size 64 TechIndex 0x4, size 0x40 Entering no zone 3 Check DIMM Ranks - 45ms Send Data -- Started Send Data - 0ms Initialize Memory -- Started Initialize Memory - 0ms Gather SPD Data -- Started Checkpoint Code: Socket 0, 0xB2, 0x00, 0x0000 N0: SMB Clock Period = 2992 primaryWidthDDR4: 1, rowBitsDDR4: 15, columnBitsDDR4: 10, bankGroupsDDR4: 4 Entering no zone 4 Gather SPD Data - 25ms Configure XMP -- Started Configure XMP - 35ms Platform NVDIMM Status -- Started N0: CoreNVDIMMStatus Platform NVDIMM Status - 2ms Early Configuration -- Started Checkpoint Code: Socket 0, 0xB3, 0x00, 0x0000 Mem Timings: N0.C1: tCCD=4 N0.C1: tCCD_L=6 N0.C1: tCWL=14 N0.C1: tCL=15 N0.C1: tRP=15 N0.C1: tRCD=15 N0.C1: tRRD_S=4 N0.C1: tRRD_L=6 N0.C1: tWTR=3 N0.C1: tRAS=35 N0.C1: tRTP=8 N0.C1: tWR=16 N0.C1: tFAW=23 N0.C1: tRC=49 N0.C1: tRFC=278 N0.C1: casSup=0x7FF8 N0: xoverModeVar = 1 N0.C1: trrMode = 4 N0.C1: twoXRefresh = 0 N0.C1: t_stagger_ref = 0x3 N0.C1.D0.R0: DRAM Rtt_wr = 0, Rtt_park = 60, Rtt_nom = 60 Entering no zone 5 Early Configuration - 41ms DDRIO Initialization -- Started Checkpoint Code: Socket 0, 0xB6, 0x00, 0x0000 N0: Enable xovercal N0: Enabling xover 2:2 mode N0.C1: piDelay CMDn0 CMDn1 CMDs0 CMDs1 CTL CKE CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 13 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 18 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 19 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 20 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 22 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 23 1 1 1 1 1 1 1 X 0 1 1 1 1 1 1 1 X 0 1 1 1 1 1 1 1 24 1 1 1 1 1 1 1 X X 1 1 1 1 1 0 1 X X 1 1 1 1 1 0 1 25 1 0 1 1 1 1 1 X X 1 1 1 1 1 X 1 X X 1 1 1 1 1 X 1 26 0 X 1 1 1 1 1 X X 0 1 1 1 0 X 1 X X 0 1 1 1 0 X 1 27 X X 0 1 1 1 1 X X X 1 1 0 X X 1 X X X 1 1 0 X X 1 28 X X X 1 0 1 1 X X X 0 1 X X X 1 X X X 0 1 X X X 1 29 X X X 1 X 1 1 X X X X 1 X X X 1 X X X X 1 X X X 1 30 X X X 0 X 1 1 X X X X 0 X X X 0 X X X X 0 X X X 0 31 X X X X X 1 1 X X X X X X X X X X X X X X X X X X 32 X X X X X 0 1 X X X X X X X X X X X X X X X X X X 33 X X X X X X 0 X X X X X X X X X X X X X X X X X X breakOut set! N0.C1: Edge not found in first 0-63. Setting invert pi clk for second sweep N0.C1: InvertPiClk CLK CMDn0 CMDn1 CMDs0 CMDs1 CKE CTL 0 1 2 3 4 5 6 7 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N0.C1: piDelay CMDn0 CMDn1 CMDs0 CMDs1 CTL CKE CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 X X X X X X X X X X X X X X X X X X X X X X X X X breakOut set! N0.C1: CMDn0 CMDn1 CMDs0 CMDs1 CTL CKE CLK 0 1 2 3 4 5 6 7 8 26 27 25 30 28 32 33 22 23 26 28 30 27 26 24 30 Adding +112 to CMD, Adding +112 to CTL and reevaluating Invert Pi Clk. Adding +112 to CLK and reevaluating Invert Pi Clk. Adding +0 to TxDq and reevaluating InvertPiClk. Adding +33 to RcvEn. Adding +40 to TxDqs. Adding +32 to odd fubs. Adding +36 to TxPerBitDeskew. N0.C1: InvertPiClk CMDn0 CMDn1 CMDs0 CMDs1 CKE CTL CLK 0 1 2 3 4 5 6 7 8 n n n n n n n n n n n n n n n n N0.C1: CMDn0 CMDn1 CMDs0 CMDs1 CTL CKE CLK 0 1 2 3 4 5 6 7 8 10 43 41 46 44 16 49 22 55 26 60 30 59 26 56 30 N0: SetStartingCCC => CpuSku= 0, CtlEntries= 84 N0.C1: CTL Group 6, CTL side 1, piDelay 108 N0.C1: CTL Group 0, CTL side 1, piDelay 108 N0.C1: CTL Group 0, CTL side 0, piDelay 108 N0.C1: CTL Group 8, CTL side 1, piDelay 108 N0.C1: CTL Group 7, CTL side 1, piDelay 108 N0.C1: CTL Group 1, CTL side 1, piDelay 108 N0.C1: CTL Group 1, CTL side 0, piDelay 108 N0.C1: CTL Group 9, CTL side 1, piDelay 108 N0.C1: CTL Group 2, CTL side 1, piDelay 108 N0.C1: CTL Group 2, CTL side 0, piDelay 108 N0.C1: CTL Group 6, CTL side 0, piDelay 108 N0.C1: CTL Group 7, CTL side 0, piDelay 108 N0.C1: CTL Group 10, CTL side 1, piDelay 108 N0.C1: CTL Group 3, CTL side 1, piDelay 108 N0.C1: CTL Group 3, CTL side 0, piDelay 108 N0.C1: CTL Group 4, CTL side 0, piDelay 108 N0.C1: CTL Group 5, CTL side 0, piDelay 108 N0.C1: CTL Group 8, CTL side 0, piDelay 108 N0.C1: CTL Group 9, CTL side 0, piDelay 108 N0.C1: CTL Group 4, CTL side 1, piDelay 108 N0.C1: CTL Group 5, CTL side 1, piDelay 108 N0: SetStartingCCC => CpuSku= 0, CmdEntries= 48 N0.C1: CMD Group 0, CMD side 1, piDelay 103 N0.C1: CMD Group 3, CMD side 1, piDelay 103 N0.C1: CMD Group 4, CMD side 1, piDelay 103 N0.C1: CMD Group 1, CMD side 1, piDelay 103 N0.C1: CMD Group 1, CMD side 0, piDelay 103 N0.C1: CMD Group 0, CMD side 0, piDelay 103 N0.C1: CMD Group 3, CMD side 0, piDelay 103 N0.C1: CMD Group 4, CMD side 0, piDelay 103 N0.C1: CMD Group 2, CMD side 1, piDelay 103 N0.C1: CMD Group 2, CMD side 0, piDelay 103 N0.C1: CMD Group 5, CMD side 1, piDelay 103 N0.C1: CMD Group 5, CMD side 0, piDelay 103 N0: SetStartingCCC => CpuSku= 0, ClkEntries= 16 N0.C1: CLK 0, piDelay 128 N0.C1: CLK 2, piDelay 128 N0.C1: CLK 1, piDelay 128 N0.C1: CLK 3, piDelay 128 Reset All Channels JEDEC Init N0.C1.D0.R0: Write RC00 = 0x00 N0.C1.D0.R0: Write RC01 = 0x00 N0.C1.D0.R0: Write RC02 = 0x00 N0.C1.D0.R0: Write RC03 = 0x00 N0.C1.D0.R0: Write RC04 = 0x00 N0.C1.D0.R0: Write RC05 = 0x00 N0.C1.D0.R0: Write RC40 = 0x0F N0.C1.D0.R0: Write RC08 = 0x0B N0.C1.D0.R0: Write RC0A = 0x02 N0.C1.D0.R0: Write RC0B = 0x08 N0.C1.D0.R0: Write RC0C = 0x00 N0.C1.D0.R0: Write RC0E = 0x00 N0.C1.D0.R0: Write RC0F = 0x00 N0.C1.D0.R0: Write RC30 = 0x2C N0.C1.D0.R0: Write RC40 = 0x26 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x27 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x28 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x29 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x21 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x22 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x23 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x24 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x25 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC09 = 0x0C N0.C1.D0.R0: Write RC0D = 0x04 N0.C1: Issue ZQCL N0: Stage 1: Vref Offset Training Plot Of SumOfBits across Vref settings VR SA 0 1 2 3 4 5 6 7 8 N0.C1: 10 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 10 11 0 0 0 0 0 0 0 0 0 N0.C1: 11 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 11 11 0 0 0 0 0 0 0 0 0 N0.C1: 12 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 12 11 0 0 0 0 0 0 0 0 0 N0.C1: 13 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 13 11 0 0 0 0 0 0 0 0 0 N0.C1: 14 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 14 11 0 0 0 0 0 0 0 0 0 N0.C1: 15 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 15 11 0 0 0 0 0 0 0 0 0 N0.C1: 16 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 16 11 0 0 0 0 0 0 0 0 0 N0.C1: 17 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 17 11 0 0 0 0 0 0 0 0 0 N0.C1: 18 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 18 11 0 0 0 0 0 0 0 0 0 N0.C1: 19 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 19 11 0 0 0 0 0 0 0 0 0 N0.C1: 20 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 20 11 0 0 0 0 0 0 0 0 0 N0.C1: 21 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 21 11 0 0 0 0 0 0 0 0 0 N0.C1: 22 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 22 11 0 0 0 0 0 0 0 0 0 N0.C1: 23 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 23 11 0 0 0 0 0 0 0 0 0 N0.C1: 24 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 24 11 0 0 0 0 0 0 0 0 0 N0.C1: 25 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 25 11 0 0 0 0 0 0 0 0 0 N0.C1: 26 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 26 11 0 0 0 0 0 0 0 0 0 N0.C1: 27 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 27 11 0 0 0 0 0 0 0 0 0 N0.C1: 28 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 28 11 0 0 0 0 0 0 0 0 0 N0.C1: 29 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 29 11 0 0 0 0 0 0 0 0 0 N0.C1: 30 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 30 11 0 0 0 0 0 0 0 0 0 N0.C1: 31 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 31 11 0 0 0 0 0 0 0 0 0 N0.C1: 32 19 -8 -8 -8 -8 -8 -8 -8 -8 -8 N0.C1: 32 11 0 0 0 0 0 0 0 0 0 N0.C1: 33 19 -8 -8 -8 -8 -7 -8 -8 -8 -8 N0.C1: 33 11 0 0 0 0 1 0 0 0 0 N0.C1: 34 19 -8 -8 -8 -8 -7 -8 -8 -8 -8 N0.C1: 34 11 0 0 0 0 1 0 0 0 0 N0.C1: 35 19 -8 -8 -8 -8 -6 -8 -8 -8 -8 N0.C1: 35 11 0 0 0 0 2 0 0 0 0 N0.C1: 36 19 -8 -7 -7 -8 -5 -7 -7 -7 -8 N0.C1: 36 11 0 1 1 0 3 1 1 1 0 N0.C1: 37 19 -6 -4 -6 -8 -4 -7 -6 -6 -8 N0.C1: 37 11 2 4 2 0 4 1 2 2 0 N0.C1: 38 19 -3 -4 -5 -8 -4 -4 -4 -4 -6 N0.C1: 38 11 5 4 3 0 4 4 4 4 2 N0.C1: 39 19 -3 -4 -3 -2 -4 -3 -3 -2 -4 N0.C1: 39 11 5 4 5 6 4 5 5 6 4 N0.C1: 40 19 -3 -3 -2 -1 -1 -2 -1 -1 -1 N0.C1: 40 11 5 5 6 7 7 6 7 7 7 N0.C1: 41 19 -2 -2 0 0 0 -1 -1 0 0 N0.C1: 41 11 6 6 8 8 8 7 7 8 8 N0.C1: 42 19 0 0 0 0 0 0 0 0 0 N0.C1: 42 11 8 8 8 8 8 8 8 8 8 N0.C1: 43 19 0 0 0 0 0 0 0 0 0 N0.C1: 43 11 8 8 8 8 8 8 8 8 8 N0.C1: 44 19 0 0 0 0 0 0 0 0 0 N0.C1: 44 11 8 8 8 8 8 8 8 8 8 N0.C1: 45 19 0 0 0 0 0 0 0 0 0 N0.C1: 45 11 8 8 8 8 8 8 8 8 8 N0.C1: 46 19 0 0 0 0 0 0 0 0 0 N0.C1: 46 11 8 8 8 8 8 8 8 8 8 N0.C1: 47 19 0 0 0 0 0 0 0 0 0 N0.C1: 47 11 8 8 8 8 8 8 8 8 8 N0.C1: 48 19 0 0 0 0 0 0 0 0 0 N0.C1: 48 11 8 8 8 8 7 8 8 8 8 N0.C1: 49 19 0 0 0 0 0 0 0 0 0 N0.C1: 49 11 8 8 8 8 7 8 8 8 8 N0.C1: 50 19 0 0 0 0 0 0 0 0 0 N0.C1: 50 11 8 8 7 8 6 8 8 7 8 N0.C1: 51 19 0 0 0 0 0 0 0 0 0 N0.C1: 51 11 8 4 7 8 5 7 7 7 8 N0.C1: 52 19 0 0 0 0 0 0 0 0 0 N0.C1: 52 11 5 4 5 8 5 7 5 5 6 N0.C1: 53 19 0 0 0 0 0 0 0 0 0 N0.C1: 53 11 3 4 5 8 4 5 4 3 5 N0.C1: 54 19 0 0 0 0 0 0 0 0 0 N0.C1: 54 11 3 4 3 3 3 3 3 2 4 N0.C1: 55 19 0 0 0 0 0 0 0 0 0 N0.C1: 55 11 3 3 0 1 1 2 1 0 0 N0.C1: 56 19 0 0 0 0 0 0 0 0 0 N0.C1: 56 11 1 2 0 0 0 0 0 0 0 N0.C1: 57 19 0 0 0 0 0 0 0 0 0 N0.C1: 57 11 0 0 0 0 0 0 0 0 0 N0.C1: 58 19 0 0 0 0 0 0 0 0 0 N0.C1: 58 11 0 0 0 0 0 0 0 0 0 N0.C1: 59 19 0 0 0 0 0 0 0 0 0 N0.C1: 59 11 0 0 0 0 0 0 0 0 0 N0.C1: 60 19 0 0 0 0 0 0 0 0 0 N0.C1: 60 11 0 0 0 0 0 0 0 0 0 N0.C1: 61 19 0 0 0 0 0 0 0 0 0 N0.C1: 61 11 0 0 0 0 0 0 0 0 0 N0.C1: 62 19 0 0 0 0 0 0 0 0 0 N0.C1: 62 11 0 0 0 0 0 0 0 0 0 N0.C1: 63 19 0 0 0 0 0 0 0 0 0 N0.C1: 63 11 0 0 0 0 0 0 0 0 0 N0.C1: 64 19 0 0 0 0 0 0 0 0 0 N0.C1: 64 11 0 0 0 0 0 0 0 0 0 N0.C1: 65 19 0 0 0 0 0 0 0 0 0 N0.C1: 65 11 0 0 0 0 0 0 0 0 0 N0.C1: 66 19 0 0 0 0 0 0 0 0 0 N0.C1: 66 11 0 0 0 0 0 0 0 0 0 N0.C1: 67 19 0 0 0 0 0 0 0 0 0 N0.C1: 67 11 0 0 0 0 0 0 0 0 0 N0.C1: 68 19 0 0 0 0 0 0 0 0 0 N0.C1: 68 11 0 0 0 0 0 0 0 0 0 N0.C1: 69 19 0 0 0 0 0 0 0 0 0 N0.C1: 69 11 0 0 0 0 0 0 0 0 0 N0.C1: 70 19 0 0 0 0 0 0 0 0 0 N0.C1: 70 11 0 0 0 0 0 0 0 0 0 N0.C1: 71 19 0 0 0 0 0 0 0 0 0 N0.C1: 71 11 0 0 0 0 0 0 0 0 0 N0.C1: 72 19 0 0 0 0 0 0 0 0 0 N0.C1: 72 11 0 0 0 0 0 0 0 0 0 N0.C1: 73 19 0 0 0 0 0 0 0 0 0 N0.C1: 73 11 0 0 0 0 0 0 0 0 0 N0.C1: 74 19 0 0 0 0 0 0 0 0 0 N0.C1: 74 11 0 0 0 0 0 0 0 0 0 N0.C1: Vref 47 47 46 48 45 47 47 46 47 Stage 2: SampOffset Training 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 SA 01230123 01230123 01230123 01230123 01230123 01230123 01230123 01230123 01230123 N0.C1: 0 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 1 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 2 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 3 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 4 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 5 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 6 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 7 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 8 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 9 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 10 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 11 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 12 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111111 N0.C1: 13 11110101 11111111 11111111 11111111 11111111 11011111 11111101 11110111 11111111 N0.C1: 14 10000100 11101001 11101001 10010111 10011001 11010111 00101101 10110110 11111110 N0.C1: 15 10000100 11000000 11100001 10000000 10001001 11000110 00000100 00010100 11000000 N0.C1: 16 10000000 00000000 00100000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 17 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 18 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 19 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 20 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 21 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 22 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 23 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 24 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 25 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 26 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 27 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 28 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 29 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 30 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 N0.C1: 31 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 BitSAmp bit: 0 1 2 3 N0.C1: Nibble 0: 16 13 13 13 N0.C1: Nibble 1: 12 15 12 13 N0.C1: Nibble 2: 15 15 14 13 N0.C1: Nibble 3: 14 13 13 14 N0.C1: Nibble 4: 15 15 16 13 N0.C1: Nibble 5: 14 13 13 15 N0.C1: Nibble 6: 15 13 13 14 N0.C1: Nibble 7: 13 14 14 14 N0.C1: Nibble 8: 15 13 13 14 N0.C1: Nibble 9: 15 13 13 15 N0.C1: Nibble 10: 15 15 12 14 N0.C1: Nibble 11: 13 15 15 14 N0.C1: Nibble 12: 13 13 14 13 N0.C1: Nibble 13: 14 15 12 14 N0.C1: Nibble 14: 14 13 14 15 N0.C1: Nibble 15: 12 15 14 13 N0.C1: Nibble 16: 15 15 14 14 N0.C1: Nibble 17: 14 14 14 13 N0: SenseAmpOffset - 929ms N0.C1: Number of DIMMS in channel: 1 Entering no zone 6 DDRIO Initialization - 1778ms Pre-Training Initialization -- Started Pre-Training Initialization - 0ms Early CTL/CLK -- Started Checkpoint Code: Socket 0, 0xB7, 0x1A, 0x0000 N0.D0.R0: RecEn Pi Scanning: Summary: Early Ctl Clk Receive Enable Pi S0, Ch1, DIMM0, Rank0 ------------------------------------------------------------------------------------- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 1 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 2 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 3 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 4 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 5 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 6 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 7 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 8 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 9 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 10 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 11 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 12 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 13 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 14 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 15 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 16 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 17 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 18 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 19 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 20 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 21 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 22 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 1 0 23 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 24 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 25 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 26 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 27 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 28 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 29 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 30 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 31 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 32 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 33 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 34 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 35 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 36 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 37 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 38 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 39 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 40 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 41 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 42 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 43 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 44 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 45 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 46 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 47 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 48 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 49 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 50 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 51 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 52 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 53 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 54 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 55 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 56 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 57 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 58 0 0 0 1 1 1 0 0 1 0 0 0 0 1 1 0 0 1 59 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 60 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 61 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 62 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 63 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 64 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 65 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 66 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 67 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 68 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 69 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 70 0 0 0 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 71 0 0 0 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 72 0 0 0 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 73 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 74 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 75 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 76 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 77 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 78 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 79 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 80 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 1 0 1 81 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 1 0 1 82 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 83 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 84 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 85 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 86 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 87 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 88 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 89 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 90 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 91 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 92 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 93 0 0 1 1 0 1 1 0 0 0 0 1 1 0 1 1 0 1 94 0 0 1 1 0 1 1 0 0 0 0 1 1 0 1 1 0 0 95 0 0 1 1 0 1 1 0 0 0 0 1 1 0 1 1 0 0 96 0 0 1 1 0 1 1 1 0 0 0 1 1 0 1 1 0 0 97 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 98 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 99 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 100 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 101 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 102 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 103 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 104 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 105 0 1 1 0 0 0 1 1 0 0 0 1 1 0 1 1 0 0 106 0 1 1 0 0 0 1 1 0 0 0 1 1 0 1 1 1 0 107 0 1 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 0 108 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 109 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 110 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 111 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 112 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 113 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 114 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 115 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 116 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 117 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 118 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 119 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 120 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 121 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 122 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 123 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 124 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 125 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 126 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 127 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 ---------------------------------------------------------------------------- RE: 118 97 73 47 25 39 70 96 27 1 107 84 59 37 53 80 106 39 CP: 18 125 102 76 53 68 98 124 54 29 8 112 87 65 80 108 6 66 FE: 46 25 3 105 82 97 127 24 82 57 37 12 116 93 108 9 35 94 PW: 56 56 58 58 57 58 57 56 55 56 58 56 57 56 55 57 57 55 N0.C1.D0.R0.S00: Rec En Delay 18 N0.C1.D0.R0.S01: Rec En Delay 125 N0.C1.D0.R0.S02: Rec En Delay 102 N0.C1.D0.R0.S03: Rec En Delay 76 N0.C1.D0.R0.S04: Rec En Delay 53 N0.C1.D0.R0.S05: Rec En Delay 68 N0.C1.D0.R0.S06: Rec En Delay 98 N0.C1.D0.R0.S07: Rec En Delay 124 N0.C1.D0.R0.S08: Rec En Delay 54 N0.C1.D0.R0.S09: Rec En Delay 29 N0.C1.D0.R0.S10: Rec En Delay 8 N0.C1.D0.R0.S11: Rec En Delay 112 N0.C1.D0.R0.S12: Rec En Delay 87 N0.C1.D0.R0.S13: Rec En Delay 65 N0.C1.D0.R0.S14: Rec En Delay 80 N0.C1.D0.R0.S15: Rec En Delay 108 N0.C1.D0.R0.S16: Rec En Delay 6 N0.C1.D0.R0.S17: Rec En Delay 66 N0.C1.D0.R0: Round trip latency = 73 IO latency = 4 N0.D0.R0: Round trip latency N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 71 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 69 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 67 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 65 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 63 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 61 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 59 N0.C1.D0.R0: IO Latency = 6 zeroFlag = 0x10601, allZeros[1] = 0x3FFFF N0.C1.D0.R0.S00: Rec En Delay = 146 N0.C1.D0.R0.S09: Rec En Delay = 157 N0.C1.D0.R0.S10: Rec En Delay = 136 N0.C1.D0.R0.S16: Rec En Delay = 134 N0.C1.D0.R0: Round trip latency: Found all zeros Early CTL CLK Receive Enable Summary ------------------------ START_DATA_EARLY_CTL_CLK_REC_EN N0.C1.D0.R0.S00: Pi setting = 178 N0.C1.D0.R0.S01: Pi setting = 157 N0.C1.D0.R0.S02: Pi setting = 134 N0.C1.D0.R0.S03: Pi setting = 108 N0.C1.D0.R0.S04: Pi setting = 85 N0.C1.D0.R0.S05: Pi setting = 100 N0.C1.D0.R0.S06: Pi setting = 130 N0.C1.D0.R0.S07: Pi setting = 156 N0.C1.D0.R0.S08: Pi setting = 86 N0.C1.D0.R0.S09: Pi setting = 189 N0.C1.D0.R0.S10: Pi setting = 168 N0.C1.D0.R0.S11: Pi setting = 144 N0.C1.D0.R0.S12: Pi setting = 119 N0.C1.D0.R0.S13: Pi setting = 97 N0.C1.D0.R0.S14: Pi setting = 112 N0.C1.D0.R0.S15: Pi setting = 140 N0.C1.D0.R0.S16: Pi setting = 166 N0.C1.D0.R0.S17: Pi setting = 98 N0.C1.D0.R0: IO Latency = 6 N0.C1.D0.R0: Round Trip = 59 STOP_DATA_EARLY_CTL_CLK_REC_EN Starting Senseamp and ODT delay calculations ------------------------------------------------------------ N0.C1.S00: MaxRcven=178, New Senseamp/Odt delay=14 N0.C1.S01: MaxRcven=157, New Senseamp/Odt delay=14 N0.C1.S02: MaxRcven=134, New Senseamp/Odt delay=14 N0.C1.S03: MaxRcven=108, New Senseamp/Odt delay=14 N0.C1.S04: MaxRcven= 85, New Senseamp/Odt delay=14 N0.C1.S05: MaxRcven=100, New Senseamp/Odt delay=14 N0.C1.S06: MaxRcven=130, New Senseamp/Odt delay=14 N0.C1.S07: MaxRcven=156, New Senseamp/Odt delay=14 N0.C1.S08: MaxRcven= 86, New Senseamp/Odt delay=14 N0.C1.S09: MaxRcven=189, New Senseamp/Odt delay=14 N0.C1.S10: MaxRcven=168, New Senseamp/Odt delay=14 N0.C1.S11: MaxRcven=144, New Senseamp/Odt delay=14 N0.C1.S12: MaxRcven=119, New Senseamp/Odt delay=14 N0.C1.S13: MaxRcven= 97, New Senseamp/Odt delay=14 N0.C1.S14: MaxRcven=112, New Senseamp/Odt delay=14 N0.C1.S15: MaxRcven=140, New Senseamp/Odt delay=14 N0.C1.S16: MaxRcven=166, New Senseamp/Odt delay=14 N0.C1.S17: MaxRcven= 98, New Senseamp/Odt delay=14 START_DATA_CMD 0n 1n 2n 3n 4n 5n 0s 1s 2s 3s 4s 5s N0.C1: 103 103 103 103 103 103 103 103 103 103 103 103 START_DATA_CLK 0 1 2 3 N0.C1: 0 0 0 0 START_DATA_CTL 0n 1n 2n 3n 4n 5n 6n 7n 8n 9n 0s 1s 2s 3s 4s 5s 6s 7s 8s 9s 10s N0.C1: 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 N0.C1.D0.R0: le = -64 - re = 65 width = 129 N0.C1: Ctl group 0, left edge = -64 - right edge = 65 offset == 0 width =129 START_DATA_CMD 0n 1n 2n 3n 4n 5n 0s 1s 2s 3s 4s 5s N0.C1: 103 103 103 103 103 103 103 103 103 103 103 103 START_DATA_CLK 0 1 2 3 N0.C1: 0 0 0 0 START_DATA_CTL 0n 1n 2n 3n 4n 5n 6n 7n 8n 9n 0s 1s 2s 3s 4s 5s 6s 7s 8s 9s 10s N0.C1: 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 Entering no zone 7 Early CTL/CLK - 1500ms Early CMD/CLK -- Started Checkpoint Code: Socket 0, 0xB7, 0x0C, 0x0000 START_PARITY_CMD_CLK N0.C1: Setting cmd timing to 0 N0.C1.D0.R0: Setting RTL to 55 N0.C1.D0.R0: Write RC0E = 0x01 N0: Enabling C/A Parity N0.C1.D0.R0: PAR -> **********************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000****************************************************************************************** N0.C1.D0.R0: le = -69 - re = 62 N0.C1.D0.R0: CAS_N -> **********************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************************** N0.C1.D0.R0: le = -69 - re = 60 N0.C1.D0.R0: A13 -> **************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000**************************************************************************************** N0.C1.D0.R0: le = -65 - re = 64 N0.C1.D0.R0: RAS_N -> ************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000****************************************************************************************** N0.C1.D0.R0: le = -67 - re = 62 N0.C1.D0.R0: WE_N -> **********************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************************** N0.C1.D0.R0: le = -69 - re = 60 N0.C1.D0.R0: A10 -> ************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************************** N0.C1.D0.R0: le = -67 - re = 60 N0.C1.D0.R0: BA1 -> **************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000****************************************************************************************** N0.C1.D0.R0: le = -65 - re = 62 N0.C1.D0.R0: A0 -> ******************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000********************************************************************************************** N0.C1.D0.R0: le = -73 - re = 58 N0.C1.D0.R0: BA0 -> **********************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************************** N0.C1.D0.R0: le = -69 - re = 60 N0.C1.D0.R0: A1 -> **********************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************************** N0.C1.D0.R0: le = -69 - re = 60 N0.C1.D0.R0: A3 -> **********************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************************** N0.C1.D0.R0: le = -69 - re = 60 N0.C1.D0.R0: A2 -> ********************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000********************************************************************************************** N0.C1.D0.R0: le = -71 - re = 58 N0.C1.D0.R0: A4 -> ************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000****************************************************************************************** N0.C1.D0.R0: le = -67 - re = 62 N0.C1.D0.R0: A5 -> ************************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000****************************************************************************************** N0.C1.D0.R0: le = -67 - re = 62 N0.C1.D0.R0: A6 -> ************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************************** N0.C1.D0.R0: le = -67 - re = 60 N0.C1.D0.R0: A7 -> ********************************000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************************** N0.C1.D0.R0: le = -71 - re = 60 N0.C1.D0.R0: A8 -> **********************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000********************************************************************************************** N0.C1.D0.R0: le = -69 - re = 58 N0.C1.D0.R0: A9 -> ************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************************** N0.C1.D0.R0: le = -67 - re = 60 N0.C1.D0.R0: A12 -> **********************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************************** N0.C1.D0.R0: le = -69 - re = 60 N0.C1.D0.R0: A11 -> ************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************************** N0.C1.D0.R0: le = -67 - re = 60 N0.C1.D0.R0: BG1 -> ********************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000********************************************************************************************** N0.C1.D0.R0: le = -71 - re = 58 N0.C1.D0.R0: ACT_N -> **********************************0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************************** N0.C1.D0.R0: le = -69 - re = 60 N0.C1.D0.R0: BG0 -> ************************************00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000******************************************************************************************** N0.C1.D0.R0: le = -67 - re = 60 N0.C1.D0.R0: Write RC0E = 0x00 N0.C1: PAR: CMD Pi Group 9 clk 0: le -69 re = 62, cmdLeft = -69 cmdRight = 62 N0.C1: CAS_N: CMD Pi Group 7 clk 0: le -69 re = 60, cmdLeft = -69 cmdRight = 60 N0.C1: A13: CMD Pi Group 11 clk 0: le -65 re = 64, cmdLeft = -65 cmdRight = 64 N0.C1: RAS_N: CMD Pi Group 1 clk 0: le -67 re = 62, cmdLeft = -67 cmdRight = 62 N0.C1: WE_N: CMD Pi Group 7 clk 0: le -69 re = 60, cmdLeft = -69 cmdRight = 60 N0.C1: A10: CMD Pi Group 1 clk 0: le -67 re = 60, cmdLeft = -67 cmdRight = 60 N0.C1: BA1: CMD Pi Group 11 clk 0: le -65 re = 62, cmdLeft = -65 cmdRight = 62 N0.C1: A0: CMD Pi Group 9 clk 0: le -73 re = 58, cmdLeft = -69 cmdRight = 58 N0.C1: BA0: CMD Pi Group 4 clk 0: le -69 re = 60, cmdLeft = -69 cmdRight = 60 N0.C1: A1: CMD Pi Group 3 clk 0: le -69 re = 60, cmdLeft = -69 cmdRight = 60 N0.C1: A3: CMD Pi Group 8 clk 0: le -69 re = 60, cmdLeft = -69 cmdRight = 60 N0.C1: A2: CMD Pi Group 3 clk 0: le -71 re = 58, cmdLeft = -69 cmdRight = 58 N0.C1: A4: CMD Pi Group 8 clk 0: le -67 re = 62, cmdLeft = -67 cmdRight = 60 N0.C1: A5: CMD Pi Group 2 clk 0: le -67 re = 62, cmdLeft = -67 cmdRight = 62 N0.C1: A6: CMD Pi Group 2 clk 0: le -67 re = 60, cmdLeft = -67 cmdRight = 60 N0.C1: A7: CMD Pi Group 6 clk 0: le -71 re = 60, cmdLeft = -71 cmdRight = 60 N0.C1: A8: CMD Pi Group 6 clk 0: le -69 re = 58, cmdLeft = -69 cmdRight = 58 N0.C1: A9: CMD Pi Group 0 clk 0: le -67 re = 60, cmdLeft = -67 cmdRight = 60 N0.C1: A12: CMD Pi Group 4 clk 0: le -69 re = 60, cmdLeft = -69 cmdRight = 60 N0.C1: A11: CMD Pi Group 0 clk 0: le -67 re = 60, cmdLeft = -67 cmdRight = 60 N0.C1: BG1: CMD Pi Group 10 clk 0: le -71 re = 58, cmdLeft = -71 cmdRight = 58 N0.C1: ACT_N: CMD Pi Group 5 clk 0: le -69 re = 60, cmdLeft = -69 cmdRight = 60 N0.C1: BG0: CMD Pi Group 10 clk 0: le -67 re = 60, cmdLeft = -67 cmdRight = 58 N0.C1: CS2_N: CMD Pi Group 12 clk 0: le -511 re = 511, cmdLeft = -255 cmdRight = 255 N0.C1: CS3_N: CMD Pi Group 12 clk 0: le -511 re = 511, cmdLeft = -255 cmdRight = 255 N0.C1: C2: CMD Pi Group 5 clk 0: le -511 re = 511, cmdLeft = -69 cmdRight = 60 N0.C1: CMD Pi Group 0 clk 0 cmdOffset -3 N0.C1: CMD Pi Group 1 clk 0 cmdOffset -3 N0.C1: CMD Pi Group 2 clk 0 cmdOffset -3 N0.C1: CMD Pi Group 3 clk 0 cmdOffset -5 N0.C1: CMD Pi Group 4 clk 0 cmdOffset -4 N0.C1: CMD Pi Group 5 clk 0 cmdOffset -4 N0.C1: CMD Pi Group 6 clk 0 cmdOffset -5 N0.C1: CMD Pi Group 7 clk 0 cmdOffset -4 N0.C1: CMD Pi Group 8 clk 0 cmdOffset -3 N0.C1: CMD Pi Group 9 clk 0 cmdOffset -5 N0.C1: CMD Pi Group 10 clk 0 cmdOffset -4 N0.C1: CMD Pi Group 11 clk 0 cmdOffset -1 N0.C1: CMD Pi Group 12 clk 0 cmdOffset 0 N0.C1: CMD Pi Group 13 clk 0 cmdOffset 0 N0.C1: CMD Pi Group 14 clk 0 cmdOffset 0 N0.C1: CMD Pi Group 0: maxOffset = -3, minOffset = -3, cmdOffset = -3 N0.C1: CMD Pi Group 1: maxOffset = -3, minOffset = -3, cmdOffset = -3 N0.C1: CMD Pi Group 2: maxOffset = -3, minOffset = -3, cmdOffset = -3 N0.C1: CMD Pi Group 3: maxOffset = -5, minOffset = -5, cmdOffset = -5 N0.C1: CMD Pi Group 4: maxOffset = -4, minOffset = -4, cmdOffset = -4 N0.C1: CMD Pi Group 5: maxOffset = -4, minOffset = -4, cmdOffset = -4 N0.C1: CMD Pi Group 6: maxOffset = -5, minOffset = -5, cmdOffset = -5 N0.C1: CMD Pi Group 7: maxOffset = -4, minOffset = -4, cmdOffset = -4 N0.C1: CMD Pi Group 8: maxOffset = -3, minOffset = -3, cmdOffset = -3 N0.C1: CMD Pi Group 9: maxOffset = -5, minOffset = -5, cmdOffset = -5 N0.C1: CMD Pi Group 10: maxOffset = -4, minOffset = -4, cmdOffset = -4 N0.C1: CMD Pi Group 11: maxOffset = -1, minOffset = -1, cmdOffset = -1 N0.C1: CMD Pi Group 0: maxOffset = 0, minOffset = 0, cmdOffset = 0 N0.C1: CMD Pi Group 1: maxOffset = 0, minOffset = 0, cmdOffset = 0 N0.C1: CMD Pi Group 2: maxOffset = 0, minOffset = 0, cmdOffset = 0 N0.C1: <--CMD Pi Group 0 clk 0: cmdLeft -64 - cmdRight 63 N0.C1: <--CMD Pi Group 1 clk 0: cmdLeft -64 - cmdRight 63 N0.C1: <--CMD Pi Group 2 clk 0: cmdLeft -64 - cmdRight 63 N0.C1: <--CMD Pi Group 3 clk 0: cmdLeft -64 - cmdRight 63 N0.C1: <--CMD Pi Group 4 clk 0: cmdLeft -65 - cmdRight 64 N0.C1: <--CMD Pi Group 5 clk 0: cmdLeft -65 - cmdRight 64 N0.C1: <--CMD Pi Group 6 clk 0: cmdLeft -64 - cmdRight 63 N0.C1: <--CMD Pi Group 7 clk 0: cmdLeft -65 - cmdRight 64 N0.C1: <--CMD Pi Group 8 clk 0: cmdLeft -64 - cmdRight 63 N0.C1: <--CMD Pi Group 9 clk 0: cmdLeft -64 - cmdRight 63 N0.C1: <--CMD Pi Group 10 clk 0: cmdLeft -63 - cmdRight 62 N0.C1: <--CMD Pi Group 11 clk 0: cmdLeft -64 - cmdRight 63 N0.C1: <--CMD Pi Group 12 clk 0: cmdLeft -255 - cmdRight 255 N0.C1: <--CMD Pi Group 13 clk 0: cmdLeft -255 - cmdRight 255 N0.C1: <--CMD Pi Group 14 clk 0: cmdLeft -255 - cmdRight 255 N0.C1: <----clk 0 ckOffset 0: -(maxLeftOffset:-63 + minRightOffset:62) / 2 START_DATA_CMD 0n 1n 2n 3n 4n 5n 0s 1s 2s 3s 4s 5s N0.C1: 100 100 99 98 100 99 100 98 99 99 98 102 START_DATA_CLK 0 1 2 3 N0.C1: 0 0 0 0 START_DATA_CTL 0n 1n 2n 3n 4n 5n 6n 7n 8n 9n 0s 1s 2s 3s 4s 5s 6s 7s 8s 9s 10s N0.C1: 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 Entering no zone 8 Early CMD/CLK - 1368ms Lrdimm BS Phase RX -- Started Checkpoint Code: Socket 0, 0xB7, 0x14, 0x0000 Entering no zone 9 Lrdimm BS Phase RX - 0ms Lrdimm BS Cycle RX -- Started Checkpoint Code: Socket 0, 0xB7, 0x15, 0x0000 Entering no zone 10 Lrdimm BS Cycle RX - 0ms Lrdimm BS Delay RX -- Started Checkpoint Code: Socket 0, 0xB7, 0x16, 0x0000 Entering no zone 11 Lrdimm BS Delay RX - 0ms Receive Enable -- Started Checkpoint Code: Socket 0, 0xB7, 0x00, 0x0000 N0.D0.R0: RecEn Pi Scanning: Summary: Receive Enable Pi S0, Ch1, DIMM0, Rank0 ------------------------------------------------------------------------------------- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 1 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 2 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 3 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 4 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 5 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 6 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 7 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 8 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 1 1 0 9 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 10 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 11 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 12 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 13 1 1 0 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 14 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 15 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 16 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 17 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 18 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 19 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 20 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 21 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 22 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 23 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 1 0 24 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 25 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 26 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 27 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 28 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 29 1 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 30 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 31 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 32 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 33 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 1 0 34 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 0 35 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 36 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 37 1 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 38 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 39 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 40 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 41 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 42 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 43 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 44 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 45 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 46 1 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 47 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 48 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 49 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 50 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 51 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 1 52 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 53 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 54 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 55 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 56 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 57 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 58 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 1 59 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 60 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 61 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 62 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 63 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 64 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 65 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 66 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 67 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 68 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 69 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 70 0 0 0 1 1 1 0 0 1 0 0 0 1 1 1 0 0 1 71 0 0 0 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 72 0 0 0 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 73 0 0 0 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 74 0 0 0 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 75 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 76 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 77 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 78 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 79 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 80 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 81 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 0 0 1 82 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 0 0 1 83 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 84 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 85 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 1 0 1 86 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 87 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 88 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 89 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 90 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 91 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 92 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 93 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 1 0 1 94 0 0 1 1 0 1 1 0 0 0 0 1 1 0 1 1 0 0 95 0 0 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 96 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 97 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 98 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 99 0 0 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 100 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 101 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 102 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 103 0 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 104 0 1 1 0 0 0 1 1 0 0 0 1 1 0 1 1 1 0 105 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 106 0 1 1 0 0 0 1 1 0 0 0 1 1 0 1 1 1 0 107 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 1 0 108 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 109 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 110 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 111 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 112 0 1 1 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 113 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 114 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 115 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 116 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 117 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 118 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 119 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 120 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 121 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 122 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 123 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 124 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 125 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 126 1 1 1 0 0 0 1 1 0 0 1 1 0 0 0 1 1 0 127 1 1 1 0 0 0 0 1 0 0 1 1 0 0 0 1 1 0 ---------------------------------------------------------------------------- RE: 120 100 75 48 25 41 71 95 30 0 108 86 59 38 52 83 106 41 CP: 19 126 103 76 53 68 99 123 55 29 7 114 86 66 78 110 6 67 FE: 47 25 3 104 81 95 127 24 81 59 35 14 113 94 105 9 34 94 PW: 55 53 56 56 56 54 56 57 51 59 55 56 54 56 53 54 56 53 N0.C1.D0.R0.S00: Rec En Delay 19 N0.C1.D0.R0.S01: Rec En Delay 126 N0.C1.D0.R0.S02: Rec En Delay 103 N0.C1.D0.R0.S03: Rec En Delay 76 N0.C1.D0.R0.S04: Rec En Delay 53 N0.C1.D0.R0.S05: Rec En Delay 68 N0.C1.D0.R0.S06: Rec En Delay 99 N0.C1.D0.R0.S07: Rec En Delay 123 N0.C1.D0.R0.S08: Rec En Delay 55 N0.C1.D0.R0.S09: Rec En Delay 29 N0.C1.D0.R0.S10: Rec En Delay 7 N0.C1.D0.R0.S11: Rec En Delay 114 N0.C1.D0.R0.S12: Rec En Delay 86 N0.C1.D0.R0.S13: Rec En Delay 66 N0.C1.D0.R0.S14: Rec En Delay 78 N0.C1.D0.R0.S15: Rec En Delay 110 N0.C1.D0.R0.S16: Rec En Delay 6 N0.C1.D0.R0.S17: Rec En Delay 67 N0.C1.D0.R0: Round trip latency = 73 IO latency = 4 N0.D0.R0: Round trip latency N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 71 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 69 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 67 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 65 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 63 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 61 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 59 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 57 N0.C1.D0.R0: Round trip latency: No zeros found Round trip latency = 55 N0.C1.D0.R0: IO Latency = 6 zeroFlag = 0x10601, allZeros[1] = 0x3FFFF N0.C1.D0.R0.S00: Rec En Delay = 147 N0.C1.D0.R0.S09: Rec En Delay = 157 N0.C1.D0.R0.S10: Rec En Delay = 135 N0.C1.D0.R0.S16: Rec En Delay = 134 N0.C1.D0.R0: Round trip latency: Found all zeros Receive Enable Summary ------------------------ START_DATA_REC_EN_BASIC N0.C1.D0.R0.S00: Pi setting = 179 N0.C1.D0.R0.S01: Pi setting = 158 N0.C1.D0.R0.S02: Pi setting = 135 N0.C1.D0.R0.S03: Pi setting = 108 N0.C1.D0.R0.S04: Pi setting = 85 N0.C1.D0.R0.S05: Pi setting = 100 N0.C1.D0.R0.S06: Pi setting = 131 N0.C1.D0.R0.S07: Pi setting = 155 N0.C1.D0.R0.S08: Pi setting = 87 N0.C1.D0.R0.S09: Pi setting = 189 N0.C1.D0.R0.S10: Pi setting = 167 N0.C1.D0.R0.S11: Pi setting = 146 N0.C1.D0.R0.S12: Pi setting = 118 N0.C1.D0.R0.S13: Pi setting = 98 N0.C1.D0.R0.S14: Pi setting = 110 N0.C1.D0.R0.S15: Pi setting = 142 N0.C1.D0.R0.S16: Pi setting = 166 N0.C1.D0.R0.S17: Pi setting = 99 N0.C1.D0.R0: IO Latency = 6 N0.C1.D0.R0: Round Trip = 55 STOP_DATA_REC_EN_BASIC Starting Senseamp and ODT delay calculations ------------------------------------------------------------ N0.C1.S00: MaxRcven=179, New Senseamp/Odt delay=14 N0.C1.S01: MaxRcven=158, New Senseamp/Odt delay=14 N0.C1.S02: MaxRcven=135, New Senseamp/Odt delay=14 N0.C1.S03: MaxRcven=108, New Senseamp/Odt delay=14 N0.C1.S04: MaxRcven= 85, New Senseamp/Odt delay=14 N0.C1.S05: MaxRcven=100, New Senseamp/Odt delay=14 N0.C1.S06: MaxRcven=131, New Senseamp/Odt delay=14 N0.C1.S07: MaxRcven=155, New Senseamp/Odt delay=14 N0.C1.S08: MaxRcven= 87, New Senseamp/Odt delay=14 N0.C1.S09: MaxRcven=189, New Senseamp/Odt delay=14 N0.C1.S10: MaxRcven=167, New Senseamp/Odt delay=14 N0.C1.S11: MaxRcven=146, New Senseamp/Odt delay=14 N0.C1.S12: MaxRcven=118, New Senseamp/Odt delay=14 N0.C1.S13: MaxRcven= 98, New Senseamp/Odt delay=14 N0.C1.S14: MaxRcven=110, New Senseamp/Odt delay=14 N0.C1.S15: MaxRcven=142, New Senseamp/Odt delay=14 N0.C1.S16: MaxRcven=166, New Senseamp/Odt delay=14 N0.C1.S17: MaxRcven= 99, New Senseamp/Odt delay=14 Entering no zone 12 Receive Enable - 1371ms Rx Dq/Dqs Basic -- Started Checkpoint Code: Socket 0, 0xB7, 0x03, 0x0000 N0.D0.R0: RxDqDqs Pi Scanning... Read DQ/DQS summary for socket:0 channel:1 dimm:0 rank:0 ------------------------------------------------------------------------------------- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 # # # # # # # # # # # # # # # # # # 1 # # # # # # # # # # # # # # # # # # 2 # # # # # # # # # # # # # # # # # # 3 # # # # # # # # # # # # # # # # # # 4 # # # # # # # # # # # # # # # # # # 5 # # # # # # # # # # # # # # # # # # 6 # # # # # # # # # # . # # # . # . # 7 # # # # # . # . # . . # # . . # . . 8 # # # # . . # . # . . . # . . . . . 9 # # # # . . # . . . . . . . . . . . 10 # . # # . . # . . . . . . . . . . . 11 . . # . . . . . . . . . . . . . . . 12 . . . . . . . . . . . . . . . . . . 13 . . . . . . . . . . . . . . . . . . 14 . . . . . . . . . . . . . . . . . . 15 . . . . . . . . . . . . . . . . . . 16 . . . . . . . . . . . . . . . . . . 17 . . . . . . . . . . . . . . . . . . 18 . . . . . . . . . . . . . . . . . . 19 . . . . . . . . . . . . . . . . . . 20 . . . . . . . . . . . . . . . . . . 21 . . . . . . . . . . . . . . . . . . 22 . . . . . . . . . . . . . . . . . . 23 . . . . . . . . . . . . . . . . . . 24 . . . . . . . . . . . . . . . . . . 25 . . . . . . . . . . . . . . . . . . 26 . . . . . . . . . . . . . . . . . . 27 . . . . . . . . . . . . . . . . . . 28 . . . . . . . . . . . . . . . . . . 29 . . . . . . . . . . . . . . . . . . 30 . . . . . . . . . . . . . . . . . . 31 . . . . . . . . . . . . . . . . . . 32 . . . . . . . . . . . . . . . . . . 33 . . . . . . . . . . . . . . . . . . 34 . . . . . . . . . . . . . . . . . . 35 . . . . . . . . . . . . . . . . . . 36 . . . . . . . . . . . . . . . . . . 37 . . . . . . . . . . . . . . . . . . 38 . . . . . . . . . . . . . . . . . . 39 . . . . . . . . . . . . . . . . . . 40 . . . . . . . . . . . . . . . . . . 41 . . . . . . . . . . . . . . . . . . 42 . . . . . . . . . . . . . . . . . . 43 . . . . . . . . . . . . . . . . . . 44 . . . . . . . . . . . . . . . . . . 45 . . . . . . . . . . . . . . . . . . 46 . . . . . . . . . . . . . . . . . . 47 . . . . . . . . . . . . . . . . . . 48 . . . . . . . . . . . . . . . . . . 49 . . . . . . . . . . . . . . . . . . 50 . . . . . . . . . . . . . . . . . . 51 . . . . . . . . . . . . . . . . . . 52 . . . . . . . . . . . . . . . . . . 53 . . . . . . . . . . . . . . . . . . 54 . . . . . . . . . . . . . . . . . . 55 . . . . . . . . . . . . . . . . . . 56 . . . . . . . . . . . . . . . . . . 57 . . . . . . . . . . . . . . . . . . 58 . . . . . . . . . . . . . . . . . . 59 . . . . . . . # . . . # # # . # . # 60 . . . . . . . # . # # # # # # # # # 61 . . . # # # # # . # # # # # # # # # 62 # # # # # # # # . # # # # # # # # # 63 # # # # # # # # # # # # # # # # # # 64 # # # # # # # # # # # # # # # # # # 65 # # # # # # # # # # # # # # # # # # 66 # # # # # # # # # # # # # # # # # # 67 # # # # # # # # # # # # # # # # # # 68 # # # # # # # # # # # # # # # # # # 69 # # # # # # # # # # # # # # # # # # 70 # # # # # # # # # # # # # # # # # # 71 # # # # # # # # # # # # # # # # # # ---------------------------------------------------------------------------- EE: 11 10 12 11 8 7 11 7 9 7 6 8 9 7 6 8 6 7 PP: 36 35 36 35 34 33 35 32 35 33 32 33 33 32 32 33 32 32 FE: 61 61 61 60 60 60 60 58 62 59 59 58 58 58 59 58 59 58 START_DATA_RX_DQS_BASIC N0.C1.D0.R0.S00: Pi = 36 N0.C1.D0.R0.S01: Pi = 35 N0.C1.D0.R0.S02: Pi = 36 N0.C1.D0.R0.S03: Pi = 35 N0.C1.D0.R0.S04: Pi = 34 N0.C1.D0.R0.S05: Pi = 33 N0.C1.D0.R0.S06: Pi = 35 N0.C1.D0.R0.S07: Pi = 32 N0.C1.D0.R0.S08: Pi = 35 N0.C1.D0.R0.S09: Pi = 33 N0.C1.D0.R0.S10: Pi = 32 N0.C1.D0.R0.S11: Pi = 33 N0.C1.D0.R0.S12: Pi = 33 N0.C1.D0.R0.S13: Pi = 32 N0.C1.D0.R0.S14: Pi = 32 N0.C1.D0.R0.S15: Pi = 33 N0.C1.D0.R0.S16: Pi = 32 N0.C1.D0.R0.S17: Pi = 32 STOP_DATA_RX_DQS_BASIC Entering no zone 13 Rx Dq/Dqs Basic - 755ms Lrdimm BS Fine WL -- Started Checkpoint Code: Socket 0, 0xB7, 0x17, 0x0000 Entering no zone 14 Lrdimm BS Fine WL - 0ms Lrdimm BS Coarse WL -- Started Checkpoint Code: Socket 0, 0xB7, 0x18, 0x0000 Entering no zone 15 Lrdimm BS Coarse WL - 0ms Lrdimm BS Delay TX -- Started Checkpoint Code: Socket 0, 0xB7, 0x1C, 0x0000 Entering no zone 16 Lrdimm BS Delay TX - 0ms Write Leveling -- Started Checkpoint Code: Socket 0, 0xB7, 0x01, 0x0000 N0.C1: ODT Override: 0x1 N0.D0.R0: Write Leveling Pi Scanning... Summary: Write Leveling Pi S0, Ch1, DIMM0, Rank0 --------------------------------------- 0 1 2 3 4 5 6 7 8 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 1 4 1 1 1 1 1 1 1 1 1 5 1 1 1 1 1 1 1 1 1 6 1 1 1 1 1 1 1 1 1 7 1 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 1 9 1 1 1 1 1 1 1 1 1 10 1 1 1 1 0 1 1 1 0 11 1 1 1 1 0 1 1 1 0 12 1 1 1 1 0 1 1 1 0 13 1 1 1 1 0 1 1 1 0 14 1 1 1 1 0 1 1 1 0 15 1 1 1 1 0 1 1 1 0 16 1 1 1 1 0 1 1 1 0 17 1 1 1 1 0 1 1 1 0 18 1 1 1 1 0 1 1 1 0 19 1 1 1 1 0 1 1 1 0 20 1 1 1 1 0 1 1 1 0 21 1 1 1 0 0 0 1 1 0 22 1 1 1 0 0 0 1 1 0 23 1 1 1 0 0 0 1 1 0 24 1 1 1 0 0 0 1 1 0 25 1 1 1 0 0 0 1 1 0 26 1 1 1 0 0 0 1 1 0 27 1 1 0 0 0 0 1 1 0 28 1 1 0 0 0 0 1 1 0 29 1 1 0 0 0 0 1 1 0 30 1 1 0 0 0 0 1 1 0 31 1 1 0 0 0 0 1 1 0 32 1 1 0 0 0 0 1 1 0 33 1 1 0 0 0 0 1 1 0 34 1 1 0 0 0 0 1 1 0 35 1 1 0 0 0 0 0 1 0 36 1 1 0 0 0 0 0 1 0 37 1 1 0 0 0 0 0 1 0 38 1 1 0 0 0 0 0 0 0 39 1 0 0 0 0 0 0 0 0 40 1 0 0 0 0 0 0 0 0 41 1 0 0 0 0 0 0 0 0 42 1 0 0 0 0 0 0 0 0 43 1 0 0 0 0 0 0 0 0 44 1 0 0 0 0 0 0 0 0 45 1 0 0 0 0 0 0 0 0 46 1 0 0 0 0 0 0 0 0 47 1 0 0 0 0 0 0 0 0 48 1 0 0 0 0 0 0 0 0 49 1 0 0 0 0 0 0 0 0 50 0 0 0 0 0 0 0 0 0 51 0 0 0 0 0 0 0 0 0 52 0 0 0 0 0 0 0 0 0 53 0 0 0 0 0 0 0 0 0 54 0 0 0 0 0 0 0 0 0 55 0 0 0 0 0 0 0 0 0 56 0 0 0 0 0 0 0 0 0 57 0 0 0 0 0 0 0 0 0 58 0 0 0 0 0 0 0 0 0 59 0 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 61 0 0 0 0 0 0 0 0 0 62 0 0 0 0 0 0 0 0 0 63 0 0 0 0 0 0 0 0 0 64 0 0 0 0 0 0 0 0 0 65 0 0 0 0 0 0 0 0 0 66 0 0 0 0 0 0 0 0 0 67 0 0 0 0 0 0 0 0 0 68 0 0 0 0 0 0 0 0 0 69 0 0 0 0 0 0 0 0 0 70 0 0 0 0 0 0 0 0 0 71 0 0 0 0 0 0 0 0 0 72 0 0 0 0 0 0 0 0 0 73 0 0 0 0 0 0 0 0 1 74 0 0 0 0 0 0 0 0 1 75 0 0 0 0 1 0 0 0 1 76 0 0 0 0 1 0 0 0 1 77 0 0 0 0 1 0 0 0 1 78 0 0 0 0 1 0 0 0 1 79 0 0 0 0 1 0 0 0 1 80 0 0 0 0 1 0 0 0 1 81 0 0 0 0 1 0 0 0 1 82 0 0 0 0 1 0 0 0 1 83 0 0 0 0 1 0 0 0 1 84 0 0 0 0 1 0 0 0 1 85 0 0 0 0 1 0 0 0 1 86 0 0 0 0 1 0 0 0 1 87 0 0 0 1 1 1 0 0 1 88 0 0 0 1 1 1 0 0 1 89 0 0 0 1 1 1 0 0 1 90 0 0 0 1 1 1 0 0 1 91 0 0 1 1 1 1 0 0 1 92 0 0 1 1 1 1 0 0 1 93 0 0 1 1 1 1 0 0 1 94 0 0 1 1 1 1 0 0 1 95 0 0 1 1 1 1 0 0 1 96 0 0 1 1 1 1 0 0 1 97 0 0 1 1 1 1 1 0 1 98 0 0 1 1 1 1 1 0 1 99 0 0 1 1 1 1 1 0 1 100 0 0 1 1 1 1 1 0 1 101 0 0 1 1 1 1 1 0 1 102 0 0 1 1 1 1 1 0 1 103 0 0 1 1 1 1 1 1 1 104 0 1 1 1 1 1 1 1 1 105 0 1 1 1 1 1 1 1 1 106 0 1 1 1 1 1 1 1 1 107 0 1 1 1 1 1 1 1 1 108 0 1 1 1 1 1 1 1 1 109 0 1 1 1 1 1 1 1 1 110 0 1 1 1 1 1 1 1 1 111 0 1 1 1 1 1 1 1 1 112 0 1 1 1 1 1 1 1 1 113 0 1 1 1 1 1 1 1 1 114 0 1 1 1 1 1 1 1 1 115 0 1 1 1 1 1 1 1 1 116 1 1 1 1 1 1 1 1 1 117 1 1 1 1 1 1 1 1 1 118 1 1 1 1 1 1 1 1 1 119 1 1 1 1 1 1 1 1 1 120 1 1 1 1 1 1 1 1 1 121 1 1 1 1 1 1 1 1 1 122 1 1 1 1 1 1 1 1 1 123 1 1 1 1 1 1 1 1 1 124 1 1 1 1 1 1 1 1 1 125 1 1 1 1 1 1 1 1 1 126 1 1 1 1 1 1 1 1 1 127 1 1 1 1 1 1 1 1 1 ---------------------------------------------------------------------------- RE: 180 168 155 151 139 151 161 167 137 CP: 19 7 123 118 106 118 2 6 105 FE: 178 167 155 149 138 149 163 166 138 PW: 62 63 64 62 63 62 66 63 65 START_DATA_WR_LVL_BASIC N0.C1.D0.R0.S00: WrLevel Delay = 180 N0.C1.D0.R0.S01: WrLevel Delay = 168 N0.C1.D0.R0.S02: WrLevel Delay = 155 N0.C1.D0.R0.S03: WrLevel Delay = 151 N0.C1.D0.R0.S04: WrLevel Delay = 139 N0.C1.D0.R0.S05: WrLevel Delay = 151 N0.C1.D0.R0.S06: WrLevel Delay = 161 N0.C1.D0.R0.S07: WrLevel Delay = 167 N0.C1.D0.R0.S08: WrLevel Delay = 137 STOP_DATA_WR_LVL_BASIC Entering no zone 17 Write Leveling - 608ms Write Fly By -- Started Checkpoint Code: Socket 0, 0xB7, 0x02, 0x0000 N0.D0.R0: Current DQS offset delay is -1 DClks (DQS offset index=0) N0.D0.R0: Current DQS offset delay is 0 DClks (DQS offset index=1) N0.C1.D0.R0: Write Tx DQ/DQS Flyby delay: GlobalByteOff = 0, CRAddDelay = 0 Dqs Index Dqs Offset (DClks) DqOffset (PI) Prev Pass Current Error strobePass ------------------------------------------------------------------------------------------------------------------- N0.C1.D0.R0: 0 1 0 NO 0x001FF 0x00000 N0.C1.D0.R0: 0 1 -4 NO 0x001FF 0x00000 N0.C1.D0.R0: 0 1 4 NO 0x001FF 0x00000 N0.C1.D0.R0: 0 1 -8 NO 0x001FF 0x00000 N0.C1.D0.R0: 0 1 8 NO 0x001FF 0x00000 N0.C1.D0.R0: 0 1 -12 NO 0x001FF 0x00000 N0.C1.D0.R0: 0 1 12 NO 0x001FF 0x00000 N0.C1.D0.R0: 0 1 -20 NO 0x001FF 0x00000 N0.C1.D0.R0: 0 1 20 NO 0x001FF 0x00000 N0.C1.D0.R0: 0 1 -40 NO 0x001FF 0x00000 N0.C1.D0.R0: 0 1 40 NO 0x001FF 0x00000 N0.D0.R0: Current DQS offset delay is 1 DClks (DQS offset index=2) N0.C1.D0.R0: Write Tx DQ/DQS Flyby delay: GlobalByteOff = 0, CRAddDelay = 1 Dqs Index Dqs Offset (DClks) DqOffset (PI) Prev Pass Current Error strobePass ------------------------------------------------------------------------------------------------------------------- N0.C1.D0.R0: 1 2 0 NO 0x001FF 0x00000 N0.C1.D0.R0: 1 2 -4 NO 0x001FF 0x00000 N0.C1.D0.R0: 1 2 4 NO 0x001FF 0x00000 N0.C1.D0.R0: 1 2 -8 NO 0x001FF 0x00000 N0.C1.D0.R0: 1 2 8 NO 0x001FF 0x00000 N0.C1.D0.R0: 1 2 -12 NO 0x001FF 0x00000 N0.C1.D0.R0: 1 2 12 NO 0x001FF 0x00000 N0.C1.D0.R0: 1 2 -20 NO 0x001FF 0x00000 N0.C1.D0.R0: 1 2 20 NO 0x001FF 0x00000 N0.C1.D0.R0: 1 2 -40 NO 0x001FF 0x00000 N0.C1.D0.R0: 1 2 40 NO 0x001FF 0x00000 N0.D0.R0: Current DQS offset delay is 2 DClks (DQS offset index=3) N0.C1.D0.R0: Write Tx DQ/DQS Flyby delay: GlobalByteOff = 0, CRAddDelay = 2 Dqs Index Dqs Offset (DClks) DqOffset (PI) Prev Pass Current Error strobePass ------------------------------------------------------------------------------------------------------------------- N0.C1.D0.R0: 2 3 0 NO 0x00000 0x001FF -------------------------------------------------------------------------------- N0.C1.D0.R0: Current values: GlobalByteOff = 0 DClks, CRAddDelay[1] = 2 DClks N0.C1.D0.R0: Refining TargetOffset for all byte lanes... TgtOffset ByteOff -------------------------------------------------------------------------------- N0.C1.D0.R0.S00: 2 DClks 2 DClks N0.C1.D0.R0.S01: 2 DClks 2 DClks N0.C1.D0.R0.S02: 2 DClks 2 DClks N0.C1.D0.R0.S03: 2 DClks 2 DClks N0.C1.D0.R0.S04: 2 DClks 2 DClks N0.C1.D0.R0.S05: 2 DClks 2 DClks N0.C1.D0.R0.S06: 2 DClks 2 DClks N0.C1.D0.R0.S07: 2 DClks 2 DClks N0.C1.D0.R0.S08: 2 DClks 2 DClks TxDq (PI) TxDqs (PI) PI Offset -------------------------------------------------------------------------------- N0.C1.D0.R0.S00: 212 180 0 N0.C1.D0.R0.S01: 200 168 0 N0.C1.D0.R0.S02: 187 155 0 N0.C1.D0.R0.S03: 183 151 0 N0.C1.D0.R0.S04: 171 139 0 N0.C1.D0.R0.S05: 183 151 0 N0.C1.D0.R0.S06: 193 161 0 N0.C1.D0.R0.S07: 199 167 0 N0.C1.D0.R0.S08: 169 137 0 START_DATA_WR_LVL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1: t_cwl_adj = 2 N0.C1.D0.R0: 180 168 155 151 139 151 161 167 137 Entering no zone 18 Write Fly By - 336ms Tx Dq Basic -- Started Checkpoint Code: Socket 0, 0xB7, 0x04, 0x0000 N0.D0.R0: TxDqDqs Pi Scanning... Write DQ/DQS summary for socket:0 channel:1 dimm:0 rank:0 ------------------------------------------------------------------------------------- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 # # # # # # # # # # # # # # # # # # 1 # # # # # # # # # # # # # # # # # # 2 # # # # # # # # # # # # # # # # # # 3 # # # # # # # # # # # # # # # # # # 4 # # # # # # # # # # # # # # # # # # 5 # # # # # # # # # # # # # # # # # # 6 # # # # # # # # # # # # # # # # # # 7 # # # # # # # # # # # # # # # # # # 8 # # # # # # # # # # # # # # # # # # 9 # # # # # # # # # # # # # # # # # # 10 # # # # # # # # # # # # # # # # # # 11 # # # # # # # # # # # # # # # # # # 12 # # # # # # # # # # # # # # # # # # 13 # # # # # # # # # # # # # # # # # # 14 # # # # # # # # # # # # # # # # # # 15 # # # # # # # # # # # # # # # # # # 16 # # # # # # # # # # # # # # # # # # 17 # # # # # # # # # # # # # # # # # # 18 # # # # # # # # # # # # # # # # # # 19 # # # # # # # # # # # # # # # # # # 20 # # # # # # # # # # # # # # # # # # 21 # # # # # # # # # # # # # # # # # # 22 # # # # # # # # # # # # # # # # # # 23 # # # # # # # # # # # # # # # # # # 24 # # # # # # # # # # # # # # # # # # 25 # # # # # # # # # # # # # # # # # # 26 # # # # # # # # # # # # # # # # # # 27 # # # # # # # # # # # # # # # # # # 28 # # # # # # # # # # # # # # # # # # 29 # # # # # # # # # # # # # # # # # # 30 # # # # # # # # # # # # # # # # # # 31 # # # # # # # # # # # # # # # # # # 32 # # # # # # # # # # # # # # # # # # 33 # # # # # # # # # # # # # # # # # # 34 # # # # # # # # # # # # # # # # # # 35 # # # # # # # # # # # # # # # # # # 36 # # # # # # # # # # # # # # # # # # 37 . # # # # # # # # # # # # # # # # # 38 . . . # # . # # # # # # # # # # # # 39 . . . . # . . # # # # # # # # # # # 40 . . . . . . . . . # # # # # # # # # 41 . . . . . . . . . # # # # # # # # # 42 . . . . . . . . . # # # # # # # # # 43 . . . . . . . . . . # # # # # # # # 44 . . . . . . . . . . # . # # # # . # 45 . . . . . . . . . . . . # . # . . # 46 . . . . . . . . . . . . # . . . . # 47 . . . . . . . . . . . . . . . . . . 48 . . . . . . . . . . . . . . . . . . 49 . . . . . . . . . . . . . . . . . . 50 . . . . . . . . . . . . . . . . . . 51 . . . . . . . . . . . . . . . . . . 52 . . . . . . . . . . . . . . . . . . 53 . . . . . . . . . . . . . . . . . . 54 . . . . . . . . . . . . . . . . . . 55 . . . . . . . . . . . . . . . . . . 56 . . . . . . . . . . . . . . . . . . 57 . . . . . . . . . . . . . . . . . . 58 . . . . . . . . . . . . . . . . . . 59 . . . . . . . . . . . . . . . . . . 60 . . . . . . . . . . . . . . . . . . 61 . . . . . . . . . . . . . . . . . . 62 . . . . . . . . . . . . . . . . . . 63 . . . . . . . . . . . . . . . . . . 64 . . . . . . . . . . . . . . . . . . 65 . . . . . . . . . . . . . . . . . . 66 . . . . . . . . . . . . . . . . . . 67 . . . . . . . . . . . . . . . . . . 68 . . . . . . . . . . . . . . . . . . 69 . . . . . . . . . . . . . . . . . . 70 . . . . . . . . . . . . . . . . . . 71 . . . . . . . . . . . . . . . . . . 72 . . . . . . . . . . . . . . . . . . 73 . . . . . . . . . . . . . . . . . . 74 . . . . . . . . . . . . . . . . . . 75 . . . . . . . . . . . . . . . . . . 76 . . . . . . . . . . . . . . . . . . 77 . . . . . . . . . . . . . . . . . . 78 . . . . . . . . . . . . . . . . . . 79 . . . . . . . . . . . . . . . . . . 80 . . . . . . . . . . . . . . . . . . 81 . . . . . . . . . . . . . . . . . . 82 . . . . . . . . . . . . . . . . . . 83 . . . . . . . . . . . . . . . . . . 84 . . . . . . . . . . . . . . . . . . 85 . . . . . . . . . . . . . . . . . . 86 . . . . . . . . . . . . . . . . . . 87 . . . . . . . . . . . . . . . . . . 88 . . . . . . . . . . . . . . . . . . 89 . . . . . . . . . . . . . . . . . . 90 . . . . . . . . . . . . . . . . . . 91 . . . . . . . . . . . . . . . . . . 92 . . . . . . . . . . . . . . . . . . 93 . . . . . . . . . . . . . . . . . . 94 . . . . . . . . . . . . . . . . . . 95 # . . . . . . . . . . . . . . . . . 96 # . . # . . # . . . . . . . . . . . 97 # . # # . # # . . . . . # . . . . . 98 # # # # # # # # # # . # # . . . . . 99 # # # # # # # # # # . # # . . . . . 100 # # # # # # # # # # # # # # # . . # 101 # # # # # # # # # # # # # # # # # # 102 # # # # # # # # # # # # # # # # # # 103 # # # # # # # # # # # # # # # # # # 104 # # # # # # # # # # # # # # # # # # 105 # # # # # # # # # # # # # # # # # # 106 # # # # # # # # # # # # # # # # # # 107 # # # # # # # # # # # # # # # # # # 108 # # # # # # # # # # # # # # # # # # 109 # # # # # # # # # # # # # # # # # # 110 # # # # # # # # # # # # # # # # # # 111 # # # # # # # # # # # # # # # # # # 112 # # # # # # # # # # # # # # # # # # 113 # # # # # # # # # # # # # # # # # # 114 # # # # # # # # # # # # # # # # # # 115 # # # # # # # # # # # # # # # # # # 116 # # # # # # # # # # # # # # # # # # 117 # # # # # # # # # # # # # # # # # # 118 # # # # # # # # # # # # # # # # # # 119 # # # # # # # # # # # # # # # # # # 120 # # # # # # # # # # # # # # # # # # 121 # # # # # # # # # # # # # # # # # # 122 # # # # # # # # # # # # # # # # # # 123 # # # # # # # # # # # # # # # # # # 124 # # # # # # # # # # # # # # # # # # 125 # # # # # # # # # # # # # # # # # # 126 # # # # # # # # # # # # # # # # # # 127 # # # # # # # # # # # # # # # # # # ---------------------------------------------------------------------------- EE: 185 174 161 158 147 157 168 175 145 191 181 167 166 152 165 174 179 152 PP: 213 203 190 186 175 186 196 203 173 218 208 193 190 179 191 201 207 178 FE: 242 233 219 214 204 215 224 232 202 245 235 220 215 206 218 229 235 204 START_DATA_TX_DQ_BASIC N0.C1.D0.R0.S00: TxDqDqs: Pi = 213 N0.C1.D0.R0.S01: TxDqDqs: Pi = 203 N0.C1.D0.R0.S02: TxDqDqs: Pi = 190 N0.C1.D0.R0.S03: TxDqDqs: Pi = 186 N0.C1.D0.R0.S04: TxDqDqs: Pi = 175 N0.C1.D0.R0.S05: TxDqDqs: Pi = 186 N0.C1.D0.R0.S06: TxDqDqs: Pi = 196 N0.C1.D0.R0.S07: TxDqDqs: Pi = 203 N0.C1.D0.R0.S08: TxDqDqs: Pi = 173 N0.C1.D0.R0.S09: TxDqDqs: Pi = 218 N0.C1.D0.R0.S10: TxDqDqs: Pi = 208 N0.C1.D0.R0.S11: TxDqDqs: Pi = 193 N0.C1.D0.R0.S12: TxDqDqs: Pi = 190 N0.C1.D0.R0.S13: TxDqDqs: Pi = 179 N0.C1.D0.R0.S14: TxDqDqs: Pi = 191 N0.C1.D0.R0.S15: TxDqDqs: Pi = 201 N0.C1.D0.R0.S16: TxDqDqs: Pi = 207 N0.C1.D0.R0.S17: TxDqDqs: Pi = 178 STOP_DATA_TX_DQ_BASIC Entering no zone 19 Tx Dq Basic - 1281ms PPR Flow -- Started Checkpoint Code: Socket 0, 0xB7, 0x36, 0x0000 PPR Flow - 0ms Wr Early Vref Centering -- Started Checkpoint Code: Socket 0, 0xB7, 0x32, 0x0000 Previous Settings START_DATA_TxVref 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 82 82 82 82 82 82 82 82 82 START_DATA_TX_DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 213 203 190 186 175 186 196 203 173 218 208 193 190 179 191 201 207 178 N0.C1: Cycling through ranks to check eye width for 2DPC margining W/A!! N0.C1.D0.R0: Checking for eye widths!! Current VREF offset is 0 N0.C1.D0.R0: txVrefSafe = 0x55 New Settings START_DATA_TxVref 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 85 85 85 85 85 85 85 85 85 START_DATA_TX_DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 212 202 189 184 175 185 196 202 172 218 207 192 189 178 191 200 207 177 Wr Early Vref Centering - 114ms Rd Early Vref Centering -- Started Checkpoint Code: Socket 0, 0xB7, 0x31, 0x0000 Previous Settings START_DATA_RxVref N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 63 START_DATA_RX_DQS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 36 35 36 35 34 33 35 32 35 33 32 33 33 32 32 33 32 32 N0.C1: Cycling through ranks to check eye width for 2DPC margining W/A!! N0.C1.D0.R0: Checking for eye widths!! Current VREF offset is 0 New Settings START_DATA_RxVref N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 START_DATA_RX_DQS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 34 33 33 32 32 32 33 30 32 30 30 30 31 30 30 30 30 29 Rd Early Vref Centering - 198ms CMD Vref Centering -- Started Checkpoint Code: Socket 0, 0xB7, 0x24, 0x0000 N0.C1.D0.R0: High = 31 - Low = -31 N0.C1: Composite High = 31 - Composite Low = -31 final_offset = 0 Reset All Channels JEDEC Init N0.C1.D0.R0: Write RC00 = 0x00 N0.C1.D0.R0: Write RC01 = 0x00 N0.C1.D0.R0: Write RC02 = 0x00 N0.C1.D0.R0: Write RC03 = 0x00 N0.C1.D0.R0: Write RC04 = 0x00 N0.C1.D0.R0: Write RC05 = 0x00 N0.C1.D0.R0: Write RC40 = 0x0F N0.C1.D0.R0: Write RC08 = 0x0B N0.C1.D0.R0: Write RC0A = 0x02 N0.C1.D0.R0: Write RC0B = 0x08 N0.C1.D0.R0: Write RC0C = 0x00 N0.C1.D0.R0: Write RC0E = 0x00 N0.C1.D0.R0: Write RC0F = 0x00 N0.C1.D0.R0: Write RC30 = 0x2C N0.C1.D0.R0: Write RC40 = 0x26 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x27 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x28 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x29 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x21 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x22 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x23 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x24 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x25 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC09 = 0x0C N0.C1.D0.R0: Write RC0D = 0x04 N0.C1: Issue ZQCL N0.C4: (compHigh + compLow)/2 = 32 START_DATA_CMD_VREF_CENTERING N0.C0: Applying offset of 0... N0.C1: Applying offset of 0... N0.C2: Applying offset of 0... N0.C3: Applying offset of 0... STOP_DATA_CMD_VREF_CENTERING CMD Vref Centering - 183ms Late Cmd/Clk -- Started Checkpoint Code: Socket 0, 0xB7, 0x05, 0x0000 START_CMD_CLK_PER_GROUP_FINAL N0: Calling GetMargins for CmdAll C1.D0.R0: Platform Group = CmdAll C1.D0.R0: Found CMD Pi group: 0 side 0 C1.D0.R0: cmdLeft[0][0] = -56 : cmdRight[0][0] = 52 C1.D0.R0: Found CMD Pi group: 0 side 1 C1.D0.R0: cmdLeft[1][0] = -56 : cmdRight[1][0] = 52 C1.D0.R0: Found CMD Pi group: 1 side 0 C1.D0.R0: cmdLeft[2][0] = -56 : cmdRight[2][0] = 52 C1.D0.R0: Found CMD Pi group: 1 side 1 C1.D0.R0: cmdLeft[3][0] = -56 : cmdRight[3][0] = 52 C1.D0.R0: Found CMD Pi group: 2 side 0 C1.D0.R0: cmdLeft[4][0] = -56 : cmdRight[4][0] = 52 C1.D0.R0: Found CMD Pi group: 2 side 1 C1.D0.R0: cmdLeft[5][0] = -56 : cmdRight[5][0] = 52 C1.D0.R0: Found CMD Pi group: 3 side 0 C1.D0.R0: cmdLeft[6][0] = -56 : cmdRight[6][0] = 52 C1.D0.R0: Found CMD Pi group: 3 side 1 C1.D0.R0: cmdLeft[7][0] = -56 : cmdRight[7][0] = 52 C1.D0.R0: Found CMD Pi group: 4 side 0 C1.D0.R0: cmdLeft[8][0] = -56 : cmdRight[8][0] = 52 C1.D0.R0: Found CMD Pi group: 4 side 1 C1.D0.R0: cmdLeft[9][0] = -56 : cmdRight[9][0] = 52 C1.D0.R0: Found CMD Pi group: 5 side 0 C1.D0.R0: cmdLeft[10][0] = -56 : cmdRight[10][0] = 52 C1.D0.R0: Found CMD Pi group: 5 side 1 C1.D0.R0: cmdLeft[11][0] = -56 : cmdRight[11][0] = 52 N0.C1: CMD Pi Group 0 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 1 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 2 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 3 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 4 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 5 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 6 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 7 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 8 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 9 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 10 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 11 clk 0 cmdOffset -2 N0.C1: CMD Pi Group 0: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 1: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 2: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 3: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 4: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 5: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 6: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 7: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 8: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 9: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 10: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: CMD Pi Group 11: maxOffset = -2, minOffset = -2, cmdOffset = -2 N0.C1: <--CMD Pi Group 0 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 1 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 2 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 3 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 4 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 5 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 6 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 7 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 8 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 9 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 10 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <--CMD Pi Group 11 clk 0: cmdLeft -54 - cmdRight 54 N0.C1: <----clk 0 ckOffset 0: -(maxLeftOffset:-54 + minRightOffset:54) / 2 STOP_CMD_CLK_PER_GROUP_FINAL Reset All Channels JEDEC Init N0.C1.D0.R0: Write RC00 = 0x00 N0.C1.D0.R0: Write RC01 = 0x00 N0.C1.D0.R0: Write RC02 = 0x00 N0.C1.D0.R0: Write RC03 = 0x00 N0.C1.D0.R0: Write RC04 = 0x00 N0.C1.D0.R0: Write RC05 = 0x00 N0.C1.D0.R0: Write RC40 = 0x0F N0.C1.D0.R0: Write RC08 = 0x0B N0.C1.D0.R0: Write RC0A = 0x02 N0.C1.D0.R0: Write RC0B = 0x08 N0.C1.D0.R0: Write RC0C = 0x00 N0.C1.D0.R0: Write RC0E = 0x00 N0.C1.D0.R0: Write RC0F = 0x00 N0.C1.D0.R0: Write RC30 = 0x2C N0.C1.D0.R0: Write RC40 = 0x26 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x27 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x28 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x29 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x21 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x22 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x23 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x24 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x25 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC09 = 0x0C N0.C1.D0.R0: Write RC0D = 0x04 N0.C1: Issue ZQCL Late Cmd/Clk - 497ms Tx Eq -- Started Checkpoint Code: Socket 0, 0xB7, 0x1B, 0x0000 Printing initialized array of cached values... Tx Eq Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C1.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting 0 Params [0] 0x0 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 60 60 60 57 60 60 60 60 59 60 60 60 57 60 60 60 60 59 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 49 49 48 48 51 53 49 52 47 49 49 48 48 51 53 49 52 47 Setting 1 Params [0] 0x2 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 60 60 60 58 60 60 60 60 59 60 60 60 58 60 60 60 60 59 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 50 49 48 49 51 53 49 52 48 50 49 48 49 51 53 49 52 48 Setting 2 Params [0] 0x4 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 60 60 60 58 60 60 60 60 59 60 60 60 58 60 60 60 60 59 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 50 49 48 49 52 54 49 52 48 50 49 48 49 52 54 49 52 48 Setting 3 Params [0] 0x6 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 60 60 60 58 60 60 60 60 60 60 60 60 58 60 60 60 60 60 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 50 49 49 49 52 54 49 53 48 50 49 49 49 52 54 49 53 48 Setting 4 Params [0] 0x8 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 60 60 60 59 60 60 60 60 60 60 60 60 59 60 60 60 60 60 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 50 50 49 50 52 54 49 53 48 50 50 49 50 52 54 49 53 48 Setting 5 Params [0] 0xA Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 60 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 50 50 48 50 51 53 50 53 47 50 50 48 50 51 53 50 53 47 Setting 6 Params [0] 0xC Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 60 60 60 58 60 60 60 60 59 60 60 60 58 60 60 60 60 59 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 50 50 48 50 52 53 50 53 48 50 50 48 50 52 53 50 53 48 Setting 7 Params [0] 0xE Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 59 57 59 56 59 59 58 60 55 59 57 59 56 59 59 58 60 55 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 48 49 48 49 52 52 49 53 48 48 49 48 49 52 52 49 53 48 Setting 8 Params [0] 0x10 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 58 55 56 54 57 58 55 58 52 58 55 56 54 57 58 55 58 52 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 48 49 48 49 51 52 49 52 48 48 49 48 49 51 52 49 52 48 Setting 9 Params [0] 0x12 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 55 52 53 50 54 55 53 55 50 55 52 53 50 54 55 53 55 50 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 48 48 47 49 51 51 49 51 47 48 48 47 49 51 51 49 51 47 Setting 10 Params [0] 0x14 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 49 46 48 46 48 49 48 50 45 49 46 48 46 48 49 48 50 45 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 47 47 46 47 50 50 48 51 46 47 47 46 47 50 50 48 51 46 Setting 11 Params [0] 0x16 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 47 45 44 44 46 47 45 47 43 47 45 44 44 46 47 45 47 43 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 46 47 46 46 49 50 48 50 46 46 47 46 46 49 50 48 50 46 Setting 12 Params [0] 0x18 Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 44 42 43 41 44 44 43 44 39 44 42 43 41 44 44 43 44 39 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 46 46 47 49 49 47 50 46 45 46 46 47 49 49 47 50 46 Setting 13 Params [0] 0x1A Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 43 43 41 43 44 43 45 40 45 43 43 41 43 44 43 45 40 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 46 46 47 49 50 47 50 45 45 46 46 47 49 50 47 50 45 Setting 14 Params [0] 0x1C Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 42 43 41 43 45 44 45 39 45 42 43 41 43 45 44 45 39 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 46 46 46 47 49 50 47 50 46 46 46 46 47 49 50 47 50 46 Setting 15 Params [0] 0x1E Tx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 41 43 41 44 44 43 45 39 45 41 43 41 44 44 43 45 39 Tx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 46 46 46 47 49 49 47 51 45 46 46 46 47 49 49 47 51 45 Power TrendLine Calculation N0.C1.D0.R0.S00: minPower = 0 : maxPower = 1500 AveOfMax = 550 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 0: N0.C1.D0.R0.S01: minPower = 0 : maxPower = 1500 AveOfMax = 550 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 1: N0.C1.D0.R0.S02: minPower = 0 : maxPower = 1500 AveOfMax = 540 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 2: N0.C1.D0.R0.S03: minPower = 0 : maxPower = 1500 AveOfMax = 545 : maxMarginAllGroups = 590 : slope = 0 FindOptimalTradeoff for Strobe 3: N0.C1.D0.R0.S04: minPower = 0 : maxPower = 1500 AveOfMax = 560 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 4: N0.C1.D0.R0.S05: minPower = 0 : maxPower = 1500 AveOfMax = 570 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 5: N0.C1.D0.R0.S06: minPower = 0 : maxPower = 1500 AveOfMax = 545 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 6: N0.C1.D0.R0.S07: minPower = 0 : maxPower = 1500 AveOfMax = 565 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 7: N0.C1.D0.R0.S08: minPower = 0 : maxPower = 1500 AveOfMax = 540 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 8: N0.C1.D0.R0.S09: minPower = 0 : maxPower = 1500 AveOfMax = 550 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 9: N0.C1.D0.R0.S10: minPower = 0 : maxPower = 1500 AveOfMax = 550 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 10: N0.C1.D0.R0.S11: minPower = 0 : maxPower = 1500 AveOfMax = 540 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 11: N0.C1.D0.R0.S12: minPower = 0 : maxPower = 1500 AveOfMax = 545 : maxMarginAllGroups = 590 : slope = 0 FindOptimalTradeoff for Strobe 12: N0.C1.D0.R0.S13: minPower = 0 : maxPower = 1500 AveOfMax = 560 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 13: N0.C1.D0.R0.S14: minPower = 0 : maxPower = 1500 AveOfMax = 570 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 14: N0.C1.D0.R0.S15: minPower = 0 : maxPower = 1500 AveOfMax = 545 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 15: N0.C1.D0.R0.S16: minPower = 0 : maxPower = 1500 AveOfMax = 565 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 16: N0.C1.D0.R0.S17: minPower = 0 : maxPower = 1500 AveOfMax = 540 : maxMarginAllGroups = 600 : slope = 0 FindOptimalTradeoff for Strobe 17: START_OPTIMAL_TRAINING_RESULTS Tx Eq Per Strobe Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C1.D0.R0: 4 10 0 10 6 6 0 8 4 4 10 0 10 6 6 0 8 4 END_OPTIMAL_TRAINING_RESULTS Reset All Channels JEDEC Init N0.C1.D0.R0: Write RC00 = 0x00 N0.C1.D0.R0: Write RC01 = 0x00 N0.C1.D0.R0: Write RC02 = 0x00 N0.C1.D0.R0: Write RC03 = 0x00 N0.C1.D0.R0: Write RC04 = 0x00 N0.C1.D0.R0: Write RC05 = 0x00 N0.C1.D0.R0: Write RC40 = 0x0F N0.C1.D0.R0: Write RC08 = 0x0B N0.C1.D0.R0: Write RC0A = 0x02 N0.C1.D0.R0: Write RC0B = 0x08 N0.C1.D0.R0: Write RC0C = 0x00 N0.C1.D0.R0: Write RC0E = 0x00 N0.C1.D0.R0: Write RC0F = 0x00 N0.C1.D0.R0: Write RC30 = 0x2C N0.C1.D0.R0: Write RC40 = 0x26 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x27 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x28 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x29 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x21 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x22 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x23 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x24 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC40 = 0x25 N0.C1.D0.R0: Write RC60 = 0x00 N0.C1.D0.R0: Write RC06 = 0x05 N0.C1.D0.R0: Write RC09 = 0x0C N0.C1.D0.R0: Write RC0D = 0x04 N0.C1: Issue ZQCL Tx Eq - 1517ms Imode -- Started Checkpoint Code: Socket 0, 0xB7, 0x1D, 0x0000 Imode - 0ms CTLE -- Started Checkpoint Code: Socket 0, 0xB7, 0x67, 0x0000 Printing initialized array of cached values... Rx Eq Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C1.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTLE C Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C1.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTLE R Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C1.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Setting 0 Params Rx Eq 0x0 CTLE C 0x0 CTLE R 0x0 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 96 96 94 95 96 96 96 96 96 96 96 94 95 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 46 45 42 45 47 49 45 47 47 46 45 42 45 47 49 45 47 47 Setting 1 Params Rx Eq 0x2 CTLE C 0x1 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 46 45 43 44 46 48 44 46 47 46 45 43 44 46 48 44 46 47 Setting 2 Params Rx Eq 0x2 CTLE C 0x2 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 96 96 95 95 96 96 96 96 96 96 96 95 95 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 45 42 43 46 48 44 47 47 45 45 42 43 46 48 44 47 47 Setting 3 Params Rx Eq 0x2 CTLE C 0x3 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 96 96 94 94 96 96 96 96 96 96 96 94 94 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 46 45 43 43 46 46 44 47 46 46 45 43 43 46 46 44 47 46 Setting 4 Params Rx Eq 0x3 CTLE C 0x1 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 45 42 44 46 48 45 46 47 45 45 42 44 46 48 45 46 47 Setting 5 Params Rx Eq 0x3 CTLE C 0x2 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 45 42 43 45 47 44 46 46 45 45 42 43 45 47 44 46 46 Setting 6 Params Rx Eq 0x3 CTLE C 0x3 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 44 41 42 45 46 43 45 45 45 44 41 42 45 46 43 45 45 Setting 7 Params Rx Eq 0x4 CTLE C 0x1 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 45 42 44 46 48 44 47 46 45 45 42 44 46 48 44 47 46 Setting 8 Params Rx Eq 0x4 CTLE C 0x2 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 44 41 43 45 47 43 45 46 45 44 41 43 45 47 43 45 46 Setting 9 Params Rx Eq 0x4 CTLE C 0x3 CTLE R 0x3 Rx Eye Heights Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 96 Rx Eye Widths Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------------ N0.C1.D0.R0: 45 44 40 42 44 45 43 44 44 45 44 40 42 44 45 43 44 44 Power TrendLine Calculation N0.C1.D0.R0.S00: minPower = 0 : maxPower = 900 AveOfMax = 710 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 0: N0.C1.D0.R0.S01: minPower = 0 : maxPower = 900 AveOfMax = 705 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 1: N0.C1.D0.R0.S02: minPower = 0 : maxPower = 900 AveOfMax = 695 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 2: N0.C1.D0.R0.S03: minPower = 0 : maxPower = 900 AveOfMax = 705 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 3: N0.C1.D0.R0.S04: minPower = 0 : maxPower = 900 AveOfMax = 715 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 4: N0.C1.D0.R0.S05: minPower = 0 : maxPower = 900 AveOfMax = 725 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 5: N0.C1.D0.R0.S06: minPower = 0 : maxPower = 900 AveOfMax = 705 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 6: N0.C1.D0.R0.S07: minPower = 0 : maxPower = 900 AveOfMax = 715 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 7: N0.C1.D0.R0.S08: minPower = 0 : maxPower = 900 AveOfMax = 715 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 8: N0.C1.D0.R0.S09: minPower = 0 : maxPower = 900 AveOfMax = 710 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 9: N0.C1.D0.R0.S10: minPower = 0 : maxPower = 900 AveOfMax = 705 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 10: N0.C1.D0.R0.S11: minPower = 0 : maxPower = 900 AveOfMax = 695 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 11: N0.C1.D0.R0.S12: minPower = 0 : maxPower = 900 AveOfMax = 705 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 12: N0.C1.D0.R0.S13: minPower = 0 : maxPower = 900 AveOfMax = 715 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 13: N0.C1.D0.R0.S14: minPower = 0 : maxPower = 900 AveOfMax = 725 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 14: N0.C1.D0.R0.S15: minPower = 0 : maxPower = 900 AveOfMax = 705 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 15: N0.C1.D0.R0.S16: minPower = 0 : maxPower = 900 AveOfMax = 715 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 16: N0.C1.D0.R0.S17: minPower = 0 : maxPower = 900 AveOfMax = 715 : maxMarginAllGroups = 960 : slope = 0 FindOptimalTradeoff for Strobe 17: START_OPTIMAL_TRAINING_RESULTS Rx Eq Per Strobe Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C1.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTLE C Per Strobe Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C1.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTLE R Per Strobe Strobe 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------- N0.C1.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 END_OPTIMAL_TRAINING_RESULTS CTLE - 1109ms Tx Per Bit Deskew -- Started Checkpoint Code: Socket 0, 0xB7, 0x0E, 0x0000 N0: START_PER_BIT_DESKEW ============================================================================== N0: Per Bit Deskew Tx ============================================================================== PatternLength: 64 Per bit margins: TxDq 0------7 8-----15 16----23 24----31 32----39 40----47 48----55 56----63 64----71 30 ******** ******* ******** ******* ******** ******** ******** ******** ******** 29 ******** ******* ******** ******* ******** ******* ******** * ***** ******** 28 ******** ******* ******** *** *** * *** ** ******* ******** * * *** ******** 27 ** **** *** *** ******** * ** * *** * * * *** ******** * * ** * ***** 26 * * * * ** ***** * * ** ** * * *** * ***** * * * * **** 25 * * ** * *** * ** * * ** * *** * * * 24 * * ** * *** * * ** *** * 23 * * ** * * * * 22 * * -20 * * -21 * * * -22 * * * * ** * * * -23 * * ** ** * ** * *** * * * * * -24 ** * *** ** ** *** **** *** * * ** * * ** * -25 ** * * **** ** **** *** **** *** * * * * ** * * ** ** *** -26 **** * * **** ** **** *** **** *** ** * * ** * *** *** **** *** ** *** -27 **** *** **** *** **** *** ******** ** *** **** ** **** *** ******** **** *** -28 **** *** ******** ******** ******** **** *** ******** **** *** ******** ******** -29 **** *** ******** ******** ******** ******** ******** ******** ******** ******** -30 ******** ******** ******** ******** ******** ******** ******** ******** ******** N0.C1.D0.R0: TxDq - Per bit margins 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 26 27 28 27 23 27 27 28 24 27 26 28 24 24 27 31 23 26 24 23 22 27 24 27 26 28 28 29 23 25 28 31 27 29 27 26 -26 -24 -23 -26 -30 -25 -27 -23 -25 -24 -24 -24 -28 -27 -23 -21 -25 -23 -23 -25 -28 -24 -24 -20 -22 -23 -24 -22 -27 -23 -22 -20 -28 -26 -25 -28 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 25 29 27 28 25 28 26 28 23 24 26 30 25 27 24 24 23 26 25 27 26 30 26 29 26 27 28 30 25 28 27 26 22 26 26 28 -29 -25 -27 -22 -27 -27 -26 -26 -28 -28 -27 -24 -26 -24 -24 -27 -29 -25 -26 -23 -26 -26 -26 -26 -27 -26 -25 -23 -27 -22 -24 -27 -28 -25 -25 -22 N0.C1: Calculating Bit Centers N0.C1: dimm = 0, rank = 0 Per Bit Margin Center Per Bit Skew N# = Nibble, BCx = Bit Center, BSx = Bit Skew , MSL = Most Skewed Lane N# BC0-BC1-BC2-BC3 BS0-BS1-BS2-BS3 ============================================================================== 0 0 1 2 0 0 1 2 0 1 -3 1 0 2 0 4 3 5 2 0 1 1 2 0 1 1 2 3 -2 -1 2 5 0 1 4 7 4 -1 1 0 -1 0 2 1 0 5 -3 1 0 3 0 4 3 6 6 2 2 2 3 0 0 0 1 7 -2 1 3 5 0 3 5 7 8 0 1 1 -1 1 2 2 0 9 -2 2 0 3 0 4 2 5 10 -1 0 0 1 0 1 1 2 11 -2 -2 0 3 0 0 2 5 12 0 1 0 -1 1 2 1 0 13 -3 0 0 2 0 3 3 5 14 0 2 0 1 0 2 0 1 15 0 0 1 3 0 0 1 3 16 -1 3 1 0 0 4 2 1 17 -3 0 0 3 0 3 3 6 START_DATA_TX_DQ_PER_BIT N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 20 21 22 20 23 27 26 28 10 11 11 12 13 14 17 20 60 62 61 60 61 65 64 67 58 58 58 59 59 62 64 66 47 48 48 46 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 48 52 50 53 56 57 57 58 61 61 63 66 4 5 4 3 5 8 8 10 10 12 10 11 15 15 16 18 43 47 45 44 46 49 49 52 N0: STOP_PER_BIT_DESKEW Tx Per Bit Deskew - 457ms Rx Per Bit Deskew -- Started Checkpoint Code: Socket 0, 0xB7, 0x0D, 0x0000 N0: START_PER_BIT_DESKEW ============================================================================== N0: Per Bit Deskew Rx P ============================================================================== PatternLength: 64 Per bit margins: Rx DqsP 0------7 8-----15 16----23 24----31 32----39 40----47 48----55 56----63 64----71 30 ******** ******** ******** ** *** * **** * * ******** ******** ** ***** ******** 29 ******** ******** **** ** ** *** * *** * * ** ***** ******** * *** * ******** 28 **** *** ****** * *** ** * * * * * * ** ** * **** * * ******** 27 **** *** ** * * *** * * * * ** * **** * *** ** 26 *** ** ** * * * * * * * * * *** * 25 ** * * * * * 24 * * -21 * -22 * * * * ** -23 * * * * ** * ** * ** * * * * ** -24 ** ** * *** ** ** * ** * ** * *** ** * * * * ** -25 ** ** * *** *** *** *** *** * * *** * ** *** ** * ***** *** ** -26 ** ** * * *** *** **** *** *** *** *** * * *** *** **** ******** ******* -27 ** *** * * **** *** **** ******* *** **** * * **** ******** ******** ******** -28 ** **** ******** ******** ******** ******** ******** ******** ******** ******** -29 *** **** ******** ******** ******** ******** ******** ******** ******** ******** -30 *** **** ******** ******** ******** ******** ******** ******** ******** ******** N0.C1.D0.R0: RxDqsP - Per bit margins 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 27 26 25 25 29 27 26 24 26 26 28 26 28 28 29 26 29 27 27 26 30 30 28 26 29 27 31 28 29 29 31 26 30 28 29 28 -24 -24 -29 -31 -23 -24 -27 -28 -23 -28 -26 -28 -23 -24 -24 -27 -21 -24 -25 -28 -22 -23 -25 -26 -22 -25 -25 -27 -22 -23 -25 -28 -24 -26 -25 -28 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 31 29 31 28 28 27 30 27 27 29 29 25 27 26 27 26 29 29 29 25 30 29 31 29 29 29 30 28 28 26 26 25 28 28 27 24 -24 -24 -25 -27 -25 -28 -26 -28 -26 -25 -24 -27 -23 -24 -24 -27 -23 -23 -26 -26 -23 -26 -23 -25 -25 -25 -23 -26 -23 -25 -25 -26 -22 -22 -26 -27 N0.C1: Calculating Bit Centers N0.C1: dimm = 0, rank = 0 Per Bit Margin Center Per Bit Skew N# = Nibble, BCx = Bit Center, BSx = Bit Skew , MSL = Most Skewed Lane N# BC0-BC1-BC2-BC3 BS0-BS1-BS2-BS3 MSL ============================================================================== 0 1 1 -2 -3 4 4 1 0 1 3 1 0 -2 5 3 2 0 2 1 -1 1 -1 2 0 2 0 3 2 2 2 0 2 2 2 0 4 4 1 1 -1 5 2 2 0 5 4 3 1 0 4 3 1 0 6 3 1 3 0 3 1 3 0 7 3 3 3 -1 4 4 4 0 8 3 1 2 0 3 1 2 0 9 3 2 3 0 3 2 3 0 10 1 0 2 0 1 0 2 0 11 0 2 2 -1 1 3 3 0 12 2 1 1 0 2 1 1 0 13 3 3 1 0 3 3 1 0 14 3 1 4 2 2 0 3 1 15 2 2 3 1 1 1 2 0 16 2 0 0 0 2 0 0 0 17 3 3 0 -1 4 4 1 0 START_DATA_RX_DQS_P_PER_BIT N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 4 4 1 0 5 3 2 0 2 0 2 0 2 2 2 0 5 2 2 0 4 3 1 0 3 1 3 0 4 4 4 0 3 1 2 0 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 3 2 3 0 1 0 2 0 1 3 3 0 2 1 1 0 3 3 1 0 2 0 3 1 1 1 2 0 2 0 0 0 4 4 1 0 N0: STOP_PER_BIT_DESKEW N0: START_PER_BIT_DESKEW ============================================================================== N0: Per Bit Deskew Rx N ============================================================================== PatternLength: 64 Per bit margins: Rx DqsN 0------7 8-----15 16----23 24----31 32----39 40----47 48----55 56----63 64----71 30 ******** ******** ******** ******** ******** ******** ******** ******** ******** 29 ******** ******** ******** ******** ******** ******** ******** ******** ******** 28 ******** ******** ******** ******** ******** ******** ******** ******** ******** 27 **** *** ******** ******** ******** ******** ** *** * ******** ******** ******** 26 *** *** ******** ******** ******** ******* ** ** * ******** * ***** *** ** 25 *** *** ******** **** *** ** ***** *** *** * * **** *** * *** * *** * 24 *** ** ****** * ** * ** *** * *** *** * * *** ** * * * * * 23 * * * * * ** * * * * ** * * * * * * 22 * * * * * * * * * * 21 * * 20 * -25 * * * -26 * * ** * * * * * * * ** -27 ** ** * * * ** * * * * * *** * * * * ** -28 ** ** * *** * ** * * *** * *** * * *** * * ** * ** * * ** -29 ** ** * **** *** **** ******* * * **** * * **** *** **** * ***** ******** -30 ** **** * * **** *** **** ******** *** **** ******** *** **** ******** ******** N0.C1.D0.R0: RxDqsN - Per bit margins 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 27 24 24 23 28 25 24 22 24 22 24 23 24 24 25 23 25 25 23 22 26 25 25 21 24 22 26 24 24 23 25 20 27 24 23 23 -25 -27 -31 -31 -27 -27 -30 -30 -27 -31 -30 -31 -27 -28 -28 -29 -25 -29 -29 -31 -26 -26 -29 -29 -26 -29 -28 -29 -27 -28 -28 -30 -26 -30 -29 -31 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 26 24 24 22 26 24 28 26 26 27 28 24 25 23 24 22 26 25 24 22 27 24 27 25 24 25 26 23 27 25 25 24 27 27 26 22 -28 -27 -28 -29 -26 -30 -28 -30 -27 -26 -27 -29 -28 -29 -28 -31 -27 -28 -29 -29 -26 -30 -26 -28 -29 -29 -29 -30 -26 -29 -28 -29 -26 -25 -29 -29 N0.C1: Calculating Bit Centers N0.C1: dimm = 0, rank = 0 Per Bit Margin Center Per Bit Skew N# = Nibble, BCx = Bit Center, BSx = Bit Skew , MSL = Most Skewed Lane N# BC0-BC1-BC2-BC3 BS0-BS1-BS2-BS3 MSL ============================================================================== 0 1 -1 -3 -4 5 3 1 0 1 0 -1 -3 -4 4 3 1 0 2 -1 -4 -3 -4 3 0 1 0 3 -1 -2 -1 -3 2 1 2 0 4 0 -2 -3 -4 4 2 1 0 5 0 0 -2 -4 4 4 2 0 6 -1 -3 -1 -2 2 0 2 1 7 -1 -2 -1 -5 4 3 4 0 8 0 -3 -3 -4 4 1 1 0 9 -1 -1 -2 -3 2 2 1 0 10 0 -3 0 -2 3 0 3 1 11 0 0 0 -2 2 2 2 0 12 -1 -3 -2 -4 3 1 2 0 13 0 -1 -2 -3 3 2 1 0 14 0 -3 0 -1 3 0 3 2 15 -2 -2 -1 -3 1 1 2 0 16 0 -2 -1 -2 2 0 1 0 17 0 1 -1 -3 3 4 2 0 START_DATA_RX_DQS_N_PER_BIT N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 5 3 1 0 4 3 1 0 3 0 1 0 2 1 2 0 4 2 1 0 4 4 2 0 2 0 2 1 4 3 4 0 4 1 1 0 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 2 2 1 0 3 0 3 1 2 2 2 0 3 1 2 0 3 2 1 0 3 0 3 2 1 1 2 0 2 0 1 0 3 4 2 0 N0: STOP_PER_BIT_DESKEW Rx Per Bit Deskew - 863ms Wr Vref Centering (LRDIMM) -- Started Checkpoint Code: Socket 0, 0xB7, 0x1E, 0x0000 Wr Vref Centering (LRDIMM) - 0ms Rd Vref Centering (LRDIMM) -- Started Checkpoint Code: Socket 0, 0xB7, 0x33, 0x0000 Rd Vref Centering (LRDIMM) - 0ms Wr Dq Centering (LRDIMM) -- Started Checkpoint Code: Socket 0, 0xB7, 0x34, 0x0000 Wr Dq Centering (LRDIMM) - 0ms Rd Dq Centering (LRDIMM) -- Started Checkpoint Code: Socket 0, 0xB7, 0x35, 0x0000 Rd Dq Centering (LRDIMM) - 0ms Wr Vref Centering -- Started Checkpoint Code: Socket 0, 0xB7, 0x09, 0x0000 N0: Timing offsets to test N0: tOffset 0 1 2 N0.C1.D0.R0: -4 4 0 N0: Get vref margins at 3 timing points START_TX_VREF_CENTER N0: vref Margins - 0 + N0.C1.D0.R0.S00: -31 : 29, -31 : 29, -31 : 29 N0.C1.D0.R0.S01: -31 : 29, -31 : 29, -31 : 29 N0.C1.D0.R0.S02: -31 : 29, -31 : 29, -31 : 29 N0.C1.D0.R0.S03: -31 : 29, -31 : 29, -31 : 29 N0.C1.D0.R0.S04: -31 : 29, -31 : 29, -31 : 29 N0.C1.D0.R0.S05: -31 : 29, -31 : 29, -31 : 29 N0.C1.D0.R0.S06: -31 : 29, -31 : 29, -31 : 29 N0.C1.D0.R0.S07: -31 : 29, -31 : 29, -31 : 29 N0.C1.D0.R0.S08: -31 : 29, -31 : 29, -31 : 29 STOP_TX_VREF_CENTER vrefLo vrefHi offset N0.C1.D0.R0.S00: -31 29 -1 N0.C1.D0.R0.S01: -31 29 -1 N0.C1.D0.R0.S02: -31 29 -1 N0.C1.D0.R0.S03: -31 29 -1 N0.C1.D0.R0.S04: -31 29 -1 N0.C1.D0.R0.S05: -31 29 -1 N0.C1.D0.R0.S06: -31 29 -1 N0.C1.D0.R0.S07: -31 29 -1 N0.C1.D0.R0.S08: -31 29 -1 N0.C1.D0.R0: txVrefSafe = 0x54 Wr Vref Centering - 137ms Rd Vref Centering -- Started Checkpoint Code: Socket 0, 0xB7, 0x08, 0x0000 N0: Timing offsets to test N0: tOffset 0 1 2 N0.C1.D0.R0: -4 4 0 N0: Get vref margins at 3 timing points START_RX_VREF_CENTER N0: vref Margins - 0 + N0.C1.D0.R0.S00: -48 : 47, -48 : 48, -48 : 48 N0.C1.D0.R0.S01: -48 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S02: -45 : 46, -48 : 48, -48 : 48 N0.C1.D0.R0.S03: -46 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S04: -48 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S05: -48 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S06: -48 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S07: -48 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S08: -48 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S09: -48 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S10: -47 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S11: -46 : 46, -48 : 48, -48 : 48 N0.C1.D0.R0.S12: -45 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S13: -48 : 47, -48 : 48, -48 : 48 N0.C1.D0.R0.S14: -48 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S15: -48 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S16: -48 : 48, -48 : 48, -48 : 48 N0.C1.D0.R0.S17: -47 : 47, -48 : 48, -48 : 48 STOP_RX_VREF_CENTER vrefLo vrefHi offset N0.C1.S00: -48 47 0 N0.C1.S01: -48 48 0 N0.C1.S02: -47 47 0 N0.C1.S03: -47 48 0 N0.C1.S04: -48 48 0 N0.C1.S05: -48 48 0 N0.C1.S06: -48 48 0 N0.C1.S07: -48 48 0 N0.C1.S08: -48 48 0 N0.C1.S09: -48 48 0 N0.C1.S10: -47 48 0 N0.C1.S11: -47 47 0 N0.C1.S12: -47 48 0 N0.C1.S13: -48 47 0 N0.C1.S14: -48 48 0 N0.C1.S15: -48 48 0 N0.C1.S16: -48 48 0 N0.C1.S17: -47 47 0 Rd Vref Centering - 213ms Tx Dq Adv -- Started Checkpoint Code: Socket 0, 0xB7, 0x07, 0x0000 N0: Get eye width N0.C1.D0.R0: High = 24 - Low = -22 N0.C1: Composite High = 24 - Composite Low = -22 N0: Low: -22 High: 24 N0: Offset = 1 N0: Eye width = 46 N0: Get eye height N0.C1.D0.R0: High = 30 - Low = -31 N0.C1: Composite High = 30 - Composite Low = -31 N0.C1.D0.R0: txVrefSafe = 0x54 N0: Low: -31 High: 30 N0: Eye height = 61 N0: numerator: 0 N0: denominator: 238400 N0: vrefRatio: 754, vrefRatioSpec: 1200 N0: Max offset from timing center: 0 N0: Timing Limited N0: GetMultiVref: patternLength = 64, stepSize = 7, numPoints = 7 margin = 0, vIndex = 3, Running 7 times pattern length START_DATA_TX_DQ_ADV N0.C1.D0.R0.S01: Truncated: -1 -> -2 N0.C1.D0.R0.S05: Truncated: 0 -> -1 N0.C1.D0.R0.S11: Truncated: -1 -> 0 N0.C1.D0.R0.S14: Truncated: -1 -> -2 Results for N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------- Vref offset: 21 Left: -17 -17 -17 -18 -20 -18 -18 -19 -18 -17 -16 -16 -18 -19 -19 -18 -18 -18 Right: 15 12 14 14 15 15 14 15 14 14 13 13 13 15 16 15 15 12 Vref offset: 14 Left: -21 -21 -19 -21 -22 -21 -21 -22 -21 -20 -20 -19 -20 -21 -22 -21 -22 -21 Right: 20 16 17 18 19 20 18 18 19 18 18 16 17 20 19 19 19 18 Vref offset: 7 Left: -24 -23 -22 -23 -24 -24 -23 -25 -23 -23 -23 -21 -23 -24 -25 -24 -24 -23 Right: 22 20 20 20 22 22 21 22 22 21 21 20 21 23 22 22 23 21 Vref offset: 0 Left: -26 -26 -24 -25 -27 -26 -25 -27 -26 -25 -26 -23 -25 -26 -27 -26 -27 -25 Right: 25 23 23 23 25 25 23 25 24 24 24 23 23 25 24 24 25 24 Vref offset: -7 Left: -26 -26 -25 -25 -27 -27 -25 -27 -26 -27 -27 -25 -25 -27 -28 -26 -28 -25 Right: 22 24 22 21 23 25 22 24 22 23 23 21 21 24 24 22 25 22 Vref offset: -14 Left: -24 -23 -24 -23 -24 -24 -23 -25 -24 -24 -24 -23 -23 -25 -25 -24 -25 -23 Right: 19 20 19 18 20 22 19 20 18 20 19 18 17 21 21 20 22 18 Vref offset: -21 Left: -21 -20 -21 -20 -22 -21 -20 -23 -21 -21 -21 -20 -20 -22 -23 -21 -23 -21 Right: 15 15 16 14 16 18 15 17 14 16 15 14 13 16 17 14 18 14 ------------------------------------------------------------------------------- Prev Pi: 213 203 189 187 175 185 196 203 172 216 206 190 188 177 190 198 208 175 New Pi: 212 201 188 186 174 184 195 202 171 215 205 190 187 176 188 197 207 174 Diff: -1 -2 -1 -1 -1 -1 -1 -1 -1 -1 -1 0 -1 -1 -2 -1 -1 -1 STOP_DATA_TX_DQ_ADV Tx Dq Adv - 329ms Rx Dq/Dqs Adv -- Started Checkpoint Code: Socket 0, 0xB7, 0x06, 0x0000 N0: Get eye width N0.C1.D0.R0: High = 24 - Low = -25 N0.C1: Composite High = 24 - Composite Low = -25 N0: Low: -25 High: 24 N0: Offset = 0 N0: Eye width = 49 N0: Get eye height N0.C1.D0.R0: High = 48 - Low = -48 N0.C1: Composite High = 48 - Composite Low = -48 N0: Low: -48 High: 48 N0: Eye height = 60 N0: numerator: 0 N0: denominator: 257960 N0: vrefRatio: 816, vrefRatioSpec: 1333 N0: Max offset from timing center: 0 N0: Timing Limited N0: GetMultiVref: patternLength = 64, stepSize = 7, numPoints = 7 margin = 0, vIndex = 3, Running 7 times pattern length START_DATA_RX_DQSN_ADV N0.C1.D0.R0.S00: Truncated: 0 -> -1 N0.C1.D0.R0.S01: Truncated: 0 -> -1 N0.C1.D0.R0.S03: Truncated: 1 -> 0 N0.C1.D0.R0.S04: Truncated: 0 -> -1 N0.C1.D0.R0.S06: Truncated: 0 -> -1 N0.C1.D0.R0.S07: Truncated: 0 -> -1 N0.C1.D0.R0.S08: Truncated: 1 -> 0 N0.C1.D0.R0.S09: Truncated: 1 -> 0 N0.C1.D0.R0.S10: Truncated: 0 -> -1 N0.C1.D0.R0.S11: Truncated: 0 -> -1 N0.C1.D0.R0.S12: Truncated: 0 -> -1 N0.C1.D0.R0.S13: Truncated: 0 -> -1 N0.C1.D0.R0.S15: Truncated: 0 -> -1 N0.C1.D0.R0.S16: Truncated: 0 -> -1 N0.C1.D0.R0.S17: Truncated: 0 -> -1 Results for N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------- Vref offset: 21 Left: -24 -24 -22 -23 -22 -25 -25 -24 -22 -23 -25 -22 -23 -23 -27 -24 -25 -24 Right: 24 24 23 25 24 25 25 25 26 25 24 24 24 24 25 24 25 24 Vref offset: 14 Left: -26 -26 -24 -25 -25 -27 -27 -26 -24 -26 -26 -24 -25 -26 -28 -26 -27 -25 Right: 25 26 26 26 26 27 27 26 27 26 26 24 25 25 27 26 26 26 Vref offset: 7 Left: -28 -27 -27 -26 -27 -27 -28 -27 -26 -26 -27 -26 -26 -27 -27 -27 -27 -26 Right: 26 26 27 26 27 27 26 27 27 27 26 26 25 26 27 25 27 27 Vref offset: 0 Left: -26 -26 -25 -24 -26 -26 -26 -26 -26 -25 -26 -25 -25 -26 -26 -26 -26 -26 Right: 24 24 25 25 25 26 24 25 26 25 25 24 24 24 26 24 25 25 Vref offset: -7 Left: -24 -24 -23 -23 -24 -25 -24 -24 -24 -23 -24 -24 -24 -25 -24 -25 -25 -24 Right: 23 23 24 24 25 24 24 25 24 24 24 24 23 24 25 23 24 24 Vref offset: -14 Left: -22 -22 -22 -21 -22 -23 -23 -23 -23 -21 -22 -22 -22 -22 -23 -23 -24 -22 Right: 22 22 23 23 23 23 23 23 23 23 23 23 22 22 23 22 23 23 Vref offset: -21 Left: -20 -21 -19 -19 -20 -21 -21 -21 -20 -19 -20 -20 -19 -20 -21 -21 -22 -19 Right: 21 21 21 22 22 22 21 21 23 22 22 22 21 22 22 22 22 23 ------------------------------------------------------------------------------- Prev Pi: 30 29 29 29 28 29 29 27 30 26 27 26 26 27 28 27 27 26 New Pi: 29 28 29 29 27 29 28 26 30 26 26 25 25 26 28 26 26 25 Diff: -1 -1 0 0 -1 0 -1 -1 0 0 -1 -1 -1 -1 0 -1 -1 -1 STOP_DATA_RX_DQSN_ADV N0: Get eye width N0.C1.D0.R0: High = 24 - Low = -24 N0.C1: Composite High = 24 - Composite Low = -24 N0: Low: -24 High: 24 N0: Offset = 0 N0: Eye width = 48 N0: Get eye height N0.C1.D0.R0: High = 48 - Low = -48 N0.C1: Composite High = 48 - Composite Low = -48 N0: Low: -48 High: 48 N0: Eye height = 60 N0: numerator: 0 N0: denominator: 255960 N0: vrefRatio: 800, vrefRatioSpec: 1333 N0: Max offset from timing center: 0 N0: Timing Limited N0: GetMultiVref: patternLength = 64, stepSize = 7, numPoints = 7 margin = 0, vIndex = 3, Running 7 times pattern length START_DATA_RX_DQSP_ADV N0.C1.D0.R0.S00: Truncated: 1 -> 0 N0.C1.D0.R0.S01: Truncated: 1 -> 0 N0.C1.D0.R0.S02: Truncated: 0 -> -1 N0.C1.D0.R0.S03: Truncated: 1 -> 0 N0.C1.D0.R0.S04: Truncated: 1 -> 0 N0.C1.D0.R0.S05: Truncated: 1 -> 0 N0.C1.D0.R0.S06: Truncated: 1 -> 0 N0.C1.D0.R0.S07: Truncated: 1 -> 0 N0.C1.D0.R0.S08: Truncated: 0 -> -1 N0.C1.D0.R0.S09: Truncated: 1 -> 0 N0.C1.D0.R0.S10: Truncated: 1 -> 0 N0.C1.D0.R0.S11: Truncated: 1 -> 0 N0.C1.D0.R0.S12: Truncated: 1 -> 0 N0.C1.D0.R0.S14: Truncated: 1 -> 0 N0.C1.D0.R0.S15: Truncated: 1 -> 0 N0.C1.D0.R0.S16: Truncated: 1 -> 0 N0.C1.D0.R0.S17: Truncated: 0 -> -1 Results for N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ------------------------------------------------------------------------------- Vref offset: 21 Left: -21 -22 -21 -23 -22 -23 -23 -22 -21 -22 -23 -20 -22 -23 -23 -23 -23 -22 Right: 25 25 24 26 26 26 26 26 25 25 26 25 25 27 27 26 26 26 Vref offset: 14 Left: -23 -24 -23 -25 -24 -25 -25 -24 -23 -24 -25 -22 -24 -25 -25 -25 -25 -24 Right: 26 26 25 27 27 27 27 27 25 27 27 26 26 28 28 27 28 27 Vref offset: 7 Left: -25 -26 -25 -26 -25 -27 -26 -25 -25 -26 -27 -24 -26 -27 -27 -27 -27 -26 Right: 26 27 26 26 28 28 27 28 26 27 26 26 26 28 27 27 28 26 Vref offset: 0 Left: -24 -24 -25 -25 -27 -26 -25 -26 -25 -24 -25 -25 -25 -25 -26 -25 -26 -25 Right: 24 25 24 25 27 26 25 27 24 25 26 26 25 27 26 25 27 24 Vref offset: -7 Left: -23 -23 -23 -24 -25 -24 -23 -24 -24 -22 -24 -23 -24 -24 -24 -24 -24 -24 Right: 24 24 23 25 26 26 25 27 24 24 24 25 25 26 25 25 26 24 Vref offset: -14 Left: -21 -21 -22 -22 -23 -23 -22 -23 -22 -21 -21 -22 -22 -22 -23 -22 -23 -22 Right: 23 24 22 23 25 24 24 25 23 23 23 23 24 25 24 24 24 22 Vref offset: -21 Left: -18 -19 -19 -18 -22 -21 -20 -21 -20 -19 -20 -20 -20 -21 -21 -21 -21 -20 Right: 21 22 21 22 24 23 22 24 22 22 22 22 22 24 23 23 24 22 ------------------------------------------------------------------------------- Prev Pi: 31 32 32 32 32 32 33 31 32 28 30 30 30 30 29 30 31 28 New Pi: 31 32 31 32 32 32 33 31 31 28 30 30 30 31 29 30 31 27 Diff: 0 0 -1 0 0 0 0 0 -1 0 0 0 0 1 0 0 0 -1 STOP_DATA_RX_DQSP_ADV Rx Dq/Dqs Adv - 649ms Round Trip Optimization -- Started Checkpoint Code: Socket 0, 0xB7, 0x13, 0x0000 Round Trip Optimization - 0ms Display Training Results -- Started N0: START_TRAINING_REGISTER_DUMP START_DATA_XOVER CMDn0 CMDn1 CMDs0 CMDs1 CTL CKE CLK 0 1 2 3 4 5 6 7 8 N0.C1: 10 43 41 46 44 16 49 22 55 26 60 30 59 26 56 30 START_DATA_REC_EN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 179 158 135 108 85 100 131 155 87 189 167 146 118 98 110 142 166 99 N0.C1.D0.R0: IO Latency = 6, Round Trip = 55 START_DATA_RX_DQSP 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 31 32 31 32 32 32 33 31 31 28 30 30 30 31 29 30 31 27 START_DATA_RX_DQSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 29 28 29 29 27 29 28 26 30 26 26 25 25 26 28 26 26 25 START_DATA_WR_LVL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1: t_cwl_adj = 2 N0.C1.D0.R0: 180 168 155 151 139 151 161 167 137 START_DATA_TX_DQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 212 201 188 186 174 184 195 202 171 215 205 190 187 176 188 197 207 174 START_DATA_RX_VREF 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1: 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 65 START_DATA_TxVref 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 84 84 84 84 84 84 84 84 84 START_DATA_CMD 0n 1n 2n 3n 4n 5n 0s 1s 2s 3s 4s 5s N0.C1: 98 98 97 96 98 97 98 96 97 97 96 100 START_DATA_CLK 0 1 2 3 N0.C1: 0 0 0 0 START_DATA_CTL 0n 1n 2n 3n 4n 5n 6n 7n 8n 9n 0s 1s 2s 3s 4s 5s 6s 7s 8s 9s 10s N0.C1: 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 START_DATA_MRS MR0 MR1 MR2 MR3 MR4 MR5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 738 101 E0 0 0 40 894 894 894 894 894 894 894 894 894 START_DATA_RX_DQS_P_PER_BIT N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 4 4 1 0 5 3 2 0 2 0 2 0 2 2 2 0 5 2 2 0 4 3 1 0 3 1 3 0 4 4 4 0 3 1 2 0 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 3 2 3 0 1 0 2 0 1 3 3 0 2 1 1 0 3 3 1 0 2 0 3 1 1 1 2 0 2 0 0 0 4 4 1 0 START_DATA_RX_DQS_N_PER_BIT N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 5 3 1 0 4 3 1 0 3 0 1 0 2 1 2 0 4 2 1 0 4 4 2 0 2 0 2 1 4 3 4 0 4 1 1 0 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 2 2 1 0 3 0 3 1 2 2 2 0 3 1 2 0 3 2 1 0 3 0 3 2 1 1 2 0 2 0 1 0 3 4 2 0 START_DATA_TX_DQ_PER_BIT N0.C1.D0.R0: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 20 21 22 20 23 27 26 28 9 10 10 11 13 14 17 20 60 62 61 60 62 66 65 68 58 58 58 59 59 62 64 66 47 48 48 46 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 48 52 50 53 56 57 57 58 60 60 62 65 4 5 4 3 5 8 8 10 10 12 10 11 15 15 16 18 43 47 45 44 46 49 49 52 START_DATA_CMD_VREF_CENTERING_OFFSETS N0.C1: 32 START_SENSE_AMP_TRAINING_OFFSETS BitSAmp for Channel 1 bit: 0 1 2 3 N0.C1: Nibble 0: 16 13 13 13 N0.C1: Nibble 1: 12 15 12 13 N0.C1: Nibble 2: 15 15 14 13 N0.C1: Nibble 3: 14 13 13 14 N0.C1: Nibble 4: 15 15 16 13 N0.C1: Nibble 5: 14 13 13 15 N0.C1: Nibble 6: 15 13 13 14 N0.C1: Nibble 7: 13 14 14 14 N0.C1: Nibble 8: 15 13 13 14 N0.C1: Nibble 9: 15 13 13 15 N0.C1: Nibble 10: 15 15 12 14 N0.C1: Nibble 11: 13 15 15 14 N0.C1: Nibble 12: 13 13 14 13 N0.C1: Nibble 13: 14 15 12 14 N0.C1: Nibble 14: 14 13 14 15 N0.C1: Nibble 15: 12 15 14 13 N0.C1: Nibble 16: 15 15 14 14 N0.C1: Nibble 17: 14 14 14 13 START_POWER_TRAINING_DUMP START_DATA_TX_IMODE 0 1 2 3 4 5 6 7 8 N0.C1.D0.R0: 15 15 15 15 15 15 15 15 15 START_DATA_RX_EQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_DATA_RX_CTLE_C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_DATA_RX_CTLE_R 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_DATA_DRAM_DRVSTR N0.C1.D0.R0: 34 START_DATA_TX_RON N0.C1: -32693 START_DATA_WR_ODT N0.C1.D0.R0: 0 START_DATA_RX_ODT N0.C1: -32693 START_DATA_PARK_ODT N0.C1.D0.R0: 60 START_DATA_NOM_ODT N0.C1.D0.R0: 60 START_DATA_TX_EQ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 N0.C1.D0.R0: 4 10 0 10 6 6 0 8 4 4 10 0 10 6 6 0 8 4 START_SWIZZLE_TRAINING_RESULTS Pattern 0 1 2 3 4 5 N0.C1: E400FE00 E4E4E4E4 E4E4E4E4 E4E4E4E4 E4E4E4E4 E4 START_COMP_REG_DUMP Ch COMP 0 1 2 3 4 5 6 7 8 1 DrvUp 47 47 47 47 47 47 47 47 47 1 DrvDn 43 43 43 43 43 43 43 43 43 Ch COMP 0 1 2 3 4 5 6 7 8 1 ODTUp 38 38 38 38 38 38 38 38 38 1 ODTDn 36 36 36 36 36 36 36 36 36 Ch COMP 0 1 2 3 4 5 6 7 8 1 Scomp 10 10 10 10 10 10 10 10 10 Ch COMP CLK CMD_n CMD_s CTL_cke CTL_ctl 1 DrvUp 44 17 17 44 44 1 DrvDn 40 17 17 40 40 Ch COMP CLK CMD_n CMD_s CTL_cke CTL_ctl 1 Scomp 10 15 15 10 10 N0: STOP_TRAINING_REGISTER_DUMP N0: STOP_TRAINING_REGISTER_DUMP Display Training Results - 750ms Post-Training Initialization -- Started N0.C0.D0: dimmMtr: 0x001F000C N0.C0.D1: dimmMtr: 0x000F000C N0.C0.D2: dimmMtr: 0x000F000C N0.C1.D0: dimmMtr: 0x001E414C N0.C1.D1: dimmMtr: 0x000F0000 N0.C1.D2: dimmMtr: 0x000F0000 N0.C2.D0: dimmMtr: 0x001F000C N0.C2.D1: dimmMtr: 0x000F000C N0.C2.D2: dimmMtr: 0x000F000C N0.C3.D0: dimmMtr: 0x001F000C N0.C3.D1: dimmMtr: 0x000F000C N0.C3.D2: dimmMtr: 0x000F000C N0: (x10000) tck = 9375, tPDM_RD=20313, tPDM_WR=20313, tWRPRE=0, tRPRE=0, BL=80000, specMin=4 N0.C1: tRRDR = 1 N0.C1: tRRDD = 1 N0.C1: odtStretch = 0 N0.C1: tWWDR = 3, minWWDR = 3 N0.C1: odtStretch = 0 N0.C1: tWWDD = 3, minWWDD = 3 N0.C1: specMin = 4, tRWSR = 4 N0.C1: specMin = 4, tRWDR = 5 N0.C1: tRWDD = 5 N0.C1: odtStretch = 0 N0.C1: tWRDR = 1 N0.C1: odtStretch = 0 N0.C1: tWRDD = 1 N0.C1: t_rrdr = 1, t_rrdd = 1 Post-Training Initialization - 78ms Rank Margin Tool -- Started Checkpoint Code: Socket 0, 0xB7, 0x10, 0x0000 Rank Margin Tool - 0ms Fill BDAT Structure -- Started Fill BDAT Structure - 0ms Platform Restore NVDIMMs -- Started N0: PlatformRestoreNVDIMMs Platform Restore NVDIMMs - 2ms Platform Arm NVDIMMs -- Started N0: PlatformArmNVDIMMs Platform Arm NVDIMMs - 2ms Late Configuration -- Started Checkpoint Code: Socket 0, 0xB7, 0x11, 0x0000 N0: DRAM Maintenance N0.C1.D0.R0: Write RC0E = 0x0D N0: Enabling C/A Parity N0.C1.D0.R0: Write RC20 = 0x01 No Pending Reset, clearing the ADR status bit Late Configuration - 15ms Initialize Throttling -- Started Checkpoint Code: Socket 0, 0xB8, 0x00, 0x0000 Initialize Throttling N0.C1.D0: Initialize DRAM RAPL N0: Initialize DRAM Phase Shedding Initialize Throttling - 150ms Advanced MemTest -- Started Checkpoint Code: Socket 0, 0xB9, 0x00, 0x0000 Advanced MemTest - 0ms MemTest -- Started Checkpoint Code: Socket 0, 0xB9, 0x00, 0x0000 MemTest - 832ms MemInit -- Started Checkpoint Code: Socket 0, 0xBA, 0x00, 0x0000 MemInit - 423ms Check Ras Support After MemInit -- Started N0.C0.D0: dimmMtr: 0x001F000C N0.C0.D1: dimmMtr: 0x000F000C N0.C0.D2: dimmMtr: 0x000F000C N0.C1.D0: dimmMtr: 0x001E414C N0.C1.D1: dimmMtr: 0x000F0000 N0.C1.D2: dimmMtr: 0x000F0000 N0.C2.D0: dimmMtr: 0x001F000C N0.C2.D1: dimmMtr: 0x000F000C N0.C2.D2: dimmMtr: 0x000F000C N0.C3.D0: dimmMtr: 0x001F000C N0.C3.D1: dimmMtr: 0x000F000C N0.C3.D2: dimmMtr: 0x000F000C Check Ras Support After MemInit - 36ms Switch to Normal Mode -- Started Checkpoint Code: Socket 0, 0xB7, 0x12, 0x0000 N0: MboxStatus: 0 PCU_MISC_CONFIG = 0x1000000 N0: MBoxStatus: 0 PCU_MISC_CONFIG = 0x0 Switch to Normal Mode - 8ms Get NVRAM Data -- Started Get NVRAM Data - 0ms Initialize Memory Map -- Started Checkpoint Code: Socket 0, 0xBB, 0x00, 0x0000 N0.C1.D0: Memory Found! TAD setup HA 0 ----------- Memory Map Info ---------------- Socket XOR Config = Non-XOR mode Socket RAS Config = Channel Independent NUMA Config Socket Interleave Ways: 1 System Mem Size (64MB granularity): 0x40 SAD Table Rule Enable Limit Mode Ways Interleave List(right to left) ------------------------------------------------------------------- 0 1 0x60 0 1 00000000 ----------- Socket Info ---------------- ----------- Socket 0 Socket Enabled Socket max DIMM pop count = 1 Socket mem size (64MB) = 0x40 ----------- TAD Info ---------------- TAD Table (Socket 0) Rule Enable Limit Mode Ch Ways --------------------------------------- Home Agent 0 0 1 0x20 0 1 TAD Interleave List Way Target Offset ChIndex 0 1 0x0 0 1 0 0x0 0 2 0 0x0 0 3 0 0x0 0 1 1 0x60 0 1 TAD Interleave List Way Target Offset ChIndex 0 1 0x0 0 1 0 0x20 0 2 0 0x0 0 3 0 0x0 0 ----------- Channel Info ---------------- ----------- Channel 0 Channel not enabled ----------- Channel 1 Channel Enabled Channel mem size (64MB) = 0x40 ----------- RIR Info ---------------- RIR Table (Socket 0, Channel 1) ---------------------------------------------- Rule Enable Limit(Ch Space) Ways 0 1 0x40 1 Rank Interleave List Way Target Offset 0 0 0 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 ----------- Channel 2 Channel not enabled ----------- Channel 3 Channel not enabled ----------- Socket 1 Socket not enabled ----------- Socket 2 Socket not enabled ----------- Socket 3 Socket not enabled highMemBase: 0x40 highMemSize: 0x20 TOLM: 0x1F TOHM: 0x5F Initialize Memory Map - 168ms Set RAS Configuration -- Started Checkpoint Code: Socket 0, 0xBC, 0x00, 0x0000 Set RAS Config N0: Independent ch mode enabled N0: Patrol scrub enabled and started N0: Demand scrub enabled ECC is enabled Set RAS Configuration - 12ms Memory Late -- Started Memory Late - 0ms DIMM Information -- Started START_DIMMINFO_TABLE ====================================================================================== START_SOCKET_0_TABLE BDX V2/V3 - DE ====================================================================================== S| Channel 0 | Channel 1 | Channel 2 | Channel 3 | ====================================================================================== 0| Not installed | DIMM: Micron | Not installed | Not installed | | | DRAM: Micron | | | | | RCD: Montage | | | | | 4GB(4Gbx8 1H SR) | | | | | DDR4 RDIMM R/C-D | | | | | 2400 15-15-15 | | | | | ww12 2018 | | | | |9ASF51272PZ-2G3B1 | | | | |0x0000000000000000 | | | | | | | | -------------------------------------------------------------------------------------- 1| Not installed | Not installed | Not installed | Not installed | -------------------------------------------------------------------------------------- STOP_SOCKET_0_TABLE ====================================================================================== ====================================================================================== | Socket 0 | Socket 1 | Socket 2 | Socket 3 | System | ====================================================================================== Active Memory | 4GB | N/A | N/A | N/A | 4GB | DDR Freq | | | | | DDR4-2133 | Ch1 CL-RCD-RP-CMD |15-15-15-1n | | | | | DDR Vdd | | | | | 1.20V | ECC Checking | | | | | On | CAP Checking | | | | | On | Patrol/Demand Scrub | | | | | On/On | RAS Mode | | | | | Indep | Xover Mode | | | | | 2:2 | Paging Policy | | | | | Adapt Open | Data Scrambling | | | | | On | CCMRC Revision | | | | | 00.50.00 | RC Revision | | | | | 02.04.00 | ====================================================================================== STOP_DIMMINFO_TABLE ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Platform DIMM Configuration ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Socket : 0 Channel : 0 ddr4Size : 0 volSize : 0 perSize : 0 blkSize : 0 Channel : 1 ddr4Size : 64 volSize : 0 perSize : 0 blkSize : 0 Channel : 2 ddr4Size : 0 volSize : 0 perSize : 0 blkSize : 0 Channel : 3 ddr4Size : 0 volSize : 0 perSize : 0 blkSize : 0 DIMM Information - 353ms Total MRC time = 19203ms Setting Last Boot Date = 7272 days STOP_MRC_RUN Checkpoint Code: Socket 0, 0xBF, 0x00, 0x0000 nvram[0].ppin.hi: 0x25BEAAB, var[0].ppin.hi: 0x25BEAAB nvram[0].ppin.lo: 0x51561DAB, var[0].ppin.lo: 0x51561DAB Install EFI Memory Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE MRC: lowMemBase:0 lowMemSize:20 MRC: highMemBase:40 highMemSize:20 TSEG Unaligned Size is 0x00800000 TSEG Aligned Size is 0x00800000 Low Memory Discovered at 0x00000000 - 0x7F800000 PeiInstallPeiMemory MemoryBegin 0x7F000000, MemoryLength 0x800000 TopOfHighMem 0x180000000 High Memory Discovered at 0x100000000 - 0x180000000 Save NVRAM restore data into Hob MRC status = 00000000 UMA: Memory retrain occurred during warm reset. Force ME FW reload. ME UMA: ------------- MePlatformPolicyPpi Dump Begin ------------- Revision : 0x2 DidEnabled : 0x1 DidTimeout : 0x0 DidInitStat : 0x0 ME UMA: ------------- MePlatformPolicyPpi Dump End ---------------- ME UMA: Entered ME DRAM Init Done procedure. ME UMA: MeUmaBase read: FFF80000 ME UMA: InitStat: 3 ME UMA: ME H_GS written: 1300FFFF ME UMA: HFS read before DID ACK: 0x000F0345 ME UMA: BiosAction = 0 MeDramInitDone Complete. Checking for reset... ME UMA: MeFwsts2 = 3800E000. ME UMA: DID Ack was not received, no BIOS Action to process. Reset Requested: 0 Pipe Exit starting...Pipe Exit completed! Reset Requested: 0 Checking for Reset Requests ... None Continue with system BIOS POST ... mmCfgBase 80000000 QPI: CPU[0] bus = FF QPI: IIO[0] bus = 0 QPI: IIO[0] busbase = 0 Limit=FF QPI: IIO[0] IoBase = 0 IoLimit=FFFF QPI: IIO[0] IoApicBase = FEC00000 IoApicLimit=FEC3FFFF QPI: IIO[0] Mem32Base = 90000000 Mem32Limit=FBFFFFFF QPI: IIO[0] VtdBarAddress = FBFFC000 RcbaAddress=FBFFE000 PCI: IIO[0] NEW!PciResourceMem32Limit=FBFFBFFF QPI: CPU[1] is invalid QPI: IoApic[1] is invalid QPI: CPU[2] is invalid QPI: IoApic[2] is invalid QPI: CPU[3] is invalid QPI: IoApic[3] is invalid QPI: num of Cpus = 1 QPI: num of IIOs = 1 Node:0 BaseAddress:00000000 ElementSize:00000060 Setting pam0_hienable = 3 Setting pam1_loenable = 3 Setting pam1_hienable = 3 Setting pam2_loenable = 3 Setting pam2_hienable = 3 Setting pam3_loenable = 3 Setting pam3_hienable = 3 Setting pam4_loenable = 3 Setting pam4_hienable = 3 Setting pam5_loenable = 3 Setting pam5_hienable = 3 Setting pam6_loenable = 3 Setting pam6_hienable = 3 PeimMemoryQpiInit END Temp Stack : BaseAddress=0xFE184000 Length=0x7C000 Temp Heap : BaseAddress=0xFE108000 Length=0x27210 Total temporary memory: 1015808 bytes. temporary memory stack ever used: 482048 bytes. temporary memory heap used: 160272 bytes. Old Stack size 507904, New stack size 1048576 Heap Offset = 0x0 Stack Offset = 0x7F100000 Stack Hob: BaseAddress=0x7F000000 Length=0x100000 Loading PEIM at 0x0007F7F5198 EntryPoint=0x0007F7F5260 PeiCore.efi Reinstall PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3 Reinstall PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A Reinstall PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6 Install PPI: F894643D-C449-42D1-8EA8-85BDD8C65BDE Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: FFEDAD80 Memory Discovered Notify invoked ... Loading PEIM at 0x0007F7EF188 EntryPoint=0x0007F7EF260 FspDxeIpl.efi Install PPI: EE4E5898-3914-4259-9D6E-DC7BD79403CF Install PPI: 0AE8CE5D-E448-4437-A8D7-EBF5F194F731 Install PPI: 1A36E4E7-FAB6-476A-8E75-695A0576FDD7 Loading PEIM at 0x0007F7E4000 EntryPoint=0x0007F7E4260 PcatSingleSegmentPciCfg2Pei.efi Install PPI: 057A449A-1FDC-4C06-BFC9-F53F6A99BB92 Loading PEIM at 0x0007F7CB000 EntryPoint=0x0007F7CB260 PlatformEarlyInit.efi PowerStateAfterG3 Default has been overridden by UPD option to 0 Install PPI: A7CED760-C71C-4E1A-ACB1-89604D5216CB Install PPI: 15344673-D365-4BE2-8513-1497CC07611D Loading PEIM at 0x0007F7B4000 EntryPoint=0x0007F7B4260 PchInitPeim.efi InstallPchInitPpi() - Start Rcba needs to be programmed before here PchMiscEarlyInit() - Start PchMiscEarlyInit() - End Install PPI: ED097352-9041-445A-80B6-B29D509E8845 Install PPI: 09EA894A-BE0D-4230-A003-EDC693B48E95 Register PPI Notify: 15344673-D365-4BE2-8513-1497CC07611D Notify: PPI Guid: 15344673-D365-4BE2-8513-1497CC07611D, Peim notify entry point: 7F7B5327 PchInitialize() - Start PchSataInit() - Start PchSataInit() - End [MPHY] Creating HOB to adjust Hsio settings from DXE, if required. [MPHY] SystemConfiguration.MeMphyDebugEnableSurvivabilityTable:0 [MPHY] SystemConfiguration.MeMphyDebugCorruptEndpoints:0 [MPHY] Suppress passing the expected ChipsetInit table to the DXE code, and further on to ME Unsupported PCH Stepping for PchDmiHsio PchInitialize() - End Install PPI: 1EDCBDF9-FFC6-4BD4-94F6-195D1DE17056 InstallPchInitPpi() - End Loading PEIM at 0x0007F7A7000 EntryPoint=0x0007F7A7260 IioDmiInitPeim.efi DEBUG:::: IioDmiInitPeiEntryPoint() Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE, Peim notify entry point: 7F7A7515 PchDmiGen2Prog() Start PchDmiGen2Prog() End DEBUG:::: DmiVc1 = 0 ; DmiVcp = 0 ; DmiVcm = 0 Register PPI Notify: 1E2ACC41-E26A-483D-AFC7-A056C34E087B Notify: PPI Guid: 1E2ACC41-E26A-483D-AFC7-A056C34E087B, Peim notify entry point: 7F7A7E1E DEBUG:::: IioSouthComplexPeiInit() Enable/disable the SC CBDMA and GbE ports in the IIO IOSF bridge...(0,2,0,0x190) = 0x33 Loading PEIM at 0x0007F796000 EntryPoint=0x0007F796260 CpuCsrAccess.efi Install PPI: 0067835F-9A50-433A-8CBB-852078197814 Loading PEIM at 0x0007F74F000 EntryPoint=0x0007F74F280 IioInit.efi IsocEn changed because QPI config. IsocEn =0 Bifurcation of the ConfigIOU1 (Port#3) for CBM will be updated to = 4 Bifurcation of the ConfigIOU2 (Port#1) for CBM will be updated to = 1 Install PPI: DDC3080A-2740-4EC2-9AA5-A0ADEFD6FF9C Socket 0 does not support uplink port! Update iioErrPinDatReg = 7 EarlyCtlePhaseSettings for IIO[0] LbcPerIouData Addr 30604 = 0x3C46 LbcPerIouControl Addr 30600 = 0x975 LbcPerIouData Addr 30604 = 0x3C46 LbcPerIouControl Addr 30600 = 0x1175 LbcPerIouData Addr 30604 = 0x3C46 LbcPerIouControl Addr 30600 = 0x2175 LbcPerIouData Addr 30604 = 0x3C46 LbcPerIouControl Addr 30600 = 0x4175 LbcPerIouData Addr 31604 = 0x3C46 LbcPerIouControl Addr 31600 = 0x975 LbcPerIouData Addr 31604 = 0x3C46 LbcPerIouControl Addr 31600 = 0x1175 LbcPerIouData Addr 31604 = 0x3C46 LbcPerIouControl Addr 31600 = 0x2175 LbcPerIouData Addr 31604 = 0x3C46 LbcPerIouControl Addr 31600 = 0x4175 LbcPerIouData Addr 31604 = 0x3C46 LbcPerIouControl Addr 31600 = 0x8175 LbcPerIouData Addr 31604 = 0x3C46 LbcPerIouControl Addr 31600 = 0x10175 LbcPerIouData Addr 31604 = 0x3C46 LbcPerIouControl Addr 31600 = 0x20175 LbcPerIouData Addr 31604 = 0x3C46 LbcPerIouControl Addr 31600 = 0x40175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x975 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x1175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x2175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x4175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x8175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x10175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x20175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x40175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x80175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x100175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x200175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x400175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x800175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x1000175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x2000175 LbcPerIouData Addr 38604 = 0x3C46 LbcPerIouControl Addr 38600 = 0x4000175 Program Uniphy recipe Revision 6.00 Program RX Recipe values Start. B0 D6 F0 O30760h = 0x55 B0 D6 F1 O31760h = 0xAAAA B0 D7 F0 O38760h = 0xAAAAAAAA B0 D6 F0 O30710h = 0x208 B0 D6 F1 O31710h = 0x208208 B0 D7 F0 O38710h = 0x8208208 B0 D7 F0 O38714h = 0x8208 B0 D6 F0 O30708h = 0x410 B0 D6 F1 O31708h = 0x410410 B0 D7 F0 O38708h = 0x10410410 B0 D7 F0 O3870Ch = 0x10410 B0 D6 F0 O30704h = 0x12 B0 D6 F1 O31704h = 0x492 B0 D7 F0 O38704h = 0x492492 B0 D6 F0 O30700h = 0x24 B0 D6 F1 O31700h = 0x924 B0 D7 F0 O38700h = 0x924924 B0 D6 F0 O30730h = 0x0 B0 D6 F1 O31730h = 0x0 B0 D7 F0 O38730h = 0x0 B0 D6 F0 O30734h = 0x0 B0 D6 F1 O31734h = 0x0 B0 D7 F0 O38734h = 0x0 B0 D7 F0 O38738h = 0x0 B0 D6 F0 O30A50h = 0x3 B0 D6 F1 O31A50h = 0xF B0 D7 F0 O38A50h = 0xFF B0 D6 F0 O30A60h = 0x0 B0 D6 F1 O31A60h = 0x0 B0 D7 F0 O38A60h = 0x0 B0 D6 F1 O31A64h = 0xAA B0 D7 F0 O38A64h = 0xAAAA B0 D6 F0 O30788h = 0xAA B0 D6 F1 O31788h = 0xAAAA B0 D7 F0 O38788h = 0xAAAAAAAA B0 D6 F0 O30780h = 0xA B0 D6 F1 O31780h = 0xAA B0 D7 F0 O38780h = 0xAAAA B0 D6 F0 O30790h = 0xF B0 D6 F1 O31790h = 0xFF B0 D7 F0 O38790h = 0xFFFF B0 D6 F0 O306ECh = 0x42108 B0 D6 F1 O316ECh = 0x10842108 B0 D6 F1 O316F0h = 0x108 B0 D7 F0 O386ECh = 0x10842108 B0 D7 F0 O386F0h = 0x10842108 B0 D7 F0 O386F4h = 0x42108 B0 D6 F1 O316E0h = 0x16B5AD6B B0 D6 F1 O316E4h = 0x16B B0 D7 F0 O386E0h = 0x16B5AD6B B0 D7 F0 O386E4h = 0x16B5AD6B B0 D7 F0 O386E8h = 0x5AD6B B0 D6 F0 O307B0h = 0xFF B0 D6 F1 O317B0h = 0xFFFF B0 D7 F0 O387B0h = 0xFFFFFFFF B0 D6 F0 O30798h = 0xF B0 D6 F1 O31798h = 0xFF B0 D7 F0 O38798h = 0xFFFF B0 D6 F0 O30794h = 0x0 B0 D6 F1 O31794h = 0x0 B0 D7 F0 O38794h = 0x0 B0 D6 F0 O307A0h = 0x0 B0 D6 F1 O317A0h = 0x0 B0 D7 F0 O387A0h = 0x0 B0 D7 F0 O387A4h = 0x0 B0 D6 F0 O306C8h = 0x5 B0 D6 F1 O316C8h = 0x55 B0 D7 F0 O386C8h = 0x5555 B0 D6 F0 O306CCh = 0x3 B0 D6 F1 O316CCh = 0xF B0 D7 F0 O386CCh = 0xFF B0 D6 F7 O37650h = 0xC B0 D6 F0 O306ACh = 0xF B0 D6 F1 O316ACh = 0xFF B0 D7 F0 O386ACh = 0xFFFF B0 D6 F0 O306A0h = 0xFF B0 D6 F1 O316A0h = 0xFFFF B0 D7 F0 O386A0h = 0xFFFFFFFF B0 D6 F1 O31A38h = 0x200020 B0 D6 F1 O31A3Ch = 0x200020 B0 D7 F0 O38A38h = 0x200020 B0 D7 F0 O38A3Ch = 0x200020 B0 D7 F0 O38A40h = 0x200020 B0 D7 F0 O38A44h = 0x200020 B0 D6 F1 O31A88h = 0x5555 B0 D7 F0 O38A88h = 0x55555555 B0 D6 F0 O30A8Ch = 0x55 B0 D6 F1 O31A8Ch = 0x5555 B0 D7 F0 O38A8Ch = 0x55555555 B0 D6 F1 O31A90h = 0xBBBB B0 D7 F0 O38A90h = 0xBBBBBBBB B0 D6 F0 O30840h = 0x1EF B0 D6 F1 O31840h = 0x5AD6B B0 D7 F0 O38840h = 0x16B5AD6B B0 D7 F0 O38844h = 0x16B B0 D6 F0 O30838h = 0x16B B0 D6 F1 O31838h = 0x9CE73 B0 D7 F0 O38838h = 0x2739CE73 B0 D7 F0 O3883Ch = 0x273 B0 D6 F7 O37644h = 0x238100 B0 D6 F7 O37648h = 0x14000200 B0 D6 F7 O37628h = 0x12 B0 D6 F7 O37638h = 0x132 B0 D6 F7 O37614h = 0x202C000 B0 D6 F7 O3760Ch = 0xB B0 D6 F7 O37608h = 0x5000010 B0 D6 F7 O37608h = 0x4000010 B0 D6 F7 O37608h = 0x4000010 B0 D6 F7 O37634h = 0x24010 B0 D6 F7 O37654h = 0x1 B0 D6 F0 O30300h = 0x81300000 B0 D6 F1 O31300h = 0x81300000 B0 D6 F2 O32300h = 0x81300000 B0 D7 F0 O38300h = 0x81300000 B0 D7 F1 O39300h = 0x81300000 B0 D7 F2 O3A300h = 0x81300000 B0 D7 F3 O3B300h = 0x81300000 B0 D6 F0 O30300h = 0x81300000 B0 D6 F1 O31300h = 0x81300000 B0 D6 F2 O32300h = 0x81300000 B0 D7 F0 O38300h = 0x81300000 B0 D7 F1 O39300h = 0x81300000 B0 D7 F2 O3A300h = 0x81300000 B0 D7 F3 O3B300h = 0x81300000 B0 D6 F0 O30300h = 0x81200000 B0 D6 F1 O31300h = 0x81200000 B0 D6 F2 O32300h = 0x81200000 B0 D7 F0 O38300h = 0x81200000 B0 D7 F1 O39300h = 0x81200000 B0 D7 F2 O3A300h = 0x81200000 B0 D7 F3 O3B300h = 0x81200000 B0 D6 F0 O306B0h = 0x0 B0 D6 F1 O316B0h = 0x0 B0 D7 F0 O386B0h = 0x0 B0 D7 F0 O386B4h = 0x0 B0 D1 F0 O825Ch = 0x2777 B0 D1 F1 O925Ch = 0x2777 B0 D3 F0 O1825Ch = 0x2777 B0 D3 F1 O1925Ch = 0x2777 B0 D3 F2 O1A25Ch = 0x2777 B0 D3 F3 O1B25Ch = 0x2777 B0 D6 F0 O307C0h = 0x36 B0 D6 F1 O317C0h = 0xDB6 B0 D7 F0 O387C0h = 0xDB6DB6 B0 D6 F0 O30480h = 0xAE0449E2 B0 D6 F1 O31480h = 0xAE0449E2 B0 D7 F0 O38480h = 0xAE0449E2 B0 D6 F0 O30464h = 0x70BFE3 B0 D6 F1 O31464h = 0x70BFE3 B0 D7 F0 O38464h = 0x70BFE3 B0 D6 F1 O31464h = 0x73FFE3 B0 D7 F0 O38464h = 0x73FFE3 B0 D6 F0 O30490h = 0x4 B0 D6 F1 O31490h = 0x4 B0 D6 F2 O32490h = 0x4 B0 D7 F0 O38490h = 0x4 B0 D7 F1 O39490h = 0x4 B0 D7 F2 O3A490h = 0x4 B0 D7 F3 O3B490h = 0x4 B0 D6 F0 O304BCh = 0x29439104 B0 D6 F1 O314BCh = 0x29439105 B0 D7 F0 O384BCh = 0x29439105 B0 D6 F0 O30B04h = 0x48087185 B0 D6 F1 O31B04h = 0x48006181 B0 D7 F0 O38B04h = 0x48006181 B0 D6 F0 O303F4h = 0x8A340C10 B0 D6 F1 O313F4h = 0x8A340C10 B0 D7 F0 O383F4h = 0x8A340C10 B0 D6 F0 O3048Ch = 0x2120000 B0 D6 F1 O3148Ch = 0x2020000 B0 D7 F0 O3848Ch = 0x2020000 B0 D6 F0 O304C4h = 0x10083 B0 D6 F1 O314C4h = 0x10083 B0 D7 F0 O384C4h = 0x10083 B0 D6 F1 O3139Ch = 0x641000 B0 D6 F2 O3239Ch = 0x641000 B0 D7 F0 O3839Ch = 0x641000 B0 D7 F1 O3939Ch = 0x641000 B0 D7 F2 O3A39Ch = 0x641000 B0 D7 F3 O3B39Ch = 0x641000 B0 D6 F1 O313F0h = 0x3C002000 B0 D7 F0 O383F0h = 0x3C002000 B0 D6 F1 O313FCh = 0x2 B0 D7 F0 O383FCh = 0x2 B0 D6 F1 O313CCh = 0x1000480 B0 D6 F2 O323CCh = 0x1000480 B0 D7 F0 O383CCh = 0x1000480 B0 D7 F1 O393CCh = 0x1000480 B0 D7 F2 O3A3CCh = 0x1000480 B0 D7 F3 O3B3CCh = 0x1000480 B0 D6 F1 O31438h = 0x2057F B0 D7 F0 O38438h = 0x2057F B0 D6 F1 O31B24h = 0x10011 B0 D7 F0 O38B24h = 0x10011 Program RX Recipe values End. Gen3: Gen3PrelinkOverride(SKT=0, PORT=1a(1), Phase2=0, Phase3=11) Gen3: Gen3PrelinkOverride(SKT=0, PORT=1b(2), Phase2=0, Phase3=11) Gen3: Gen3PrelinkOverride(SKT=0, PORT=3a(7), Phase2=0, Phase3=11) Gen3: Gen3PrelinkOverride(SKT=0, PORT=3b(8), Phase2=0, Phase3=11) Gen3: Gen3PrelinkOverride(SKT=0, PORT=3c(9), Phase2=0, Phase3=11) Gen3: Gen3PrelinkOverride(SKT=0, PORT=3d(10), Phase2=0, Phase3=11) PcieLinkTrainingInit at device scanning... IIO=0, IOU2=1. IIO=0, IOU0=3. IIO=0, IOU1=4. DumpIioPcieLinkStatus()..... Skt[0], D[1]:F[0] Link Down! Skt[0], D[1]:F[1] Link Down! Skt[0], D[2]:F[0] Link up as x01 Gen1! Skt[0], D[2]:F[1] Link up as x01 Gen1! Skt[0], D[2]:F[2] Link up as x01 Gen1! Skt[0], D[2]:F[3] Link up as x01 Gen1! Skt[0], D[3]:F[0] Link up as x08 Gen2! Skt[0], D[3]:F[1] Link Down! Skt[0], D[3]:F[2] Link Down! Skt[0], D[3]:F[3] Link Down! Gen3: Gen3Override(SKT=0, PORT=1a(1), Phase2=0, Phase3=11) Socket:[0] Port:[1] GEN3 retrain reset skipped... Gen3: Gen3Override(SKT=0, PORT=1b(2), Phase2=0, Phase3=11) Gen3: Gen3Override(SKT=0, PORT=3a(7), Phase2=0, Phase3=11) Socket:[0] Port:[7] GEN3 retrain reset skipped... Gen3: Gen3Override(SKT=0, PORT=3b(8), Phase2=0, Phase3=11) Gen3: Gen3Override(SKT=0, PORT=3c(9), Phase2=0, Phase3=11) Gen3: Gen3Override(SKT=0, PORT=3d(10), Phase2=0, Phase3=11) Program WA 4986406 Skt[0], D[1]:F[0] : Link Down , WA not required! Skt[0], D[3]:F[0] : Link up in Gen1/Gen2 , Process Lanes for WA LBC Read value on lane:0 is 0x3DDF DumpIioPcieLinkStatus()..... Skt[0], D[1]:F[0] Link Down! Skt[0], D[1]:F[1] Link Down! Skt[0], D[2]:F[0] Link up as x01 Gen1! Skt[0], D[2]:F[1] Link up as x01 Gen1! Skt[0], D[2]:F[2] Link up as x01 Gen1! Skt[0], D[2]:F[3] Link up as x01 Gen1! Skt[0], D[3]:F[0] Link up as x08 Gen2! Skt[0], D[3]:F[1] Link Down! Skt[0], D[3]:F[2] Link Down! Skt[0], D[3]:F[3] Link Down! DMI IIOInitPhase1... Initialize IIO:0 PCIE port:1 Func:0... PciEarlyInit at device scanning... Initialize IIO:0 PCIE port:2 Func:0... PciEarlyInit at device scanning... Initialize IIO:0 PCIE port:2 Func:2... PciEarlyInit at device scanning... Initialize IIO:0 PCIE port:3 Func:0... PciEarlyInit at device scanning... DMI IIOInitPhase2... Enabling PCIE Dev:1 Func:0 Slot Power... (auto mode) No speed change required! IIO 0 Port 1 ASPM configured as 7 Vendor specific pcie Link Init port:2 Func0... Vendor specific pcie Link Init port:2 Func2... Enabling PCIE Dev:3 Func:0 Slot Power... (auto mode) No speed change required! IIO 0 Port 7 ASPM configured as 7 DMI IIOInitPhase3... DMI Link Retrain() DMI speed is 5Gb/s (Gen2) PciPostInit port:1 Func0... PciPostInit port:2 Func0... PciPostInit port:2 Func2... PciPostInit port:3 Func0... Initialize IIO[0] IOxAPIC... IIO[0] IOxAPIC Base=FEC01000 IIO[0] TOMMIOL_OB = FEF00000 VT-d Chipset Initialization for IIO0 ... Vt-D base address : 0x7F130935FBFFC000 VtDGenCtrlReg : 0x000080A8 VtDIsoCtrlReg : 0x00000001 Non-Iso Engine CapReg : 0x08D2078C106F0466 Non-Iso Engine ExtCapReg : 0x0000000000F020DF IIOMISCCTRL for IIO 0 = 0x42030170 Initializing NTB for SKT0 setup PPD 0 Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Calling IioClockDisables: Socket=0 IioClockDisables: Socket=0, Port=0 IioClockDisables: Data Link Active or skipped for D0 : F0 IioClockDisables: DisableBitMap=CEE0000 IioClockDisables: Socket=0, Port=1 IioClockDisables: Socket=0, Port=2 IioClockDisables: Socket=0, Port=3 IioClockDisables: Data Link Active or skipped for D2 : F0 IioClockDisables: DisableBitMap=8AA0000 IioClockDisables: Socket=0, Port=4 IioClockDisables: Data Link Active or skipped for D2 : F1 IioClockDisables: DisableBitMap=8AA0000 IioClockDisables: Socket=0, Port=5 IioClockDisables: Data Link Active or skipped for D2 : F2 IioClockDisables: DisableBitMap=8AA0000 IioClockDisables: Socket=0, Port=6 IioClockDisables: Data Link Active or skipped for D2 : F3 IioClockDisables: DisableBitMap=8AA0000 IioClockDisables: Socket=0, Port=7 IioClockDisables: Data Link Active or skipped for D3 : F0 IioClockDisables: DisableBitMap=220000 IioClockDisables: Socket=0, Port=8 IioClockDisables: Socket=0, Port=9 IioClockDisables: Socket=0, Port=10 IIO Port/Clocks Powering down: Socket=0, Disable Bit Map=80220000 IioInit Secure the Platform (TXT).. IioInit PCIe device hide.. Bus=255, Device=1, Function=1 is hidden. Bus=255, Device=2, Function=1 is hidden. Bus=255, Device=2, Function=3 is hidden. Bus=255, Device=3, Function=1 is hidden. Bus=255, Device=3, Function=2 is hidden. Bus=255, Device=3, Function=3 is hidden. Skt[0], D[1]:F[0] Link Down! Skt[0], D[2]:F[0] Link up as x01 Gen1! Skt[0], D[2]:F[2] Link up as x01 Gen1! Skt[0], D[3]:F[0] Link up as x08 Gen2! Register PPI Notify: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793 Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Loading PEIM at 0x0007F73C000 EntryPoint=0x0007F73C260 MpInit.efi Install PPI: DD29124D-7819-4F15-BB07-351E7451D71C Loading PEIM at 0x0007F72F000 EntryPoint=0x0007F72F260 HeciInitDxe.efi [HECI-0] VID-DID: 8086-8C3A Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Loading PEIM at 0x0007F71C000 EntryPoint=0x0007F71C260 PlatformLateInit.efi TempMmioBase = 90000000 TempMmioLimit = FBFFFFFF TempIoBase = 1000 TempIoLimit = FFFF XHCI (14h) = 90000000...90003000 (00003000) EHCI (1Dh) = 90003000...90003400 (00000400) EHCI2 (1Ah) = 90003400...90003800 (00000400) SATA (1Fh.2) [AHCI] = 90003800...90004800 (00001000) PCI Root Port[0] Status from UPD = 1 PCI Root Port[1] Status from UPD = 1 PCI Root Port[2] Status from UPD = 1 PCI Root Port[3] Status from UPD = 1 PCI Root Port[4] Status from UPD = 1 PCI Root Port[5] Status from UPD = 1 PCI Root Port[6] Status from UPD = 1 PCI Root Port[7] Status from UPD = 1 Cpu Type= 0x56, Cpu Stepping= 0x3 Install PPI: 4B0165A9-61D6-4E23-A0B5-3EC79C2E30D5 Number of Active Cores / Threads = 6 / C :::: CapId5 = 6000965, PlatformInfo->CpuData.SkuSlices = 965 :::: CapId4 = 24080D03, PlatformInfo->CpuData.CpuPCPSInfo = 3000C Socket Present BitMap, mmCfgBase, dimmTypePresent, BoardId, CpuType 1, 80000000, 7F130E8E, 0 56 EFI_PPM_STRUCT size: 166 :: !!! PPM Revision: Major:00Minor:01Rev:0000!!!. :: Reading MSR_TURBO_POWER_LIMIT (610) =4381C2 0 :: Reading Socket = 0, CSR_TURBO_POWER_LIMIT=0 0 :: Wrote Socket = 0, CSR_PCIE_ILTR_OVRD=0 Program FAST_RAPL_NSTRIKE_PL2_DUTY_CYCLE as 100 (39) Detected Boot Mode 0 Detected 12 CPU threads Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Register PPI Notify: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793 Loading PEIM at 0x0007F6E6000 EntryPoint=0x0007F6E6260 PchInitDxe.efi PchInitEntryPoint() Start PCH Device: ------------- RCBA 0xFED1C000 PmBase 0x400 GpioBase 0x500 ------------- ------------------------ PCH Dump platform protocol Start ----------------- PCH PLATFORM POLICY Revision= 1 PCH PLATFORM POLICY BusNumber= 0 ------------------------ PCH_DEVICE_ENABLE ----------------- PCH_DEVICE_ENABLE Lan= 1 PCH_DEVICE_ENABLE Azalia= 2 PCH_DEVICE_ENABLE Sata= 1 PCH_DEVICE_ENABLE Smbus= 1 PCH_DEVICE_ENABLE PciClockRun= 1 PCH_DEVICE_ENABLE Display= 1 PCH_DEVICE_ENABLE Crid0 ------------------------ PCH_USB_CONFIG ----------------- PCH_USB_CONFIG UsbPerPortCtl= 0 PCH_USB_CONFIG Ehci1Usbr= 0 PCH_USB_CONFIG Ehci2Usbr= 0 PCH_USB_CONFIG PortSettings[0] Enabled= 1 PCH_USB_CONFIG PortSettings[0] Location= 1 PCH_USB_CONFIG PortSettings[1] Enabled= 1 PCH_USB_CONFIG PortSettings[1] Location= 1 PCH_USB_CONFIG PortSettings[2] Enabled= 1 PCH_USB_CONFIG PortSettings[2] Location= 1 PCH_USB_CONFIG PortSettings[3] Enabled= 1 PCH_USB_CONFIG PortSettings[3] Location= 1 PCH_USB_CONFIG PortSettings[4] Enabled= 1 PCH_USB_CONFIG PortSettings[4] Location= 1 PCH_USB_CONFIG PortSettings[5] Enabled= 1 PCH_USB_CONFIG PortSettings[5] Location= 1 PCH_USB_CONFIG PortSettings[6] Enabled= 1 PCH_USB_CONFIG PortSettings[6] Location= 1 PCH_USB_CONFIG PortSettings[7] Enabled= 1 PCH_USB_CONFIG PortSettings[7] Location= 1 PCH_USB_CONFIG PortSettings[8] Enabled= 1 PCH_USB_CONFIG PortSettings[8] Location= 1 PCH_USB_CONFIG PortSettings[9] Enabled= 1 PCH_USB_CONFIG PortSettings[9] Location= 1 PCH_USB_CONFIG PortSettings[10] Enabled= 1 PCH_USB_CONFIG PortSettings[10] Location= 1 PCH_USB_CONFIG PortSettings[11] Enabled= 1 PCH_USB_CONFIG PortSettings[11] Location= 1 PCH_USB_CONFIG PortSettings[12] Enabled= 1 PCH_USB_CONFIG PortSettings[12] Location= 1 PCH_USB_CONFIG PortSettings[13] Enabled= 1 PCH_USB_CONFIG PortSettings[13] Location= 1 PCH_USB_CONFIG Usb20Settings[0] Enabled= 1 PCH_USB_CONFIG Usb20Settings[1] Enabled= 0 PCH_USB_CONFIG Usb30Settings.Mode= 2 PCH_USB_CONFIG Usb30Settings.PreBootSupport= 0 XhciStreams is obsoleted, it doesn't effect any setting change since Revision 2. PCH_USB_CONFIG Usb30Settings.ManualMode= 0 PCH_USB_CONFIG Usb30Settings.XhciIdleL1= 1 PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[0]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[1]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[2]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[3]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[4]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[5]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[6]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[7]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[8]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[9]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[10]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[11]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[12]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb20PerPinRoute[13]= EHCI PCH_USB_CONFIG Usb30Settings.ManualModeUsb30PerPinEnable[0]= 0 PCH_USB_CONFIG Usb30Settings.ManualModeUsb30PerPinEnable[1]= 0 PCH_USB_CONFIG Usb30Settings.ManualModeUsb30PerPinEnable[2]= 0 PCH_USB_CONFIG Usb30Settings.ManualModeUsb30PerPinEnable[3]= 0 PCH_USB_CONFIG Usb30Settings.ManualModeUsb30PerPinEnable[4]= 0 PCH_USB_CONFIG Usb30Settings.ManualModeUsb30PerPinEnable[5]= 0 PCH_USB_CONFIG Usb20OverCurrentPins[0]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[1]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[2]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[3]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[4]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[5]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[6]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[7]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[8]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[9]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[10]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[11]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[12]= OC8 PCH_USB_CONFIG Usb20OverCurrentPins[13]= OC8 PCH_USB_CONFIG Usb30OverCurrentPins[0]= OC8 PCH_USB_CONFIG Usb30OverCurrentPins[1]= OC8 PCH_USB_CONFIG Usb30OverCurrentPins[2]= OC8 PCH_USB_CONFIG Usb30OverCurrentPins[3]= OC8 PCH_USB_CONFIG Usb30OverCurrentPins[4]= OC8 PCH_USB_CONFIG Usb30OverCurrentPins[5]= OC8 PCH_USB_CONFIG Usb20PortLength[0]= 23.8 PCH_USB_CONFIG Usb20PortLength[1]= 15.9 PCH_USB_CONFIG Usb20PortLength[2]= 23.8 PCH_USB_CONFIG Usb20PortLength[3]= 23.8 PCH_USB_CONFIG Usb20PortLength[4]= 23.8 PCH_USB_CONFIG Usb20PortLength[5]= 23.8 PCH_USB_CONFIG Usb20PortLength[6]= 23.8 PCH_USB_CONFIG Usb20PortLength[7]= 23.8 PCH_USB_CONFIG Usb20PortLength[8]= 23.8 PCH_USB_CONFIG Usb20PortLength[9]= 23.8 PCH_USB_CONFIG Usb20PortLength[10]= 23.8 PCH_USB_CONFIG Usb20PortLength[11]= 23.8 PCH_USB_CONFIG Usb20PortLength[12]= 23.8 PCH_USB_CONFIG Usb20PortLength[13]= 10.1 ------------------------ PCH_PCI_EXPRESS_CONFIG ----------------- PCH_PCI_EXPRESS_CONFIG TempRootPortBusNumMin= 2 PCH_PCI_EXPRESS_CONFIG TempRootPortBusNumMax= 2 PCH_PCI_EXPRESS_CONFIG RootPort[0] Enabled= 1 PCH_PCI_EXPRESS_CONFIG RootPort[0] Hide= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] SlotImplemented= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] HotPlug= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] PmSci= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] ExtSync= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] UnsupportedRequestReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] FatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] NoFatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] CorrectableErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] PmeInterrupt= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] SystemErrorOnFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] SystemErrorOnNonFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] SystemErrorOnCorrectableError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] AdvancedErrorReporting= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] TransmitterHalfSwing= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] FunctionNumber= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] PhysicalSlotNumber= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] CompletionTimeout= 0 PCH_PCI_EXPRESS_CONFIG RootPort[0] Aspm= 4 PCH_PCI_EXPRESS_CONFIG RootPort[1] Enabled= 1 PCH_PCI_EXPRESS_CONFIG RootPort[1] Hide= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] SlotImplemented= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] HotPlug= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] PmSci= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] ExtSync= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] UnsupportedRequestReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] FatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] NoFatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] CorrectableErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] PmeInterrupt= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] SystemErrorOnFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] SystemErrorOnNonFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] SystemErrorOnCorrectableError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] AdvancedErrorReporting= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] TransmitterHalfSwing= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] FunctionNumber= 1 PCH_PCI_EXPRESS_CONFIG RootPort[1] PhysicalSlotNumber= 1 PCH_PCI_EXPRESS_CONFIG RootPort[1] CompletionTimeout= 0 PCH_PCI_EXPRESS_CONFIG RootPort[1] Aspm= 4 PCH_PCI_EXPRESS_CONFIG RootPort[2] Enabled= 1 PCH_PCI_EXPRESS_CONFIG RootPort[2] Hide= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] SlotImplemented= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] HotPlug= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] PmSci= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] ExtSync= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] UnsupportedRequestReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] FatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] NoFatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] CorrectableErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] PmeInterrupt= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] SystemErrorOnFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] SystemErrorOnNonFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] SystemErrorOnCorrectableError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] AdvancedErrorReporting= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] TransmitterHalfSwing= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] FunctionNumber= 2 PCH_PCI_EXPRESS_CONFIG RootPort[2] PhysicalSlotNumber= 2 PCH_PCI_EXPRESS_CONFIG RootPort[2] CompletionTimeout= 0 PCH_PCI_EXPRESS_CONFIG RootPort[2] Aspm= 4 PCH_PCI_EXPRESS_CONFIG RootPort[3] Enabled= 1 PCH_PCI_EXPRESS_CONFIG RootPort[3] Hide= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] SlotImplemented= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] HotPlug= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] PmSci= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] ExtSync= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] UnsupportedRequestReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] FatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] NoFatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] CorrectableErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] PmeInterrupt= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] SystemErrorOnFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] SystemErrorOnNonFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] SystemErrorOnCorrectableError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] AdvancedErrorReporting= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] TransmitterHalfSwing= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] FunctionNumber= 3 PCH_PCI_EXPRESS_CONFIG RootPort[3] PhysicalSlotNumber= 3 PCH_PCI_EXPRESS_CONFIG RootPort[3] CompletionTimeout= 0 PCH_PCI_EXPRESS_CONFIG RootPort[3] Aspm= 4 PCH_PCI_EXPRESS_CONFIG RootPort[4] Enabled= 1 PCH_PCI_EXPRESS_CONFIG RootPort[4] Hide= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] SlotImplemented= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] HotPlug= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] PmSci= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] ExtSync= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] UnsupportedRequestReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] FatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] NoFatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] CorrectableErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] PmeInterrupt= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] SystemErrorOnFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] SystemErrorOnNonFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] SystemErrorOnCorrectableError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] AdvancedErrorReporting= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] TransmitterHalfSwing= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] FunctionNumber= 4 PCH_PCI_EXPRESS_CONFIG RootPort[4] PhysicalSlotNumber= 4 PCH_PCI_EXPRESS_CONFIG RootPort[4] CompletionTimeout= 0 PCH_PCI_EXPRESS_CONFIG RootPort[4] Aspm= 4 PCH_PCI_EXPRESS_CONFIG RootPort[5] Enabled= 1 PCH_PCI_EXPRESS_CONFIG RootPort[5] Hide= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] SlotImplemented= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] HotPlug= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] PmSci= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] ExtSync= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] UnsupportedRequestReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] FatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] NoFatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] CorrectableErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] PmeInterrupt= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] SystemErrorOnFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] SystemErrorOnNonFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] SystemErrorOnCorrectableError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] AdvancedErrorReporting= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] TransmitterHalfSwing= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] FunctionNumber= 5 PCH_PCI_EXPRESS_CONFIG RootPort[5] PhysicalSlotNumber= 5 PCH_PCI_EXPRESS_CONFIG RootPort[5] CompletionTimeout= 0 PCH_PCI_EXPRESS_CONFIG RootPort[5] Aspm= 4 PCH_PCI_EXPRESS_CONFIG RootPort[6] Enabled= 1 PCH_PCI_EXPRESS_CONFIG RootPort[6] Hide= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] SlotImplemented= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] HotPlug= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] PmSci= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] ExtSync= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] UnsupportedRequestReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] FatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] NoFatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] CorrectableErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] PmeInterrupt= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] SystemErrorOnFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] SystemErrorOnNonFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] SystemErrorOnCorrectableError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] AdvancedErrorReporting= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] TransmitterHalfSwing= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] FunctionNumber= 6 PCH_PCI_EXPRESS_CONFIG RootPort[6] PhysicalSlotNumber= 6 PCH_PCI_EXPRESS_CONFIG RootPort[6] CompletionTimeout= 0 PCH_PCI_EXPRESS_CONFIG RootPort[6] Aspm= 4 PCH_PCI_EXPRESS_CONFIG RootPort[7] Enabled= 1 PCH_PCI_EXPRESS_CONFIG RootPort[7] Hide= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] SlotImplemented= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] HotPlug= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] PmSci= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] ExtSync= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] UnsupportedRequestReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] FatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] NoFatalErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] CorrectableErrorReport= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] PmeInterrupt= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] SystemErrorOnFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] SystemErrorOnNonFatalError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] SystemErrorOnCorrectableError= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] AdvancedErrorReporting= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] TransmitterHalfSwing= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] FunctionNumber= 7 PCH_PCI_EXPRESS_CONFIG RootPort[7] PhysicalSlotNumber= 7 PCH_PCI_EXPRESS_CONFIG RootPort[7] CompletionTimeout= 0 PCH_PCI_EXPRESS_CONFIG RootPort[7] Aspm= 4 PCH_PCI_EXPRESS_CONFIG NumOfDevAspmOverride= 26 PCH_PCI_EXPRESS_CONFIG DevAspmOverride VendorId= 8086 PCH_PCI_EXPRESS_CONFIG DevAspmOverride DeviceId= 422B PCH_PCI_EXPRESS_CONFIG DevAspmOverride RevId= FF PCH_PCI_EXPRESS_CONFIG DevAspmOverride BaseClassCode= FF PCH_PCI_EXPRESS_CONFIG DevAspmOverride SubClassCode= FF PCH_PCI_EXPRESS_CONFIG DevAspmOverride EndPointAspm= 2 PCH_PCI_EXPRESS_CONFIG PchPcieSbdePort= 0 PCH_PCI_EXPRESS_CONFIG RootPortClockGating= 1 PCH_PCI_EXPRESS_CONFIG EnableSubDecode= 0 ------------------------ PCH_SATA_CONFIG ----------------- PCH_SATA_CONFIG PortSettings[0] Enabled= 1 PCH_SATA_CONFIG PortSettings[0] HotPlug= 1 PCH_SATA_CONFIG PortSettings[0] InterlockSw= 0 PCH_SATA_CONFIG PortSettings[0] External= 0 PCH_SATA_CONFIG PortSettings[0] SpinUp= 0 PCH_SATA_CONFIG PortSettings[0] SolidStateDrive= 0 PCH_SATA_CONFIG PortSettings[0] EnableDitoConfig= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DmVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DitoVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[1] Enabled= 1 PCH_SATA_CONFIG PortSettings[1] HotPlug= 1 PCH_SATA_CONFIG PortSettings[1] InterlockSw= 0 PCH_SATA_CONFIG PortSettings[1] External= 0 PCH_SATA_CONFIG PortSettings[1] SpinUp= 0 PCH_SATA_CONFIG PortSettings[1] SolidStateDrive= 0 PCH_SATA_CONFIG PortSettings[0] EnableDitoConfig= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DmVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DitoVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[2] Enabled= 1 PCH_SATA_CONFIG PortSettings[2] HotPlug= 1 PCH_SATA_CONFIG PortSettings[2] InterlockSw= 0 PCH_SATA_CONFIG PortSettings[2] External= 0 PCH_SATA_CONFIG PortSettings[2] SpinUp= 0 PCH_SATA_CONFIG PortSettings[2] SolidStateDrive= 0 PCH_SATA_CONFIG PortSettings[0] EnableDitoConfig= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DmVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DitoVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[3] Enabled= 1 PCH_SATA_CONFIG PortSettings[3] HotPlug= 1 PCH_SATA_CONFIG PortSettings[3] InterlockSw= 0 PCH_SATA_CONFIG PortSettings[3] External= 0 PCH_SATA_CONFIG PortSettings[3] SpinUp= 0 PCH_SATA_CONFIG PortSettings[3] SolidStateDrive= 0 PCH_SATA_CONFIG PortSettings[0] EnableDitoConfig= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DmVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DitoVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[4] Enabled= 1 PCH_SATA_CONFIG PortSettings[4] HotPlug= 1 PCH_SATA_CONFIG PortSettings[4] InterlockSw= 0 PCH_SATA_CONFIG PortSettings[4] External= 0 PCH_SATA_CONFIG PortSettings[4] SpinUp= 0 PCH_SATA_CONFIG PortSettings[4] SolidStateDrive= 0 PCH_SATA_CONFIG PortSettings[0] EnableDitoConfig= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DmVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DitoVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[5] Enabled= 1 PCH_SATA_CONFIG PortSettings[5] HotPlug= 1 PCH_SATA_CONFIG PortSettings[5] InterlockSw= 0 PCH_SATA_CONFIG PortSettings[5] External= 0 PCH_SATA_CONFIG PortSettings[5] SpinUp= 0 PCH_SATA_CONFIG PortSettings[5] SolidStateDrive= 0 PCH_SATA_CONFIG PortSettings[0] EnableDitoConfig= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DmVal= 7F0FDEA0 PCH_SATA_CONFIG PortSettings[0] DitoVal= 7F0FDEA0 PCH_SATA_CONFIG RaidAlternateId= 0 PCH_SATA_CONFIG Raid0= 1 PCH_SATA_CONFIG Raid1= 1 PCH_SATA_CONFIG Raid10= 1 PCH_SATA_CONFIG Raid5= 1 PCH_SATA_CONFIG Irrt= 1 PCH_SATA_CONFIG OromUiBanner= 1 PCH_SATA_CONFIG HddUnlock= 1 PCH_SATA_CONFIG LedLocate= 1 PCH_SATA_CONFIG IrrtOnly= 1 PCH_SATA_CONFIG TestMode= 0 PCH_SATA_CONFIG SalpSupport= 1 PCH_SATA_CONFIG LegacyMode= 0 PCH_SATA_CONFIG SmartStorage= 1 PCH_SATA_CONFIG OromUiDelay= 0 PCH_SATA_CONFIG SpeedSupport= 3 ------------------------ PCH_AZALIA_CONFIG ----------------- PCH_AZALIA_CONFIG Pme= 0 PCH_AZALIA_CONFIG DS= 0 PCH_AZALIA_CONFIG DA= 0 PCH_AZALIA_CONFIG AzaliaVerbTableNum= B PCH_AZALIA_CONFIG AzaliaVerbTable Header VendorDeviceId= 10EC0272 PCH_AZALIA_CONFIG AzaliaVerbTable Header SubSystemId= 0 PCH_AZALIA_CONFIG AzaliaVerbTable Header RevisionId= 0 PCH_AZALIA_CONFIG AzaliaVerbTable Header FrontPanelSupport= 1 PCH_AZALIA_CONFIG AzaliaVerbTable Header NumberOfRearJacks= E PCH_AZALIA_CONFIG AzaliaVerbTable Header NumberOfFrontJacks= 2 PCH_AZALIA_CONFIG AzaliaVerbTable VerbTableData= 7F7208B8 PCH_AZALIA_CONFIG ResetWaitTimer= 12C ------------------------ PCH_SMBUS_CONFIG ----------------- PCH_SMBUS_CONFIG NumRsvdSmbusAddresses= 4 PCH_SMBUS_CONFIG RsvdSmbusAddressTable= 7F7208A8 ------------------------ PCH_MISC_PM_CONFIG ----------------- PCH_MISC_PM_CONFIG PowerResetStatusClear MeWakeSts= 1 PCH_MISC_PM_CONFIG PowerResetStatusClear MeHrstColdSts= 1 PCH_MISC_PM_CONFIG PowerResetStatusClear MeHrstWarmSts= 1 PCH_MISC_PM_CONFIG PowerResetStatusClear MeHostPowerDn= 0 PCH_MISC_PM_CONFIG PowerResetStatusClear WolOvrWkSts= 0 PCH_MISC_PM_CONFIG WakeConfig PmeB0S5Dis= 0 PCH_MISC_PM_CONFIG WakeConfig WolEnableOverride= 0 PCH_MISC_PM_CONFIG WakeConfig Gp27WakeFromDeepSx= 0 PCH_MISC_PM_CONFIG PchDeepSxPol= 0 PCH_MISC_PM_CONFIG PchSlpS3MinAssert= 2 PCH_MISC_PM_CONFIG PchSlpS4MinAssert= 4 PCH_MISC_PM_CONFIG PchSlpSusMinAssert= 3 PCH_MISC_PM_CONFIG PchSlpAMinAssert= 3 PCH_MISC_PM_CONFIG SlpStrchSusUp= 0 PCH_MISC_PM_CONFIG SlpLanLowDc= 1 PCH_MISC_PM_CONFIG PchPwrCycDur= 4 ------------------------ PCH_IO_APIC_CONFIG ----------------- PCH_IO_APIC_CONFIG BdfValid= 1 PCH_IO_APIC_CONFIG BusNumber= F0 PCH_IO_APIC_CONFIG DeviceNumber= 1F PCH_IO_APIC_CONFIG FunctionNumber= 7 ------------------------ PCH_DEFAULT_SVID_SID ----------------- PCH_DEFAULT_SVID_SID SubSystemVendorId= 8086 PCH_DEFAULT_SVID_SID SubSystemId= 7270 ------------------------ PCH_LOCK_DOWN_CONFIG ----------------- PCH_LOCK_DOWN_CONFIG GlobalSmi= 1 PCH_LOCK_DOWN_CONFIG BiosInterface= 1 PCH_LOCK_DOWN_CONFIG GpioLockDown= 0 PCH_LOCK_DOWN_CONFIG RtcLock= 1 PCH_LOCK_DOWN_CONFIG BiosLock= 0 PCH_LOCK_DOWN_CONFIG PchBiosLockIoTrapAddress= 0 PCH_LOCK_DOWN_CONFIG GbeFlashLockDown= 0 ------------------------ PCH_THERMAL_CONFIG ----------------- PCH_THERMAL_CONFIG ThermalAlertEnable TselLock 1 PCH_THERMAL_CONFIG ThermalAlertEnable TscLock 1 PCH_THERMAL_CONFIG ThermalAlertEnable TsmicLock= 1 PCH_THERMAL_CONFIG ThermalAlertEnable PhlcLock= 1 PCH_THERMAL_CONFIG ThermalDeviceEnable (D31:F6) 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING THERMAL_THROTTLE_LEVELS T0Level 6B centigrade degree PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING THERMAL_THROTTLE_LEVELS T1Level 6E centigrade degree PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING THERMAL_THROTTLE_LEVELS T2Level 71 centigrade degree PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING THERMAL_THROTTLE_LEVELS TTEnable 1 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING THERMAL_THROTTLE_LEVELS TTState13Enable 1 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING THERMAL_THROTTLE_LEVELS TTLock 1 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING THERMAL_THROTTLE_LEVELS SuggestedSetting 1 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING DMI_HW_WIDTH_CONTROL DmiTsawEn 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING DMI_HW_WIDTH_CONTROL TS0TW 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING DMI_HW_WIDTH_CONTROL TS1TW 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING DMI_HW_WIDTH_CONTROL TS2TW 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING DMI_HW_WIDTH_CONTROL TS3TW 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING DMI_HW_WIDTH_CONTROL SuggestedSetting 1 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P0T1M 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P0T2M 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P0T3M 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P0TDisp 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P0Tinact 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P0TDispFinit 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P1T1M 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P1T2M 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P1T3M 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P1TDisp 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P1Tinact 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE P1TDispFinit 0 PCH_THERMAL_CONFIG PCH_THERMAL_THROTTLING SATA_THERMAL_THROTTLE SuggestedSetting 1 PCH_THERMAL_CONFIG PchHotLevel = 73 ------------------------ PCH_LPC_HPET_CONFIG ----------------- PCH_LPC_HPET_CONFIG HpetConfig 1 PCH_LPC_HPET_CONFIG Hpet[0] BusNumber F0 PCH_LPC_HPET_CONFIG Hpet[0] DeviceNumber F PCH_LPC_HPET_CONFIG Hpet[0] FunctionNumber 0 PCH_LPC_HPET_CONFIG Hpet[1] BusNumber F0 PCH_LPC_HPET_CONFIG Hpet[1] DeviceNumber F PCH_LPC_HPET_CONFIG Hpet[1] FunctionNumber 0 PCH_LPC_HPET_CONFIG Hpet[2] BusNumber F0 PCH_LPC_HPET_CONFIG Hpet[2] DeviceNumber F PCH_LPC_HPET_CONFIG Hpet[2] FunctionNumber 0 PCH_LPC_HPET_CONFIG Hpet[3] BusNumber F0 PCH_LPC_HPET_CONFIG Hpet[3] DeviceNumber F PCH_LPC_HPET_CONFIG Hpet[3] FunctionNumber 0 PCH_LPC_HPET_CONFIG Hpet[4] BusNumber F0 PCH_LPC_HPET_CONFIG Hpet[4] DeviceNumber F PCH_LPC_HPET_CONFIG Hpet[4] FunctionNumber 0 PCH_LPC_HPET_CONFIG Hpet[5] BusNumber F0 PCH_LPC_HPET_CONFIG Hpet[5] DeviceNumber F PCH_LPC_HPET_CONFIG Hpet[5] FunctionNumber 0 PCH_LPC_HPET_CONFIG Hpet[6] BusNumber F0 PCH_LPC_HPET_CONFIG Hpet[6] DeviceNumber F PCH_LPC_HPET_CONFIG Hpet[6] FunctionNumber 0 PCH_LPC_HPET_CONFIG Hpet[7] BusNumber F0 PCH_LPC_HPET_CONFIG Hpet[7] DeviceNumber F PCH_LPC_HPET_CONFIG Hpet[7] FunctionNumber 0 ------------------------ PCH_LPC_SIRQ_CONFIG ----------------- PCH_LPC_SIRQ_CONFIG SirqEnable= 1 PCH_LPC_SIRQ_CONFIG SirqMode= 0 PCH_LPC_SIRQ_CONFIG StartFramePulse= 0 ------------------------ PCH_DMI_CONFIG ----------------- PCH_DMI_CONFIG DmiAspm= 1 PCH_DMI_CONFIG DmiExtSync= 0 PCH_DMI_CONFIG DmiIot= 0 ------------------------ PCH_PWR_OPT_CONFIG ----------------- PCH_PWR_OPT_CONFIG PchPwrOptDmi= 1 PCH_PWR_OPT_CONFIG PchPwrOptGbe= 1 PCH_PWR_OPT_CONFIG PchPwrOptXhci= 0 PCH_PWR_OPT_CONFIG PchPwrOptEhci= 0 PCH_PWR_OPT_CONFIG PchPwrOptSata= 0 PCH_PWR_OPT_CONFIG MemCloseStateEn= 1 PCH_PWR_OPT_CONFIG InternalObffEn= 1 PCH_PWR_OPT_CONFIG ExternalObffEn= 0 PCH_PWR_OPT_CONFIG RootPort[0] LtrEnable= 1 PCH_PWR_OPT_CONFIG RootPort[0] ObffEnable= 0 PCH_PWR_OPT_CONFIG RootPort[1] LtrEnable= 1 PCH_PWR_OPT_CONFIG RootPort[1] ObffEnable= 0 PCH_PWR_OPT_CONFIG RootPort[2] LtrEnable= 1 PCH_PWR_OPT_CONFIG RootPort[2] ObffEnable= 0 PCH_PWR_OPT_CONFIG RootPort[3] LtrEnable= 1 PCH_PWR_OPT_CONFIG RootPort[3] ObffEnable= 0 PCH_PWR_OPT_CONFIG RootPort[4] LtrEnable= 1 PCH_PWR_OPT_CONFIG RootPort[4] ObffEnable= 0 PCH_PWR_OPT_CONFIG RootPort[5] LtrEnable= 1 PCH_PWR_OPT_CONFIG RootPort[5] ObffEnable= 0 PCH_PWR_OPT_CONFIG RootPort[6] LtrEnable= 1 PCH_PWR_OPT_CONFIG RootPort[6] ObffEnable= 0 PCH_PWR_OPT_CONFIG RootPort[7] LtrEnable= 1 PCH_PWR_OPT_CONFIG RootPort[7] ObffEnable= 0 PCH_PWR_OPT_CONFIG NumOfDevLtrOverride= 0 PCH_PWR_OPT_CONFIG DevLtrOverride VendorId= 0 PCH_PWR_OPT_CONFIG DevLtrOverride DeviceId= 0 PCH_PWR_OPT_CONFIG DevLtrOverride RevId= 0 PCH_PWR_OPT_CONFIG DevLtrOverride SnoopLatency= 0 PCH_PWR_OPT_CONFIG DevLtrOverride NonSnoopLatency= 0 PCH_PWR_OPT_CONFIG LegacyDmaDisable= 0 ------------------------ PCH Dump platform protocol End ----------------- InitializePchDevice() Start ChipsetInitSettingsCheck() Start ConfigureMiscPm() Start ConfigureMiscPm() End ConfigureDmi() Start ConfigureDmi() End ConfigureMiscItems() Start ConfigureMiscItems() End ConfigureLan() Start LAN can be enabled or disabled as SPI is in Descriptor Mode. ConfigureLan() End ConfigureUsb() Start CommonUsbInit() - Start CommonUsbInit() - End ConfigureUsb() End PchInitRootPorts() Start PCI Root Port[0] Status = 1 PCI Root Port[1] Status = 1 PCI Root Port[2] Status = 1 PCI Root Port[3] Status = 1 PCI Root Port[4] Status = 1 PCI Root Port[5] Status = 1 PCI Root Port[6] Status = 1 PCI Root Port[7] Status = 1 PCI Function 1 disabled as port is not hot plug enabled and no PCIe card is detected PCI Function 2 disabled as specified in the Fuse Straps PCI Function 3 disabled as port is not hot plug enabled and no PCIe card is detected PCI Function 4 disabled as port is not hot plug enabled and no PCIe card is detected PCI Function 5 disabled as port is not hot plug enabled and no PCIe card is detected PCI Function 6 disabled as specified in the Fuse Straps PCI Function 7 disabled as specified in the Fuse Straps PCI Function 8 disabled as specified in the Fuse Straps PCH PCI Root Port Clock Gating is 1 PchInitRootPorts() End ConfigureSata() Start ConfigureSata() End ConfigureDisplay() Start ConfigureDisplay() End ConfigureClockGating() Start ConfigureClockGating() End ConfigureIoApic() Start ConfigureIoApic() End ProgramSvidSid() Start ProgramSvidSid() End Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B InitializePchDevice() End PchInitEntryPoint() End Loading PEIM at 0x0007F6D9000 EntryPoint=0x0007F6D9260 SpsDxe.efi [SPS] DXE PHASE [SPS] Getting Info from PEI [SPS] Looking for SPS HOB info from PEI [SPS] HOB: flow 1, feature set 0x2106, pwr opt boot 0, cores2disable 0 [HECI-0] VID-DID: 8086-8C3A [SPS] Sending PCH temperature reporting configuration to ME [SPS] PCH Temperatur Reporting Interval: 0x00FA [SPS] PCH Temperatur Maximum Low Power Interval: 0x03E8 [HECI-0] Send msg: 80060020 [HECI-0] Got msg: 80040020 [SPS] SiliconEnabling Mode Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Register PPI Notify: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B DXE IPL Entry FSP HOB is located at 0x7F100000 Install PPI: 605EA650-C65C-42E1-BA80-91A52AB618C6 FSP is waiting for NOTIFY romstage_main_continue status: 0 hob_list_ptr: 7f100000 FSP Status: 0x0 CBMEM: IMD: root @ 7efff000 254 entries. IMD: root @ 7effec00 62 entries. CBFS @ 200200 size 5ffe00 CBFS: 'Master Header Locator' located CBFS at [200200:800000) CBFS: Locating 'fallback/ramstage' CBFS: Checking offset 0 CBFS: File @ offset 0 size 20 CBFS: Unmatched 'cbfs master header' at 0 CBFS: Checking offset 80 CBFS: File @ offset 80 size 44a4 CBFS: Unmatched 'fallback/romstage' at 80 CBFS: Checking offset 45c0 CBFS: File @ offset 45c0 size 19800 CBFS: Unmatched 'cpu_microcode_blob.bin' at 45c0 CBFS: Checking offset 1de40 CBFS: File @ offset 1de40 size f868 CBFS: Found @ offset 1de40 size f868 Decompressing stage fallback/ramstage @ 0x7eeb3fc0 (1350040 bytes) Loading module at 7eeb4000 with entry 7eeb4000. filesize: 0x1ff58 memsize: 0x149958 Processing 2601 relocs. Offset value of 0x7e0b4000 coreboot-4.10-ae317695e3f03d55fbba1805ff06e004383e67c8 Sat Dec 7 08:49:16 UTC 2019 ramstage starting (log level: 8)... TEST: Entering boot_state_schedule_static_entries TEST: Entering boot_state_sched_on_entry TEST: Entering boot_state_sched_callback TEST: Entering boot_state_sched_on_exit TEST: Entering boot_state_sched_callback TEST: Entering boot_state_sched_on_entry TEST: Entering boot_state_sched_callback TEST: Entering boot_state_sched_on_entry TEST: Entering boot_state_sched_callback TEST: Entering boot_state_sched_on_exit TEST: Entering boot_state_sched_callback TEST: Entering boot_state_sched_on_exit TEST: Entering boot_state_sched_callback TEST: Entering boot_state_sched_on_entry TEST: Entering boot_state_sched_callback TEST: Entering boot_state_sched_on_entry TEST: Entering boot_state_sched_callback TEST: Entering bs_walk_state_machine TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_pre_device TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_report_time BS: BS_PRE_DEVICE times (us): entry 6303 run 5917 exit 6302 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_dev_init_chips TEST: Entering dev_initialize_chips CBFS @ 200200 size 5ffe00 CBFS: 'Master Header Locator' located CBFS at [200200:800000) CBFS: Locating 'cpu_microcode_blob.bin' CBFS: Checking offset 0 CBFS: File @ offset 0 size 20 CBFS: Unmatched 'cbfs master header' at 0 CBFS: Checking offset 80 CBFS: File @ offset 80 size 44a4 CBFS: Unmatched 'fallback/romstage' at 80 CBFS: Checking offset 45c0 CBFS: File @ offset 45c0 size 19800 CBFS: Found @ offset 45c0 size 19800 microcode: sig=0x50663 pf=0x10 revision=0x700000c CPUID: 00050663 Cores: 12 Stepping: V2 Revision ID: 05 msr(17) = 0010000000000000 msr(ce) = 20080833f3811600 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_report_time BS: BS_DEV_INIT_CHIPS times (us): entry 6302 run 68480 exit 6302 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_dev_enumerate TEST: Entering dev_enumerate Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 APIC: 00: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:19.0: enabled 1 PCI: 00:1d.0: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.5: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:03.0: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:19.0: enabled 1 PCI: 00:1d.0: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.5: enabled 1 PCI: 00:01.0: enabled 1 PCI: 00:03.0: enabled 1 TEST: Entering scan_bus Root Device scanning... root_dev_scan_bus for Root Device enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 7) CPU_CLUSTER: 0 enabled enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 6) DOMAIN: 0000 enabled TEST: Entering scan_bus DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:00.0 [8086/6f00] ops fsp_header_ptr: ffeb0094 FSP Header Version: 1 FSP Revision: 3.3 PCI: 00:00.0 [8086/6f00] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) TEST: Entering set_pci_ops TEST: Entering device_id_match PCI: 00:01.0 [8086/0000] bus ops PCI: 00:01.0 [8086/6f02] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering get_pci_bridge_ops PCI: 00:02.0 subordinate bus PCI Express PCI: 00:02.0 [8086/6f04] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering get_pci_bridge_ops PCI: 00:02.2 subordinate bus PCI Express PCI: 00:02.2 [8086/6f06] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) TEST: Entering set_pci_ops TEST: Entering device_id_match PCI: 00:03.0 [8086/0000] bus ops PCI: 00:03.0 [8086/6f08] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:05.0 [8086/6f28] ops PCI: 00:05.0 [8086/6f28] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:05.1 [8086/6f29] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:05.2 [8086/6f2a] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:05.4 [8086/6f2c] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:05.6 [8086/6f39] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:06.0 [8086/6f10] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:06.1 [8086/6f11] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:06.2 [8086/6f12] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:06.3 [8086/6f13] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:06.4 [8086/6f14] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:06.5 [8086/6f15] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:06.6 [8086/6f16] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:06.7 [8086/6f17] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:07.0 [8086/6f18] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:07.1 [8086/6f19] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:07.2 [8086/6f1a] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:07.3 [8086/6f1b] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:07.4 [8086/6f1c] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:14.0 [8086/8c31] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:16.0 [8086/8c3a] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:16.1 [8086/8c3b] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:16.2 [8086/8c3c] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:16.3 [8086/8c3d] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) PCI: Static device PCI: 00:19.0 not found, disabling it. TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:1d.0 [8086/8c26] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:1f.0 [8086/8c54] bus ops PCI: 00:1f.0 [8086/8c54] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:1f.2 [8086/8c02] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:1f.3 [8086/0000] bus ops PCI: 00:1f.3 [8086/8c22] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev enable_dev(Intel(R) Xeon(R) Processor D-1500 Product Family, 2) PCI: Static device PCI: 00:1f.5 not found, disabling it. TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 00:1f.6 [8086/8c24] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev PCI: Leftover static devices: PCI: 00:19.0 PCI: 00:1f.5 PCI: Check your devicetree.cb. TEST: Entering scan_bus PCI: 00:01.0 scanning... TEST: Entering pci_scan_bridge TEST: Entering do_pci_scan_bridge do_pci_scan_bridge for PCI: 00:01.0 TEST: Entering pci_bridge_route PCI: pci_scan_bus for bus 01 TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_bridge_route scan_bus: scanning of bus PCI: 00:01.0 took 217406 usecs TEST: Entering scan_bus PCI: 00:02.0 scanning... TEST: Entering do_pci_scan_bridge do_pci_scan_bridge for PCI: 00:02.0 TEST: Entering pci_bridge_route PCI: pci_scan_bus for bus 02 TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 02:00.0 [8086/6f50] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 02:00.1 [8086/6f51] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 02:00.2 [8086/6f52] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 02:00.3 [8086/6f53] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev PCIE CLK PM is not supported by endpoint ASPM: Enabled None PCIE CLK PM is not supported by endpoint ASPM: Enabled None PCIE CLK PM is not supported by endpoint ASPM: Enabled None PCIE CLK PM is not supported by endpoint ASPM: Enabled None TEST: Entering pci_bridge_route Failed to enable LTR for dev = PCI: 02:00.0 Failed to enable LTR for dev = PCI: 02:00.1 Failed to enable LTR for dev = PCI: 02:00.2 Failed to enable LTR for dev = PCI: 02:00.3 scan_bus: scanning of bus PCI: 00:02.0 took 442884 usecs TEST: Entering scan_bus PCI: 00:02.2 scanning... TEST: Entering do_pci_scan_bridge do_pci_scan_bridge for PCI: 00:02.2 TEST: Entering pci_bridge_route PCI: pci_scan_bus for bus 03 TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 03:00.0 [8086/15ac] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match TEST: Entering device_id_match PCI: 03:00.1 [8086/15ac] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled L1 Enabling Common Clock Configuration PCIE CLK PM is not supported by endpoint ASPM: Enabled L1 TEST: Entering pci_bridge_route scan_bus: scanning of bus PCI: 00:02.2 took 348064 usecs TEST: Entering scan_bus PCI: 00:03.0 scanning... TEST: Entering pci_scan_bridge TEST: Entering do_pci_scan_bridge do_pci_scan_bridge for PCI: 00:03.0 TEST: Entering pci_bridge_route PCI: pci_scan_bus for bus 04 TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops PCI: 04:00.0 [10de/128b] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering alloc_dev TEST: Entering __alloc_dev TEST: Entering set_pci_ops PCI: 04:00.1 [10de/0e0f] enabled TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_scan_get_dev TEST: Entering pci_probe_dev TEST: Entering pci_bridge_route scan_bus: scanning of bus PCI: 00:03.0 took 282674 usecs TEST: Entering scan_bus PCI: 00:1f.0 scanning... scan_lpc_bus for PCI: 00:1f.0 scan_lpc_bus for PCI: 00:1f.0 done scan_bus: scanning of bus PCI: 00:1f.0 took 9021 usecs TEST: Entering scan_bus PCI: 00:1f.3 scanning... scan_generic_bus for PCI: 00:1f.3 scan_generic_bus for PCI: 00:1f.3 done scan_bus: scanning of bus PCI: 00:1f.3 took 9796 usecs scan_bus: scanning of bus DOMAIN: 0000 took 3043319 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 3078225 usecs done TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks FspNotify(EnumInitPhaseAfterPciEnumeration) FSP Got Notification. Notification Value : 0x00000020 FSP Post PCI Enumeration ... Install PPI: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793 Notify: PPI Guid: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793, Peim notify entry point: 7F759A3C IIO PCI callback event after PCI bus assignment.. Found the CBDMA on bus:2 Found the GbE on bus:3 Hide devices in Bus:255 IIO PCI callback event after PCI resource allocation.. BDF=2,0,0 - CB_BAR=0x0 CB BAR not initialized! CBDMA[0].version=0x33 Enable IIO[0] IOxAPIC Notify: PPI Guid: 30CFE3E7-3DE1-4586-BE20-DEABA1B3B793, Peim notify entry point: 7F71C2AA FSP Notification Handler Returns : 0x00000000 Returned from FspNotify(EnumInitPhaseAfterPciEnumeration) TEST: Entering bs_sample_time TEST: Entering bs_report_time BS: BS_DEV_ENUMERATE times (us): entry 6301 run 3174258 exit 78801 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_dev_resources TEST: Entering dev_configure TEST: Entering set_vga_bridge_bits found VGA at PCI: 04:00.0 Setting up VGA for PCI: 04:00.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:03.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... TEST: Entering read_resources Root Device read_resources bus 0 link: 0 TEST: Entering read_resources CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done TEST: Entering pci_domain_read_resources TEST: Entering read_resources DOMAIN: 0000 read_resources bus 0 link: 0 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 fsp_mem_base: 0x7f000000 fsp_mem_len: 0x00800000 tseg_base: 0x7f800000 tseg_len: 0x00800000 highmem_size: 0x00000000 80000000 tolm: 0x80000000 Top of system low memory: 0x80000000 FSP memory location: 0x7f000000 (size: 8M) tseg: 0x7f800000 (size: 0x00800000) Available memory above 4GB: 2048M Adding PCIe config bar base=0x80000000 size=0x10000000 TEST: Entering pci_bus_read_resources TEST: Entering pci_bridge_read_bases TEST: Entering pci_moving_config8 TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config8 TEST: Entering pci_moving_config16 TEST: Entering pci_record_bridge_resource TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config32 TEST: Entering pci_record_bridge_resource TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config16 TEST: Entering pci_record_bridge_resource TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering read_resources PCI: 00:01.0 read_resources bus 1 link: 0 PCI: 00:01.0 read_resources bus 1 link: 0 done TEST: Entering pci_bus_read_resources TEST: Entering pci_bridge_read_bases TEST: Entering pci_moving_config8 TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config8 TEST: Entering pci_moving_config16 TEST: Entering pci_record_bridge_resource TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config32 TEST: Entering pci_record_bridge_resource TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config16 TEST: Entering pci_record_bridge_resource TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering read_resources PCI: 00:02.0 read_resources bus 2 link: 0 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:02.0 read_resources bus 2 link: 0 done TEST: Entering pci_bus_read_resources TEST: Entering pci_bridge_read_bases TEST: Entering pci_moving_config8 TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config8 TEST: Entering pci_moving_config16 TEST: Entering pci_record_bridge_resource TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config32 TEST: Entering pci_record_bridge_resource TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config16 TEST: Entering pci_record_bridge_resource TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering read_resources PCI: 00:02.2 read_resources bus 3 link: 0 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:02.2 read_resources bus 3 link: 0 done TEST: Entering pci_bus_read_resources TEST: Entering pci_bridge_read_bases TEST: Entering pci_moving_config8 TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config8 TEST: Entering pci_moving_config16 TEST: Entering pci_record_bridge_resource TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config32 TEST: Entering pci_record_bridge_resource TEST: Entering pci_moving_config16 TEST: Entering pci_moving_config16 TEST: Entering pci_record_bridge_resource TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering read_resources PCI: 00:03.0 read_resources bus 4 link: 0 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:03.0 read_resources bus 4 link: 0 done TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:05.6 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:05.6 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:05.6 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:05.6 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:05.6 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:05.6 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:05.6 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.0 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.0 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.0 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.0 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.0 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.0 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:06.0 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.1 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.1 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.1 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.1 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.1 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.1 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:06.1 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.2 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.2 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.2 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.2 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.2 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.2 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:06.2 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.3 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.3 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.3 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.3 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.3 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.3 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:06.3 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.4 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.4 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.4 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.4 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.4 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.4 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:06.4 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.5 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.5 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.5 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.5 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.5 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.5 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:06.5 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.6 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.6 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.6 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.6 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.6 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.6 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:06.6 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.7 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.7 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.7 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.7 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.7 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:06.7 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:06.7 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.0 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.0 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.0 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.0 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.0 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.0 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:07.0 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.1 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.1 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.1 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.1 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.1 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.1 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:07.1 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.2 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.2 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.2 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.2 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.2 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.2 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:07.2 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.3 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.3 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.3 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.3 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.3 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.3 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:07.3 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.4 register 10(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.4 register 14(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.4 register 18(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.4 register 1c(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.4 register 20(ffffffff), read-only ignoring it TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 PCI: 00:07.4 register 24(ffffffff), read-only ignoring it TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 PCI: 00:07.4 register 30(ffffffff), read-only ignoring it TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 TEST: Entering pci_dev_read_resources TEST: Entering pci_read_bases TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_resource TEST: Entering pci_moving_config32 TEST: Entering pci_get_rom_resource TEST: Entering pci_moving_config32 DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base 100000 size 7ef00000 align 0 gran 0 limit 0 flags e0004200 index 1 PCI: 00:00.0 resource base 7f800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 2 PCI: 00:00.0 resource base 7f000000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base 100000000 size 80000000 align 0 gran 0 limit 0 flags e0004200 index 4 PCI: 00:00.0 resource base 80000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base a0000 size 60000 align 0 gran 0 limit 0 flags f0000200 index 6 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 00:02.0 child on link 0 PCI: 02:00.0 PCI: 00:02.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 PCI: 02:00.1 PCI: 02:00.1 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 PCI: 02:00.2 PCI: 02:00.2 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 PCI: 02:00.3 PCI: 02:00.3 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.2 child on link 0 PCI: 03:00.0 PCI: 00:02.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 1201 index 10 PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20 PCI: 03:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30 PCI: 03:00.1 PCI: 03:00.1 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 1201 index 10 PCI: 03:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20 PCI: 03:00.1 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30 PCI: 00:03.0 child on link 0 PCI: 04:00.0 PCI: 00:03.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:03.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 04:00.0 PCI: 04:00.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffff flags 200 index 10 PCI: 04:00.0 resource base 0 size 8000000 align 27 gran 27 limit ffffffffffffffff flags 1201 index 14 PCI: 04:00.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffffffffffff flags 1201 index 1c PCI: 04:00.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 24 PCI: 04:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 2200 index 30 PCI: 04:00.1 PCI: 04:00.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10 PCI: 00:05.0 PCI: 00:05.0 resource base fbffc000 size 2000 align 0 gran 0 limit 0 flags f0000200 index 180 PCI: 00:05.1 PCI: 00:05.2 PCI: 00:05.4 PCI: 00:05.4 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 00:05.6 PCI: 00:06.0 PCI: 00:06.1 PCI: 00:06.2 PCI: 00:06.3 PCI: 00:06.4 PCI: 00:06.5 PCI: 00:06.6 PCI: 00:06.7 PCI: 00:07.0 PCI: 00:07.1 PCI: 00:07.2 PCI: 00:07.3 PCI: 00:07.4 PCI: 00:14.0 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 PCI: 00:16.0 PCI: 00:16.0 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10 PCI: 00:16.1 PCI: 00:16.1 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10 PCI: 00:16.2 PCI: 00:16.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:16.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:16.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:16.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:16.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:16.3 PCI: 00:16.3 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:16.3 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:1d.0 PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10 PCI: 00:1f.0 PCI: 00:1f.0 resource base feb00000 size 10000 align 0 gran 0 limit 0 flags f0000200 index feb0 PCI: 00:1f.0 resource base feb80000 size 80000 align 0 gran 0 limit 0 flags f0000200 index feb8 PCI: 00:1f.0 resource base fec00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fec0 PCI: 00:1f.0 resource base fec01000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fec1 PCI: 00:1f.0 resource base fed00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fed0 PCI: 00:1f.0 resource base fef00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fef0 PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index ff00 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:1f.0 resource base 500 size 80 align 0 gran 0 limit 0 flags c0000100 index 48 PCI: 00:1f.2 PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24 PCI: 00:1f.3 PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10 PCI: 00:1f.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 PCI: 00:1f.6 PCI: 00:1f.6 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff TEST: Entering largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff TEST: Entering largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:02.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff TEST: Entering largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:03.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 04:00.0 24 * [0x0 - 0x7f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:03.0 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:03.0 1c * [0x0 - 0xfff] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 20 * [0x1000 - 0x101f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:1f.3 20 * [0x1020 - 0x103f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:16.2 20 * [0x1040 - 0x104f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:16.2 10 * [0x1050 - 0x1057] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:16.2 18 * [0x1058 - 0x105f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:16.3 10 * [0x1060 - 0x1067] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 10 * [0x1068 - 0x106f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 18 * [0x1070 - 0x1077] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:16.2 14 * [0x1078 - 0x107b] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:16.2 1c * [0x107c - 0x107f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 14 * [0x1080 - 0x1083] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 1c * [0x1084 - 0x1087] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str DOMAIN: 0000 io: base: 1088 size: 1088 align: 12 gran: 0 limit: ffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff TEST: Entering largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff TEST: Entering largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff TEST: Entering largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:02.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:02.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 02:00.0 10 * [0x0 - 0x1fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 02:00.1 10 * [0x2000 - 0x3fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 02:00.2 10 * [0x4000 - 0x5fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 02:00.3 10 * [0x6000 - 0x7fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:02.0 mem: base: 8000 size: 100000 align: 20 gran: 20 limit: ffffffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 03:00.0 10 * [0x0 - 0x1fffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 03:00.1 10 * [0x200000 - 0x3fffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 03:00.0 20 * [0x400000 - 0x403fff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 03:00.1 20 * [0x404000 - 0x407fff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:02.2 prefmem: base: 408000 size: 500000 align: 21 gran: 20 limit: ffffffffffffffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:02.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 03:00.0 30 * [0x0 - 0x7ffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 03:00.1 30 * [0x80000 - 0xfffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:02.2 mem: base: 100000 size: 100000 align: 20 gran: 20 limit: ffffffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:03.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 04:00.0 14 * [0x0 - 0x7ffffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 04:00.0 1c * [0x8000000 - 0x9ffffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:03.0 prefmem: base: a000000 size: a000000 align: 27 gran: 20 limit: ffffffffffffffff done TEST: Entering round TEST: Entering compute_resources TEST: Entering resource2str PCI: 00:03.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 04:00.0 10 * [0x0 - 0xffffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 04:00.0 30 * [0x1000000 - 0x107ffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 04:00.1 10 * [0x1080000 - 0x1083fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:03.0 mem: base: 1084000 size: 1100000 align: 24 gran: 20 limit: ffffffff done TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:03.0 24 * [0x0 - 0x9ffffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:03.0 20 * [0xa000000 - 0xb0fffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:02.2 24 * [0xb200000 - 0xb6fffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:02.0 20 * [0xb700000 - 0xb7fffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:02.2 20 * [0xb800000 - 0xb8fffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:14.0 10 * [0xb900000 - 0xb90ffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:05.4 10 * [0xb910000 - 0xb910fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:16.3 14 * [0xb911000 - 0xb911fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:1f.6 10 * [0xb912000 - 0xb912fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 24 * [0xb913000 - 0xb9137ff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:1d.0 10 * [0xb914000 - 0xb9143ff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:1f.3 10 * [0xb915000 - 0xb9150ff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:16.0 10 * [0xb916000 - 0xb91600f] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering resource2str PCI: 00:16.1 10 * [0xb917000 - 0xb91700f] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str DOMAIN: 0000 mem: base: b917010 size: b917010 align: 27 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_is avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource2str constrain_resources: PCI: 00:00.0 00 base 00000000 limit 0009ffff mem (fixed) TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource2str constrain_resources: PCI: 00:00.0 01 base 00100000 limit 7effffff mem (fixed) TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource2str constrain_resources: PCI: 00:00.0 02 base 7f800000 limit 7fffffff mem (fixed) TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource2str constrain_resources: PCI: 00:00.0 05 base 80000000 limit 8fffffff mem (fixed) TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource2str constrain_resources: PCI: 00:05.0 180 base fbffc000 limit fbffdfff mem (fixed) TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_is TEST: Entering resource2str constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_is TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering constrain_resources TEST: Entering resource_limit TEST: Entering resource_is TEST: Entering resource_is TEST: Entering resource_limit TEST: Entering resource_is Setting resources... TEST: Entering allocate_resources TEST: Entering resource2str DOMAIN: 0000 io: base:1000 size:1088 align:12 gran:0 limit:ffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:03.0 1c * [0x1000 - 0x1fff] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 20 * [0x2000 - 0x201f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:1f.3 20 * [0x2020 - 0x203f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:16.2 20 * [0x2040 - 0x204f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:16.2 10 * [0x2050 - 0x2057] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:16.2 18 * [0x2058 - 0x205f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:16.3 10 * [0x2060 - 0x2067] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 10 * [0x2068 - 0x206f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 18 * [0x2070 - 0x2077] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:16.2 14 * [0x2078 - 0x207b] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:16.2 1c * [0x207c - 0x207f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 14 * [0x2080 - 0x2083] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 1c * [0x2084 - 0x2087] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering resource2str DOMAIN: 0000 io: next_base: 2088 size: 1088 align: 12 gran: 0 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:01.0 io: base:ffff size:0 align:12 gran:12 limit:ffff TEST: Entering largest_resource TEST: Entering resource2str PCI: 00:01.0 io: next_base: ffff size: 0 align: 12 gran: 12 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:02.0 io: base:ffff size:0 align:12 gran:12 limit:ffff TEST: Entering largest_resource TEST: Entering resource2str PCI: 00:02.0 io: next_base: ffff size: 0 align: 12 gran: 12 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:02.2 io: base:ffff size:0 align:12 gran:12 limit:ffff TEST: Entering largest_resource TEST: Entering resource2str PCI: 00:02.2 io: next_base: ffff size: 0 align: 12 gran: 12 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:03.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 04:00.0 24 * [0x1000 - 0x107f] io TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering resource2str PCI: 00:03.0 io: next_base: 1080 size: 1000 align: 12 gran: 12 done TEST: Entering allocate_resources TEST: Entering resource2str DOMAIN: 0000 mem: base:f0000000 size:b917010 align:27 gran:0 limit:fbffbfff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:03.0 24 * [0xf0000000 - 0xf9ffffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:03.0 20 * [0xfa000000 - 0xfb0fffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:02.2 24 * [0xfb200000 - 0xfb6fffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:02.0 20 * [0xfb700000 - 0xfb7fffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:02.2 20 * [0xfb800000 - 0xfb8fffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:14.0 10 * [0xfb900000 - 0xfb90ffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:05.4 10 * [0xfb910000 - 0xfb910fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:16.3 14 * [0xfb911000 - 0xfb911fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:1f.6 10 * [0xfb912000 - 0xfb912fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:1f.2 24 * [0xfb913000 - 0xfb9137ff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:1d.0 10 * [0xfb914000 - 0xfb9143ff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:1f.3 10 * [0xfb915000 - 0xfb9150ff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:16.0 10 * [0xfb916000 - 0xfb91600f] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 00:16.1 10 * [0xfb917000 - 0xfb91700f] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering resource2str DOMAIN: 0000 mem: next_base: fb917010 size: b917010 align: 27 gran: 0 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:01.0 prefmem: base:fbffbfff size:0 align:20 gran:20 limit:fbffbfff TEST: Entering largest_resource TEST: Entering resource2str PCI: 00:01.0 prefmem: next_base: fbffbfff size: 0 align: 20 gran: 20 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:01.0 mem: base:fbffbfff size:0 align:20 gran:20 limit:fbffbfff TEST: Entering largest_resource TEST: Entering resource2str PCI: 00:01.0 mem: next_base: fbffbfff size: 0 align: 20 gran: 20 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:02.0 prefmem: base:fbffbfff size:0 align:20 gran:20 limit:fbffbfff TEST: Entering largest_resource TEST: Entering resource2str PCI: 00:02.0 prefmem: next_base: fbffbfff size: 0 align: 20 gran: 20 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:02.0 mem: base:fb700000 size:100000 align:20 gran:20 limit:fb7fffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 02:00.0 10 * [0xfb700000 - 0xfb701fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 02:00.1 10 * [0xfb702000 - 0xfb703fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 02:00.2 10 * [0xfb704000 - 0xfb705fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 02:00.3 10 * [0xfb706000 - 0xfb707fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering resource2str PCI: 00:02.0 mem: next_base: fb708000 size: 100000 align: 20 gran: 20 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:02.2 prefmem: base:fb200000 size:500000 align:21 gran:20 limit:fb6fffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 03:00.0 10 * [0xfb200000 - 0xfb3fffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 03:00.1 10 * [0xfb400000 - 0xfb5fffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 03:00.0 20 * [0xfb600000 - 0xfb603fff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 03:00.1 20 * [0xfb604000 - 0xfb607fff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering resource2str PCI: 00:02.2 prefmem: next_base: fb608000 size: 500000 align: 21 gran: 20 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:02.2 mem: base:fb800000 size:100000 align:20 gran:20 limit:fb8fffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 03:00.0 30 * [0xfb800000 - 0xfb87ffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 03:00.1 30 * [0xfb880000 - 0xfb8fffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering resource2str PCI: 00:02.2 mem: next_base: fb900000 size: 100000 align: 20 gran: 20 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:03.0 prefmem: base:f0000000 size:a000000 align:27 gran:20 limit:f9ffffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 04:00.0 14 * [0xf0000000 - 0xf7ffffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 04:00.0 1c * [0xf8000000 - 0xf9ffffff] prefmem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering resource2str PCI: 00:03.0 prefmem: next_base: fa000000 size: a000000 align: 27 gran: 20 done TEST: Entering allocate_resources TEST: Entering resource2str PCI: 00:03.0 mem: base:fa000000 size:1100000 align:24 gran:20 limit:fb0fffff TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 04:00.0 10 * [0xfa000000 - 0xfaffffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 04:00.0 30 * [0xfb000000 - 0xfb07ffff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering round TEST: Entering round TEST: Entering resource2str PCI: 04:00.1 10 * [0xfb080000 - 0xfb083fff] mem TEST: Entering largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering pick_largest_resource TEST: Entering resource2str PCI: 00:03.0 mem: next_base: fb084000 size: 1100000 align: 24 gran: 20 done TEST: Entering assign_resources Root Device assign_resources, bus 0 link: 0 TEST: Entering assign_resources DOMAIN: 0000 assign_resources, bus 0 link: 0 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io TEST: Entering pci_set_resource PCI: 00:01.0 24 <- [0x00fbffbfff - 0x00fbffbffe] size 0x00000000 gran 0x14 bus 01 prefmem TEST: Entering pci_set_resource PCI: 00:01.0 20 <- [0x00fbffbfff - 0x00fbffbffe] size 0x00000000 gran 0x14 bus 01 mem TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:02.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io TEST: Entering pci_set_resource PCI: 00:02.0 24 <- [0x00fbffbfff - 0x00fbffbffe] size 0x00000000 gran 0x14 bus 02 prefmem TEST: Entering pci_set_resource PCI: 00:02.0 20 <- [0x00fb700000 - 0x00fb7fffff] size 0x00100000 gran 0x14 bus 02 mem TEST: Entering assign_resources PCI: 00:02.0 assign_resources, bus 2 link: 0 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 02:00.0 10 <- [0x00fb700000 - 0x00fb701fff] size 0x00002000 gran 0x0d mem64 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 02:00.1 10 <- [0x00fb702000 - 0x00fb703fff] size 0x00002000 gran 0x0d mem64 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 02:00.2 10 <- [0x00fb704000 - 0x00fb705fff] size 0x00002000 gran 0x0d mem64 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 02:00.3 10 <- [0x00fb706000 - 0x00fb707fff] size 0x00002000 gran 0x0d mem64 PCI: 00:02.0 assign_resources, bus 2 link: 0 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:02.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io TEST: Entering pci_set_resource PCI: 00:02.2 24 <- [0x00fb200000 - 0x00fb6fffff] size 0x00500000 gran 0x14 bus 03 prefmem TEST: Entering pci_set_resource PCI: 00:02.2 20 <- [0x00fb800000 - 0x00fb8fffff] size 0x00100000 gran 0x14 bus 03 mem TEST: Entering assign_resources PCI: 00:02.2 assign_resources, bus 3 link: 0 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 03:00.0 10 <- [0x00fb200000 - 0x00fb3fffff] size 0x00200000 gran 0x15 prefmem64 TEST: Entering pci_set_resource PCI: 03:00.0 20 <- [0x00fb600000 - 0x00fb603fff] size 0x00004000 gran 0x0e prefmem64 TEST: Entering pci_set_resource PCI: 03:00.0 30 <- [0x00fb800000 - 0x00fb87ffff] size 0x00080000 gran 0x13 romem TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 03:00.1 10 <- [0x00fb400000 - 0x00fb5fffff] size 0x00200000 gran 0x15 prefmem64 TEST: Entering pci_set_resource PCI: 03:00.1 20 <- [0x00fb604000 - 0x00fb607fff] size 0x00004000 gran 0x0e prefmem64 TEST: Entering pci_set_resource PCI: 03:00.1 30 <- [0x00fb880000 - 0x00fb8fffff] size 0x00080000 gran 0x13 romem PCI: 00:02.2 assign_resources, bus 3 link: 0 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:03.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 04 io TEST: Entering pci_set_resource PCI: 00:03.0 24 <- [0x00f0000000 - 0x00f9ffffff] size 0x0a000000 gran 0x14 bus 04 prefmem TEST: Entering pci_set_resource PCI: 00:03.0 20 <- [0x00fa000000 - 0x00fb0fffff] size 0x01100000 gran 0x14 bus 04 mem TEST: Entering assign_resources PCI: 00:03.0 assign_resources, bus 4 link: 0 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 04:00.0 10 <- [0x00fa000000 - 0x00faffffff] size 0x01000000 gran 0x18 mem TEST: Entering pci_set_resource PCI: 04:00.0 14 <- [0x00f0000000 - 0x00f7ffffff] size 0x08000000 gran 0x1b prefmem64 TEST: Entering pci_set_resource PCI: 04:00.0 1c <- [0x00f8000000 - 0x00f9ffffff] size 0x02000000 gran 0x19 prefmem64 TEST: Entering pci_set_resource PCI: 04:00.0 24 <- [0x0000001000 - 0x000000107f] size 0x00000080 gran 0x07 io TEST: Entering pci_set_resource PCI: 04:00.0 30 <- [0x00fb000000 - 0x00fb07ffff] size 0x00080000 gran 0x13 romem TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 04:00.1 10 <- [0x00fb080000 - 0x00fb083fff] size 0x00004000 gran 0x0e mem PCI: 00:03.0 assign_resources, bus 4 link: 0 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:05.4 10 <- [0x00fb910000 - 0x00fb910fff] size 0x00001000 gran 0x0c mem TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:14.0 10 <- [0x00fb900000 - 0x00fb90ffff] size 0x00010000 gran 0x10 mem64 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:16.0 10 <- [0x00fb916000 - 0x00fb91600f] size 0x00000010 gran 0x04 mem64 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:16.1 10 <- [0x00fb917000 - 0x00fb91700f] size 0x00000010 gran 0x04 mem64 TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:16.2 10 <- [0x0000002050 - 0x0000002057] size 0x00000008 gran 0x03 io TEST: Entering pci_set_resource PCI: 00:16.2 14 <- [0x0000002078 - 0x000000207b] size 0x00000004 gran 0x02 io TEST: Entering pci_set_resource PCI: 00:16.2 18 <- [0x0000002058 - 0x000000205f] size 0x00000008 gran 0x03 io TEST: Entering pci_set_resource PCI: 00:16.2 1c <- [0x000000207c - 0x000000207f] size 0x00000004 gran 0x02 io TEST: Entering pci_set_resource PCI: 00:16.2 20 <- [0x0000002040 - 0x000000204f] size 0x00000010 gran 0x04 io TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:16.3 10 <- [0x0000002060 - 0x0000002067] size 0x00000008 gran 0x03 io TEST: Entering pci_set_resource PCI: 00:16.3 14 <- [0x00fb911000 - 0x00fb911fff] size 0x00001000 gran 0x0c mem TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:1d.0 10 <- [0x00fb914000 - 0x00fb9143ff] size 0x00000400 gran 0x0a mem TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_set_resource TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:1f.2 10 <- [0x0000002068 - 0x000000206f] size 0x00000008 gran 0x03 io TEST: Entering pci_set_resource PCI: 00:1f.2 14 <- [0x0000002080 - 0x0000002083] size 0x00000004 gran 0x02 io TEST: Entering pci_set_resource PCI: 00:1f.2 18 <- [0x0000002070 - 0x0000002077] size 0x00000008 gran 0x03 io TEST: Entering pci_set_resource PCI: 00:1f.2 1c <- [0x0000002084 - 0x0000002087] size 0x00000004 gran 0x02 io TEST: Entering pci_set_resource PCI: 00:1f.2 20 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io TEST: Entering pci_set_resource PCI: 00:1f.2 24 <- [0x00fb913000 - 0x00fb9137ff] size 0x00000800 gran 0x0b mem TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:1f.3 10 <- [0x00fb915000 - 0x00fb9150ff] size 0x00000100 gran 0x08 mem64 TEST: Entering pci_set_resource PCI: 00:1f.3 20 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io TEST: Entering pci_dev_set_resources TEST: Entering pci_set_resource PCI: 00:1f.6 10 <- [0x00fb912000 - 0x00fb912fff] size 0x00001000 gran 0x0c mem64 DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1000 size 1088 align 12 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base f0000000 size b917010 align 27 gran 0 limit fbffbfff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 0 PCI: 00:00.0 resource base 100000 size 7ef00000 align 0 gran 0 limit 0 flags e0004200 index 1 PCI: 00:00.0 resource base 7f800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 2 PCI: 00:00.0 resource base 7f000000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base 100000000 size 80000000 align 0 gran 0 limit 0 flags e0004200 index 4 PCI: 00:00.0 resource base 80000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base a0000 size 60000 align 0 gran 0 limit 0 flags f0000200 index 6 PCI: 00:01.0 PCI: 00:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:01.0 resource base fbffbfff size 0 align 20 gran 20 limit fbffbfff flags 60081202 index 24 PCI: 00:01.0 resource base fbffbfff size 0 align 20 gran 20 limit fbffbfff flags 60080202 index 20 PCI: 00:02.0 child on link 0 PCI: 02:00.0 PCI: 00:02.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.0 resource base fbffbfff size 0 align 20 gran 20 limit fbffbfff flags 60081202 index 24 PCI: 00:02.0 resource base fb700000 size 100000 align 20 gran 20 limit fb7fffff flags 60080202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base fb700000 size 2000 align 13 gran 13 limit fb701fff flags 60000201 index 10 PCI: 02:00.1 PCI: 02:00.1 resource base fb702000 size 2000 align 13 gran 13 limit fb703fff flags 60000201 index 10 PCI: 02:00.2 PCI: 02:00.2 resource base fb704000 size 2000 align 13 gran 13 limit fb705fff flags 60000201 index 10 PCI: 02:00.3 PCI: 02:00.3 resource base fb706000 size 2000 align 13 gran 13 limit fb707fff flags 60000201 index 10 PCI: 00:02.2 child on link 0 PCI: 03:00.0 PCI: 00:02.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.2 resource base fb200000 size 500000 align 21 gran 20 limit fb6fffff flags 60081202 index 24 PCI: 00:02.2 resource base fb800000 size 100000 align 20 gran 20 limit fb8fffff flags 60080202 index 20 PCI: 03:00.0 PCI: 03:00.0 resource base fb200000 size 200000 align 21 gran 21 limit fb3fffff flags 60001201 index 10 PCI: 03:00.0 resource base fb600000 size 4000 align 14 gran 14 limit fb603fff flags 60001201 index 20 PCI: 03:00.0 resource base fb800000 size 80000 align 19 gran 19 limit fb87ffff flags 60002200 index 30 PCI: 03:00.1 PCI: 03:00.1 resource base fb400000 size 200000 align 21 gran 21 limit fb5fffff flags 60001201 index 10 PCI: 03:00.1 resource base fb604000 size 4000 align 14 gran 14 limit fb607fff flags 60001201 index 20 PCI: 03:00.1 resource base fb880000 size 80000 align 19 gran 19 limit fb8fffff flags 60002200 index 30 PCI: 00:03.0 child on link 0 PCI: 04:00.0 PCI: 00:03.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c PCI: 00:03.0 resource base f0000000 size a000000 align 27 gran 20 limit f9ffffff flags 60081202 index 24 PCI: 00:03.0 resource base fa000000 size 1100000 align 24 gran 20 limit fb0fffff flags 60080202 index 20 PCI: 04:00.0 PCI: 04:00.0 resource base fa000000 size 1000000 align 24 gran 24 limit faffffff flags 60000200 index 10 PCI: 04:00.0 resource base f0000000 size 8000000 align 27 gran 27 limit f7ffffff flags 60001201 index 14 PCI: 04:00.0 resource base f8000000 size 2000000 align 25 gran 25 limit f9ffffff flags 60001201 index 1c PCI: 04:00.0 resource base 1000 size 80 align 7 gran 7 limit 107f flags 60000100 index 24 PCI: 04:00.0 resource base fb000000 size 80000 align 19 gran 19 limit fb07ffff flags 60002200 index 30 PCI: 04:00.1 PCI: 04:00.1 resource base fb080000 size 4000 align 14 gran 14 limit fb083fff flags 60000200 index 10 PCI: 00:05.0 PCI: 00:05.0 resource base fbffc000 size 2000 align 0 gran 0 limit 0 flags f0000200 index 180 PCI: 00:05.1 PCI: 00:05.2 PCI: 00:05.4 PCI: 00:05.4 resource base fb910000 size 1000 align 12 gran 12 limit fb910fff flags 60000200 index 10 PCI: 00:05.6 PCI: 00:06.0 PCI: 00:06.1 PCI: 00:06.2 PCI: 00:06.3 PCI: 00:06.4 PCI: 00:06.5 PCI: 00:06.6 PCI: 00:06.7 PCI: 00:07.0 PCI: 00:07.1 PCI: 00:07.2 PCI: 00:07.3 PCI: 00:07.4 PCI: 00:14.0 PCI: 00:14.0 resource base fb900000 size 10000 align 16 gran 16 limit fb90ffff flags 60000201 index 10 PCI: 00:16.0 PCI: 00:16.0 resource base fb916000 size 10 align 12 gran 4 limit fb91600f flags 60000201 index 10 PCI: 00:16.1 PCI: 00:16.1 resource base fb917000 size 10 align 12 gran 4 limit fb91700f flags 60000201 index 10 PCI: 00:16.2 PCI: 00:16.2 resource base 2050 size 8 align 3 gran 3 limit 2057 flags 60000100 index 10 PCI: 00:16.2 resource base 2078 size 4 align 2 gran 2 limit 207b flags 60000100 index 14 PCI: 00:16.2 resource base 2058 size 8 align 3 gran 3 limit 205f flags 60000100 index 18 PCI: 00:16.2 resource base 207c size 4 align 2 gran 2 limit 207f flags 60000100 index 1c PCI: 00:16.2 resource base 2040 size 10 align 4 gran 4 limit 204f flags 60000100 index 20 PCI: 00:16.3 PCI: 00:16.3 resource base 2060 size 8 align 3 gran 3 limit 2067 flags 60000100 index 10 PCI: 00:16.3 resource base fb911000 size 1000 align 12 gran 12 limit fb911fff flags 60000200 index 14 PCI: 00:1d.0 PCI: 00:1d.0 resource base fb914000 size 400 align 12 gran 10 limit fb9143ff flags 60000200 index 10 PCI: 00:1f.0 PCI: 00:1f.0 resource base feb00000 size 10000 align 0 gran 0 limit 0 flags f0000200 index feb0 PCI: 00:1f.0 resource base feb80000 size 80000 align 0 gran 0 limit 0 flags f0000200 index feb8 PCI: 00:1f.0 resource base fec00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fec0 PCI: 00:1f.0 resource base fec01000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fec1 PCI: 00:1f.0 resource base fed00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fed0 PCI: 00:1f.0 resource base fef00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index fef0 PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags f0000200 index ff00 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:1f.0 resource base 500 size 80 align 0 gran 0 limit 0 flags c0000100 index 48 PCI: 00:1f.2 PCI: 00:1f.2 resource base 2068 size 8 align 3 gran 3 limit 206f flags 60000100 index 10 PCI: 00:1f.2 resource base 2080 size 4 align 2 gran 2 limit 2083 flags 60000100 index 14 PCI: 00:1f.2 resource base 2070 size 8 align 3 gran 3 limit 2077 flags 60000100 index 18 PCI: 00:1f.2 resource base 2084 size 4 align 2 gran 2 limit 2087 flags 60000100 index 1c PCI: 00:1f.2 resource base 2000 size 20 align 5 gran 5 limit 201f flags 60000100 index 20 PCI: 00:1f.2 resource base fb913000 size 800 align 12 gran 11 limit fb9137ff flags 60000200 index 24 PCI: 00:1f.3 PCI: 00:1f.3 resource base fb915000 size 100 align 12 gran 8 limit fb9150ff flags 60000201 index 10 PCI: 00:1f.3 resource base 2020 size 20 align 5 gran 5 limit 203f flags 60000100 index 20 PCI: 00:1f.6 PCI: 00:1f.6 resource base fb912000 size 1000 align 12 gran 12 limit fb912fff flags 60000201 index 10 Done allocating resources. TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_report_time BS: BS_DEV_RESOURCES times (us): entry 6302 run 14338656 exit 6303 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_dev_enable TEST: Entering dev_enable Enabling resources... TEST: Entering enable_resources TEST: Entering enable_resources TEST: Entering enable_resources TEST: Entering pci_dev_enable_resources PCI: 00:00.0 subsystem <- 8086/6f00 TEST: Entering pci_dev_set_subsystem PCI: 00:00.0 cmd <- 400 TEST: Entering pci_bus_enable_resources PCI: 00:01.0 bridge ctrl <- 0003 TEST: Entering pci_dev_enable_resources PCI: 00:01.0 cmd <- 00 TEST: Entering pci_bus_enable_resources PCI: 00:02.0 bridge ctrl <- 0003 TEST: Entering pci_dev_enable_resources PCI: 00:02.0 cmd <- 06 TEST: Entering pci_bus_enable_resources PCI: 00:02.2 bridge ctrl <- 0003 TEST: Entering pci_dev_enable_resources PCI: 00:02.2 cmd <- 06 TEST: Entering pci_bus_enable_resources PCI: 00:03.0 bridge ctrl <- 000b TEST: Entering pci_dev_enable_resources PCI: 00:03.0 cmd <- 07 TEST: Entering pci_dev_enable_resources PCI: 00:05.1 cmd <- 04 TEST: Entering pci_dev_enable_resources PCI: 00:05.2 cmd <- 04 TEST: Entering pci_dev_enable_resources PCI: 00:05.4 cmd <- 06 TEST: Entering pci_dev_enable_resources PCI: 00:05.6 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:06.0 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:06.1 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:06.2 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:06.3 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:06.4 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:06.5 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:06.6 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:06.7 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:07.0 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:07.1 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:07.2 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:07.3 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:07.4 cmd <- ffff TEST: Entering pci_dev_enable_resources PCI: 00:14.0 subsystem <- 8086/8c31 TEST: Entering pci_dev_set_subsystem PCI: 00:14.0 cmd <- 02 TEST: Entering pci_dev_enable_resources PCI: 00:16.0 cmd <- 06 TEST: Entering pci_dev_enable_resources PCI: 00:16.1 cmd <- 02 TEST: Entering pci_dev_enable_resources PCI: 00:16.2 cmd <- 01 TEST: Entering pci_dev_enable_resources PCI: 00:16.3 cmd <- 03 TEST: Entering pci_dev_enable_resources PCI: 00:1d.0 subsystem <- 8086/8c26 TEST: Entering pci_dev_set_subsystem PCI: 00:1d.0 cmd <- 02 TEST: Entering pci_dev_enable_resources PCI: 00:1f.2 subsystem <- 8086/8c02 TEST: Entering pci_dev_set_subsystem PCI: 00:1f.2 cmd <- 03 TEST: Entering pci_dev_enable_resources PCI: 00:1f.3 cmd <- 03 TEST: Entering pci_dev_enable_resources PCI: 00:1f.6 cmd <- 02 TEST: Entering enable_resources TEST: Entering enable_resources TEST: Entering pci_dev_enable_resources PCI: 02:00.0 cmd <- 06 TEST: Entering pci_dev_enable_resources PCI: 02:00.1 cmd <- 06 TEST: Entering pci_dev_enable_resources PCI: 02:00.2 cmd <- 06 TEST: Entering pci_dev_enable_resources PCI: 02:00.3 cmd <- 06 TEST: Entering enable_resources TEST: Entering pci_dev_enable_resources PCI: 03:00.0 cmd <- 02 TEST: Entering pci_dev_enable_resources PCI: 03:00.1 cmd <- 02 TEST: Entering enable_resources TEST: Entering pci_dev_enable_resources PCI: 04:00.0 cmd <- 03 TEST: Entering pci_dev_enable_resources PCI: 04:00.1 cmd <- 02 done. TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_report_time BS: BS_DEV_ENABLE times (us): entry 6302 run 340699 exit 6302 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_dev_init TEST: Entering dev_initialize Initializing devices... calling init_dev() TEST: Entering init_dev Root Device init ... Root Device init finished in 2134 usecs TEST: Entering init_link TEST: Entering init_dev CPU_CLUSTER: 0 init ... MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled Setting up local APIC... apic_id: 0x00 done. Setting up SMI for CPU Will perform SMM setup. CPU: Intel(R) Xeon(R) CPU D-1531 @ 2.20GHz. TEST: Entering alloc_find_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev TEST: Entering alloc_find_dev TEST: Entering __alloc_dev Loading module at 00030000 with entry 00030000. filesize: 0x130 memsize: 0x130 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 11 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 2 apic_id 1. done. AP: slot 8 apic_id 9. AP: slot 9 apic_id 8. AP: slot 6 apic_id b. AP: slot 3 apic_id a. Waiting for 2nd SIPI to complete...done. AP: slot 7 apic_id 7. AP: slot 5 apic_id 6. AP: slot 4 apic_id 5. AP: slot 1 apic_id 4. AP: slot 11 apic_id 2. AP: slot 10 apic_id 3. Loading module at 00038000 with entry 00038000. filesize: 0x1c0 memsize: 0x1c0 Processing 13 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call 7eec50ec(00000000) Installing SMM handler to 0x7f800000 Loading module at 7f810000 with entry 7f81002b. filesize: 0x188 memsize: 0x4190 Processing 11 relocs. Offset value of 0x7f810000 Loading module at 7f808000 with entry 7f808000. filesize: 0x1c0 memsize: 0x1c0 Processing 13 relocs. Offset value of 0x7f808000 SMM Module: placing jmp sequence at 7f807c00 rel16 0x03fd SMM Module: placing jmp sequence at 7f807800 rel16 0x07fd SMM Module: placing jmp sequence at 7f807400 rel16 0x0bfd SMM Module: placing jmp sequence at 7f807000 rel16 0x0ffd SMM Module: placing jmp sequence at 7f806c00 rel16 0x13fd SMM Module: placing jmp sequence at 7f806800 rel16 0x17fd SMM Module: placing jmp sequence at 7f806400 rel16 0x1bfd SMM Module: placing jmp sequence at 7f806000 rel16 0x1ffd SMM Module: placing jmp sequence at 7f805c00 rel16 0x23fd SMM Module: placing jmp sequence at 7f805800 rel16 0x27fd SMM Module: placing jmp sequence at 7f805400 rel16 0x2bfd SMM Module: stub loaded at 7f808000. Will call 7f81002b(00000000) Initializing Southbridge SMI... ... pmbase = 0x0400 SMI_STS: PM1 PM1_STS: TMROF New SMBASE 0x7f800000 In relocation handler: CPU 0 Relocation complete. Doing parallel SMM relocation. New SMBASE 0x7f7fe800 In relocation handler: CPU 6 New SMBASE 0x7f7fd800 New SMBASE 0x7f7fdc00 New SMBASE 0x7f7fe000 In relocation handler: CPU 8 New SMBASE=0x7f7fe000 IEDBASE=0x7fc00000 In relocation handler: CPU 9 New SMBASE 0x7f7fec00 New SMBASE 0x7f7fe400 In relocation handler: CPU 7 New SMBASE=0x7f7fe400 IEDBASE=0x7fc00000 In relocation handler: CPU 5 New SMBASE=0x7f7fec00 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff800800 Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. Relocation complete. New SMBASE 0x7f7fd400 In relocation handler: CPU 11 New SMBASE=0x7f7fd400 IEDBASE=0x7fc00000 New SMBASE=0x7f7fdc00 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff800800 Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. Relocation complete. microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date New SMBASE=0x7f7fe800 IEDBASE=0x7fc00000 New SMBASE 0x7f7ff400 In relocation handler: CPU 3 New SMBASE=0x7f7ff400 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff800800 Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. Relocation complete. microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date In relocation handler: CPU 10 New SMBASE=0x7f7fd800 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff800800 Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. Relocation complete. microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date New SMBASE 0x7f800000 In relocation handler: CPU 0 New SMBASE 0x7f7ff800 In relocation handler: CPU 2 New SMBASE=0x7f7ff800 IEDBASE=0x7fc00000 New SMBASE=0x7f800000 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff800800 Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. Relocation complete. microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date New SMBASE 0x7f7ffc00 New SMBASE 0x7f7ff000 In relocation handler: CPU 1 In relocation handler: CPU 4 New SMBASE=0x7f7ffc00 IEDBASE=0x7fc00000 New SMBASE=0x7f7ff000 IEDBASE=0x7fc00000 Writing SMRR. base = 0x7f800006, mask=0xff800800 Writing SMRR. base = 0x7f800006, mask=0xff800800 Relocation complete. Relocation complete. microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date Initializing CPU #0 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 Init Broadwell-DE core. CPU #0 initialized Initializing CPU #2 Initializing CPU #8 Initializing CPU #9 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 Init Broadwell-DE core. Init Broadwell-DE core. Initializing CPU #10 Initializing CPU #11 CPU: vendor Intel device 50663 CPU: vendor Intel device 50663 Initializing CPU #3 Initializing CPU #6 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 Init Broadwell-DE core. Init Broadwell-DE core. CPU #3 initialized CPU #9 initialized Initializing CPU #7 Initializing CPU #5 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 Init Broadwell-DE core. CPU #8 initialized Initializing CPU #4 CPU #6 initialized CPU: family 06, model 56, stepping 03 CPU: family 06, model 56, stepping 03 Init Broadwell-DE core. CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 Init Broadwell-DE core. Init Broadwell-DE core. CPU #7 initialized CPU #5 initialized CPU #2 initialized CPU: vendor Intel device 50663 CPU #11 initialized Init Broadwell-DE core. CPU: family 06, model 56, stepping 03 Initializing CPU #1 Init Broadwell-DE core. CPU #10 initialized CPU #4 initialized CPU: vendor Intel device 50663 CPU: family 06, model 56, stepping 03 Init Broadwell-DE core. CPU #1 initialized bsp_do_flight_plan done after 560 msecs. Enabling SMIs. Locking SMM. CPU_CLUSTER: 0 init finished in 707348 usecs TEST: Entering init_dev TEST: Entering init_link TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_link TEST: Entering init_dev TEST: Entering init_dev PCI: 00:01.0 init ... PCI: 00:01.0 init finished in 2231 usecs TEST: Entering init_dev TEST: Entering init_dev TEST: Entering init_dev PCI: 00:03.0 init ... PCI: 00:03.0 init finished in 2231 usecs TEST: Entering init_dev TEST: Entering init_dev PCI: 00:05.1 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:05.1 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:05.2 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:05.2 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:05.4 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x800 TEST: if 2 false, returning PCI: 00:05.4 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:05.6 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x1101 TEST: if 2 false, returning PCI: 00:05.6 init finished in 12025 usecs TEST: Entering init_dev PCI: 00:06.0 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:06.0 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:06.1 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:06.1 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:06.2 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:06.2 init finished in 11928 usecs TEST: Entering init_dev PCI: 00:06.3 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:06.3 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:06.4 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:06.4 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:06.5 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:06.5 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:06.6 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:06.6 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:06.7 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:06.7 init finished in 11928 usecs TEST: Entering init_dev PCI: 00:07.0 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:07.0 init finished in 11928 usecs TEST: Entering init_dev PCI: 00:07.1 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:07.1 init finished in 11928 usecs TEST: Entering init_dev PCI: 00:07.2 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:07.2 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:07.3 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:07.3 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:07.4 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 00:07.4 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:14.0 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0xc03 TEST: if 2 false, returning PCI: 00:14.0 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:16.0 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x780 TEST: if 2 false, returning PCI: 00:16.0 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:16.1 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x780 TEST: if 2 false, returning PCI: 00:16.1 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:16.2 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x101 TEST: if 2 false, returning PCI: 00:16.2 init finished in 11928 usecs TEST: Entering init_dev PCI: 00:16.3 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x700 TEST: if 2 false, returning PCI: 00:16.3 init finished in 11928 usecs TEST: Entering init_dev PCI: 00:1d.0 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0xc03 TEST: if 2 false, returning PCI: 00:1d.0 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:1f.0 init ... soc: southcluster_init Programming PIRQ[A-H] Routing Control Register PIRQ[A]: 05 PIRQ[B]: 06 PIRQ[C]: 07 PIRQ[D]: 0a PIRQ[E]: 0b PIRQ[F]: 0c PIRQ[G]: 0e PIRQ[H]: 0f PCI_CFG IRQ: Write PCI config space IRQ assignments TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:00.00 using PIN A Warning: PCI Device 0 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:14.00 using PIN D INT_PIN : 4 (PIN D) PIRQ : D INT_LINE : 0xA (IRQ 10) TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:1D.00 using PIN C INT_PIN : 3 (PIN C) PIRQ : C INT_LINE : 0x7 (IRQ 7) TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:1F.02 using PIN A INT_PIN : 1 (PIN A) PIRQ : A INT_LINE : 0x5 (IRQ 5) TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:1F.03 using PIN C INT_PIN : 3 (PIN C) PIRQ : C INT_LINE : 0x7 (IRQ 7) TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:01.00 using PIN A Warning: PCI Device 1 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:03.00 using PIN A Warning: PCI Device 3 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:02.00 using PIN A Warning: PCI Device 2 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:02.02 using PIN A Warning: PCI Device 2 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:16.00 using PIN A INT_PIN : 1 (PIN A) PIRQ : A INT_LINE : 0x5 (IRQ 5) TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:16.01 using PIN B INT_PIN : 2 (PIN B) PIRQ : B INT_LINE : 0x6 (IRQ 6) TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:16.02 using PIN A INT_PIN : 1 (PIN A) PIRQ : A INT_LINE : 0x5 (IRQ 5) TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:16.03 using PIN B INT_PIN : 2 (PIN B) PIRQ : B INT_LINE : 0x6 (IRQ 6) TEST: Entering get_pci_irq_pins PCI IRQ: Found device 0:1F.06 using PIN C INT_PIN : 3 (PIN C) PIRQ : C INT_LINE : 0x7 (IRQ 7) TEST: Entering get_pci_irq_pins PCI IRQ: Found device 2:00.00 using PIN A TEST: Entering swizzle_irq_pins With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.00h Warning: PCI Device 2 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 2:00.01 using PIN B TEST: Entering swizzle_irq_pins With INT_PIN swizzled to PIN B Attached to bridge device 0:02h.00h Warning: PCI Device 2 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 2:00.02 using PIN C TEST: Entering swizzle_irq_pins With INT_PIN swizzled to PIN C Attached to bridge device 0:02h.00h Warning: PCI Device 2 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 2:00.03 using PIN D TEST: Entering swizzle_irq_pins With INT_PIN swizzled to PIN D Attached to bridge device 0:02h.00h Warning: PCI Device 2 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 3:00.00 using PIN A TEST: Entering swizzle_irq_pins With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.02h Warning: PCI Device 2 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 3:00.01 using PIN B TEST: Entering swizzle_irq_pins With INT_PIN swizzled to PIN B Attached to bridge device 0:02h.02h Warning: PCI Device 2 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 4:00.00 using PIN A TEST: Entering swizzle_irq_pins With INT_PIN swizzled to PIN A Attached to bridge device 0:03h.00h Warning: PCI Device 3 does not have an IRQ entry, skipping it TEST: Entering get_pci_irq_pins PCI IRQ: Found device 4:00.01 using PIN B TEST: Entering swizzle_irq_pins With INT_PIN swizzled to PIN B Attached to bridge device 0:03h.00h Warning: PCI Device 3 does not have an IRQ entry, skipping it PCI_CFG IRQ: Finished writing PCI config space IRQ assignments PCI: 00:1f.0 init finished in 467708 usecs TEST: Entering init_dev PCI: 00:1f.2 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x106 TEST: if 2 false, returning PCI: 00:1f.2 init finished in 11927 usecs TEST: Entering init_dev PCI: 00:1f.3 init ... PCI: 00:1f.3 init finished in 2233 usecs TEST: Entering init_dev PCI: 00:1f.6 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x1180 TEST: if 2 false, returning PCI: 00:1f.6 init finished in 12024 usecs TEST: Entering init_link TEST: Entering init_link TEST: Entering init_dev PCI: 02:00.0 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 02:00.0 init finished in 11927 usecs TEST: Entering init_dev PCI: 02:00.1 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 02:00.1 init finished in 11928 usecs TEST: Entering init_dev PCI: 02:00.2 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 02:00.2 init finished in 11927 usecs TEST: Entering init_dev PCI: 02:00.3 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x880 TEST: if 2 false, returning PCI: 02:00.3 init finished in 11926 usecs TEST: Entering init_link TEST: Entering init_dev PCI: 03:00.0 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x200 TEST: if 2 false, returning PCI: 03:00.0 init finished in 11928 usecs TEST: Entering init_dev PCI: 03:00.1 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x200 TEST: if 2 false, returning PCI: 03:00.1 init finished in 11927 usecs TEST: Entering init_link TEST: Entering init_dev PCI: 04:00.0 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x300 TEST: Entering should_load_oprom TEST: Entering should_run_oprom TEST: calling TEST: Exiting should_run_oprom TEST: if 2:returning 1 TEST: Entering pci_rom_probe CBFS @ 200200 size 5ffe00 CBFS: 'Master Header Locator' located CBFS at [200200:800000) CBFS: Locating 'pci10de,128b.rom' CBFS: Checking offset 0 CBFS: File @ offset 0 size 20 CBFS: Unmatched 'cbfs master header' at 0 CBFS: Checking offset 80 CBFS: File @ offset 80 size 44a4 CBFS: Unmatched 'fallback/romstage' at 80 CBFS: Checking offset 45c0 CBFS: File @ offset 45c0 size 19800 CBFS: Unmatched 'cpu_microcode_blob.bin' at 45c0 CBFS: Checking offset 1de40 CBFS: File @ offset 1de40 size f868 CBFS: Unmatched 'fallback/ramstage' at 1de40 CBFS: Checking offset 2d700 CBFS: File @ offset 2d700 size 3dd CBFS: Unmatched 'config' at 2d700 CBFS: Checking offset 2db40 CBFS: File @ offset 2db40 size 2b8 CBFS: Unmatched 'revision' at 2db40 CBFS: Checking offset 2de40 CBFS: File @ offset 2de40 size 368 CBFS: Unmatched 'cmos_layout.bin' at 2de40 CBFS: Checking offset 2e200 CBFS: File @ offset 2e200 size 25ca CBFS: Unmatched 'fallback/dsdt.aml' at 2e200 CBFS: Checking offset 30840 CBFS: File @ offset 30840 size 410038 CBFS: Unmatched 'img/uefi' at 30840 CBFS: Checking offset 4408c0 CBFS: File @ offset 4408c0 size 109f0 CBFS: Unmatched 'fallback/payload' at 4408c0 CBFS: Checking offset 451300 CBFS: File @ offset 451300 size 639 CBFS: Unmatched 'payload_config' at 451300 CBFS: Checking offset 451980 CBFS: File @ offset 451980 size 100 CBFS: Unmatched 'payload_revision' at 451980 CBFS: Checking offset 451b00 CBFS: File @ offset 451b00 size 5e298 CBFS: Unmatched '' at 451b00 CBFS: Checking offset 4afdc0 CBFS: File @ offset 4afdc0 size 120000 CBFS: Unmatched 'fsp.bin' at 4afdc0 CBFS: Checking offset 5cfe00 CBFS: File @ offset 5cfe00 size 2fa18 CBFS: Unmatched '' at 5cfe00 CBFS: Checking offset 5ff840 CBFS: File @ offset 5ff840 size 580 CBFS: Unmatched 'bootblock' at 5ff840 CBFS: Checking offset 5ffe00 CBFS: 'pci10de,128b.rom' not found. Option ROM address for PCI: 04:00.0 = fb000000 PCI expansion ROM, signature 0xaa55, INIT size 0xf200, data ptr 0x0190 PCI ROM image, vendor ID 10de, device ID 128b, PCI ROM image, Class Code 030000, Code Type 00 TEST: Entering pci_rom_load Copying VGA ROM Image from fb000000 to 0xc0000, 0xf200 bytes TEST: Entering should_run_oprom TEST: should_run = 1 TEST: calling run_bios Real mode stub @00000600: 889 bytes Calling Option ROM... ... Option ROM returned. TEST: calling gfx_set_init_done VGA Option ROM was run TEST: Exiting pci_dev_init PCI: 04:00.0 init finished in 539522 usecs TEST: Entering init_dev PCI: 04:00.1 init ... TEST: Entering pci_dev_init TEST: Calling if 2, dev_class>>8 = 0x403 TEST: if 2 false, returning PCI: 04:00.1 init finished in 11928 usecs Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 APIC: 00: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:19.0: enabled 0 PCI: 00:1d.0: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.5: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:05.0: enabled 1 PCI: 00:05.1: enabled 1 PCI: 00:05.2: enabled 1 PCI: 00:05.4: enabled 1 PCI: 00:05.6: enabled 1 PCI: 00:06.0: enabled 1 PCI: 00:06.1: enabled 1 PCI: 00:06.2: enabled 1 PCI: 00:06.3: enabled 1 PCI: 00:06.4: enabled 1 PCI: 00:06.5: enabled 1 PCI: 00:06.6: enabled 1 PCI: 00:06.7: enabled 1 PCI: 00:07.0: enabled 1 PCI: 00:07.1: enabled 1 PCI: 00:07.2: enabled 1 PCI: 00:07.3: enabled 1 PCI: 00:07.4: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 1 PCI: 00:16.2: enabled 1 PCI: 00:16.3: enabled 1 PCI: 00:1f.6: enabled 1 PCI: 02:00.0: enabled 1 PCI: 02:00.1: enabled 1 PCI: 02:00.2: enabled 1 PCI: 02:00.3: enabled 1 PCI: 03:00.0: enabled 1 PCI: 03:00.1: enabled 1 PCI: 04:00.0: enabled 1 PCI: 04:00.1: enabled 1 APIC: 04: enabled 1 APIC: 01: enabled 1 APIC: 0a: enabled 1 APIC: 05: enabled 1 APIC: 06: enabled 1 APIC: 0b: enabled 1 APIC: 07: enabled 1 APIC: 09: enabled 1 APIC: 08: enabled 1 APIC: 03: enabled 1 APIC: 02: enabled 1 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_report_time BS: BS_DEV_INIT times (us): entry 6308 run 2575615 exit 6303 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_post_device TEST: Entering dev_finalize Finalize devices... TEST: Entering final_dev TEST: Entering final_link TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_link TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_link TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_link TEST: Entering final_link TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_link TEST: Entering final_dev TEST: Entering final_dev TEST: Entering final_link TEST: Entering final_dev TEST: Entering final_dev Devices finalized TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_report_time BS: BS_POST_DEVICE times (us): entry 6302 run 172245 exit 6302 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_os_resume_check TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_report_time BS: BS_OS_RESUME_CHECK times (us): entry 6303 run 6401 exit 6302 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks === FSP HOB Data Structure === FSP Hoblistptr: 0x7f100000 HOB 0x7f100000 is an EFI_HOB_TYPE_HANDOFF (type 0x1) HOB 0x7f100038 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f100038 with length0x0 Address: 7f100040 Guid: ea296d92-0b69-423c-8c2833b4e0a91268 HOB 0x7f1000d8 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f1000d8 with length0x0 Address: 7f1000e0 Guid: 9b3ada4f-ae56-4c24-8deaf03b7558ae50 HOB 0x7f100170 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f100170 with length0x0 Address: 7f100178 Guid: 1e2acc41-e26a-483d-afc7a056c34e087b HOB 0x7f100260 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f100270 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f100288 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f100520 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f100520 with length0x0 Address: 7f100528 Guid: 489d2a71-ba4a-444c-9fe2a6b7e5cd7847 HOB 0x7f100570 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_SYSTEM_MEMORY (0x0) has attributes 0x3c07 at location 0x0 with length 0xa0000 HOB 0x7f1005a0 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_MEMORY_RESERVED (0x5) has attributes 0x3c07 at location 0xa0000 with length 0x60000 HOB 0x7f1005d0 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_SYSTEM_MEMORY (0x0) has attributes 0x3c07 at location 0x100000 with length 0x7ef00000 HOB 0x7f100600 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_MEMORY_RESERVED (0x5) has attributes 0x3c07 at location 0x7f000000 with length 0x800000 HOB 0x7f100630 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_MEMORY_RESERVED (0x5) has attributes 0x3c07 at location 0x7f800000 with length 0x800000 HOB 0x7f100660 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_SYSTEM_MEMORY (0x0) has attributes 0x3c07 at location 0x0 with length 0x80000000 HOB 0x7f100690 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f100690 with length0xffff Address: 7f100698 Guid: 1de25879-6e2a-4d72-a768288ccb9fa719 HOB 0x7f10f6a8 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f10f6a8 with length0xffff Address: 7f10f6b0 Guid: 1de25879-6e2a-4d72-a768288ccb9fa719 HOB 0x7f11e6c0 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f11e6c0 with length0x0 Address: 7f11e6c8 Guid: 1de25879-6e2a-4d72-a768288ccb9fa719 HOB 0x7f121bd8 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f121bd8 with length0x0 Address: 7f121be0 Guid: 7ff396a1-ee7d-431e-ba538fca127c44c0 HOB 0x7f123158 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f123158 with length0x0 Address: 7f123160 Guid: f8870015-6994-4b98-95a2bd56da91c07f HOB 0x7f127208 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f000000 with length 0x100000 HOB 0x7f127238 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7ff000 with length 0x1000 HOB 0x7f127268 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7f5000 with length 0xa000 HOB 0x7f127298 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f127298 with length0xffff Address: 7f1272a0 Guid: bbcff46c-c8d3-4113-8985b9d4f3b3f64e HOB 0x7f12f2b0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7ef000 with length 0x6000 HOB 0x7f12f2e0 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f12f2e0 with length0x0 Address: 7f12f2e8 Guid: 98c8588c-640a-4bb4-aea03f81cde17524 HOB 0x7f12f490 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f12f490 with length0x0 Address: 7f12f498 Guid: ee4e5898-3914-4259-9d6edc7bd79403cf HOB 0x7f12f4b8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f4d0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7eb000 with length 0x4000 HOB 0x7f12f500 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7e7000 with length 0x4000 HOB 0x7f12f530 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7e4000 with length 0x3000 HOB 0x7f12f560 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7e0000 with length 0x4000 HOB 0x7f12f590 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7d5000 with length 0xb000 HOB 0x7f12f5c0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7cb000 with length 0xa000 HOB 0x7f12f5f0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f600 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f618 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f630 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f688 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f698 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f6a8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f6b8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f6c8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f6d8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f6e8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f718 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f740 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f750 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f760 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f850 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7c7000 with length 0x4000 HOB 0x7f12f880 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7bd000 with length 0xa000 HOB 0x7f12f8b0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7b4000 with length 0x9000 HOB 0x7f12f8e0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f8f8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f12f930 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) at location 7f12f930 with length0x0 Address: 7f12f938 Guid: c1392859-1f65-446e-b3f58435fcc7d1c4 HOB 0x7f12fa60 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7b0000 with length 0x4000 HOB 0x7f12fa90 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7ab000 with length 0x5000 HOB 0x7f12fac0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7a7000 with length 0x4000 HOB 0x7f12faf0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f7a3000 with length 0x4000 HOB 0x7f12fb20 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f79c000 with length 0x7000 HOB 0x7f12fb50 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f796000 with length 0x6000 HOB 0x7f12fb80 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f792000 with length 0x4000 HOB 0x7f12fbb0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f770000 with length 0x22000 HOB 0x7f12fbe0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f74f000 with length 0x21000 HOB 0x7f12fc10 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f130c50 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) Resource EFI_RESOURCE_MEMORY_MAPPED_IO (0x1) has attributes 0x403 at location 0xfbffc000 with length 0x2000 HOB 0x7f130c80 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f74b000 with length 0x4000 HOB 0x7f130cb0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f743000 with length 0x8000 HOB 0x7f130ce0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f73c000 with length 0x7000 HOB 0x7f130d10 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f738000 with length 0x4000 HOB 0x7f130d40 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f733000 with length 0x5000 HOB 0x7f130d70 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f72f000 with length 0x4000 HOB 0x7f130da0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f130de0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f72b000 with length 0x4000 HOB 0x7f130e10 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f723000 with length 0x8000 HOB 0x7f130e40 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f71c000 with length 0x7000 HOB 0x7f130e70 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f130eb0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f130f60 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f131168 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f70c000 with length 0x10000 HOB 0x7f131198 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f1312b8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f708000 with length 0x4000 HOB 0x7f1312e8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f6f6000 with length 0x12000 HOB 0x7f131318 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f6e6000 with length 0x10000 HOB 0x7f131348 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f131360 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f6e2000 with length 0x4000 HOB 0x7f131390 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f6dd000 with length 0x5000 HOB 0x7f1313c0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) Memory type EfiBootServicesData (0x4) at location 0x7f6d9000 with length 0x4000 HOB 0x7f1313f0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7f132908 is an EFI_HOB_TYPE_END_OF_HOB_LIST (type 0xffff) === End of FSP HOB Data Structure === TEST: Entering bs_sample_time TEST: Entering bs_write_tables CBFS @ 200200 size 5ffe00 CBFS: 'Master Header Locator' located CBFS at [200200:800000) CBFS: Locating 'fallback/dsdt.aml' CBFS: Checking offset 0 CBFS: File @ offset 0 size 20 CBFS: Unmatched 'cbfs master header' at 0 CBFS: Checking offset 80 CBFS: File @ offset 80 size 44a4 CBFS: Unmatched 'fallback/romstage' at 80 CBFS: Checking offset 45c0 CBFS: File @ offset 45c0 size 19800 CBFS: Unmatched 'cpu_microcode_blob.bin' at 45c0 CBFS: Checking offset 1de40 CBFS: File @ offset 1de40 size f868 CBFS: Unmatched 'fallback/ramstage' at 1de40 CBFS: Checking offset 2d700 CBFS: File @ offset 2d700 size 3dd CBFS: Unmatched 'config' at 2d700 CBFS: Checking offset 2db40 CBFS: File @ offset 2db40 size 2b8 CBFS: Unmatched 'revision' at 2db40 CBFS: Checking offset 2de40 CBFS: File @ offset 2de40 size 368 CBFS: Unmatched 'cmos_layout.bin' at 2de40 CBFS: Checking offset 2e200 CBFS: File @ offset 2e200 size 25ca CBFS: Found @ offset 2e200 size 25ca CBFS @ 200200 size 5ffe00 CBFS: 'Master Header Locator' located CBFS at [200200:800000) CBFS: Locating 'fallback/slic' CBFS: Checking offset 0 CBFS: File @ offset 0 size 20 CBFS: Unmatched 'cbfs master header' at 0 CBFS: Checking offset 80 CBFS: File @ offset 80 size 44a4 CBFS: Unmatched 'fallback/romstage' at 80 CBFS: Checking offset 45c0 CBFS: File @ offset 45c0 size 19800 CBFS: Unmatched 'cpu_microcode_blob.bin' at 45c0 CBFS: Checking offset 1de40 CBFS: File @ offset 1de40 size f868 CBFS: Unmatched 'fallback/ramstage' at 1de40 CBFS: Checking offset 2d700 CBFS: File @ offset 2d700 size 3dd CBFS: Unmatched 'config' at 2d700 CBFS: Checking offset 2db40 CBFS: File @ offset 2db40 size 2b8 CBFS: Unmatched 'revision' at 2db40 CBFS: Checking offset 2de40 CBFS: File @ offset 2de40 size 368 CBFS: Unmatched 'cmos_layout.bin' at 2de40 CBFS: Checking offset 2e200 CBFS: File @ offset 2e200 size 25ca CBFS: Unmatched 'fallback/dsdt.aml' at 2e200 CBFS: Checking offset 30840 CBFS: File @ offset 30840 size 410038 CBFS: Unmatched 'img/uefi' at 30840 CBFS: Checking offset 4408c0 CBFS: File @ offset 4408c0 size 109f0 CBFS: Unmatched 'fallback/payload' at 4408c0 CBFS: Checking offset 451300 CBFS: File @ offset 451300 size 639 CBFS: Unmatched 'payload_config' at 451300 CBFS: Checking offset 451980 CBFS: File @ offset 451980 size 100 CBFS: Unmatched 'payload_revision' at 451980 CBFS: Checking offset 451b00 CBFS: File @ offset 451b00 size 5e298 CBFS: Unmatched '' at 451b00 CBFS: Checking offset 4afdc0 CBFS: File @ offset 4afdc0 size 120000 CBFS: Unmatched 'fsp.bin' at 4afdc0 CBFS: Checking offset 5cfe00 CBFS: File @ offset 5cfe00 size 2fa18 CBFS: Unmatched '' at 5cfe00 CBFS: Checking offset 5ff840 CBFS: File @ offset 5ff840 size 580 CBFS: Unmatched 'bootblock' at 5ff840 CBFS: Checking offset 5ffe00 CBFS: 'fallback/slic' not found. ACPI: Writing ACPI tables at 7ed3d000. ACPI: * FACS ACPI: * DSDT ACPI: * FADT SCI is IRQ9 ACPI: added table 1/32, length now 40 ACPI: * SSDT Turbo is available and visible PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 PSS: 2700MHz power 45000 control 0x1b00 status 0x1b00 PSS: 2200MHz power 45000 control 0x1600 status 0x1600 PSS: 2100MHz power 42414 control 0x1500 status 0x1500 PSS: 2000MHz power 39964 control 0x1400 status 0x1400 PSS: 1900MHz power 37514 control 0x1300 status 0x1300 PSS: 1800MHz power 35116 control 0x1200 status 0x1200 PSS: 1700MHz power 32759 control 0x1100 status 0x1100 PSS: 1600MHz power 30490 control 0x1000 status 0x1000 PSS: 1500MHz power 28224 control 0xf00 status 0xf00 PSS: 1400MHz power 26072 control 0xe00 status 0xe00 PSS: 1300MHz power 23895 control 0xd00 status 0xd00 PSS: 1200MHz power 21802 control 0xc00 status 0xc00 PSS: 1100MHz power 19755 control 0xb00 status 0xb00 PSS: 1000MHz power 17733 control 0xa00 status 0xa00 PSS: 900MHz power 15773 control 0x900 status 0x900 PSS: 800MHz power 13835 control 0x800 status 0x800 TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_ssdt TEST: Entering pci_rom_probe CBFS @ 200200 size 5ffe00 CBFS: 'Master Header Locator' located CBFS at [200200:800000) CBFS: Locating 'pci10de,128b.rom' CBFS: Checking offset 0 CBFS: File @ offset 0 size 20 CBFS: Unmatched 'cbfs master header' at 0 CBFS: Checking offset 80 CBFS: File @ offset 80 size 44a4 CBFS: Unmatched 'fallback/romstage' at 80 CBFS: Checking offset 45c0 CBFS: File @ offset 45c0 size 19800 CBFS: Unmatched 'cpu_microcode_blob.bin' at 45c0 CBFS: Checking offset 1de40 CBFS: File @ offset 1de40 size f868 CBFS: Unmatched 'fallback/ramstage' at 1de40 CBFS: Checking offset 2d700 CBFS: File @ offset 2d700 size 3dd CBFS: Unmatched 'config' at 2d700 CBFS: Checking offset 2db40 CBFS: File @ offset 2db40 size 2b8 CBFS: Unmatched 'revision' at 2db40 CBFS: Checking offset 2de40 CBFS: File @ offset 2de40 size 368 CBFS: Unmatched 'cmos_layout.bin' at 2de40 CBFS: Checking offset 2e200 CBFS: File @ offset 2e200 size 25ca CBFS: Unmatched 'fallback/dsdt.aml' at 2e200 CBFS: Checking offset 30840 CBFS: File @ offset 30840 size 410038 CBFS: Unmatched 'img/uefi' at 30840 CBFS: Checking offset 4408c0 CBFS: File @ offset 4408c0 size 109f0 CBFS: Unmatched 'fallback/payload' at 4408c0 CBFS: Checking offset 451300 CBFS: File @ offset 451300 size 639 CBFS: Unmatched 'payload_config' at 451300 CBFS: Checking offset 451980 CBFS: File @ offset 451980 size 100 CBFS: Unmatched 'payload_revision' at 451980 CBFS: Checking offset 451b00 CBFS: File @ offset 451b00 size 5e298 CBFS: Unmatched '' at 451b00 CBFS: Checking offset 4afdc0 CBFS: File @ offset 4afdc0 size 120000 CBFS: Unmatched 'fsp.bin' at 4afdc0 CBFS: Checking offset 5cfe00 CBFS: File @ offset 5cfe00 size 2fa18 CBFS: Unmatched '' at 5cfe00 CBFS: Checking offset 5ff840 CBFS: File @ offset 5ff840 size 580 CBFS: Unmatched 'bootblock' at 5ff840 CBFS: Checking offset 5ffe00 CBFS: 'pci10de,128b.rom' not found. Option ROM address for PCI: 04:00.0 = fb000000 PCI expansion ROM, signature 0xbeef, INIT size 0x0000, data ptr 0xffff Incorrect expansion ROM header signature beef PCI: 04:00.0: Missing PCI Option ROM TEST: Entering pci_rom_ssdt ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * MADT IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x08 IOAPIC: Dumping registers reg 0x0000: 0x08000000 reg 0x0001: 0x00170020 reg 0x0002: 0x00170020 IOAPIC: Initializing IOAPIC at 0xfec01000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x09 IOAPIC: Dumping registers reg 0x0000: 0x09000000 reg 0x0001: 0x00170020 reg 0x0002: 0x00000000 ACPI: added table 4/32, length now 52 current = 7ed42290 TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables ACPI: * DMAR ACPI: added table 5/32, length now 56 TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables TEST: Entering pci_rom_write_acpi_tables ACPI: done. ACPI tables: 21264 bytes. smbios_write_tables: 7ed3c000 SMBIOS: Unknown CPU SMBIOS tables: 424 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 7108 Writing coreboot table at 0x7ed61000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-000000007ed3bfff: RAM 4. 000000007ed3c000-000000007eeb3fff: CONFIGURATION TABLES 5. 000000007eeb4000-000000007effdfff: RAMSTAGE 6. 000000007effe000-000000007effffff: CONFIGURATION TABLES 7. 000000007f000000-000000008fffffff: RESERVED 8. 00000000fbffc000-00000000fbffdfff: RESERVED 9. 00000000feb00000-00000000feb0ffff: RESERVED 10. 00000000feb80000-00000000fedfffff: RESERVED 11. 00000000fef00000-00000000ffffffff: RESERVED 12. 0000000100000000-000000017fffffff: RAM Manufacturer: ef SF: Detected W25Q128_V with sector size 0x1000, total 0x1000000 SF size 0x1000000 does not correspond to CONFIG_ROM_SIZE 0x800000!! CBFS @ 200200 size 5ffe00 CBFS: 'Master Header Locator' located CBFS at [200200:800000) FMAP: Found "FLASH" version 1.1 at 200000. FMAP: base = ff800000 size = 800000 #areas = 3 Wrote coreboot table at: 7ed61000, 0x2dc bytes, checksum cafd coreboot table: 756 bytes. IMD ROOT 0. 7efff000 00001000 IMD SMALL 1. 7effe000 00001000 RAMSTAGE 2. 7eeb3000 0014b000 57a9e100 3. 7ed69000 00149958 COREBOOT 4. 7ed61000 00008000 ACPI 5. 7ed3d000 00024000 SMBIOS 6. 7ed3c000 00000800 IMD small region: IMD ROOT 0. 7effec00 00000400 HOB 1. 7effebe0 00000001 57a9e000 2. 7effebc0 00000018 COREBOOTFWD 3. 7effeb80 00000028 TEST: Entering dev_finalize_chips TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_report_time BS: BS_WRITE_TABLES times (us): entry 1071428 run 1980596 exit 6302 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_payload_load CBFS @ 200200 size 5ffe00 CBFS: 'Master Header Locator' located CBFS at [200200:800000) CBFS: Locating 'fallback/payload' CBFS: Checking offset 0 CBFS: File @ offset 0 size 20 CBFS: Unmatched 'cbfs master header' at 0 CBFS: Checking offset 80 CBFS: File @ offset 80 size 44a4 CBFS: Unmatched 'fallback/romstage' at 80 CBFS: Checking offset 45c0 CBFS: File @ offset 45c0 size 19800 CBFS: Unmatched 'cpu_microcode_blob.bin' at 45c0 CBFS: Checking offset 1de40 CBFS: File @ offset 1de40 size f868 CBFS: Unmatched 'fallback/ramstage' at 1de40 CBFS: Checking offset 2d700 CBFS: File @ offset 2d700 size 3dd CBFS: Unmatched 'config' at 2d700 CBFS: Checking offset 2db40 CBFS: File @ offset 2db40 size 2b8 CBFS: Unmatched 'revision' at 2db40 CBFS: Checking offset 2de40 CBFS: File @ offset 2de40 size 368 CBFS: Unmatched 'cmos_layout.bin' at 2de40 CBFS: Checking offset 2e200 CBFS: File @ offset 2e200 size 25ca CBFS: Unmatched 'fallback/dsdt.aml' at 2e200 CBFS: Checking offset 30840 CBFS: File @ offset 30840 size 410038 CBFS: Unmatched 'img/uefi' at 30840 CBFS: Checking offset 4408c0 CBFS: File @ offset 4408c0 size 109f0 CBFS: Found @ offset 4408c0 size 109f0 Checking segment from ROM address 0xffe40af8 Payload being loaded at below 1MiB without region being marked as RAM usable. Checking segment from ROM address 0xffe40b14 Loading segment from ROM address 0xffe40af8 code (compression=1) New segment dstaddr 0x000e06c0 memsize 0x1f940 srcaddr 0xffe40b30 filesize 0x109b8 Loading Segment: addr: 0x000e06c0 memsz: 0x000000000001f940 filesz: 0x00000000000109b8 using LZMA [ 0x000e06c0, 00100000, 0x00100000) <- ffe40b30 Loading segment from ROM address 0xffe40b14 Entry Point 0x000fd258 Loaded segments TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks TEST: Entering bs_sample_time TEST: Entering bs_report_time BS: BS_PAYLOAD_LOAD times (us): entry 6302 run 233479 exit 6303 TEST: Entering bs_sample_time TEST: Entering bs_call_callbacks FspNotify(EnumInitPhaseReadyToBoot) fsp_header_ptr: ffeb0094 FSP Header Version: 1 FSP Revision: 3.3 FSP Got Notification. Notification Value : 0x00000040 FSP Ready To Boot ... Install PPI: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F756453 Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F7598BD IioLateInitialize ReadyToBoot Callback OnExitBootServices.. IioInit Late Secure the Platform (TXT).. Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F72F2E6 Hiding ME Devices Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F73C929 MP ReadyToBootEvent() :: Set LOCK bit in PACKAGE_RAPL_LIMIT with value = 800781B0 :: Set LOCK bit in CSR_SAPMCTL with value = B8002026 :: Set LOCK bit in CSR_DRAM_PLANE_POWER_LIMIT with value = 80000000 :: Set LOCK bit in P_STATE_LIMITS_PCU_FUN0_REG with value = 800000FF :: Set LOCK bit in CSR_DESIRED_CORES_PCU_FUN1_REG with value = 80000000 Done Write MAILBOX_BIOS_CMD_WRITE_PCU_MISC_CONFIG, data = 2, SETUP Pl2SafetyNetEnable = 1 :: Read BIOS_MAILBOX_DATA_PCU_FUN1_REG back, data = 2 :: Debug PpmSetBiosInitDone Read Data: 00000606 Detected 12 CPU threads Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F6E73CF PciERWORegInit() Start PciERWORegInit() End ThermalLockDown() Start ThermalLockdown() - ThermalBaseB = 00000004 ThermalBaseB not set!! BDX-DE MCP PMSYNC enable = 1 InstallPchThermalLevelsProtocol() ThermalLockDown() End Locking Down TCO PchInitBeforeBoot() End ConfigureXhciAtBoot() Start ConfigureXhciAtBoot() End Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F6D9797 [HECI-0] VID-DID: 8086-8C3A [SPS] Sending HMRFPO_LOCK to ME [HECI-0] Send msg: 80040007 [HECI-0] Got msg: 80180007 Notify: PPI Guid: 7CE88FB3-4BD7-4679-87A8-A8D8DEE50D2B, Peim notify entry point: 7F6D9C3E [HECI-0] VID-DID: 8086-8C3A [SPS] Sending END_OF_POST to ME [HECI-0] Send msg: 80040007 [HECI-0] Got msg: 80040007 [SPS] Disabling Global Reset capability [SPS] Disabling ME functions: 0 (HECI-1) 1 (HECI-2) 2 (IDE-R) 3 (KT) FSP Notification Handler Returns : 0x00000000 ============= PEIM FSP is Completed ============= Returned from FspNotify(EnumInitPhaseReadyToBoot) TEST: Entering bs_sample_time TEST: Entering bs_payload_boot Jumping to boot code at 000fd258(7ed61000) CPU0: stack: 7eef4000 - 7eef5000, lowest used address 7eef4adc, stack used: 1316 bytes SeaBIOS (version rel-1.12.1-0-ga5cab58-dirty-20191207_141949-adlink2-Express-KL) BUILD: gcc: (coreboot toolchain v ) 8.3.0 binutils: (GNU Binutils) 2.32 Found mainboard Intel Camelback Mountain CRB Relocating init from 0x000e1d20 to 0x7ecef560 (size 51712) Found CBFS header at 0xffa00238 multiboot: eax=7eed3ac0, ebx=7eed3a74 Found 23 PCI devices (max PCI bus is 04) Copying SMBIOS entry point from 0x7ed3c000 to 0x000f6280 Copying ACPI RSDP from 0x7ed3d000 to 0x000f6250 Using pmtimer, ioport 0x408 Scan for VGA option rom Turning on vga text mode console SeaBIOS (version rel-1.12.1-0-ga5cab58-dirty-20191207_141949-adlink2-Express-KL) XHCI init on dev 00:14.0: regs @ 0xfb900000, 21 ports, 32 slots, 32 byte contexts XHCI protocol USB 2.00, 8 ports (offset 1), def 3001 XHCI protocol USB 3.00, 6 ports (offset 16), def 1000 XHCI extcap 0xc1 @ 0xfb908040 XHCI extcap 0xc0 @ 0xfb908070 XHCI extcap 0x1 @ 0xfb90846c EHCI init on dev 00:1d.0 (regs=0xfb914020) WARNING - Timeout at i8042_flush:71! AHCI controller at 00:1f.2, iobase 0xfb913000, irq 5 Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0 AHCI/0: Set transfer mode to UDMA-6 AHCI/0: registering: "AHCI/0: WDC WD5000AZLX-00CL5A0 ATA-9 Hard-Disk (465 GiBytes)" Found 0 lpt ports Found 1 serial ports Searching bootorder for: /rom@img/uefi XHCI no devices found USB keyboard initialized WARNING - Timeout at ehci_wait_td:517! ehci pipe=0x7ecec300 cur=7eccfdc0 tok=00000c00 next=7ecced40 td=0x7ecced40 status=80e80 WARNING - Timeout at ehci_waittick:178! Failure on hub port 3 reset WARNING - Timeout at ehci_wait_td:517! ehci pipe=0x7ecec300 cur=7eccfdc0 tok=00000000 next=7ecced40 td=0x7ecced40 status=80e80 WARNING - Timeout at ehci_waittick:165! Failure on hub port 3 disconnect WARNING - Timeout at ehci_wait_td:517! ehci pipe=0x7ecec300 cur=7eccfdc0 tok=00000000 next=7eccfd40 td=0x7eccfd40 status=80e80 WARNING - Timeout at ehci_waittick:165! Failure on hub port 2 detect WARNING - Timeout at ehci_wait_td:517! ehci pipe=0x7ecec300 cur=7eccfdc0 tok=00000000 next=7ecd0d40 td=0x7ecd0d40 status=80e80 WARNING - Timeout at ehci_waittick:165! Failure on hub port 1 detect Initialized USB HUB (1 ports used) WARNING - Timeout at ehci_waittick:165! All threads complete. Scan for option roms Press ESC for boot menu. Searching bootorder for: HALT drive 0x000f61e0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=976773168 Space available for UMB: c0000-ed000, f5aa0-f61e0 Returned 188416 bytes of ZoneHigh e820 map has 10 items: 0: 0000000000000000 - 000000000009fc00 = 1 RAM 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED 3: 0000000000100000 - 000000007ed2a000 = 1 RAM 4: 000000007ed2a000 - 0000000090000000 = 2 RESERVED 5: 00000000fbffc000 - 00000000fbffe000 = 2 RESERVED 6: 00000000feb00000 - 00000000feb10000 = 2 RESERVED 7: 00000000feb80000 - 00000000fee00000 = 2 RESERVED 8: 00000000fef00000 - 0000000100000000 = 2 RESERVED 9: 0000000100000000 - 0000000180000000 = 1 RAM enter handle_19: NULL Booting from Hard Disk... Booting from 0000:7c00