Index: svn/src/arch/i386/boot/acpi.c
===================================================================
--- svn.orig/src/arch/i386/boot/acpi.c
+++ svn/src/arch/i386/boot/acpi.c
@@ -212,6 +212,7 @@ void acpi_create_ssdt_generator(acpi_hea
 
 int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic)
 {
+	memset((void *)lapic, 0, sizeof(acpi_srat_lapic_t));
         lapic->type=0;
         lapic->length=sizeof(acpi_srat_lapic_t);
         lapic->flags=1;
@@ -284,7 +285,7 @@ void acpi_create_slit(acpi_slit_t *slit)
         header->length = sizeof(acpi_slit_t);
         header->revision = 1;
 
-//        current = acpi_fill_slit(current);
+        current = acpi_fill_slit(current);
 
         /* recalculate length */
         header->length= current - (unsigned long)slit;
Index: svn/src/northbridge/amd/amdk8/northbridge.c
===================================================================
--- svn.orig/src/northbridge/amd/amdk8/northbridge.c
+++ svn/src/northbridge/amd/amdk8/northbridge.c
@@ -896,6 +896,11 @@ static uint32_t hoist_memory(unsigned lo
 }
 #endif
 
+#if HAVE_HIGH_TABLES==1
+#define HIGH_TABLES_SIZE 64	// maximum size of high tables in KB
+extern uint64_t high_tables_base, high_tables_size;
+#endif
+
 static void pci_domain_set_resources(device_t dev)
 {
 #if CONFIG_PCI_64BIT_PREF_MEM == 1
@@ -1096,8 +1101,18 @@ static void pci_domain_set_resources(dev
 		}
 		ram_resource(dev, (idx | i), basek, sizek);
 		idx += 0x10;
+#if HAVE_HIGH_TABLES==1
+		printk_debug("%d: mmio_basek=%08lx, basek=%08x, limitk=%08x\n",
+			     i, mmio_basek, basek, limitk);
+		if (i==0) {
+		/* Leave some space for ACPI, PIRQ and MP tables */
+			high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
+			high_tables_size = HIGH_TABLES_SIZE * 1024;
+		}
+#endif
 	}
 	assign_resources(&dev->link[0]);
+
 }
 
 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
Index: svn/src/northbridge/amd/amdk8/amdk8_util.asl
===================================================================
--- /dev/null
+++ svn/src/northbridge/amd/amdk8/amdk8_util.asl
@@ -0,0 +1,315 @@
+/*
+ * Copyright 2005 AMD
+ */
+
+//AMD k8 util for BUSB and res range
+
+    Scope (\_SB)
+    {
+
+        Name (OSTB, Ones)
+        Method (OSTP, 0, NotSerialized)
+        {
+            If (LEqual (^OSTB, Ones))
+            {
+                Store (0x00, ^OSTB)
+            }
+
+            Return (^OSTB)
+        }
+
+       Method (SEQL, 2, Serialized)
+        {
+            Store (SizeOf (Arg0), Local0)
+            Store (SizeOf (Arg1), Local1)
+            If (LNot (LEqual (Local0, Local1))) { Return (Zero) }
+
+            Name (BUF0, Buffer (Local0) {})
+            Store (Arg0, BUF0)
+            Name (BUF1, Buffer (Local0) {})
+            Store (Arg1, BUF1)
+            Store (Zero, Local2)
+            While (LLess (Local2, Local0))
+            {
+                Store (DerefOf (Index (BUF0, Local2)), Local3)
+                Store (DerefOf (Index (BUF1, Local2)), Local4)
+                If (LNot (LEqual (Local3, Local4))) { Return (Zero) }
+
+                Increment (Local2)
+            }
+
+            Return (One)
+        }
+
+
+        Method (DADD, 2, NotSerialized)
+        {
+                Store( Arg1, Local0)
+                Store( Arg0, Local1)
+                Add( ShiftLeft(Local1,16), Local0, Local0)
+                Return (Local0)
+        }
+
+
+	Method (GHCE, 1, NotSerialized) // check if the HC enabled
+	{
+                Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
+                if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) }
+                Else { Return (0x00) }
+	}
+
+        Method (GHCN, 1, NotSerialized) // get the node num for the HC
+        {
+                Store (0x00, Local0)
+                Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
+		Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0)
+		Return (Local0)
+        }
+
+        Method (GHCL, 1, NotSerialized) // get the link num on node for the HC
+        {
+                Store (0x00, Local0)
+                Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
+                Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0)
+                Return (Local0)
+        }
+
+        Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC
+        {
+                Store (0x00, Local0)
+                Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1)
+		Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0
+		Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0
+                Store (And (ShiftRight( Local1, Local2), 0xff), Local0)
+                Return (Local0)
+        }
+
+        Method (GBUS, 2, NotSerialized)
+        {
+            Store (0x00, Local0)
+            While (LLess (Local0, 0x04))
+            {
+                Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
+                If (LEqual (And (Local1, 0x03), 0x03))
+                {
+                    If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
+                    {
+                        If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
+                        {
+                            Return (ShiftRight (And (Local1, 0x00FF0000), 0x10))
+                        }
+                    }
+                }
+
+                Increment (Local0)
+            }
+
+            Return (0x00)
+        }
+
+        Method (GWBN, 2, NotSerialized)
+        {
+            Name (BUF0, ResourceTemplate ()
+            {
+                WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+                    0x0000, // Address Space Granularity
+                    0x0000, // Address Range Minimum
+                    0x0000, // Address Range Maximum
+                    0x0000, // Address Translation Offset
+                    0x0000,,,)
+            })
+            CreateWordField (BUF0, 0x08, BMIN)
+            CreateWordField (BUF0, 0x0A, BMAX)
+            CreateWordField (BUF0, 0x0E, BLEN)
+            Store (0x00, Local0)
+            While (LLess (Local0, 0x04))
+            {
+                Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
+                If (LEqual (And (Local1, 0x03), 0x03))
+                {
+                    If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
+                    {
+                        If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
+                        {
+                            Store (ShiftRight (And (Local1, 0x00FF0000), 0x10), BMIN)
+                            Store (ShiftRight (Local1, 0x18), BMAX)
+                            Subtract (BMAX, BMIN, BLEN)
+                            Increment (BLEN)
+                            Return (RTAG (BUF0))
+                        }
+                    }
+                }
+
+                Increment (Local0)
+            }
+
+            Return (RTAG (BUF0))
+        }
+
+        Method (GMEM, 2, NotSerialized)
+        {
+            Name (BUF0, ResourceTemplate ()
+            {
+                DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+                    0x00000000, // Address Space Granularity
+                    0x00000000, // Address Range Minimum
+                    0x00000000, // Address Range Maximum
+                    0x00000000, // Address Translation Offset
+                    0x00000000,,,
+                    , AddressRangeMemory, TypeStatic)
+            })
+            CreateDWordField (BUF0, 0x0A, MMIN)
+            CreateDWordField (BUF0, 0x0E, MMAX)
+            CreateDWordField (BUF0, 0x16, MLEN)
+            Store (0x00, Local0)
+            Store (0x00, Local4)
+	    Store (0x00, Local3)
+            While (LLess (Local0, 0x10))
+            {
+                Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1)
+                Increment (Local0)
+                Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2)
+                If (LEqual (And (Local1, 0x03), 0x03))
+                {
+                    If (LEqual (Arg0, And (Local2, 0x07)))
+                    {
+                        If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
+                        {
+                            Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN)
+                            Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX)
+                            Or (MMAX, 0xFFFF, MMAX)
+                            Subtract (MMAX, MMIN, MLEN)
+
+                            If (Local4)
+                            {
+                                Concatenate (RTAG (BUF0), Local3, Local5)
+                               	Store (Local5, Local3)
+                            }
+                            Else
+                            {
+                                If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
+                                {
+                                    Store (\_SB.PCI0.TOM1, MMIN)
+                                    Subtract (MMAX, MMIN, MLEN)
+                                    Increment (MLEN)
+                                }
+
+                                Store (RTAG (BUF0), Local3)
+                            }
+
+                            Increment (Local4)
+                        }
+                    }
+                }
+
+                Increment (Local0)
+            }
+
+            If (LNot (Local4))
+            {
+                Store (BUF0, Local3)
+            }
+
+            Return (Local3)
+        }
+
+        Method (GIOR, 2, NotSerialized)
+        {
+            Name (BUF0, ResourceTemplate ()
+            {
+                DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+                    0x00000000, // Address Space Granularity
+                    0x00000000, // Address Range Minimum
+                    0x00000000, // Address Range Maximum
+                    0x00000000, // Address Translation Offset
+                    0x00000000,,,
+                    , TypeStatic)
+            })
+            CreateDWordField (BUF0, 0x0A, PMIN)
+            CreateDWordField (BUF0, 0x0E, PMAX)
+            CreateDWordField (BUF0, 0x16, PLEN)
+            Store (0x00, Local0)
+            Store (0x00, Local4)
+	    Store (0x00, Local3)
+            While (LLess (Local0, 0x08))
+            {
+                Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1)
+                Increment (Local0)
+                Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2)
+                If (LEqual (And (Local1, 0x03), 0x03))
+                {
+                    If (LEqual (Arg0, And (Local2, 0x07)))
+                    {
+                        If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
+                        {
+                            Store (And (Local1, 0x01FFF000), PMIN)
+                            Store (And (Local2, 0x01FFF000), PMAX)
+                            Or (PMAX, 0x0FFF, PMAX)
+                            Subtract (PMAX, PMIN, PLEN)
+                            Increment (PLEN)
+
+                            If (Local4)
+                            {
+                                Concatenate (RTAG (BUF0), Local3, Local5)
+       	                        Store (Local5, Local3)
+                            }
+                            Else
+                            {
+                                If (LGreater (PMAX, PMIN))
+                                {
+                                    If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
+                                    {
+                                        Store (0x0D00, PMIN)
+                                        Subtract (PMAX, PMIN, PLEN)
+                                        Increment (PLEN)
+                                    }
+
+                                    Store (RTAG (BUF0), Local3)
+                                    Increment (Local4)
+                                }
+
+                                If (And (Local1, 0x10))
+                                {
+                                    Store (0x03B0, PMIN)
+                                    Store (0x03DF, PMAX)
+                                    Store (0x30, PLEN)
+                                    If (Local4)
+                                    {
+                                        Concatenate (RTAG (BUF0), Local3, Local5)
+                                        Store (Local5, Local3)
+                                    }
+                                    Else
+                                    {
+                                        Store (RTAG (BUF0), Local3)
+                                    }
+                                }
+                            }
+
+                            Increment (Local4)
+                        }
+                    }
+                }
+
+                Increment (Local0)
+            }
+
+            If (LNot (Local4))
+            {
+                Store (RTAG (BUF0), Local3)
+            }
+
+            Return (Local3)
+        }
+
+        Method (RTAG, 1, NotSerialized)
+        {
+            Store (Arg0, Local0)
+            Store (SizeOf (Local0), Local1)
+            Subtract (Local1, 0x02, Local1)
+            Multiply (Local1, 0x08, Local1)
+            CreateField (Local0, 0x00, Local1, RETB)
+            Store (RETB, Local2)
+            Return (Local2)
+        }
+    }
+
Index: svn/src/southbridge/nvidia/ck804/ck804_lpc.c
===================================================================
--- svn.orig/src/southbridge/nvidia/ck804/ck804_lpc.c
+++ svn/src/southbridge/nvidia/ck804/ck804_lpc.c
@@ -165,7 +165,6 @@ static void rom_dummy_write(device_t dev
 		pci_write_config8(dev, 0x6d, new);
 }
 
-#if 0
 static void enable_hpet(struct device *dev)
 {
 	unsigned long hpet_address;
@@ -174,7 +173,8 @@ static void enable_hpet(struct device *d
 	hpet_address = pci_read_config32(dev, 0x44) & 0xfffffffe;
 	printk_debug("Enabling HPET @0x%x\n", hpet_address);
 }
-#endif
+
+unsigned pm_base=0;
 
 static void lpc_init(device_t dev)
 {
@@ -183,6 +183,9 @@ static void lpc_init(device_t dev)
 
 	lpc_common_init(dev);
 
+	pm_base = pci_read_config32(dev, 0x60) & 0xff00;
+	printk_info("%s: pm_base = %lx \n", __func__, pm_base);
+
 #if CK804_CHIP_REV==1
 	if (dev->bus->secondary != 1)
 		return;
@@ -251,7 +254,7 @@ static void lpc_init(device_t dev)
 	isa_dma_init();
 
 	/* Initialize the High Precision Event Timers (HPET). */
-	/* enable_hpet(dev); */
+	enable_hpet(dev);
 
 	rom_dummy_write(dev);
 }
Index: svn/src/northbridge/amd/amdk8/amdk8_acpi.c
===================================================================
--- svn.orig/src/northbridge/amd/amdk8/amdk8_acpi.c
+++ svn/src/northbridge/amd/amdk8/amdk8_acpi.c
@@ -40,6 +40,7 @@ acknowledgement of AMD's proprietary rig
 #include <console/console.h>
 #include <string.h>
 #include <arch/acpi.h>
+#include <arch/acpigen.h>
 #include <device/pci.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
@@ -127,7 +128,7 @@ void set_srat_mem(void *gp, struct devic
 	basek = resk(res->base);
 	sizek = resk(res->size);
 
-	printk_debug("set_srat_mem: dev %s, res->index=%04x startk=%08x, sizek=%08x\n",
+	printk_debug("set_srat_mem: dev %s, res->index=%04lx startk=%08lx, sizek=%08lx\n",
 		     dev_path(dev), res->index, basek, sizek);
 	/*
 	 * 0-640K must be on node 0
Index: svn/src/arch/i386/include/arch/acpi.h
===================================================================
--- svn.orig/src/arch/i386/include/arch/acpi.h
+++ svn/src/arch/i386/include/arch/acpi.h
@@ -293,7 +293,8 @@ typedef struct acpi_facs {
 unsigned long write_acpi_tables(unsigned long addr);
 unsigned long acpi_fill_madt(unsigned long current);
 unsigned long acpi_fill_mcfg(unsigned long current);
-unsigned long acpi_fill_srat(unsigned long current); 
+unsigned long acpi_fill_srat(unsigned long current);
+unsigned long acpi_fill_slit(unsigned long current);
 unsigned long acpi_fill_ssdt_generator(unsigned long current, char *oem_table_id);
 void acpi_create_ssdt_generator(acpi_header_t *ssdt, char *oem_table_id);
 void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt);
Index: svn/src/southbridge/nvidia/ck804/ck804_fadt.c
===================================================================
--- /dev/null
+++ svn/src/southbridge/nvidia/ck804/ck804_fadt.c
@@ -0,0 +1,146 @@
+/*
+ * ACPI - create the Fixed ACPI Description Tables (FADT)
+ * (C) Copyright 2005 Stefan Reinauer <stepan@openbios.org>
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+
+extern unsigned pm_base;	/* pm_base should be set in sb acpi */
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+
+	printk_debug("pm_base: 0x%04x\n", pm_base);
+
+	/* Prepare the header */
+	memset((void *)fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+#ifdef LONG_FADT
+	header->length = 244;
+#else
+	header->length = 0x74;
+#endif
+	header->revision = 1;
+	memcpy(header->oem_id, "CORE  ", 6);
+	memcpy(header->oem_table_id, "CB-FADT ", 8);
+	memcpy(header->asl_compiler_id, "IASL", 4);
+	header->asl_compiler_revision = 0;
+
+	fadt->firmware_ctrl = (u32)facs;
+	fadt->dsdt = (u32)dsdt;
+	// 3=Workstation,4=Enterprise Server, 7=Performance Server
+	fadt->preferred_pm_profile = 0;
+	fadt->sci_int = 9;
+	// disable system management mode by setting to 0:
+	fadt->smi_cmd = 0; // NVIDIA has 0x842E
+	fadt->acpi_enable = 0;
+	fadt->acpi_disable = 0;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = 0x0;
+
+	fadt->pm1a_evt_blk = pm_base;
+	fadt->pm1b_evt_blk = 0x0000;
+	fadt->pm1a_cnt_blk = pm_base + 0x04;
+	fadt->pm1b_cnt_blk = 0x0000;
+	fadt->pm2_cnt_blk = pm_base + 0x1c;
+	fadt->pm_tmr_blk = pm_base + 0x08;
+	fadt->gpe0_blk = pm_base + 0x20;
+	fadt->gpe1_blk = 0x0000;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = 0;
+	fadt->p_lvl2_lat = 0xffff;
+	fadt->p_lvl3_lat = 0xffff;
+	fadt->flush_size = 0;
+	fadt->flush_stride = 0;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 0;
+	fadt->day_alrm = 0x7d;
+	fadt->mon_alrm = 0x7e;
+	fadt->century = 0x32;
+	fadt->iapc_boot_arch = 0;
+	fadt->flags = 0xa5;
+
+#ifdef LONG_FADT
+	fadt->res2 = 0;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0x0;
+
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pm_base;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 4;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pm_base + 4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 2;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 0;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = 0x0;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pm_base + 0x08;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 32;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pm_base + 0x20;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 64;
+	fadt->x_gpe1_blk.bit_offset = 16;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = pm_base + 0xb0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+#endif
+	header->checksum = acpi_checksum((void *)fadt, header->length);
+}
Index: svn/src/southbridge/nvidia/ck804/Config.lb
===================================================================
--- svn.orig/src/southbridge/nvidia/ck804/Config.lb
+++ svn/src/southbridge/nvidia/ck804/Config.lb
@@ -1,3 +1,5 @@
+uses HAVE_ACPI_TABLES
+
 config chip.h
 driver ck804.o
 driver ck804_usb.o
@@ -12,3 +14,7 @@ driver ck804_pci.o
 driver ck804_pcie.o
 driver ck804_ht.o
 object ck804_reset.o
+
+if HAVE_ACPI_TABLES
+	object ck804_fadt.o
+end
