This is the dtc patches again + the tree mods needed to make it compile. 
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

Index: util/dtc/dtc-lexer.l
===================================================================
--- util/dtc/dtc-lexer.l	(revision 367)
+++ util/dtc/dtc-lexer.l	(working copy)
@@ -45,12 +45,15 @@
 char *code = 0;
 
 YY_BUFFER_STATE bstack = NULL;
+int line;
 
 void
 switchin(FILE *f){
 	YY_BUFFER_STATE b;
 	bstack = YY_CURRENT_BUFFER;
 	b = yy_create_buffer(f, 8192);
+	line = yylineno;
+	yylineno = 1;
 	yy_switch_to_buffer(b);
 	
 }
@@ -58,6 +61,7 @@
 void
 switchback(void){
 		yy_switch_to_buffer(bstack);
+		yylineno = line;
 }
 %}
 
Index: util/dtc/flattree.c
===================================================================
--- util/dtc/flattree.c	(revision 367)
+++ util/dtc/flattree.c	(working copy)
@@ -104,8 +104,20 @@
 	return pathname;
 }
 
+char *toname(char *path, char *suffix){
+	char *ret = malloc(strlen(path) + strlen(suffix) + 1), *cp, *src;
+	for(cp = ret, src = path; *src; cp++, src++){
+		if (*src == '/')
+			*cp = '_';
+		else
+			*cp = *src;
+	}
+	cp = ret;
+	if (suffix)
+		strcat(cp, suffix);
+	return cp;
+}
 
-
 static void bin_emit_cell(void *e, cell_t val)
 {
 	struct data *dtbuf = e;
@@ -439,15 +451,17 @@
 		return;
 
 	cleanname = clean(p->name, 1);
-	fprintf(f, "\t.%s = {", cleanname);
+	fprintf(f, "\t.%s = ", cleanname);
 	free(cleanname);
-
+	fprintf(f, "0x%lx,\n", strtoul((char *)d.val, 0, 0));
+#if 0
 	/* sorry, but right now, u32 is all you get */
 	fprintf(f, "0");
 	for(i = 0; i < vallen; i++)
 		fprintf(f, "|(0x%02x<<%d)", d.val[i], (3-i)*8);
 
-	fprintf(f, "},\n");
+	fprintf(f, ",\n");
+#endif
 }
 
 static void linuxbios_emit_beginnode(void *e, char *label)
@@ -505,6 +519,7 @@
 	struct property *prop;
 	int ops_set = 0;
 	int is_root = 0;
+	char *configname;
 
 	fprintf(f, "struct device dev_%s = {\n", tree->label);
 	/* special case -- the root has a distinguished path */
@@ -513,6 +528,10 @@
 		fprintf(f, "\t.path =  { .type = DEVICE_PATH_ROOT },\n");
 	}
 
+	if (tree->config){
+		configname = clean(tree->label, 0);
+		printf("\t.device_configuration = &%s,\n", configname);
+	}
 	for_each_property(tree, prop) {
 		if (streq(prop->name, "pcidomain")){
 			fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI_DOMAIN,.u={.pci_domain={ .domain = %s }}},\n", 
@@ -640,7 +659,32 @@
 
 }
 
-	
+static void flatten_tree_emit_constructors(struct node *tree, struct emitter *emit,
+			 void *etarget, struct data *strbuf,
+			 struct version_info *vi)
+{
+	struct property *prop;
+	struct node *child;
+	/* find any/all properties with the name constructor */
+	for_each_config(tree, prop) {
+		if (streq(prop->name, "constructor")){
+			printf("\t%s,\n", prop->val.val);
+		}
+	}
+
+	for_each_property(tree, prop) {
+		if (streq(prop->name, "constructor")){
+			printf("\t%s,\n", prop->val.val);
+		}
+	}
+
+	for_each_child(tree, child) {
+		flatten_tree_emit_constructors(child, emit, etarget, strbuf, vi);
+	}
+
+
+}
+
 static void flatten_tree_emit_structdecls(struct node *tree, struct emitter *emit,
 			 void *etarget, struct data *strbuf,
 			 struct version_info *vi)
@@ -653,7 +697,8 @@
 	FILE *f = etarget;
 
 	if (tree->config){
-		treename = clean(tree->name, 0);
+//		treename = clean(tree->label, 0);
+		treename = toname(tree->config->label, "_config");
 		emit->beginnode(etarget, treename);
 
 
@@ -668,6 +713,8 @@
 			char *cleanname;
 			if (streq(prop->name, "name"))
 				seen_name_prop = 1;
+			if (streq(prop->name, "constructor")) /* this is special */
+				continue;
 			cleanname = clean(prop->name, 0);
 			fprintf(f, "\tu32 %s;\n", cleanname);
 			free(cleanname);
@@ -679,9 +726,26 @@
 		}
 #endif
 		emit->endnode(etarget, treename);
-		free(treename);
 	}
 
+	for_each_config(tree, prop) {
+		if (! streq(prop->name, "constructor")) /* this is special */
+			continue;
+		fprintf(f, "extern struct constructor %s[];\n", prop->val.val);
+	}
+
+	for_each_property(tree, prop) {
+		if (! streq(prop->name, "constructor")) /* this is special */
+			continue;
+		fprintf(f, "extern struct constructor %s[];\n", prop->val.val);
+	}
+
+	for_each_property(tree, prop) {
+		if (! streq(prop->name, "ops")) /* this is special */
+			continue;
+		fprintf(f, "extern struct device_operations %s;\n", prop->val.val);
+	}
+
 	for_each_child(tree, child) {
 		flatten_tree_emit_structdecls(child, emit, etarget, strbuf, vi);
 	}
@@ -695,7 +759,7 @@
 			 void *etarget, struct data *strbuf,
 			 struct version_info *vi)
 {
-	char *treename;
+	char *treename, *treelabel, *structname;
 
 	struct property *configprop, *dtsprop;
 	struct node *child;
@@ -724,8 +788,14 @@
 	  */
 
 	if (tree->config){
-		treename = clean(tree->name, 0);
-		emit->beginnode(etarget, treename);
+		treelabel = clean(tree->label, 0);
+		structname = toname(tree->config->label, "_config");
+		/* beginnode does not work here. 
+		  * the design of this code is wrong and must be fixed. 
+		  * the operator should take the node itself, not a string. 
+		  */
+		printf("struct %s %s = {\n", structname, treelabel);
+//		emit->beginnode(etarget, treename);
 #if 0
 		if (vi->flags & FTF_FULLPATH)
 			emit->string(etarget, tree->fullpath, 0);
@@ -736,6 +806,8 @@
 		for_each_config(tree, configprop) {
 			char *cleanname;
 			int found = 0;
+			if (streq(configprop->name, "constructor")) /* this is special */
+				continue;
 #if 0
 			cleanname = clean(configprop->name, 0);
 			fprintf(f, "\tu32 %s = \n", cleanname);
@@ -756,8 +828,7 @@
 			fprintf(f, "\tu8 %s[%d];\n", configprop->name, configprop->val.len);
 		}
 #endif
-		emit->endnode(etarget, treename);
-		free(treename);
+		emit->endnode(etarget, treelabel);
 	}
 /*
 	for_each_property(tree, prop) {
@@ -785,7 +856,6 @@
 
 }
 
-
 static void flatten_tree(struct node *tree, struct emitter *emit,
 			 void *etarget, struct data *strbuf,
 			 struct version_info *vi)
@@ -1208,9 +1278,7 @@
 	/* steps: emit all structs. Then emit the initializers, with the pointers to other structs etc. */
 
 	fix_next(bi->dt);
-	/* emit any includes that we need  -- TODO: ONLY ONCE PER TYPE*/
-	fprintf(f, "#include <device/device.h>\n#include <device/pci.h>\n");
-	flatten_tree_emit_includes(bi->dt, &linuxbios_emitter, f, &strbuf, vi);
+	fprintf(f, "#include <statictree.h>\n");
 	/* forward declarations */
 	for(next = first_node; next; next = next->next)
 		fprintf(f, "struct device dev_%s;\n", next->label);
@@ -1218,11 +1286,46 @@
 	/* emit the code, if any */
 	if (code)
 		fprintf(f, "%s\n", code);
+	flatten_tree_emit_structinits(bi->dt, &linuxbios_emitter, f, &strbuf, vi);
+	fprintf(f, "struct constructor *all_constructors[] = {\n");
+	flatten_tree_emit_constructors(bi->dt, &linuxbios_emitter, f, &strbuf, vi);
+	fprintf(f, "\t0\n};\n");
+	data_free(strbuf);
+	/* */
 
+}
 
+void dt_to_linuxbiosh(FILE *f, struct boot_info *bi, int version, int boot_cpuid_phys)
+{
+	struct version_info *vi = NULL;
+	int i;
+	struct data strbuf = empty_data;
+	char *symprefix = "dt";
+	extern char *code;
+	struct node *next;
+	extern struct node *first_node;
+
+	labeltree(bi->dt);
+
+	for (i = 0; i < ARRAY_SIZE(version_table); i++) {
+		if (version_table[i].version == version)
+			vi = &version_table[i];
+	}
+	if (!vi)
+		die("Unknown device tree blob version %d\n", version);
+
+	/* the root is special -- the parser gives it no name. We fix that here. 
+	  * fix in parser? 
+	  */
+	bi->dt->name  = bi->dt->label  = "root";
+	/* steps: emit all structs. Then emit the initializers, with the pointers to other structs etc. */
+
+	fix_next(bi->dt);
+	/* emit any includes that we need  -- TODO: ONLY ONCE PER TYPE*/
+	fprintf(f, "#include <device/device.h>\n#include <device/pci.h>\n");
+	flatten_tree_emit_includes(bi->dt, &linuxbios_emitter, f, &strbuf, vi);
+
 	flatten_tree_emit_structdecls(bi->dt, &linuxbios_emitter, f, &strbuf, vi);
-	flatten_tree_emit_structinits(bi->dt, &linuxbios_emitter, f, &strbuf, vi);
-	data_free(strbuf);
 	/* */
 
 }
Index: util/dtc/dtc.c
===================================================================
--- util/dtc/dtc.c	(revision 367)
+++ util/dtc/dtc.c	(working copy)
@@ -201,6 +201,8 @@
 		dt_to_C(outf, bi, outversion, boot_cpuid_phys);
 	} else if (streq(outform, "linuxbios") || streq(outform, "lb")) {
 		dt_to_linuxbios(outf, bi, outversion, boot_cpuid_phys);
+	} else if (streq(outform, "linuxbiosinclude") || streq(outform, "lbh")) {
+		dt_to_linuxbiosh(outf, bi, outversion, boot_cpuid_phys);
 	} else if (streq(outform, "null")) {
 		/* do nothing */
 	} else {
Index: util/dtc/dtc-parser.y
===================================================================
--- util/dtc/dtc-parser.y	(revision 367)
+++ util/dtc/dtc-parser.y	(working copy)
@@ -138,8 +138,13 @@
 		}  '{' proplist '}' ';' {
 			void	switchback(void);
 			switchback();
+			
 		}
-		')' ';' { $$ = $6}
+		')' ';' { 
+				/* convention: first property is labeled with path */
+				$6->label = strdup($3.val);
+				$$ = $6
+			}
 	|
 	;
 
Index: mainboard/emulation/qemu-x86/dts
===================================================================
--- mainboard/emulation/qemu-x86/dts	(revision 367)
+++ mainboard/emulation/qemu-x86/dts	(working copy)
@@ -18,43 +18,25 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 /{
-	config = "mainboard,emulation,qemu-x86";
 	enabled;
-
+	constructor = "qemuvga_constructors";
 	cpus {
 		enabled;
 	};
 	domain0 {
-		enabled;
-		config = "northbridge,intel,i440bxemulation";
+		/config/("northbridge/intel/i440bxemulation");
 		ops = "i440bxemulation_pcidomainops";
+		enabled;
 		pcidomain = "0";
 		device0,0 {
 			enabled;
 			pcipath = "0,0";
 		};
-/*		southbridge,intel,piix4{
-			pcipath = "0,0";
+		southbridge,intel,piix4{
+			/config/("southbridge/intel/i82371eb");
+			pcipath = "1,0";
 			enabled;
 		};
-*/
 	};
 
 };
-
-%%
-
-#include <southbridge/intel/i82371eb/config.h>
-extern struct constructor qemuvga_constructors[];
-
-struct mainboard_emulation_qemu_x86_config root = {
-	.nothing = 1,
-};
-
-struct northbridge_intel_i440bx_config domain0 = {
-	.ramsize = CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE,
-};
-
-struct constructor *all_constructors[] = {
-	i440bx_constructors, i82371eb_constructors, qemuvga_constructors, 0
-};
Index: mainboard/emulation/qemu-x86/Makefile
===================================================================
--- mainboard/emulation/qemu-x86/Makefile	(revision 367)
+++ mainboard/emulation/qemu-x86/Makefile	(working copy)
@@ -52,11 +52,15 @@
 
 $(obj)/mainboard/$(MAINBOARDDIR)/mainboard.o: $(obj)/mainboard/$(MAINBOARDDIR)/statictree.o
 
-$(obj)/mainboard/$(MAINBOARDDIR)/statictree.o: $(obj)/mainboard/$(MAINBOARDDIR)/statictree.c
+$(obj)/mainboard/$(MAINBOARDDIR)/statictree.o: $(obj)/mainboard/$(MAINBOARDDIR)/statictree.c $(obj)/statictree.h
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
-	$(Q)$(CC) $(CFLAGS) $(LINUXBIOSINCLUDE) -c -o $@ $<
+	$(Q)$(CC) $(INITCFLAGS) $(LINUXBIOSINCLUDE) -c -o $@ $<
 
-$(obj)/mainboard/$(MAINBOARDDIR)/statictree.c: $(src)/mainboard/$(MAINBOARDDIR)/dts $(obj)/util/dtc/dtc
+$(obj)/statictree.h: $(src)/mainboard/$(MAINBOARDDIR)/dts $(obj)/util/dtc/dtc
+	$(Q)printf "  DTC (static.h)     $(subst $(shell pwd)/,,$(@))\n"
+	$(Q)$(obj)/util/dtc/dtc -O lbh mainboard/$(MAINBOARDDIR)/dts > $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/statictree.c: $(src)/mainboard/$(MAINBOARDDIR)/dts $(obj)/util/dtc/dtc $(obj)/statictree.h
 	$(Q)printf "  DTC     $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(obj)/util/dtc/dtc -O lb mainboard/$(MAINBOARDDIR)/dts > $@
 
Index: southbridge/amd/cs5536/cs5536.c
===================================================================
--- southbridge/amd/cs5536/cs5536.c	(revision 0)
+++ southbridge/amd/cs5536/cs5536.c	(revision 0)
@@ -0,0 +1,657 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <types.h>
+#include <lib.h>
+#include <console.h>
+#include <post_code.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <msr.h>
+#include <io.h>
+#include <amd_geodelx.h>
+#include <cpu.h>
+#include <device/pci_ids.h>
+#include <statictree.h>
+#include "cs5536.h"
+
+extern void setup_i8259(void);
+
+struct msrinit {
+	u32 msrnum;
+	msr_t msr;
+};
+
+/*	Master Configuration Register for Bus Masters.*/
+struct msrinit SB_MASTER_CONF_TABLE[] = {
+	{USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}},
+	{ATA_SB_GLD_MSR_CONF,  {.hi = 0,.lo = 0x00048f000}},
+	{AC97_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}},
+	{MDD_SB_GLD_MSR_CONF,  {.hi = 0,.lo = 0x00000f000}},
+	{0, {0, 0}}
+};
+
+/*	5536 Clock Gating*/
+struct msrinit CS5536_CLOCK_GATING_TABLE[] = {
+	/* MSR		  Setting*/
+	{GLIU_SB_GLD_MSR_PM,  {.hi = 0,.lo = 0x000000004}},
+	{GLPCI_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}},
+	{GLCP_SB_GLD_MSR_PM,  {.hi = 0,.lo = 0x000000004}},
+	{MDD_SB_GLD_MSR_PM,   {.hi = 0,.lo = 0x050554111}},	/*  SMBus clock gating errata (PBZ 2226 & SiBZ 3977) */
+	{ATA_SB_GLD_MSR_PM,   {.hi = 0,.lo = 0x000000005}},
+	{AC97_SB_GLD_MSR_PM,  {.hi = 0,.lo = 0x000000005}},
+	{0, {0, 0}}
+};
+
+struct acpiinit {
+	u16 ioreg;
+	u32 regdata;
+};
+
+struct acpiinit acpi_init_table[] = {
+	{ACPI_IO_BASE + 0x00, 0x01000000},
+	{ACPI_IO_BASE + 0x08, 0},
+	{ACPI_IO_BASE + 0x0C, 0},
+	{ACPI_IO_BASE + 0x1C, 0},
+	{ACPI_IO_BASE + 0x18, 0x0FFFFFFFF},
+	{ACPI_IO_BASE + 0x00, 0x0000FFFF},
+	{PMS_IO_BASE + PM_SCLK, 0x000000E00},
+	{PMS_IO_BASE + PM_SED, 0x000004601},
+	{PMS_IO_BASE + PM_SIDD, 0x000008C02},
+	{PMS_IO_BASE + PM_WKD, 0x0000000A0},
+	{PMS_IO_BASE + PM_WKXD, 0x0000000A0},
+	{0, 0}
+};
+
+struct FLASH_DEVICE {
+	unsigned char fType;	/* Flash type: NOR or NAND */
+	unsigned char fInterface;	/* Flash interface: I/O or Memory */
+	unsigned long fMask;	/* Flash size/mask */
+};
+
+struct FLASH_DEVICE FlashInitTable[] = {
+	{FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K},	/* CS0, or Flash Device 0 */
+	{FLASH_TYPE_NONE, 0, 0},	/* CS1, or Flash Device 1 */
+	{FLASH_TYPE_NONE, 0, 0},	/* CS2, or Flash Device 2 */
+	{FLASH_TYPE_NONE, 0, 0},	/* CS3, or Flash Device 3 */
+};
+
+#define FlashInitTableLen (sizeof(FlashInitTable)/sizeof(FlashInitTable[0]))
+
+u32 FlashPort[] = {
+	MDD_LBAR_FLSH0,
+	MDD_LBAR_FLSH1,
+	MDD_LBAR_FLSH2,
+	MDD_LBAR_FLSH3
+};
+
+/**
+  *	Program ACPI LBAR and initialize ACPI registers. 
+  */
+static void pm_chipset_init(void)
+{
+	u32 val = 0;
+	u16 port;
+
+	port = (PMS_IO_BASE + 0x010);
+	val = 0x0E00;		/*  1ms */
+	outl(val, port);
+
+	/*      PM_WKXD */
+	/*      Make sure bits[3:0]=0000b to clear the */
+	/*      saved Sx state */
+	port = (PMS_IO_BASE + 0x034);
+	val = 0x0A0;		/*  5ms */
+	outl(val, port);
+
+	/*      PM_WKD */
+	port = (PMS_IO_BASE + 0x030);
+	outl(val, port);
+
+	/*      PM_SED */
+	port = (PMS_IO_BASE + 0x014);
+	val = 0x04601;		/*  5ms, # of 3.57954MHz clock edges */
+	outl(val, port);
+
+	/*      PM_SIDD */
+	port = (PMS_IO_BASE + 0x020);
+	val = 0x08C02;		/*  10ms, # of 3.57954MHz clock edges */
+	outl(val, port);
+}
+
+/**	
+  * Flash LBARs need to be setup before VSA init so the PCI BARs have
+  *	correct size info.	Call this routine only if flash needs to be
+  *	configured (don't call it if you want IDE).
+  *
+  */
+static void chipset_flash_setup(void)
+{
+	msr_t msr;
+	int i;
+	int numEnabled = 0;
+
+	printk(BIOS_DEBUG, "chipset_flash_setup: Start\n");
+	for (i = 0; i < FlashInitTableLen; i++) {
+		if (FlashInitTable[i].fType != FLASH_TYPE_NONE) {
+			printk(BIOS_DEBUG, "Enable CS%d\n", i);
+			/* we need to configure the memory/IO mask */
+			msr = rdmsr(FlashPort[i]);
+			msr.hi = 0;	/* start with the "enabled" bit clear */
+			if (FlashInitTable[i].fType == FLASH_TYPE_NAND)
+				msr.hi |= 0x00000002;
+			else
+				msr.hi &= ~0x00000002;
+			if (FlashInitTable[i].fInterface == FLASH_IF_MEM)
+				msr.hi |= 0x00000004;
+			else
+				msr.hi &= ~0x00000004;
+			msr.hi |= FlashInitTable[i].fMask;
+			printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", FlashPort[i],
+				     msr.hi, msr.lo);
+			wrmsr(FlashPort[i], msr);
+
+			/* now write-enable the device */
+			msr = rdmsr(MDD_NORF_CNTRL);
+			msr.lo |= (1 << i);
+			printk(BIOS_DEBUG, "MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL,
+				     msr.hi, msr.lo);
+			wrmsr(MDD_NORF_CNTRL, msr);
+
+			/* update the number enabled */
+			numEnabled++;
+		}
+	}
+
+	printk(BIOS_DEBUG, "chipset_flash_setup: Finish\n");
+
+}
+
+/**
+  * Use this in the event that you have a FLASH part instead of an IDE drive. 
+  *Run after VSA init to enable the flash PCI device header
+  */
+static void enable_ide_nand_flash_header(void)
+{
+	/* Tell VSA to use FLASH PCI header. Not IDE header. */
+	outl(0x80007A40, 0xCF8);
+	outl(0xDEADBEEF, 0xCFC);
+}
+
+#define RTC_CENTURY 0x32
+#define RTC_DOMA	0x3D
+#define RTC_MONA	0x3E
+
+/**
+  * standard init function for the lpc bus. Sets up the "serial irq" interrupt, 
+  * which is NOT the same as serial interrupt, and also enables DMA from 
+  * the LPC bus. Configures the PC clock, enables rtc and ISA DMA. 
+  * @param southbridge config structure 
+  */
+static void lpc_init(struct southbridge_amd_cs5536_config *sb)
+{
+	msr_t msr;
+
+	if (sb->lpc_serirq_enable) {
+		msr.lo = sb->lpc_serirq_enable;
+		msr.hi = 0;
+		wrmsr(MDD_IRQM_LPC, msr);
+		if (sb->lpc_serirq_polarity) {
+			msr.lo = sb->lpc_serirq_polarity << 16;
+			msr.lo |= (sb->lpc_serirq_mode << 6) | (1 << 7);	/* enable */
+			msr.hi = 0;
+			wrmsr(MDD_LPC_SIRQ, msr);
+		}
+	}
+
+	/* Allow DMA from LPC */
+	msr = rdmsr(MDD_DMA_MAP);
+	msr.lo = 0x7777;
+	wrmsr(MDD_DMA_MAP, msr);
+
+	/* enable the RTC/CMOS century byte at address 32h */
+	msr = rdmsr(MDD_RTC_CENTURY_OFFSET);
+	msr.lo = RTC_CENTURY;
+	wrmsr(MDD_RTC_CENTURY_OFFSET, msr);
+
+	/* enable the RTC/CMOS day of month and month alarms */
+	msr = rdmsr(MDD_RTC_DOMA_IND);
+	msr.lo = RTC_DOMA;
+	wrmsr(MDD_RTC_DOMA_IND, msr);
+
+	msr = rdmsr(MDD_RTC_MONA_IND);
+	msr.lo = RTC_MONA;
+	wrmsr(MDD_RTC_MONA_IND, msr);
+
+	rtc_init(0);
+
+	isa_dma_init();
+}
+
+/** 
+ * Depending on settings in the config struct, enable COM1 or COM2 or both. 
+ * If the enable is NOT set, the UARTS are explicitly disabled, which is required 
+ * if (e.g.) there is a superio attached that does COM1 or COM2.
+  * @param southbridge config structure 
+  */
+static void uarts_init(struct southbridge_amd_cs5536_config *sb)
+{
+	msr_t msr;
+	u16 addr;
+	u32 gpio_addr;
+	struct device *dev;
+
+	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+			PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
+	gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
+	gpio_addr &= ~1;	/* clear IO bit */
+	printk(BIOS_DEBUG, "GPIO_ADDR: %08X\n", gpio_addr);
+
+	/* This could be extended to support IR modes */
+
+	/* COM1 */
+	if (sb->com1_enable) {
+		/* Set the address */
+		switch (sb->com1_address) {
+		case 0x3F8:
+			addr = 7;
+			break;
+
+		case 0x3E8:
+			addr = 6;
+			break;
+
+		case 0x2F8:
+			addr = 5;
+			break;
+
+		case 0x2E8:
+			addr = 4;
+			break;
+		}
+		msr = rdmsr(MDD_LEG_IO);
+		msr.lo |= addr << 16;
+		wrmsr(MDD_LEG_IO, msr);
+
+		/* Set the IRQ */
+		msr = rdmsr(MDD_IRQM_YHIGH);
+		msr.lo |= sb->com1_irq << 24;
+		wrmsr(MDD_IRQM_YHIGH, msr);
+
+		/* GPIO8 - UART1_TX */
+		/* Set: Output Enable  (0x4) */
+		outl(GPIOL_8_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
+		/* Set: OUTAUX1 Select (0x10) */
+		outl(GPIOL_8_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
+
+		/* GPIO8 - UART1_RX */
+		/* Set: Input Enable   (0x20) */
+		outl(GPIOL_9_SET, gpio_addr + GPIOL_INPUT_ENABLE);
+		/* Set: INAUX1 Select  (0x34) */
+		outl(GPIOL_9_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
+
+		/* Set: GPIO 8 + 9 Pull Up         (0x18) */
+		outl(GPIOL_8_SET | GPIOL_9_SET,
+		     gpio_addr + GPIOL_PULLUP_ENABLE);
+
+		/* enable COM1 */
+		/* Bit 1 = device enable Bit 4 = allow access to the upper banks */
+		msr.lo = (1 << 4) | (1 << 1);
+		msr.hi = 0;
+		wrmsr(MDD_UART1_CONF, msr);
+
+	} else {
+		/* Reset and disable COM1 */
+		msr = rdmsr(MDD_UART1_CONF);
+		msr.lo = 1;	// reset
+		wrmsr(MDD_UART1_CONF, msr);
+		msr.lo = 0;	// disabled
+		wrmsr(MDD_UART1_CONF, msr);
+
+		/* Disable the IRQ */
+		msr = rdmsr(MDD_LEG_IO);
+		msr.lo &= ~(0xF << 16);
+		wrmsr(MDD_LEG_IO, msr);
+	}
+
+	/* COM2 */
+	if (sb->com2_enable) {
+		switch (sb->com2_address) {
+		case 0x3F8:
+			addr = 7;
+			break;
+
+		case 0x3E8:
+			addr = 6;
+			break;
+
+		case 0x2F8:
+			addr = 5;
+			break;
+
+		case 0x2E8:
+			addr = 4;
+			break;
+		}
+		msr = rdmsr(MDD_LEG_IO);
+		msr.lo |= addr << 20;
+		wrmsr(MDD_LEG_IO, msr);
+
+		/* Set the IRQ */
+		msr = rdmsr(MDD_IRQM_YHIGH);
+		msr.lo |= sb->com2_irq << 28;
+		wrmsr(MDD_IRQM_YHIGH, msr);
+
+		/* GPIO3 - UART2_RX */
+		/* Set: Output Enable  (0x4) */
+		outl(GPIOL_3_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
+		/* Set: OUTAUX1 Select (0x10) */
+		outl(GPIOL_3_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
+
+		/* GPIO4 - UART2_TX */
+		/* Set: Input Enable   (0x20) */
+		outl(GPIOL_4_SET, gpio_addr + GPIOL_INPUT_ENABLE);
+		/* Set: INAUX1 Select  (0x34) */
+		outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
+
+		/* Set: GPIO 3 + 3 Pull Up         (0x18) */
+		outl(GPIOL_3_SET | GPIOL_4_SET,
+		     gpio_addr + GPIOL_PULLUP_ENABLE);
+
+		/* enable COM2 */
+		/* Bit 1 = device enable Bit 4 = allow access to the upper banks */
+		msr.lo = (1 << 4) | (1 << 1);
+		msr.hi = 0;
+		wrmsr(MDD_UART2_CONF, msr);
+
+	} else {
+		/* Reset and disable COM2 */
+		msr = rdmsr(MDD_UART2_CONF);
+		msr.lo = 1;	// reset
+		wrmsr(MDD_UART2_CONF, msr);
+		msr.lo = 0;	// disabled
+		wrmsr(MDD_UART2_CONF, msr);
+
+		/* Disable the IRQ */
+		msr = rdmsr(MDD_LEG_IO);
+		msr.lo &= ~(0xF << 20);
+		wrmsr(MDD_LEG_IO, msr);
+	}
+}
+
+#define HCCPARAMS		0x08
+#define IPREG04			0xA0
+	#define USB_HCCPW_SET	(1 << 1)
+#define UOCCAP			0x00
+	#define APU_SET			(1 << 15)
+#define UOCMUX			0x04
+#define PMUX_HOST		0x02
+#define PMUX_DEVICE		0x03
+	#define PUEN_SET		(1 << 2)
+#define UDCDEVCTL		0x404
+	#define UDC_SD_SET		(1 << 10)
+#define UOCCTL			0x0C
+	#define PADEN_SET		(1 << 7)
+
+/** 
+ * Depending on settings in the config struct, enable COM1 or COM2 or both. 
+ * If the enable is NOT set, the UARTS are explicitly disabled, which is required 
+ * if (e.g.) there is a superio attached that does COM1 or COM2.
+  * @param southbridge config structure 
+  */
+static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
+{
+	u32 *bar;
+	msr_t msr;
+	struct device *dev;
+
+	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+			PCI_DEVICE_ID_AMD_CS5536_EHCI, 0);
+	if (dev) {
+
+		/* Serial Short Detect Enable */
+		msr = rdmsr(USB2_SB_GLD_MSR_CONF);
+		msr.hi |= USB2_UPPER_SSDEN_SET;
+		wrmsr(USB2_SB_GLD_MSR_CONF, msr);
+
+		/* write to clear diag register */
+		wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG));
+
+		bar = (u32 *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+
+		/* Make HCCPARAMS writeable */
+		*(bar + IPREG04) |= USB_HCCPW_SET;
+
+		/* ; EECP=50h, IST=01h, ASPC=1 */
+		*(bar + HCCPARAMS) = 0x00005012;
+	}
+
+	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+			PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
+	if (dev) {
+		bar = (u32 *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+
+		*(bar + UOCMUX) &= PUEN_SET;
+
+		/* Host or Device? */
+		if (sb->enable_USBP4_device) {
+			*(bar + UOCMUX) |= PMUX_DEVICE;
+		} else {
+			*(bar + UOCMUX) |= PMUX_HOST;
+		}
+
+		/* Overcurrent configuration */
+		if (sb->enable_USBP4_overcurrent) {
+			*(bar + UOCCAP) |= sb->enable_USBP4_overcurrent;
+		}
+	}
+
+	/* PBz#6466: If the UOC(OTG) device, port 4, is configured as a device,
+	 *      then perform the following sequence:
+	 *
+	 * - set SD bit in DEVCTRL udc register
+	 * - set PADEN (former OTGPADEN) bit in uoc register
+	 * - set APU bit in uoc register */
+	if (sb->enable_USBP4_device) {
+		dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+				PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
+		if (dev) {
+			bar = (u32 *) pci_read_config32(dev, 
+					PCI_BASE_ADDRESS_0);
+			*(bar + UDCDEVCTL) |= UDC_SD_SET;
+
+		}
+
+		dev = dev_find_device(PCI_VENDOR_ID_AMD,
+				PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
+		if (dev) {
+			bar = (u32 *) pci_read_config32(dev,
+					PCI_BASE_ADDRESS_0);
+			*(bar + UOCCTL) |= PADEN_SET;
+			*(bar + UOCCAP) |= APU_SET;
+		}
+	}
+
+	/* Disable virtual PCI UDC and OTG headers */
+	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+			PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
+	if (dev) {
+		pci_write_config32(dev, 0x7C, 0xDEADBEEF);
+	}
+
+	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+			PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
+	if (dev) {
+		pci_write_config32(dev, 0x7C, 0xDEADBEEF);
+	}
+}
+
+/* ***************************************************************************/
+/* **/
+/* *	ChipsetInit */
+/*			Called from northbridge init (Pre-VSA). */
+/* **/
+/* ***************************************************************************/
+void chipsetinit(void)
+{
+	struct device *dev;
+	msr_t msr;
+	u32 msrnum;
+	struct southbridge_amd_cs5536_config *sb =
+	    (struct southbridge_amd_cs5536_config *)dev->device_configuration;
+	struct msrinit *csi;
+
+	post_code(P80_CHIPSET_INIT);
+
+	/* we hope NEVER to be in linuxbios when S3 resumes
+	   if (! IsS3Resume()) */
+	{
+		struct acpiinit *aci = acpi_init_table;
+		for (; aci->ioreg; aci++) {
+			outl(aci->regdata, aci->ioreg);
+			inl(aci->ioreg);
+		}
+
+		pm_chipset_init();
+	}
+
+	/* set hd IRQ */
+	outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
+	outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
+
+	/*      Allow IO read and writes during a ATA DMA operation. */
+	/*       This could be done in the HD rom but do it here for easier debugging. */
+	msrnum = ATA_SB_GLD_MSR_ERR;
+	msr = rdmsr(msrnum);
+	msr.lo &= ~0x100;
+	wrmsr(msrnum, msr);
+
+	/*      Enable Post Primary IDE. */
+	msrnum = GLPCI_SB_CTRL;
+	msr = rdmsr(msrnum);
+	msr.lo |= GLPCI_CRTL_PPIDE_SET;
+	wrmsr(msrnum, msr);
+
+	csi = SB_MASTER_CONF_TABLE;
+	for (; csi->msrnum; csi++) {
+		msr.lo = csi->msr.lo;
+		msr.hi = csi->msr.hi;
+		wrmsr(csi->msrnum, msr);	// MSR - see table above
+	}
+
+	/*      Flash BAR size Setup */
+	printk(BIOS_ERR, "%sDoing chipset_flash_setup()\n",
+		   sb->enable_ide_nand_flash == 1 ? "" : "Not ");
+	if (sb->enable_ide_nand_flash == 1)
+		chipset_flash_setup();
+
+	/* */
+	/*      Set up Hardware Clock Gating */
+	/* */
+	{
+		csi = CS5536_CLOCK_GATING_TABLE;
+		for (; csi->msrnum; csi++) {
+			msr.lo = csi->msr.lo;
+			msr.hi = csi->msr.hi;
+			wrmsr(csi->msrnum, msr);	// MSR - see table above
+		}
+	}
+}
+
+/** 
+ * Depending on settings in the config struct, enable COM1 or COM2 or both. 
+ * If the enable is NOT set, the UARTS are explicitly disabled, which is required 
+ * if (e.g.) there is a superio attached that does COM1 or COM2.
+  * @param southbridge config structure 
+  */
+static void southbridge_init(struct device *dev)
+{
+	struct southbridge_amd_cs5536_config *sb =
+	    (struct southbridge_amd_cs5536_config *)dev->device_configuration;
+	/*
+	 * struct device *gpiodev;
+	 * unsigned short gpiobase = MDD_GPIO;
+	 */
+
+	printk(BIOS_ERR, "cs5536: %s\n", __FUNCTION__);
+	setup_i8259();
+	lpc_init(sb);
+	uarts_init(sb);
+
+	if (sb->enable_gpio_int_route) {
+		vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_AB,
+			(sb->enable_gpio_int_route & 0xFFFF));
+		vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_CD,
+			(sb->enable_gpio_int_route >> 16));
+	}
+
+	printk(BIOS_ERR, "cs5536: %s: enable_ide_nand_flash is %d\n", __FUNCTION__,
+		   sb->enable_ide_nand_flash);
+	if (sb->enable_ide_nand_flash == 1) {
+		enable_ide_nand_flash_header();
+	}
+
+	enable_USB_port4(sb);
+
+#warning Add back in unwanted VPCI support
+#if 0
+	/* disable unwanted virtual PCI devices */
+	for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) {
+		printk(BIOS_DEBUG, "Disabling VPCI device: 0x%08X\n",
+			     sb->unwanted_vpci[i]);
+		outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8);
+		outl(0xDEADBEEF, 0xCFC);
+	}
+#endif
+}
+
+static void southbridge_enable(struct device *dev)
+{
+	printk(BIOS_ERR, "cs5536: Enter %s: dev is %p\n", __FUNCTION__, dev);
+	printk(BIOS_ERR, "cs5536: Exit %s: dev is %p\n", __FUNCTION__, dev);
+
+}
+
+/** 
+  * A slightly different enable resources than the standard. 
+  * We grab control here as VSA has played in this chip as well. 
+  * @param southbridge config structure 
+  */
+static void cs5536_pci_dev_enable_resources(struct device *dev)
+{
+	printk(BIOS_ERR, "cs5536: %s()\n", __FUNCTION__);
+	pci_dev_enable_resources(dev);
+	enable_childrens_resources(dev);
+}
+
+static struct device_operations southbridge_ops = {
+	.phase3_scan = scan_static_bus,
+	.phase4_read_resources = pci_dev_read_resources,
+	.phase4_set_resources = pci_dev_set_resources,
+	.phase5_enable_resources = cs5536_pci_dev_enable_resources,
+	.phase6_init = southbridge_init,
+};
+
+struct constructor cs5536_constructors[] = {
+  {.id = {.type = DEVICE_ID_PCI,
+	  .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD,.device = PCI_DEVICE_ID_AMD_CS5536_ISA}}},
+   	.ops = &southbridge_ops},
+  {.ops = 0},
+};
Index: southbridge/amd/cs5536/Makefile
===================================================================
--- southbridge/amd/cs5536/Makefile	(revision 367)
+++ southbridge/amd/cs5536/Makefile	(working copy)
@@ -21,7 +21,7 @@
 
 STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/cs5536.o
 
-$(obj)/southbridge/amd/cs5536/%.o: $(src)/southbridge/amd/cs5536/%.c
+$(obj)/southbridge/amd/cs5536/%.o: $(src)/southbridge/amd/cs5536/%.c $(obj)/statictree.h
 	$(Q)mkdir -p $(obj)/southbridge/amd/cs5536/
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(CC) $(INITCFLAGS) -c $< -o $@
Index: southbridge/intel/i82371eb/i82371eb.c
===================================================================
--- southbridge/intel/i82371eb/i82371eb.c	(revision 367)
+++ southbridge/intel/i82371eb/i82371eb.c	(working copy)
@@ -26,7 +26,7 @@
 #include <device/pci.h>
 #include <mc146818rtc.h>
 #include <string.h>
-#include "config.h"
+#include <statictree.h>
 
 /* The plain PCI device uses the standard PCI operations. */
 
