Index: src/southbridge/via/vt8237r/vt8237r.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r.c	(revision 0)
+++ src/southbridge/via/vt8237r/vt8237r.c	(revision 0)
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey_osgood@verizon.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <pc80/keyboard.h>
+#include "vt8237r.h"
+#include "chip.h"
+
+/* 
+ * Datasheet: http://www.via.com.tw/en/downloads/datasheets/chipsets/
+ *					VT8237R_SouthBridge_Revision2.06_Lead-Free.zip
+*/
+
+static int enabled = 0;
+
+void hard_reset(void) 
+{
+	printk_err("NO HARD RESET ON VT8237R! FIX ME!\n");
+}
+
+void dump_south(device_t dev0)
+{
+	int i,j;
+	
+	for(i = 0; i < 256; i += 16) {
+		printk_debug("0x%x: ", i);
+		for(j = 0; j < 16; j++) {
+			printk_debug("%02x ", pci_read_config8(dev0, i+j));
+		}
+		printk_debug("\n");
+	}
+}
+
+static void vt8237r_enable(struct device *dev)
+{
+	struct southbridge_via_vt8237r_config *conf = dev->chip_info;
+	uint16_t vendor, model;
+
+
+	vendor = pci_read_config16(dev,0);
+	model = pci_read_config16(dev,0x2);
+
+	printk_debug("In vt8237r_enable %04x %04x.\n", vendor, model);
+	
+	/* if this is not the southbridge itself just return */
+	
+	/* No need to check the vendor, we know it will always be Via */
+	if(/* (vendor != PCI_VENDOR_ID_VIA) ||*/ (model != 0x3227))
+	{
+		return;
+	}
+
+	printk_debug("Initialising Devices\n");
+
+	setup_i8259();   // make sure interupt controller is configured before keyboard init 
+
+	/* Enable everything but MC'97 */
+	/* To enable all devs, write 0x00 */
+	//handle in preram code
+	//pci_write_config8(dev, 0x50, 0x80);
+
+	/* turn on keyboard and RTC, no need to visit this reg twice */
+	pci_write_config8(dev, 0x51, 0x1f);
+	init_pc_keyboard(0x60, 0x64, 0);
+}
+
+struct chip_operations southbridge_via_vt8237r_ops = {
+	CHIP_NAME("VIA VT8237R Southbridge")
+	.enable_dev = vt8237r_enable,
+};
Index: src/southbridge/via/vt8237r/vt8237r_audio.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_audio.c	(revision 0)
+++ src/southbridge/via/vt8237r/vt8237r_audio.c	(revision 0)
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey_osgood@verizon.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include "vt8237r.h"
+#include "chip.h"
+
+#define DISABLE_MC97_MODEM
+
+static void audio_init(struct device *dev)
+{
+	printk_info("Enabling VIA AC'97 Audio.\n");
+
+
+}
+
+static struct device_operations audio_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = audio_init,
+	.enable           = 0,
+	.ops_pci          = 0, 
+};
+
+static struct pci_driver northbridge_driver __pci_driver = { 
+	.ops    = &audio_ops,
+	.vendor = PCI_VENDOR_ID_VIA,
+	.device = 0x3059,
+};
Index: src/southbridge/via/vt8237r/Config.lb
===================================================================
--- src/southbridge/via/vt8237r/Config.lb	(revision 0)
+++ src/southbridge/via/vt8237r/Config.lb	(revision 0)
@@ -0,0 +1,9 @@
+config chip.h
+driver vt8237r.o
+driver vt8237r_lpc.o
+driver vt8237r_sata.o
+driver vt8237r_ide.o
+driver vt8237r_nic.o
+driver vt8237r_audio.o
+driver vt8237r_usb.o
+driver vt8237r_usb_ehci.o
Index: src/southbridge/via/vt8237r/vt8237r_ide.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_ide.c	(revision 0)
+++ src/southbridge/via/vt8237r/vt8237r_ide.c	(revision 0)
@@ -0,0 +1,129 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* TODO: rename to PATA for clarity's sake
+ * Reason: that's what the datasheet refers to it as */
+
+/* Note: In the BIOS programmer's guide, this devices is referred to as IDE1 */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include "vt8237r.h"
+#include "chip.h"
+
+#include "debug.c"
+
+/* NOTE: In this file, IDE0 refers to the primary IDE 
+ * channel, and IDE1 to the secondary channel */
+
+static void ide_init(struct device *dev)
+{
+	uint8_t enables;
+
+	printk_info("Enabling Via IDE\n");
+
+	pci_write_config16(dev, 0x04, 0x0007);
+
+	//enables = pci_read_config8(dev, IDE_MODE_REG);
+	//enables |= (IDE0_NATIVE_MODE | IDE1_NATIVE_MODE);
+	//pci_write_config8(dev, IDE_MODE_REG, enables);
+
+#if 0
+	/* Set up addresses for both native and compatibility modes */
+	/* Compatibility mode addresses */
+	pci_write_config32(dev, 0x10, IDE0_DATA_ADDR | 1);
+	pci_write_config32(dev, 0x14, IDE0_CONTROL_ADDR | 1);
+	pci_write_config32(dev, 0x18, IDE1_DATA_ADDR | 1);
+	pci_write_config32(dev, 0x1b, IDE1_CONTROL_ADDR | 1);
+#endif
+
+	/* Native mode base address */
+	pci_write_config32(dev, 0x20, BUS_MASTER_ADDR | 1);
+
+	/* Enable read/write prefetch buffers */
+	enables = pci_read_config8(dev, 0x41);
+	enables |= 0xf0;
+	pci_write_config8(dev, 0x41, enables);
+
+	/* Use fixed addressing */
+	enables = pci_read_config8(dev, 0x42);
+	enables &= 0x3f;
+	pci_write_config8(dev, 0x42, enables);
+
+	/* Set FIFO thresholds like Award does */
+	enables = pci_read_config8(dev, 0x43);
+	enables &= 0xf0;
+	enables |= 0x05; /* FIFO flushed when 1/2 full */
+	pci_write_config8(dev, 0x43, enables);
+
+	/* Some miscellaneous control stuff, see datasheet */
+	pci_write_config16(dev, 0x60, 0x200);
+	pci_write_config16(dev, 0x68, 0x200);
+	pci_write_config8(dev, 0x44, 0x18);
+	pci_write_config8(dev, 0x46, 0xc0);
+
+	/* Make sure reg 0x3c isn't write protected, enable memory read multiple */
+	enables = pci_read_config8(dev, 0x45);
+	enables &= 0xef;
+	enables |= 0x0c;
+	pci_write_config8(dev, 0x45, enables);
+
+	/* Set to IRQ 15 */
+	enables = pci_read_config8(dev, 0x3c);
+	enables &= 0xf0;
+	enables |= 15; //ie 0xf
+	pci_write_config8(dev, 0x3c, 0xff);//cuz things aint workin'
+	pci_write_config8(dev, 0x3d, 0x00);//legacy mode interrupt routing, if possible
+
+	/* Set the drive timing control, according to Award */
+	pci_write_config32(dev, 0x48, 0x205d5d5d);
+	pci_write_config8(dev, 0x4c, 0xff);
+	pci_write_config8(dev, 0x4e, 0xb6);
+	pci_write_config8(dev, 0x4f, 0x20);
+	pci_write_config32(dev, 0x50, 0xe1170707);
+	pci_write_config8(dev, 0x54, 0x0c);
+	pci_write_config8(dev, 0x55, 0x03);
+
+	/* Enable both IDE channels */
+	/* Makes sense to do this last..or maybe first, we'll see */
+	enables = pci_read_config8(dev, CHANNEL_ENABLE_REG);
+	enables |= (ENABLE_IDE0 | ENABLE_IDE1);
+	pci_write_config8(dev, CHANNEL_ENABLE_REG, enables);
+
+	printk_debug("IDE device register dump:\n");
+	dump_dev(dev);
+}
+
+static struct device_operations ide_ops = {
+	.read_resources	  = pci_dev_read_resources,
+	.set_resources	  = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init		  = ide_init,
+	.enable		  = 0,
+	.ops_pci	  = 0, 
+};
+
+static struct pci_driver via_ide_driver __pci_driver = { 
+	.ops    = &ide_ops,
+	.vendor = PCI_VENDOR_ID_VIA,
+	.device = PCI_DEVICE_ID_VIA_82C586_1, //yes, this is accurate
+};
Index: src/southbridge/via/vt8237r/vt8237r_usb_ehci.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_usb_ehci.c	(revision 0)
+++ src/southbridge/via/vt8237r/vt8237r_usb_ehci.c	(revision 0)
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey_osgood@verizon.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include "vt8237r.h"
+#include "chip.h"
+
+static void usb_ehci_init(struct device *dev)
+{ //todo
+}
+
+static struct device_operations usb_ehci_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = usb_ehci_init,
+	.enable           = 0,
+	.ops_pci          = 0, 
+};
+
+static struct pci_driver via_usb_ehci_driver __pci_driver = { 
+	.ops    = &usb_ehci_ops,
+	.vendor = PCI_VENDOR_ID_VIA,
+	.device = 0x3104,
+};
Index: src/southbridge/via/vt8237r/vt8237r_early_smbus.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_early_smbus.c	(revision 0)
+++ src/southbridge/via/vt8237r/vt8237r_early_smbus.c	(revision 0)
@@ -0,0 +1,252 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey_osgood@verizon.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+ 
+/* 
+ * Datasheet: http://www.via.com.tw/en/downloads/datasheets/chipsets/
+ *					VT8237R_SouthBridge_Revision2.06_Lead-Free.zip
+*/
+
+/* SMBus info: page 125, 137-139 */
+
+
+#define SMBUS_IO_BASE		0x0500 //from award bios
+#define PMIO_BASE		0x0400 //might as well set this while we're here
+
+#define SMBHSTSTAT		SMBUS_IO_BASE + 0x0
+#define SMBSLVSTAT		SMBUS_IO_BASE + 0x1
+#define SMBHSTCTL		SMBUS_IO_BASE + 0x2
+#define SMBHSTCMD		SMBUS_IO_BASE + 0x3
+#define SMBXMITADD		SMBUS_IO_BASE + 0x4
+#define SMBHSTDAT0		SMBUS_IO_BASE + 0x5
+/* Rest of these aren't currently used... */
+#define SMBHSTDAT1		SMBUS_IO_BASE + 0x6
+#define SMBBLKDAT		SMBUS_IO_BASE + 0x7
+#define SMBSLVCTL		SMBUS_IO_BASE + 0x8
+#define SMBTRNSADD		SMBUS_IO_BASE + 0x9
+#define SMBSLVDATA 		SMBUS_IO_BASE + 0xa
+#define SMLINK_PIN_CTL		SMBUS_IO_BASE + 0xe
+#define SMBUS_PIN_CTL		SMBUS_IO_BASE + 0xf 
+
+/* Define register settings */
+#define HOST_RESET 		0xff
+#define DIMM_BASE		0xa0	// 1010000 is base for DIMM in SMBus
+#define READ_CMD		0x01	// 1 in the 0 bit of SMBHSTADD states to READ
+
+#define SMBUS_TIMEOUT		(100*1000*10)
+
+#define I2C_TRANS_CMD		0x40
+#define CLOCK_SLAVE_ADDRESS	0x69
+
+#define SMBUS_DELAY()		outb(0x80, 0x80)
+
+/* Debugging macros. Only necessary if something isn't working right */
+
+//#define DEBUG_SMBUS = 1
+	
+#ifdef DEBUG_SMBUS
+#define PRINT_DEBUG(x)		print_debug(x)
+#define PRINT_DEBUG_HEX16(x)	print_debug_hex16(x)
+#else
+#define PRINT_DEBUG(x)
+#define PRINT_DEBUG_HEX16(x)
+#endif
+
+/* Internal functions */
+
+static void smbus_print_error(unsigned char host_status_register, int loops)
+{
+	/* Check if there actually was an error */	
+	if ( host_status_register == 0x00 || host_status_register == 0x40 || 
+					host_status_register == 0x42) return;
+	print_err("smbus_error: ");
+	print_err_hex8(host_status_register);
+	print_err("\r\n");	
+	if (loops >= SMBUS_TIMEOUT) {
+		print_err("SMBus Timout\r\n");
+	}
+	if (host_status_register & (1 << 4)) {
+		print_err("Interrup/SMI# was Failed Bus Transaction\r\n");
+	}
+	if (host_status_register & (1 << 3)) {
+		print_err("Bus Error\r\n");
+	}
+	if (host_status_register & (1 << 2)) {
+		print_err("Device Error\r\n");
+	}
+	if (host_status_register & (1 << 1)) {
+		/* This isn't a real error... */
+		print_debug("Interrupt/SMI# was Successful Completion\r\n");
+	}
+	if (host_status_register & (1 << 0)) {
+		print_err("Host Busy\r\n");
+	}
+}
+
+static void smbus_wait_until_ready(void)
+{
+	int loops;
+	
+	loops = 0;
+	/* Yes, this is a mess, but it's the easiest way to do it */
+	while(((inb(SMBHSTSTAT) & 1) == 1) && (loops <= SMBUS_TIMEOUT)) ++loops;
+	smbus_print_error(inb(SMBHSTSTAT), loops);
+}
+
+static void smbus_reset(void)
+{
+	/* four resets? a little overboard? or just frustrated? */
+	outb(HOST_RESET, SMBHSTSTAT);
+	/* Datasheet says we have to read it to take ownership of SMBus */
+	inb(SMBHSTSTAT);
+	
+	/* This messes up dump_spd_data() formatting. Very annoying */
+	//PRINT_DEBUG("After reset status: ");
+	//PRINT_DEBUG_HEX16( inb(SMBHSTSTAT));
+	//PRINT_DEBUG("\r\n");
+
+}
+
+/* Public functions */
+
+static unsigned int get_spd_data(unsigned int dimm, unsigned int offset)
+{
+	unsigned int val;
+
+	smbus_reset();
+	/* clear host data port */
+	outb(0x00, SMBHSTDAT0);
+	SMBUS_DELAY();
+	smbus_wait_until_ready();
+
+	/* Do some mathmatic magic */
+	dimm = (dimm << 1);
+	/* Rudolf says these aren't necessary. trying */
+	/* Seem necessary on my board... */
+	dimm &= 0x0E;
+	dimm |= 0xA1;
+	
+	outb(dimm, SMBXMITADD);
+	outb(offset, SMBHSTCMD);
+	outb(0x48, SMBHSTCTL);
+
+	SMBUS_DELAY();
+
+	smbus_wait_until_ready();
+
+	val = inb(SMBHSTDAT0);
+	smbus_reset(); /* probably don't have to do this, but it can't hurt */
+	return val; /* can I just "return inb(SMBHSTDAT0)"? */
+}
+
+static void enable_smbus(void)
+{
+	device_t dev;
+
+	/* Power management controller */
+	/* This should work, but there are more important things to work on */
+	/* dev = PCI_DEV(0, 0x11, 0); */
+	
+	dev = pci_locate_device(PCI_ID(0x1106, 0x3227), 0);
+	
+	if (dev == PCI_DEV_INVALID)
+	{
+		/* This won't display text if enable_smbus() is before serial init */
+		die("Power Managment Controller not found\r\n");
+	}
+	
+	/* Set clock source */
+	pci_write_config8(dev, 0x94, 0xa0);
+	
+	/* Write SMBus IO base to 0xd0, and enable SMBus */
+	pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
+	 
+	/* Set to Award value */
+	pci_write_config8(dev, 0xd2, 0x01);
+	
+	/* Make it work for I/O ...*/
+	/* Note: the datasheet lists this register as read-only, but smbus 
+	doesn't work without this. Weird... */
+	pci_write_config16(dev, 0x04, 0x0001);
+	
+	/* Set the power management IO base while we're here */
+	pci_write_config32(dev, 0x88, PMIO_BASE | 1 );
+}	
+
+static void smbus_fixup(void)
+{
+	int c;
+	unsigned int byte = 0x00;
+	/* SMBus reads fail for ~22 reads without some fixup */
+	/* Read until we get the right data for a known byte */
+	/* This method has one major flaw: it needs DDR2 in DIMM0 */
+	PRINT_DEBUG("Waiting until SMBus ready");
+	for(c = 0; c < SMBUS_TIMEOUT && byte != 0x08; c++) 
+	{
+		PRINT_DEBUG(".");
+		byte = get_spd_data(0, 2);
+	}
+	if(c == SMBUS_TIMEOUT)
+	{
+		print_err("-SMBus error!-\r\n");
+	}
+	else
+	{
+	/* Will this cause any problems if DEBUG_SMBUS isn't defined? */
+		PRINT_DEBUG("Done!\r\n");
+	}
+}
+
+/* Debugging Function */
+
+#ifdef DEBUG_SMBUS
+static void dump_spd_data(void)
+{
+	int dimm, offset, regs;
+	unsigned int val;
+	
+	for(dimm = 0; dimm < 8; dimm++)
+	{
+		print_debug("SPD Data for DIMM ");
+		print_debug_hex8(dimm);
+		print_debug("\r\n");
+		
+		val = get_spd_data(dimm, 0);
+		if(val == 0xff)
+		{
+			regs = 256;
+		} else if(val == 0x80) {
+			regs = 128;
+		} else {
+			print_debug("No DIMM present\r\n");
+			regs = 0;
+		}
+		for(offset = 0; offset < regs; offset++)
+		{
+			print_debug("  Offset ");
+			print_debug_hex8(offset);
+			print_debug(" = 0x");
+			print_debug_hex8(get_spd_data(dimm, offset));
+			print_debug("\r\n");
+		}
+	}
+}
+#else
+#define dump_spd_data()
+#endif
Index: src/southbridge/via/vt8237r/vt8237r.h
===================================================================
--- src/southbridge/via/vt8237r/vt8237r.h	(revision 0)
+++ src/southbridge/via/vt8237r/vt8237r.h	(revision 0)
@@ -0,0 +1,17 @@
+/* IDE specific bits */
+#define IDE_MODE_REG		0x09
+#define IDE0_NATIVE_MODE	(1 << 0)
+#define IDE1_NATIVE_MODE	(1 << 2)
+
+/* These are default addresses according to Via */
+#define IDE0_DATA_ADDR		0x1f0
+#define IDE0_CONTROL_ADDR	0x3f4
+#define IDE1_DATA_ADDR		0x170
+#define IDE1_CONTROL_ADDR	0x370
+
+/* By Award default, Via default is 0xCC0 */
+#define BUS_MASTER_ADDR		0xfe00
+
+#define CHANNEL_ENABLE_REG	0x40
+#define ENABLE_IDE0		(1 << 0)
+#define ENABLE_IDE1		(1 << 1)
Index: src/southbridge/via/vt8237r/debug.c
===================================================================
--- src/southbridge/via/vt8237r/debug.c	(revision 0)
+++ src/southbridge/via/vt8237r/debug.c	(revision 0)
@@ -0,0 +1,12 @@
+static void dump_dev(device_t dev)
+{
+	int i,j;
+	
+	for(i = 0; i < 256; i += 16) {
+		printk_debug("0x%x: ", i);
+		for(j = 0; j < 16; j++) {
+			printk_debug("%02x ", pci_read_config8(dev, i+j));
+		}
+		printk_debug("\n");
+	}
+}
Index: src/southbridge/via/vt8237r/vt8237r_sata.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_sata.c	(revision 0)
+++ src/southbridge/via/vt8237r/vt8237r_sata.c	(revision 0)
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include "vt8237r.h"
+
+/* todo: better user configuration */
+#define DISABLE_SATA 1
+
+static void sata_init(struct device *dev)
+{
+	uint8_t	reg8;
+
+	printk_debug("Configuring VIA SATA Controller\n");
+
+	/* class IDE Disk, instead of RAID controller */
+	reg8 = pci_read_config8(dev, 0x45);
+	reg8 &= 0x7f; /* Sub Class Write Protect off */
+	pci_write_config8(dev, 0x45, reg8);
+	pci_write_config8(dev, 0x0a, 0x01);
+	reg8 |= 0x80; /* Sub Class Write Protect on */
+	pci_write_config8(dev, 0x45, reg8);
+
+#ifdef DISABLE_SATA
+#if DISABLE_SATA == 1
+	/* Disable SATA channels */
+	pci_write_config8(dev, 0x40, 0x00);
+#endif
+#endif
+
+	/* Enable IDE even if SATA disabled */
+	pci_write_config8(dev, 0xd1, 0x08);
+	pci_write_config8(dev, 0x49, 0x82);
+}
+
+static struct device_operations sata_ops = {
+	.read_resources	  = pci_dev_read_resources,
+	.set_resources	  = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init		  = sata_init,
+	.enable		  = 0,
+	.ops_pci	  = 0,
+};
+
+static struct pci_driver northbridge_driver __pci_driver = {
+	.ops    = &sata_ops,
+	.vendor = PCI_VENDOR_ID_VIA,
+	.device = 0x3149,
+};
Index: src/southbridge/via/vt8237r/chip.h
===================================================================
--- src/southbridge/via/vt8237r/chip.h	(revision 0)
+++ src/southbridge/via/vt8237r/chip.h	(revision 0)
@@ -0,0 +1,21 @@
+#ifndef _SOUTHBRIDGE_VIA_VT8237R
+#define _SOUTHBRIDGE_VIA_VT8237R
+
+extern struct chip_operations southbridge_via_vt8237r_ops;
+
+struct southbridge_via_vt8237r_config {
+	/* PCI function enables */
+	/* i.e. so that pci scan bus will find them. */
+	/* I am putting in IDE as an example but obviously this needs
+	 * to be more complete!
+	 */
+	int enable_ide;
+	/* enables of functions of devices */
+	/* USB removed, code comments essentially said it should have been long ago */
+	//int enable_native_ide;
+	/* No serial/kb on vt8237 */
+	//int enable_keyboard;
+	int enable_nvram;
+};
+
+#endif /* _SOUTHBRIDGE_VIA_VT8237R */
Index: src/southbridge/via/vt8237r/vt8237r_nic.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_nic.c	(revision 0)
+++ src/southbridge/via/vt8237r/vt8237r_nic.c	(revision 0)
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey_osgood@verizon.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include "vt8237r.h"
+#include <arch/io.h>
+
+/*
+ * Enable the ethernet device and turn off stepping (because it is integrated 
+ * inside the southbridge)
+ */
+/* The PCI ID for this for vt8237 matches vt8235. I'm not bothering to mess 
+ * with it for now, and hoping it works */
+
+#define LAN_IO_BASE 0xf600 //pulled from factory bios
+#define LAN_MEMBASE 0xfdffd000
+
+static void nic_init(struct device *dev)
+{
+	uint8_t	byte;
+
+	printk_debug("Configuring VIA Rhine LAN\n");
+
+	/* We don't need stepping - though the device supports it */
+	byte = pci_read_config8(dev, PCI_COMMAND);
+	byte &= ~PCI_COMMAND_WAIT;
+	pci_write_config8(dev, PCI_COMMAND, byte);
+	
+	/* enable IO space access */
+	pci_write_config16(dev, 0x4, 0x1);
+	
+	/* Set the LAN IO Base */
+	pci_write_config32(dev, 0x10, LAN_IO_BASE | 1);
+	
+	/* Set up the memory range */
+	pci_write_config32(dev, 0x14, LAN_MEMBASE);
+	
+//my mac: 003018-ab989e
+//   vendor ^^^ | ^^^ unique
+	/* Set up the MAC address */
+	//outl(0xbbffcccc, LAN_IO_BASE + 0);
+	
+	/* Set to IRQ11 */
+	//pci_write_config32(dev, 0x3c, 0xb);
+}
+
+static struct device_operations nic_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = nic_init,
+	.enable           = 0,
+	.ops_pci          = 0,
+};
+
+static struct pci_driver northbridge_driver __pci_driver = {
+	.ops    = &nic_ops,
+	.vendor = PCI_VENDOR_ID_VIA,
+	.device = PCI_DEVICE_ID_VIA_8233_7,
+};
Index: src/southbridge/via/vt8237r/vt8237r_usb.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_usb.c	(revision 0)
+++ src/southbridge/via/vt8237r/vt8237r_usb.c	(revision 0)
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey_osgood@verizon.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+#include "vt8237r.h"
+#include "chip.h"
+
+static void usb_init(struct device *dev)
+{
+#if 0
+	uint32_t base_addr;
+	int index;
+
+	pci_write_config8(dev, 0x04, 0x07);
+
+	index = PCI_FUNC(dev->path.u.pci.devfn);
+
+	/* Compute a base address based on which function this is */
+	base_addr = 0xfa01 + (index << 8);
+
+	printk_debug("base address for this usb controller is 0x%X\n", base_addr);
+
+	pci_write_config32(dev, 0x20, base_addr);
+
+	/* Gang the first 2 usb ports onto IRQ11, next 2 on IRQ7 (like award) */
+	if (index < 2)
+		pci_write_config8(dev, 0x3c, 0x0b);
+	else
+		pci_write_config8(dev, 0x3c, 0x07);
+#endif
+}
+
+static struct device_operations usb_ops = {
+	.read_resources   = pci_dev_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = usb_init,
+	.enable           = 0,
+	.ops_pci          = 0, 
+};
+
+static struct pci_driver via_usb_driver __pci_driver = { 
+	.ops    = &usb_ops,
+	.vendor = PCI_VENDOR_ID_VIA,
+	.device = 0x3038,
+};
Index: src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_lpc.c	(revision 0)
+++ src/southbridge/via/vt8237r/vt8237r_lpc.c	(revision 0)
@@ -0,0 +1,273 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey_osgood@verizon.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <device/pci_ids.h>
+
+#include <pc80/mc146818rtc.h>
+
+#include "vt8237r.h"
+#include "chip.h"
+
+#define ACPI_IO_BASE	0x400
+//#define PM_IO_BASE	0x??
+
+/*
+Offset 82 - ACPI Interrupt Select ....................................RW
+   4    SUSC# AC-Power-On Default Value .................RO
+        This bit is written at RTC Index 0D bit-7. If this bit
+        is 0, the system is configured to ���default on��� when
+        power is connected.
+*/
+static const unsigned char pciIrqs[4] = { 10 , 5 , 11, 9 };
+
+static const unsigned char usb1Pins[4] = { 'A', 'B', 'C', 'D' };
+static const unsigned char usb2Pins[4] = { 'B', 'C', 'D', 'A' };
+static const unsigned char usb3Pins[4] = { 'C', 'D', 'A', 'B' };
+static const unsigned char slotPins[4] = { 'B', 'C', 'D', 'A'};
+static const unsigned char vgaPins[4] = { 'A', 'B', 'C', 'D' };
+static const unsigned char nicPins[4] = { 'C', 'D', 'A', 'B' };
+static const unsigned char ac97Pins[4] = { 'C', 'D', 'A', 'B' };
+
+static unsigned char *pin_to_irq(const unsigned char *pin)
+{
+	static unsigned char Irqs[4];
+	int i;
+	for (i = 0 ; i < 4 ; i++)
+		Irqs[i] = pciIrqs[ pin[i] - 'A' ];
+
+	return Irqs;
+}
+
+static void pci_routing_fixup(struct device *dev)
+{
+/* TODO: I had the damn manual on this earlier today, and I didn't save it.
+Find it again, and map PCI space according to the jetway
+Find out if Firewire is provided, if so, disable it anyways (I don't need firewire) */	
+	
+	
+	printk_info("%s: dev is %p\n", __FUNCTION__, dev);
+
+	/* set up PCI IRQ routing */
+	pci_write_config8(dev, 0x55, pciIrqs[0] << 4);
+	pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) );
+	pci_write_config8(dev, 0x57, pciIrqs[3] << 4);
+
+
+	// Standard usb components
+	printk_info("setting usb1\n");
+	pci_assign_irqs(0, 0x10, pin_to_irq(usb1Pins));
+
+	// Standard usb components
+	printk_info("setting usb2\n");
+	pci_assign_irqs(0, 0x10, pin_to_irq(usb2Pins));
+
+	// Standard usb components
+	printk_info("setting usb3\n");
+	pci_assign_irqs(0, 0x11, pin_to_irq(usb3Pins));
+
+	// VT8237 + sound hardware
+	printk_info("setting audio\n");
+	pci_assign_irqs(0, 0x5, pin_to_irq(ac97Pins));
+	
+	// lan
+	printk_info("setting nic\n");
+	pci_assign_irqs(0, 0x10, pin_to_irq(nicPins));
+
+	// VGA
+	printk_info("setting vga\n");
+	pci_assign_irqs(1, 0x10, pin_to_irq(vgaPins));
+
+	// PCI slot
+	printk_info("setting pci slot\n");
+	pci_assign_irqs(0, 0x13, pin_to_irq(slotPins));
+
+	printk_spew("%s: DONE\n", __FUNCTION__);
+}
+
+/* 
+ * Set up the power management capabilities directly into ACPI mode.  This
+ * avoids having to handle any System Management Interrupts (SMI's) which I
+ * can't figure out how to do !!!!
+ */ 
+
+void setup_pm(device_t dev)
+{
+
+	// Set gen config 0
+	pci_write_config8(dev, 0x80, 0x20);
+
+	// Set ACPI base address to IO 0x400
+	pci_write_config16(dev, 0x88, ACPI_IO_BASE|1);
+	
+	// set ACPI irq to 5
+	pci_write_config8(dev, 0x82, 0x45);
+
+	// primary interupt channel
+	pci_write_config16(dev, 0x84, 0x30f2);
+
+	// throttle / stop clock control
+	pci_write_config8(dev, 0x8d, 0x18);
+
+	pci_write_config8(dev, 0x93, 0x88);
+	pci_write_config8(dev, 0x94, 0xb0);
+	pci_write_config8(dev, 0x95, 0xc0);
+	pci_write_config8(dev, 0x98, 0);
+	pci_write_config8(dev, 0x99, 0xea);
+	pci_write_config8(dev, 0xe4, 0x14);
+	pci_write_config8(dev, 0xe5, 0x08);
+
+
+	// Enable ACPI access (and setup like award)
+	pci_write_config8(dev, 0x81, 0xa0);
+
+	outw(0xffff, 0x400);
+	outw(0xffff, 0x420);
+	outw(0xffff, 0x428);
+	outl(0xffffffff, 0x430);
+	
+	outw(0x0, 0x424);
+	outw(0x0, 0x42a);
+	outw(0x1, 0x42c);
+	outl(0x0, 0x434);
+	outl(0x01, 0x438);
+	outb(0x0, 0x442);
+	outl(0xffff7fff, 0x448);
+	outw(0x001, 0x404);
+}
+
+/* This looks good enough to work, maybe */
+static void vt8237r_init(struct device *dev)
+{
+	unsigned char enables;
+	
+	printk_debug("vt8237r init\n");
+
+	// enable the internal I/O decode
+	enables = pci_read_config8(dev, 0x6C);
+	enables |= 0x80;
+	pci_write_config8(dev, 0x6C, enables);
+	
+	// Map 4MB of FLASH into the address space
+	pci_write_config8(dev, 0x41, 0x7f);
+	
+	// Set bit 6 of 0x40, because Award does it (IO recovery time)
+	// IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI 
+	// interrupts can be properly marked as level triggered.
+	enables = pci_read_config8(dev, 0x40);
+	enables |= 0x45;
+	pci_write_config8(dev, 0x40, enables);
+	
+	// Set 0x42 to 0xf0 to match Award bios
+	enables = pci_read_config8(dev, 0x42);
+	enables |= 0xf0;
+	pci_write_config8(dev, 0x42, enables);
+	
+	/* Set 0x58 to 0x03 to match Award */
+	pci_write_config8(dev, 0x58, 0x03);
+
+	/* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
+	enables = pci_read_config8(dev, 0x4f);
+	enables |= 0x08;
+	pci_write_config8(dev, 0x4f, enables);
+
+	// Set bit 3 of 0x4a, to match award (dummy pci request)
+	enables = pci_read_config8(dev, 0x4a);
+	enables |= 0x08;
+	pci_write_config8(dev, 0x4a, enables);
+	
+	// Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
+	enables = pci_read_config8(dev, 0x4f);
+	enables |= 0x08;
+	pci_write_config8(dev, 0x4f, enables);
+	
+	// Set 0x58 to 0x03 to match Award
+	pci_write_config8(dev, 0x58, 0x03);
+	
+	/* enable serial irq */
+	pci_write_config8(dev, 0x52, 0x9);
+
+	/* dma */
+	pci_write_config8(dev, 0x53, 0x00);
+
+	// Power management setup
+	setup_pm(dev);
+	
+	/* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
+	pci_write_config8(dev, 0x40, 0x54);
+	
+	// Start the rtc
+	rtc_init(0);
+}
+
+/* total kludge to get lxb to call our childrens set/enable functions - these are 
+   not called unless this device has a resource to set - so set a dummy one */
+void vt8237r_read_resources(device_t dev)
+{
+
+	struct resource *resource;
+	pci_dev_read_resources(dev);
+	resource = new_resource(dev, 1);
+	resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO | IORESOURCE_STORED;
+	resource->size = 2;
+	resource->base = 0x2e;
+
+}
+void vt8237r_set_resources(device_t dev)
+{
+	struct resource *resource;
+	resource = find_resource(dev,1);
+	resource->flags |= IORESOURCE_STORED;
+	pci_dev_set_resources(dev);
+}
+
+void vt8237r_enable_resources(device_t dev)
+{
+	/* vt8237r is not a pci bridge and has no resources of its own (other than 
+	   standard PC i/o addresses). however it does control the isa bus and so 
+	   we need to manually call enable childrens resources on that bus */
+	/* TODO: do we even care about ISA? If so, for what? SuperIO on LPC bus */
+	pci_dev_enable_resources(dev);
+	enable_childrens_resources(dev);
+}
+	
+static void southbridge_init(struct device *dev)
+{
+	vt8237r_init(dev);
+	pci_routing_fixup(dev);
+}
+
+static struct device_operations vt8237r_lpc_ops = {
+	.read_resources   = vt8237r_read_resources,
+	.set_resources    = vt8237r_set_resources,
+	.enable_resources = vt8237r_enable_resources,
+	.init             = &southbridge_init,
+	.scan_bus         = scan_static_bus,
+};
+
+static struct pci_driver lpc_driver __pci_driver = {
+	.ops    = &vt8237r_lpc_ops,
+	.vendor = PCI_VENDOR_ID_VIA,
+	.device = 0x3227,
+};
