Index: src/devices/hypertransport.c
===================================================================
--- src/devices/hypertransport.c.orig
+++ src/devices/hypertransport.c
@@ -279,20 +279,7 @@ static void ht_collapse_early_enumeratio
 		}
 		/* Has the link failed? */
 		if (ctrl & (1 << 4)) {
-			/*
-			 * Either the link has failed, or we have
-			 * a CRC error.
-			 * Sometimes this can happen due to link
-			 * retrain, so lets knock it down and see
-			 * if its transient
-			 */
-			ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
-			pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, ctrl);
-			ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
-			if (ctrl & ((1 << 4) | (1 << 8))) {
-				printk_alert("Detected error on Hypertransport Link\n");
-				return;
-			}
+			return;
 		}
 	} while((ctrl & (1 << 5)) == 0);
 
@@ -359,6 +346,8 @@ unsigned int hypertransport_scan_chain(s
 	struct ht_link prev;
 	device_t last_func = 0;
 	int ht_dev_num = 0;
+	unsigned temp_unitid;
+	unsigned not_use_count;
 
 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
         //let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE
@@ -396,25 +385,12 @@ unsigned int hypertransport_scan_chain(s
 		/* Wait until the link initialization is complete */
 		do {
 			ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
-
-			if (ctrl & (1 << 6))
-				goto end_of_chain;	// End of chain
-
-			if (ctrl & ((1 << 4) | (1 << 8))) {
-				/*
-				 * Either the link has failed, or we have
-				 * a CRC error.
-				 * Sometimes this can happen due to link
-				 * retrain, so lets knock it down and see
-				 * if its transient
-				 */
-				ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
-				pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, ctrl);
-				ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
-				if (ctrl & ((1 << 4) | (1 << 8))) {
-					printk_alert("Detected error on Hypertransport Link\n");
-					goto end_of_chain;
-				}
+			/* Is this the end of the hypertransport chain?
+			 * Has the link failed?
+			 * If so further scanning is pointless.
+			 */
+			if (ctrl & ((1 << 6) | (1 << 4))) {
+				goto end_of_chain;
 			}
 		} while((ctrl & (1 << 5)) == 0);
 		
@@ -449,39 +425,53 @@ unsigned int hypertransport_scan_chain(s
 		if (flags & 0x1f) {
 			break;
 		}
-
 		flags &= ~0x1f; /* mask out base Unit ID */
-                flags |= next_unitid & 0x1f;
+
+		count = (flags >> 5) & 0x1f; /* get unit count */
+		not_use_count = 0;
+		temp_unitid = next_unitid;
+#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+		if(offset_unitid) {
+			if((next_unitid+count)>=0x20) {
+		                temp_unitid = HT_CHAIN_END_UNITID_BASE;
+				//still use the old next_unitid
+				not_use_count = 1;
+			}
+
+		} 
+#endif
+
+                flags |= temp_unitid & 0x1f;
                 pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
 
 		/* Update the Unitd id in the device structure */
 		static_count = 1;
 		for(func = dev; func; func = func->sibling) {
-			func->path.u.pci.devfn += (next_unitid << 3);
+			func->path.u.pci.devfn += (temp_unitid << 3);
 			static_count = (func->path.u.pci.devfn >> 3) 
 				- (dev->path.u.pci.devfn >> 3) + 1;
 			last_func = func;
 		}
-
 		/* Compute the number of unitids consumed */
-		count = (flags >> 5) & 0x1f; /* get unit count */
 		printk_spew("%s count: %04x static_count: %04x\n", 
 			dev_path(dev), count, static_count);
 		if (count < static_count) {
 			count = static_count;
 		}
+		if(!not_use_count) 
+			next_unitid +=  count;
 
 		/* Update the Unitid of the next device */
-		ht_unitid_base[ht_dev_num] = next_unitid;
+		ht_unitid_base[ht_dev_num] = temp_unitid;
 		ht_dev_num++;
+
 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
 		if(offset_unitid) {
-	                real_last_unitid = next_unitid;
         	        real_last_pos = pos;
+			real_last_unitid = temp_unitid;
 			real_last_dev = dev;
 		}
 #endif
-		next_unitid += count;
 
 		/* Setup the hypetransport link */
 		bus->reset_needed |= ht_setup_link(&prev, dev, pos);
@@ -491,7 +481,7 @@ unsigned int hypertransport_scan_chain(s
 			dev->vendor, dev->device, 
 			(dev->enabled? "enabled": "disabled"), next_unitid);
 
-	} while((last_unitid != next_unitid) && (next_unitid <= (max_devfn >> 3)));
+	} while((last_unitid != next_unitid) && (next_unitid <= 0x1f/*(max_devfn >> 3)*/));
  end_of_chain:
 #if OPT_HT_LINK == 1
 	if(bus->reset_needed) {
@@ -503,7 +493,7 @@ unsigned int hypertransport_scan_chain(s
 #endif
 
 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-        if(offset_unitid && (ht_dev_num>0)) {
+        if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) ) {
                 uint16_t flags;
                 int i;
 		device_t last_func = 0;
@@ -511,21 +501,23 @@ unsigned int hypertransport_scan_chain(s
                 flags &= ~0x1f;
                 flags |= HT_CHAIN_END_UNITID_BASE & 0x1f;
                 pci_write_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS, flags);
-
                 for(func = real_last_dev; func; func = func->sibling) {
                         func->path.u.pci.devfn -= ((real_last_unitid - HT_CHAIN_END_UNITID_BASE) << 3);
 			last_func = func;
                 }
-		
 		ht_unitid_base[ht_dev_num-1] = HT_CHAIN_END_UNITID_BASE; // update last one
 		
                 next_unitid = real_last_unitid;
+		
         }
 #endif
 
 	if (next_unitid > 0x1f) {
 		next_unitid = 0x1f;
 	}
+	if( (bus->secondary == 0) && (next_unitid > 0x17)) { 
+		next_unitid = 0x17; // avoid K8 on bus 0
+	}
 
 	/* Die if any leftover Static devices are are found.  
 	 * There's probably a problem in the Config.lb.
@@ -543,7 +535,7 @@ unsigned int hypertransport_scan_chain(s
 	/* Now that nothing is overlapping it is safe to scan the
 	 * children. 
 	 */
-	max = pci_scan_bus(bus, 0x00, (next_unitid << 3)|7, max); 
+	max = pci_scan_bus(bus, 0x00, ((next_unitid-1) << 3)|7, max); 
 	return max; 
 }
 
Index: src/include/cpu/x86/bist.h
===================================================================
--- src/include/cpu/x86/bist.h.orig
+++ src/include/cpu/x86/bist.h
@@ -4,7 +4,7 @@
 static void report_bist_failure(unsigned long bist)
 {
 	if (bist != 0) {
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
                 printk_emerg("BIST failed: %08x", bist);
 #else
 		print_emerg("BIST failed: ");
Index: src/cpu/amd/model_fxx/init_cpus.c
===================================================================
--- src/cpu/amd/model_fxx/init_cpus.c.orig
+++ src/cpu/amd/model_fxx/init_cpus.c
@@ -356,7 +356,6 @@ static unsigned init_cpus(unsigned cpu_i
 		return bsp_apicid;
 }
 
-#if CONFIG_LOGICAL_CPUS == 1
 
 static unsigned is_core0_started(unsigned nodeid)
 {
@@ -383,4 +382,3 @@ static void wait_all_core0_started(void)
 
 }
 
-#endif
Index: src/cpu/x86/32bit/entry32.inc
===================================================================
--- src/cpu/x86/32bit/entry32.inc.orig
+++ src/cpu/x86/32bit/entry32.inc
@@ -19,11 +19,11 @@ gdtptr:
 
 	/* selgdt 0x08, flat code segment */
 	.word	0xffff, 0x0000		
-	.byte	0x00, 0x9b, 0xcf, 0x00	
+	.byte	0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */	
 
 	/* selgdt 0x10,flat data segment */
 	.word	0xffff, 0x0000		
-	.byte	0x00, 0x93, 0xcf, 0x00	
+	.byte	0x00, 0x93, 0xcf, 0x00
 
 gdt_end:
 	
Index: src/cpu/x86/mtrr/earlymtrr.c
===================================================================
--- src/cpu/x86/mtrr/earlymtrr.c.orig
+++ src/cpu/x86/mtrr/earlymtrr.c
@@ -42,6 +42,7 @@ static void set_var_mtrr(
 
 {
 	/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
+	/* FIXME: It only support 4G less range */
 	msr_t basem, maskm;
 	basem.lo = base | type;
 	basem.hi = 0;
Index: src/cpu/x86/mtrr/mtrr.c
===================================================================
--- src/cpu/x86/mtrr/mtrr.c.orig
+++ src/cpu/x86/mtrr/mtrr.c
@@ -282,10 +282,16 @@ static void set_fixed_mtrr_resource(void
 	
 }
 
+#ifndef CONFIG_VAR_MTRR_HOLE
+#define CONFIG_VAR_MTRR_HOLE 1
+#endif
+
 struct var_mtrr_state {
 	unsigned long range_startk, range_sizek;
 	unsigned int reg;
+#if CONFIG_VAR_MTRR_HOLE
 	unsigned long hole_startk, hole_sizek;
+#endif
 	unsigned address_bits;
 };
 
@@ -304,29 +310,40 @@ void set_var_mtrr_resource(void *gp, str
 	if ((basek <= 1024) || (state->range_startk + state->range_sizek == basek)) {
 		unsigned long endk = basek + sizek;
 		state->range_sizek = endk - state->range_startk;
+		printk_spew("1 state range_startk=%08x, range_sizek=%08x, hole_startk=%08x, hole_sizek=%08x\n",
+                                state->range_startk, state->range_sizek, state->hole_startk, state->hole_sizek);
+
 		return;
 	}
 	/* Write the range mtrrs */
 	if (state->range_sizek != 0) {
+#if CONFIG_VAR_MTRR_HOLE
 		if (state->hole_sizek == 0) {
 			/* We need to put that on to hole */
 			unsigned long endk = basek + sizek;
 			state->hole_startk = state->range_startk + state->range_sizek;
 			state->hole_sizek  = basek - state->hole_startk;
 			state->range_sizek = endk - state->range_startk;
+			printk_spew("2 state range_startk=%08x, range_sizek=%08x, hole_startk=%08x, hole_sizek=%08x\n",
+				state->range_startk, state->range_sizek, state->hole_startk, state->hole_sizek);
 			return;
 		}
+#endif
 		state->reg = range_to_mtrr(state->reg, state->range_startk, 
 			state->range_sizek, basek, MTRR_TYPE_WRBACK, state->address_bits);
+#if CONFIG_VAR_MTRR_HOLE
 		state->reg = range_to_mtrr(state->reg, state->hole_startk, 
 			state->hole_sizek, basek,  MTRR_TYPE_UNCACHEABLE, state->address_bits);
+#endif
 		state->range_startk = 0;
 		state->range_sizek = 0;
+#if CONFIG_VAR_MTRR_HOLE
                 state->hole_startk = 0;
                 state->hole_sizek = 0;
+#endif
 	}
 	/* Allocate an msr */  
-	printk_spew(" Allocate an msr - basek = %d, sizek = %d,\n", basek, sizek);
+	printk_spew(" Allocate an msr - basek = %08x, sizek = %08x,\n", basek, sizek);
 	state->range_startk = basek;
 	state->range_sizek  = sizek;
 }
@@ -377,8 +394,10 @@ void x86_setup_var_mtrrs(unsigned addres
 	 */
 	var_state.range_startk = 0;
 	var_state.range_sizek = 0;
+#if CONFIG_VAR_MTRR_HOLE
 	var_state.hole_startk = 0;
 	var_state.hole_sizek = 0;
+#endif
 	var_state.reg = 0;
 	var_state.address_bits = address_bits;
 	search_global_resources(
@@ -386,14 +405,19 @@ void x86_setup_var_mtrrs(unsigned addres
 		set_var_mtrr_resource, &var_state);
 
 	/* Write the last range */
+	printk_spew("3 state range_startk=%08x, range_sizek=%08x, hole_startk=%08x, hole_sizek=%08x\n",
+                                var_state.range_startk, var_state.range_sizek, var_state.hole_startk, var_state.hole_sizek);
 	var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk, 
 		var_state.range_sizek, 0, MTRR_TYPE_WRBACK, var_state.address_bits);
+#if CONFIG_VAR_MTRR_HOLE
 	var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk,
 		var_state.hole_sizek,  0, MTRR_TYPE_UNCACHEABLE, var_state.address_bits);
+#endif
 	printk_debug("DONE variable MTRRs\n");
 	printk_debug("Clear out the extra MTRR's\n");
 	/* Clear out the extra MTRR's */
 	while(var_state.reg < MTRRS) {
+		printk_spew("clearing var_state.reg=%d\n", var_state.reg);
 		set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
 	}
 	printk_spew("call enable_var_mtrr()\n");
Index: src/cpu/x86/lapic/lapic_cpu_init.c
===================================================================
--- src/cpu/x86/lapic/lapic_cpu_init.c.orig
+++ src/cpu/x86/lapic/lapic_cpu_init.c
@@ -13,6 +13,13 @@
 #include <smp/atomic.h>
 #include <smp/spinlock.h>
 #include <cpu/cpu.h>
+#include <cpu/x86/tsc.h>
+
+static inline void print_debug_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2)
+{
+        printk_debug("%s[%02x]=%08x%08x\n", str, i, val, val2);
+
+}
 
 #if CONFIG_SMP == 1
 
@@ -374,6 +381,7 @@ void initialize_cpus(struct bus *cpu_bus
 {
 	struct device_path cpu_path;
 	struct cpu_info *info;
+	tsc_t tsc;
 
 	/* Find the info struct for this cpu */
 	info = cpu_info();
@@ -400,6 +408,9 @@ void initialize_cpus(struct bus *cpu_bus
 	
         cpus_ready_for_init(); 
 
+        tsc = rdtsc();
+        print_debug_tsc_x("\nFinal              : tsc ", 10,  tsc.hi, tsc.lo);
+
 #if CONFIG_SMP == 1
 	#if SERIAL_CPU_INIT == 0
 	/* start all aps at first, so we can init ECC all together */
@@ -419,6 +430,8 @@ void initialize_cpus(struct bus *cpu_bus
 	/* Now wait the rest of the cpus stop*/
 	wait_other_cpus_stop(cpu_bus);
 #endif
+        tsc = rdtsc();
+        print_debug_tsc_x("\nFinal              : tsc ", 11,  tsc.hi, tsc.lo);
 
 }
 
Index: src/northbridge/amd/amdk8/coherent_ht.c
===================================================================
--- src/northbridge/amd/amdk8/coherent_ht.c.orig
+++ src/northbridge/amd/amdk8/coherent_ht.c
@@ -1,10 +1,3 @@
-#if USE_DCACHE_RAM
-
-#include "coherent_ht_car.c"
-
-#else
-
-
 /* coherent hypertransport initialization for AMD64 
  * 
  * written by Stefan Reinauer <stepan@openbios.org>
@@ -74,6 +67,7 @@
 #include <device/pci_ids.h>
 #include <device/hypertransport_def.h>
 #include "arch/romcc_io.h"
+
 #include "amdk8.h"
 
 #define enable_bsp_routing()	enable_routing(0)
@@ -84,8 +78,6 @@
 
 #define DEFAULT 0x00010101	/* default row entry */
 
-typedef uint8_t u8;
-typedef uint32_t u32;
 
 #ifndef CROSS_BAR_47_56
 	#define CROSS_BAR_47_56 0
@@ -101,21 +93,25 @@ typedef uint32_t u32;
 
 #ifndef K8_HT_CHECK_PENDING_LINK
 	#if CONFIG_MAX_PHYSICAL_CPUS >= 4
-	#define K8_HT_CHECK_PENDING_LINK 1
+		#define K8_HT_CHECK_PENDING_LINK 1
 	#else
-	#define K8_HT_CHECK_PENDING_LINK 0
+		#define K8_HT_CHECK_PENDING_LINK 0
 	#endif
 #endif
 
 #ifndef CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
-#define CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED 0
+	#define CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED 0
+#endif
+
+#ifndef ENABLE_APIC_EXT_ID
+        #define ENABLE_APIC_EXT_ID 0
 #endif
 
 
 static inline void print_linkn (const char *strval, uint8_t byteval) 
 {
 #if 1
-#if CONFIG_USE_INIT
+#if CONFIG_USE_PRINTK_IN_CAR
 	printk_debug("%s%02x\r\n", strval, byteval); 
 #else
 	print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n");
@@ -162,6 +158,19 @@ static void disable_probes(void)
 
 }
 
+static void enable_apic_ext_id(u8 node) 
+{
+#if ENABLE_APIC_EXT_ID==1
+#warning "FIXME Is the right place to enable apic ext id here?"
+
+      u32 val;
+
+        val = pci_read_config32(NODE_HT(node), 0x68);
+        val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
+        pci_write_config32(NODE_HT(node), 0x68, val);
+#endif
+}
+
 static void enable_routing(u8 node)
 {
 	u32 val;
@@ -199,17 +208,6 @@ static void enable_routing(u8 node)
 	print_spew(" done.\r\n");
 }
 
-static void enable_apic_ext_id(u8 node)
-{
-
-	u32 val;
-
-        val = pci_read_config32(NODE_HT(node), 0x68);
-        val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
-        pci_write_config32(NODE_HT(node), 0x68, val);
-}
-
-
 static void fill_row(u8 node, u8 row, u32 value)
 {
 	pci_write_config32(NODE_HT(node), 0x40+(row<<2), value);
@@ -259,23 +257,6 @@ static void rename_temp_node(u8 node)
 
 	print_spew(" done.\r\n");
 }
-#if K8_HT_CHECK_PENDING_LINK == 1
-static void wait_ht_stable(uint8_t node)
-{       
-        uint8_t linkn;
-        for(linkn = 0; linkn<3; linkn++) {
-                uint8_t regpos;
-                uint16_t i;
-                uint32_t reg;
-                regpos = 0x98 + 0x20 * linkn;
-                for(i = 0; i < 0xff; i++) { //wait to make sure it is done
-                        reg = pci_read_config32(NODE_HT(node), regpos);
-                        if ((reg & 0x10) == 0) break; // init complete
-                        udelay(10);
-                } 
-        }
-}
-#endif
 
 static int verify_connection(u8 dest)
 {
@@ -293,18 +274,23 @@ static int verify_connection(u8 dest)
 	return 1;
 }
 
-static unsigned read_freq_cap(device_t dev, unsigned pos)
+static uint16_t read_freq_cap(device_t dev, uint8_t pos)
 {
 	/* Handle bugs in valid hypertransport frequency reporting */
-	unsigned freq_cap;
+	uint16_t freq_cap;
 	uint32_t id;
 
 	freq_cap = pci_read_config16(dev, pos);
 	freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
 
-	if (!is_cpu_pre_e0()) {
+#if K8_HT_FREQ_1G_SUPPORT == 1
+    #if K8_REV_F_SUPPORT == 0
+	if (!is_cpu_pre_e0())
+    #endif 
+	{
 		return freq_cap;
 	}
+#endif
 
 	id = pci_read_config32(dev, 0);
 
@@ -320,8 +306,8 @@ static int optimize_connection(device_t 
 {
 	static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
 	static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
-	uint16_t freq_cap1, freq_cap2, freq_cap, freq_mask;
-	uint8_t width_cap1, width_cap2, width_cap, width, old_width, ln_width1, ln_width2;
+	uint16_t freq_cap1, freq_cap2;
+	uint8_t width_cap1, width_cap2, width, old_width, ln_width1, ln_width2;
 	uint8_t freq, old_freq;
 	int needs_reset;
 	/* Set link width and frequency */
@@ -369,6 +355,7 @@ static int optimize_connection(device_t 
 	
 	/* See if I am changing node1's width */
 	old_width = pci_read_config8(node1, link1 + PCI_HT_CAP_HOST_WIDTH + 1);
+	old_width &= 0x77;	
 	needs_reset |= old_width != width;
 
 	/* Set node1's widths */
@@ -379,10 +366,12 @@ static int optimize_connection(device_t 
 
 	/* See if I am changing node2's width */
 	old_width = pci_read_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH + 1);
+	old_width &= 0x77;
 	needs_reset |= old_width != width;
 
 	/* Set node2's widths */
 	pci_write_config8(node2, link2 + PCI_HT_CAP_HOST_WIDTH + 1, width);
+
 	return needs_reset;
 }
 
@@ -676,11 +665,6 @@ static void setup_uniprocessor(void)
 	disable_probes();
 }
 
-struct setup_smp_result {
-	int nodes;
-	int needs_reset;
-};
-
 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 static int optimize_connection_group(const u8 *opt_conn, int num) {
 	int needs_reset = 0;
@@ -695,21 +679,20 @@ static int optimize_connection_group(con
 #endif
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-static struct setup_smp_result setup_smp2(void)
+static unsigned setup_smp2(void)
 {
-	struct setup_smp_result result;
+	unsigned nodes;
 	u8 byte;
 	uint32_t val;
-	result.nodes = 2;
-	result.needs_reset = 0;
+	nodes = 2;
 
 	setup_row_local(0, 0); /* it will update the broadcast RT*/
 	
 	val = get_row(0,0);
 	byte = (val>>16) & 0xfe;
 	if(byte<0x2) { /* no coherent connection so get out.*/
-		result.nodes = 1;
-		return result;
+		nodes = 1;
+		return nodes;
 	}
 
 	/* Setup and check a temporary connection to node 1 */
@@ -766,24 +749,19 @@ static struct setup_smp_result setup_smp
 	clear_temp_row(0);
 #endif
 
-	result.needs_reset |= optimize_connection(
-		NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)),
-		NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) );
-
-	return result;
+	return nodes;
 }
 #endif /*CONFIG_MAX_PHYSICAL_CPUS > 1 */
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 
-static struct setup_smp_result setup_smp4(int needs_reset)
+static unsigned setup_smp4(void)
 {
-	struct setup_smp_result result;
+	unsigned nodes;
 	u8 byte;
 	uint32_t val;
 
-	result.nodes=4;
-	result.needs_reset = needs_reset;
+	nodes=4;
 
 	/* Setup and check temporary connection from Node 0 to Node 2 */
 	val = get_row(0,0);
@@ -791,8 +769,8 @@ static struct setup_smp_result setup_smp
 	byte = get_linkn_last_count(byte);
 
 	if((byte>>2)==0) { /* We should have two coherent for 4p and above*/
-		result.nodes = 2;
-		return result;
+		nodes = 2;
+		return nodes;
 	}
 
 	byte &= 3; /* bit [3,2] is count-1*/
@@ -940,16 +918,7 @@ static struct setup_smp_result setup_smp
 	clear_temp_row(1);
 #endif
 
-	/* optimize physical connections - by LYH */
-	static const u8 opt_conn4[] = {
-		0,2,
-		1,3,
-		2,3,
-	};
-
-	result.needs_reset |= optimize_connection_group(opt_conn4, sizeof(opt_conn4)/sizeof(opt_conn4[0]));
-
-	return result;
+	return nodes;
 
 }
 
@@ -957,14 +926,13 @@ static struct setup_smp_result setup_smp
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 4
 
-static struct setup_smp_result setup_smp6(int needs_reset)
+static unsigned setup_smp6(void)
 {
-	struct setup_smp_result result;
+	unsigned nodes;
 	u8 byte;
 	uint32_t val;
 
-	result.nodes=6;
-	result.needs_reset = needs_reset;
+	nodes=6;
 
 	/* Setup and check temporary connection from Node 0 to Node 4  through 2*/
         val = get_row(2,2);
@@ -972,8 +940,8 @@ static struct setup_smp_result setup_smp
         byte = get_linkn_last_count(byte);
 
         if((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/
-                result.nodes = 4;
-                return result;
+                nodes = 4;
+                return nodes;
         }
 
 	/* Setup and check temporary connection from Node 0 to Node 5  through 1, 3*/
@@ -982,8 +950,8 @@ static struct setup_smp_result setup_smp
         byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1);
         byte = get_linkn_last_count(byte);
         if((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/
-                result.nodes = 4;
-                return result;
+                nodes = 4;
+                return nodes;
         }
 	
 	/* We found 6 nodes so far. Now setup all nodes for 6p */
@@ -1153,17 +1121,7 @@ static struct setup_smp_result setup_smp
 	}
 #endif
 
-	/* optimize physical connections - by LYH */
-	static const uint8_t opt_conn6[] ={
-		2, 4,
-		3, 5,
-#if !CROSS_BAR_47_56
-		4, 5,
-#endif
-	}; 
-	result.needs_reset |= optimize_connection_group(opt_conn6, sizeof(opt_conn6)/sizeof(opt_conn6[0]));
-
-	return result;
+	return nodes;
 
 }
 
@@ -1171,14 +1129,13 @@ static struct setup_smp_result setup_smp
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 6
 
-static struct setup_smp_result setup_smp8(int needs_reset)
+static unsigned setup_smp8(void)
 {
-	struct setup_smp_result result;
+	unsigned nodes;
 	u8 byte;
 	uint32_t val;
 
-	result.nodes=8;
-	result.needs_reset = needs_reset;
+	nodes=8;
 
 	/* Setup and check temporary connection from Node 0 to Node 6 via 2 and 4 to 7 */
 	val = get_row(4,4);
@@ -1188,16 +1145,16 @@ static struct setup_smp_result setup_smp
 	byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
         byte = get_linkn_last_count(byte); /* Max link to 6*/
         if((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/
-                result.nodes = 6;
-                return result;
+                nodes = 6;
+                return nodes;
         }
 #endif
 
 #if CROSS_BAR_47_56 
 	byte = get_linkn_last_count(byte); /* Max link to 6*/
 	if((byte>>2)<2) { /* We should have two or three coherent links on node 4 for 8p*/
-		result.nodes = 6;
-		return result;
+		nodes = 6;
+		return nodes;
 	}
 #if TRY_HIGH_FIRST == 1
 	byte = ((val>>16) & 0xfe) - link_connection(4,2);
@@ -1215,8 +1172,8 @@ static struct setup_smp_result setup_smp
         byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3);
         byte = get_linkn_last_count(byte);
         if((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/
-                result.nodes = 6;
-                return result;
+                nodes = 6;
+                return nodes;
         }
 #endif
 
@@ -1232,6 +1189,7 @@ static struct setup_smp_result setup_smp
 		3, 6,
 		/*3, 7,*/
 		/*4, 7,*/
+		5, 6,
 #else
 		0, 6, 2, 0,
 		/*0, 7, 2, 0,*/
@@ -1513,19 +1471,7 @@ static struct setup_smp_result setup_smp
 /* ready to enable RT for Node 7 */
 	enable_routing(7);      /* enable routing on node 7 (temp.) */
 
-	static const uint8_t opt_conn8[] ={
-		4, 6,
-#if CROSS_BAR_47_56
-		4, 7,
-		5, 6,
-#endif
-		5, 7,
-		6, 7,
-	};
-	/* optimize physical connections - by LYH */
-	result.needs_reset |= optimize_connection_group(opt_conn8, sizeof(opt_conn8)/sizeof(opt_conn8[0]));
-
-	return result;
+	return nodes;
 }
 
 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 6 */
@@ -1533,36 +1479,36 @@ static struct setup_smp_result setup_smp
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 
-static struct setup_smp_result setup_smp(void)
+static unsigned setup_smp(void)
 {
-	struct setup_smp_result result;
+	unsigned nodes;
 
 	print_spew("Enabling SMP settings\r\n");
 		
-	result = setup_smp2();
+	nodes = setup_smp2();
 #if CONFIG_MAX_PHYSICAL_CPUS > 2
-	if(result.nodes == 2) 
-		result = setup_smp4(result.needs_reset);
+	if(nodes == 2) 
+		nodes = setup_smp4();
 #endif
 	
 #if CONFIG_MAX_PHYSICAL_CPUS > 4
-	if(result.nodes == 4)
-		result = setup_smp6(result.needs_reset);
+	if(nodes == 4)
+		nodes = setup_smp6();
 #endif
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 6
-	if(result.nodes == 6) 
-		result = setup_smp8(result.needs_reset);
+	if(nodes == 6) 
+		nodes = setup_smp8();
 #endif
 
-#if CONFIG_USE_INIT
-	printk_debug("%02x nodes initialized.\r\n", result.nodes);
+#if CONFIG_USE_PRINTK_IN_CAR
+	printk_debug("%02x nodes initialized.\r\n", nodes);
 #else
-	print_debug_hex8(result.nodes);
+	print_debug_hex8(nodes);
 	print_debug(" nodes initialized.\r\n");
 #endif
 	
-	return result;
+	return nodes;
 }
 
 static unsigned verify_mp_capabilities(unsigned nodes)
@@ -1601,7 +1547,7 @@ static void clear_dead_routes(unsigned n
 {
 	int last_row;
 	int node, row;
-#if CONFIG_MAX_PHYSICAL_CPUS > 6
+#if CONFIG_MAX_PHYSICAL_CPUS == 8
 	if(nodes==8) return;/* don't touch (7,7)*/
 #endif
 	last_row = nodes;
@@ -1625,9 +1571,9 @@ static void clear_dead_routes(unsigned n
 }
 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */
 
-static unsigned count_cpus(unsigned nodes)
-{
 #if CONFIG_LOGICAL_CPUS==1
+static unsigned verify_dualcore(unsigned nodes)
+{
 	unsigned node, totalcpus, tmp;
 
 	totalcpus = 0;
@@ -1637,25 +1583,27 @@ static unsigned count_cpus(unsigned node
 	}
 
 	return totalcpus;
-#else
-	return nodes;
-#endif
 		
 }
-static inline unsigned get_nodes(void)
-{
-        return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
-}
+#endif
 
 static void coherent_ht_finalize(unsigned nodes)
 {
-	unsigned total_cpus;
-	unsigned cpu_node_count;
 	unsigned node;
+#if K8_REV_F_SUPPORT == 0
 	int rev_a0;
-	total_cpus = count_cpus(nodes);
-	cpu_node_count = ((total_cpus -1)<<16)|((nodes - 1) << 4);
+#endif
+#if CONFIG_LOGICAL_CPUS==1
+	unsigned total_cpus;
 
+	if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */
+		total_cpus = verify_dualcore(nodes);
+	}
+	else {
+		total_cpus = nodes;
+	}
+#endif
+	
 	/* set up cpu count and node count and enable Limit
 	 * Config Space Range for all available CPUs.
 	 * Also clear non coherent hypertransport bus range
@@ -1663,7 +1611,9 @@ static void coherent_ht_finalize(unsigne
 	 */
 
 	print_spew("coherent_ht_finalize\r\n");
+#if K8_REV_F_SUPPORT == 0
 	rev_a0 = is_cpu_rev_a0();
+#endif
 	for (node = 0; node < nodes; node++) {
 		device_t dev;
 		uint32_t val;
@@ -1672,7 +1622,11 @@ static void coherent_ht_finalize(unsigne
 		/* Set the Total CPU and Node count in the system */
 		val = pci_read_config32(dev, 0x60);
 		val &= (~0x000F0070);
-		val |= cpu_node_count;
+#if CONFIG_LOGICAL_CPUS==1
+		val |= ((total_cpus-1)<<16)|((nodes-1)<<4);
+#else
+		val |= ((nodes-1)<<16)|((nodes-1)<<4);
+#endif
 		pci_write_config32(dev, 0x60, val);
 
 		/* Only respond to real cpu pci configuration cycles
@@ -1688,23 +1642,27 @@ static void coherent_ht_finalize(unsigne
 			(3 << HTTC_HI_PRI_BYP_CNT_SHIFT);
 		pci_write_config32(dev, HT_TRANSACTION_CONTROL, val);
 
+#if K8_REV_F_SUPPORT == 0
 		if (rev_a0) {
 			pci_write_config32(dev, 0x94, 0);
 			pci_write_config32(dev, 0xb4, 0);
 			pci_write_config32(dev, 0xd4, 0);
 		}
+#endif
 	}
 
 	print_spew("done\r\n");
 }
 
-static int apply_cpu_errata_fixes(unsigned nodes, int needs_reset)
+static int apply_cpu_errata_fixes(unsigned nodes)
 {
 	unsigned node;
+	int needs_reset = 0;
 	for(node = 0; node < nodes; node++) {
 		device_t dev;
 		uint32_t cmd;
 		dev = NODE_MC(node);
+#if K8_REV_F_SUPPORT == 0
 		if (is_cpu_pre_c0()) {
 
 			/* Errata 66
@@ -1746,13 +1704,15 @@ static int apply_cpu_errata_fixes(unsign
 				needs_reset = 1; /* Needed? */
 			}
 		}
+#endif
 	}
 	return needs_reset;
 }
 
-static int optimize_link_read_pointers(unsigned nodes, int needs_reset)
+static int optimize_link_read_pointers(unsigned nodes)
 {
 	unsigned node;
+	int needs_reset = 0;
 	for(node = 0; node < nodes; node++) {
 		device_t f0_dev, f3_dev;
 		uint32_t cmd_ref, cmd;
@@ -1782,58 +1742,98 @@ static int optimize_link_read_pointers(u
 	return needs_reset;
 }
 
-static void startup_other_cores(unsigned nodes)
+static inline unsigned get_nodes(void)
 {
-	unsigned node;
-	for(node = 0; node < nodes; node++) {
-		device_t dev;
-		unsigned siblings;
-		dev = NODE_MC(node);
-		siblings = (pci_read_config32(dev, 0xe8) >> 12) & 0x3;
-
-		if (siblings) {
-			device_t dev_f0;
-			unsigned val;
-			/* Redirect all MC4 accesses and error logging to core0 */
-			val = pci_read_config32(dev, 0x44);
-			val |= (1 << 27); //NbMcaToMstCpuEn bit
-			pci_write_config32(dev, 0x44, val);
-
-			/* Enable the second core */
-			dev_f0 = NODE_HT(node);
-			val = pci_read_config32(dev_f0, 0x68);
-			val |= ( 1 << 5);
-			pci_write_config32(dev_f0, 0x68, val);
-		}
-	}
+        return ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60)>>4) & 7) + 1;
 }
 
+static int optimize_link_coherent_ht(void)
+{
+        int needs_reset = 0;
+
+        unsigned nodes;
 
+        nodes = get_nodes();
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+        if(nodes>1) {
+                needs_reset |= optimize_connection(
+                        NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)),
+                        NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) );
+        }
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 2
+        if(nodes>2) {
+        /* optimize physical connections - by LYH */
+                static const u8 opt_conn4[] = {
+                        0,2,
+                        1,3,
+                        2,3,
+                };
+                needs_reset |= optimize_connection_group(opt_conn4, sizeof(opt_conn4)/sizeof(opt_conn4[0]));
+        }
+#endif
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 4
+        if(nodes>4) {
+                static const uint8_t opt_conn6[] ={
+                        2, 4,
+                        3, 5,
+        #if !CROSS_BAR_47_56
+                        4, 5,
+        #endif
+                };
+                needs_reset |= optimize_connection_group(opt_conn6, sizeof(opt_conn6)/sizeof(opt_conn6[0]));
+        }
+#endif
+
+#if CONFIG_MAX_PHYSICAL_CPUS > 6
+        if(nodes>6) {
+               static const uint8_t opt_conn8[] ={
+                       4, 6,
+        #if CROSS_BAR_47_56
+                       4, 7,
+                       5, 6,
+        #endif
+                       5, 7,
+                       6, 7,
+               };
+                needs_reset |= optimize_connection_group(opt_conn8, sizeof(opt_conn8)/sizeof(opt_conn8[0]));
+        }
+#endif
+
+#endif
+
+        needs_reset |= apply_cpu_errata_fixes(nodes);
+        needs_reset |= optimize_link_read_pointers(nodes);
+
+        return needs_reset;
+}
+
+#if RAMINIT_SYSINFO == 1
+static void setup_coherent_ht_domain(void)
+#else
 static int setup_coherent_ht_domain(void)
+#endif
 {
-	struct setup_smp_result result;
-	result.nodes = 1;
-	result.needs_reset = 0;
-
-#if K8_HT_CHECK_PENDING_LINK == 1 
-	//needed?
-        wait_ht_stable(0);
-#endif	
+	unsigned nodes;
+	nodes = 1;
+
 	enable_bsp_routing();
 
 #if CONFIG_MAX_PHYSICAL_CPUS > 1
-	result = setup_smp();
-	result.nodes = verify_mp_capabilities(result.nodes);
-	clear_dead_routes(result.nodes);
+        nodes = setup_smp();
+        nodes = verify_mp_capabilities(nodes);
+        clear_dead_routes(nodes);
 #endif
-	if (result.nodes == 1) {
+
+	if (nodes == 1) {
 		setup_uniprocessor();
 	}
-	coherent_ht_finalize(result.nodes);
-	startup_other_cores(result.nodes);
-	result.needs_reset = apply_cpu_errata_fixes(result.nodes, result.needs_reset);
-	result.needs_reset = optimize_link_read_pointers(result.nodes, result.needs_reset);
-	return result.needs_reset;
-}
+	coherent_ht_finalize(nodes);
 
+#if RAMINIT_SYSINFO == 0
+	return optimize_link_coherent_ht();
 #endif
+}
+
Index: src/northbridge/amd/amdk8/raminit.c
===================================================================
--- src/northbridge/amd/amdk8/raminit.c.orig
+++ src/northbridge/amd/amdk8/raminit.c
@@ -485,6 +485,14 @@ static void sdram_set_registers(const st
 	 * [31:26] Reserved
 	 */
 	PCI_ADDR(0, 0x18, 2, 0x98), 0xfc00ffff, 0x00000000,
+	/* MCA NB Status Low reg */
+	PCI_ADDR(0, 0x18, 3, 0x48), 0x00f00000, 0x00000000,
+	/* MCA NB Status high reg */
+	PCI_ADDR(0, 0x18, 3, 0x4c), 0x01801e8c, 0x00000000,
+	/* MCA NB address Low reg */
+	PCI_ADDR(0, 0x18, 3, 0x50), 0x00000007, 0x00000000,
+	/* MCA NB address high reg */
+	PCI_ADDR(0, 0x18, 3, 0x54), 0xffffff00, 0x00000000,
 	/* DRAM Scrub Control Register
 	 * F3:0x58
 	 * [ 4: 0] DRAM Scrube Rate
@@ -2334,6 +2342,16 @@ static void sdram_enable(int controllers
 	/* And if necessary toggle the the reset on the dimms by hand */
 	memreset(controllers, ctrl);
 
+	/* We need to wait a mimmium of 20 MEMCLKS to enable the  InitDram */
+#if 0
+	print_debug("prepare to InitDram:");
+	for(i=0; i<100; i++) {
+		print_debug_hex32(i);
+		print_debug("\b\b\b\b\b\b\b\b");
+	}
+	print_debug("\r\n");
+#endif
+
 	for(i = 0; i < controllers; i++) {
 		uint32_t dcl, dch;
 		if (!controller_present(ctrl + i))
Index: src/northbridge/amd/amdk8/northbridge.c
===================================================================
--- src/northbridge/amd/amdk8/northbridge.c.orig
+++ src/northbridge/amd/amdk8/northbridge.c
@@ -103,12 +103,6 @@ static unsigned int amdk8_nodeid(device_
 
 static unsigned int amdk8_scan_chain(device_t dev, unsigned nodeid, unsigned link, unsigned sblink, unsigned int max, unsigned offset_unitid)
 {
-#if 0
-	printk_debug("%s amdk8_scan_chains max: %d starting...\n", 
-		dev_path(dev), max);
-#endif
-//	I want to put sb chain in bus 0 can I?
-
 	 
 		uint32_t link_type;
 		int i;
@@ -212,10 +206,6 @@ static unsigned int amdk8_scan_chain(dev
 			((dev->link[link].subordinate) << 24);
 		f1_write_config32(config_reg, config_busses);
 
-#if 0
-		printk_debug("%s Hyper transport scan link: %d max: %d\n", 
-			dev_path(dev), link, max);
-#endif
 		/* Now we can scan all of the subordinate busses i.e. the
 		 * chain on the hypertranport link 
 		 */
@@ -224,11 +214,6 @@ static unsigned int amdk8_scan_chain(dev
 		}
 		max = hypertransport_scan_chain(&dev->link[link], 0, 0xbf, max, ht_unitid_base, offset_unitid);
 
-#if 0
-		printk_debug("%s Hyper transport scan link: %d new max: %d\n",
-			dev_path(dev), link, max);
-#endif		
-
 		/* We know the number of busses behind this bridge.  Set the
 		 * subordinate bus number to it's real value
 		 */
@@ -254,11 +239,6 @@ static unsigned int amdk8_scan_chain(dev
 
 		}
 
-#if 0
-		printk_debug("%s Hypertransport scan link: %d done\n",
-			dev_path(dev), link);
-#endif
-
 	return max;
 }
 
@@ -271,11 +251,6 @@ static unsigned int amdk8_scan_chains(de
         nodeid = amdk8_nodeid(dev);
 	
 
-#if 0
-        printk_debug("%s amdk8_scan_chains max: %d starting...\n",
-                dev_path(dev), max);
-#endif
-//      I want to put sb chain in bus 0 
 
         if(nodeid==0) {
                 sblink = (pci_read_config32(dev, 0x64)>>8) & 3;
@@ -301,10 +276,6 @@ static unsigned int amdk8_scan_chains(de
 
 		max = amdk8_scan_chain(dev, nodeid, link, sblink, max, offset_unitid);
         }
-#if 0
-        printk_debug("%s amdk8_scan_chains max: %d done\n",
-                dev_path(dev), max);
-#endif
         return max;
 }
 
@@ -332,12 +303,7 @@ static int reg_useable(unsigned reg, 
 			result = 1;
 		}
 	}
-#if 0
-	printk_debug("reg: %02x result: %d gnodeid: %u glink: %u nodeid: %u link: %u\n",
-		reg, result, 
-		goal_nodeid, goal_link, 
-		nodeid, link);
-#endif
+
 	return result;
 }
 
@@ -1258,7 +1224,7 @@ static unsigned int cpu_bus_scan(device_
 		if (dev && dev->enabled) {
 			j = pci_read_config32(dev, 0xe8);
 			j = (j >> 12) & 3; // dev is func 3
-			printk_debug("  %s siblings=%d\r\n", dev_path(dev), j);
+			printk_debug("  %s siblings=%d\n", dev_path(dev), j);
 
 			if(nb_cfg_54) {
 				// For e0 single core if nb_cfg_54 is set, apicid will be 0, 2, 4.... 
Index: src/northbridge/amd/amdk8/early_ht.c
===================================================================
--- src/northbridge/amd/amdk8/early_ht.c.orig
+++ src/northbridge/amd/amdk8/early_ht.c
@@ -13,6 +13,8 @@ static void enumerate_ht_chain(void)
 	 * links needs to be programed to point at bus 0.
 	 */
 	unsigned next_unitid, last_unitid;
+	unsigned temp_unitid;
+	unsigned not_use_count;
 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
 	//let't record the device of last ht device, So we can set the Unitid to HT_CHAIN_END_UNITID_BASE
 	unsigned real_last_unitid;
@@ -60,14 +62,21 @@ static void enumerate_ht_chain(void)
 					unsigned ctrl, ctrl_off;
 
 					flags &= ~0x1f;
-					flags |= next_unitid & 0x1f;
 					count = (flags >> 5) & 0x1f;
+					not_use_count = 0;
+					temp_unitid = next_unitid;
 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-					real_last_unitid = next_unitid;
+					if ( (count + next_unitid) >= 0x20) { 
+						temp_unitid = HT_CHAIN_END_UNITID_BASE;
+						not_use_count = 1;
+					} 
+					real_last_unitid = temp_unitid;
 					real_last_pos = pos;
-					ht_dev_num++ ;
+					ht_dev_num++;
 #endif
-					next_unitid += count;
+					flags |= temp_unitid & 0x1f;
+					if(!not_use_count) 
+						next_unitid += count;
 
 					/* Test for end of chain */
 					ctrl_off = ((flags >> 10) & 1)?
@@ -87,8 +96,9 @@ static void enumerate_ht_chain(void)
 			pos = pci_read_config8(PCI_DEV(0, 0, 0), pos + PCI_CAP_LIST_NEXT);
 		}
 	} while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
+
 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-	if(ht_dev_num>0) {
+	if((ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE)) {
 		uint16_t flags;
 		flags = pci_read_config16(PCI_DEV(0,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); 
                 flags &= ~0x1f;
Index: src/northbridge/amd/amdk8/raminit_f.c
===================================================================
--- src/northbridge/amd/amdk8/raminit_f.c.orig
+++ src/northbridge/amd/amdk8/raminit_f.c
@@ -79,16 +79,13 @@ static inline void print_t(const char *s
 	*/
 
 
-#if 1
 static void setup_resource_map(const unsigned int *register_values, int max)
 {
 	int i;
-
 	for(i = 0; i < max; i += 3) {
 		device_t dev;
 		unsigned where;
 		unsigned long reg;
-
 		dev = register_values[i] & ~0xff;
 		where = register_values[i] & 0xff;
 		reg = pci_read_config32(dev, where);
@@ -97,7 +94,6 @@ static void setup_resource_map(const uns
 		pci_write_config32(dev, where, reg);
 	}
 }
-#endif
 
 static int controller_present(const struct mem_controller *ctrl)
 {
@@ -635,218 +631,13 @@ static void sdram_set_registers(const st
 			- poll the DctAccessDone untio it = 1
 		
 	*/
-#if 0
-	static const unsigned int index_register_values[] = {
-	/* Output Driver Compensation Control Register
-	 * Index: 0x00
-	 * [ 1: 0] CkeDrvStren (CKE Drive Strength)
-	 *	00 = 1.0x
-	 *	01 = 1.25x
-	 *	10 = 1.5x (Default)
-	 *	11 = 2.0x
-	 * [ 3: 2] reserved
-	 * [ 5: 4] CsOdtDrvStren (CS/ODT Drive Strength)
-         *      00 = 1.0x
-         *      01 = 1.25x
-         *      10 = 1.5x (Default)
-         *      11 = 2.0x
-         * [ 7: 6] reserved
-	 * [ 9: 8] AddrCmdDrvStren (Address/Command Drive Strength)
-         *      00 = 1.0x
-         *      01 = 1.25x
-         *      10 = 1.5x (Default)
-         *      11 = 2.0x
-         * [11:10] reserved
-	 * [13:12] ClkDrvStren (MEMCLK Drive Strength)
-         *      00 = 0.75x
-         *      01 = 1.0x Default)
-         *      10 = 1.25x 
-         *      11 = 1.5x
-         * [15:14] reserved
-         * [17:16] DataDrvStren (Data Drive Strength)
-         *      00 = 0.75x
-         *      01 = 1.0x Default)
-         *      10 = 1.25x
-         *      11 = 1.5x
-         * [19:18] reserved
-         * [21:20] DqsDrvStren (DQS Drive Strength)
-         *      00 = 0.75x
-         *      01 = 1.0x Default)
-         *      10 = 1.25x
-         *      11 = 1.5x
-         * [27:22] reserved
-         * [29:28] ProcOdt ( Processor On-die Termination)
-         *      00 = 300 ohms +/- 20%
-         *      01 = 150 ohms +/- 20%
-         *      10 = 75 ohms +/- 20%
-         *      11 = reserved
-         * [31:30] reserved
-	 */
-	0x00, 0xcfcccccc, 0x00000000, 
-	0x20, 0xcfcccccc, 0x00000000, 
-	/* Write Data Timing Low Control Register
-	 * Index 0x01
-	 * [ 5: 0] WrDatTimeByte0 (Write Data Byte 0 Timing Control)
-	 *	000000 =  no delay
-	 *	000001 = 1/96 MEMCLK delay
-	 *	000010 = 2/96 MEMCLK delay
-	 *	...
-	 *	101111 = 47/96 MEMCLK delay
-	 *	11xxxx = reserved
-	 * [ 7: 6] reserved
-         * [13: 8] WrDatTimeByte1 (Write Data Byte 1 Timing Control)
-         * [15:14] reserved
-         * [21:16] WrDatTimeByte2 (Write Data Byte 2 Timing Control)
-         * [23:22] reserved
-         * [29:24] WrDatTimeByte3 (Write Data Byte 3 Timing Control)
-         * [31:30] reserved
-	 */
-	0x01, 0xc0c0c0c0, 0x00000000,
-	0x21, 0xc0c0c0c0, 0x00000000,
-	/* Write Data Timing High Control Register
-	 * Index 0x02
-	 * [ 5: 0] WrDatTimeByte4 (Write Data Byte 4 Timing Control)
-	 * [ 7: 6] reserved
-         * [13: 8] WrDatTimeByte5 (Write Data Byte 5 Timing Control)
-         * [15:14] reserved
-         * [21:16] WrDatTimeByte6 (Write Data Byte 6 Timing Control)
-         * [23:22] reserved
-         * [29:24] WrDatTimeByte7 (Write Data Byte 7 Timing Control)
-         * [31:30] reserved
-	 */
-	0x02, 0xc0c0c0c0, 0x00000000,
-	0x22, 0xc0c0c0c0, 0x00000000,
-
-	/* Write Data ECC Timing Control Register
-	 * Index 0x03
-	 * [ 5: 0] WrChkTime (Write Data ECC Timing Control)
-	 *	000000 =  no delay
-	 *	000001 = 1/96 MEMCLK delay
-	 *	000010 = 2/96 MEMCLK delay
-	 *	...
-	 *	101111 = 47/96 MEMCLK delay
-	 *	11xxxx = reserved
-         * [31: 6] reserved
-	 */
-	0x03, 0x000000c0, 0x00000000,
-	0x23, 0x000000c0, 0x00000000,
-
-	/* Address Timing Control Register
-	 * Index 0x04
-	 * [ 4: 0] CkeFineDelay (CKE Fine Delay)
-	 *	00000 =  no delay
-	 *	00001 = 1/64 MEMCLK delay
-	 *	00010 = 2/64 MEMCLK delay
-	 *	...
-	 *	11111 = 31/64 MEMCLK delay
-	 * [ 5: 5] CkeSetup (CKE Setup Time)
-	 *	0 = 1/2 MEMCLK
-	 *	1 = 1 MEMCLK
-         * [ 7: 6] reserved
-	 * [12: 8] CsOdtFineDelay (CS/ODT Fine Delay)
-	 *	00000 =  no delay
-	 *	00001 = 1/64 MEMCLK delay
-	 *	00010 = 2/64 MEMCLK delay
-	 *	...
-	 *	11111 = 31/64 MEMCLK delay
-	 * [13:13] CsOdtSetup (CS/ODT Setup Time)
-	 *	0 = 1/2 MEMCLK
-	 *	1 = 1 MEMCLK
-         * [15:14] reserved
-	 * [20:16] AddrCmdFineDelay (Address/Command Fine Delay)
-	 *	00000 =  no delay
-	 *	00001 = 1/64 MEMCLK delay
-	 *	00010 = 2/64 MEMCLK delay
-	 *	...
-	 *	11111 = 31/64 MEMCLK delay
-	 * [21:21] AddrCmdSetup (Address/Command Setup Time)
-	 *	0 = 1/2 MEMCLK
-	 *	1 = 1 MEMCLK
-         * [31:22] reserved
-	 */
-	0x04, 0xffc0c0c0, 0x00000000,
-	0x24, 0xffc0c0c0, 0x00000000,
-
-	/* Read DQS Timing Low Control Register
-	 * Index 0x05
-	 * [ 5: 0] RdDqsTimeByte0 (Read DQS Byte 0 Timing Control)
-	 *	000000 =  no delay
-	 *	000001 = 1/96 MEMCLK delay
-	 *	000010 = 2/96 MEMCLK delay
-	 *	...
-	 *	101111 = 47/96 MEMCLK delay
-	 *	11xxxx = reserved
-	 * [ 7: 6] reserved
-         * [13: 8] RdDqsTimeByte1 (Read DQS Byte 1 Timing Control)
-         * [15:14] reserved
-         * [21:16] RdDqsTimeByte2 (Read DQS Byte 2 Timing Control)
-         * [23:22] reserved
-         * [29:24] RdDqsTimeByte3 (Read DQS Byte 3 Timing Control)
-         * [31:30] reserved
-	 */
-	0x05, 0xc0c0c0c0, 0x00000000,
-	0x25, 0xc0c0c0c0, 0x00000000,
-
-	/* Read DQS Timing High Control Register
-	 * Index 0x06
-	 * [ 5: 0] RdDqsTimeByte4 (Read DQS Byte 4 Timing Control)
-	 * [ 7: 6] reserved
-         * [13: 8] RdDqsTimeByte5 (Read DQS Byte 5 Timing Control)
-         * [15:14] reserved
-         * [21:16] RdDqsTimeByte6 (Read DQS Byte 6 Timing Control)
-         * [23:22] reserved
-         * [29:24] RdDqsTimeByte7 (Read DQS Byte 7 Timing Control)
-         * [31:30] reserved
-	 */
-	0x06, 0xc0c0c0c0, 0x00000000,
-	0x26, 0xc0c0c0c0, 0x00000000,
-
-	/* Read DQS ECC Timing Control Register
-	 * Index 0x07
-	 * [ 5: 0] RdDqsTimeCheck (Read DQS ECC Timing Control)
-	 *	000000 =  no delay
-	 *	000001 = 1/96 MEMCLK delay
-	 *	000010 = 2/96 MEMCLK delay
-	 *	...
-	 *	101111 = 47/96 MEMCLK delay
-	 *	11xxxx = reserved
-         * [31: 6] reserved
-	 */
-	0x07, 0x000000c0, 0x00000000,
-	0x27, 0x000000c0, 0x00000000,
-
-	/* DQS Receiver Enable Timing Control Register
-	 * Index 0x10, 0x13, 0x16, 0x19,
-	 * [ 7: 0] Dqs RcvEnDelay (DQS Receiver Enable Delay)
-	 *	0x00 =  0 ps
-	 *	0x01 = 50 ps
-	 *	0x02 = 100 ps
-	 *	...
-	 *	0xae = 8.7 ns
-	 *	0xaf-0xff = reserved
-         * [31: 6] reserved
-	 */
-	0x10, 0x000000ff, 0x00000000,
-	0x13, 0x000000ff, 0x00000000,
-	0x16, 0x000000ff, 0x00000000,
-	0x19, 0x000000ff, 0x00000000,
-	0x30, 0x000000ff, 0x00000000,
-	0x33, 0x000000ff, 0x00000000,
-	0x36, 0x000000ff, 0x00000000,
-	0x39, 0x000000ff, 0x00000000,
-	};
-#endif
-
 	int i;
 	int max;
 
-#if 1
         if (!controller_present(ctrl)) {
-//                print_debug("No memory controller present\r\n");
 		sysinfo->ctrl_present[ctrl->node_id] = 0;
                 return;
         }
-#endif
 	sysinfo->ctrl_present[ctrl->node_id] = 1;
 	
 	print_spew("setting up CPU");
@@ -865,20 +656,6 @@ static void sdram_set_registers(const st
 		pci_write_config32(dev, where, reg);
 	}
 
-#if 0
-	// for index regs
-	max = sizeof(index_register_values)/sizeof(index_register_values[0]);
-	for(i = 0; i < max; i += 3) {
-		unsigned long reg;
-		unsigned index;
-		index = register_values[i];
-		reg = pci_read_config32_index_wait(ctrl->f2, DRAM_CTRL_ADDI_DATA_OFFSET, index);
-		reg &= register_values[i+1];
-		reg |= register_values[i+2];
-		pci_write_config32_index_wait(ctrl->f2, DRAM_CTRL_ADDI_DATA_OFFSET, index, reg);
-	}
-#endif
-
 	print_spew("done.\r\n");
 }
 
@@ -889,6 +666,19 @@ static int is_dual_channel(const struct 
 	return dcl & DCL_Width128;
 }
 
+static int is_opteron(const struct mem_controller *ctrl)
+{
+	/* Test to see if I am an Opteron.  
+	 * FIXME Testing dual channel capability is correct for now
+	 * but a beter test is probably required.
+	 * m2 and s1g1 support dual channel too. but only support unbuffered dimm
+	 */
+#warning "FIXME implement a better test for opterons"
+	uint32_t nbcap;
+	nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
+	return !!(nbcap & NBCAP_128Bit);
+}
+
 static int is_registered(const struct mem_controller *ctrl)
 {
 	/* Test to see if we are dealing with registered SDRAM.
@@ -1456,6 +1246,20 @@ static long spd_handle_unbuffered_dimms(
 		} 
 	}
 
+	if (is_opteron(ctrl)) {
+#if 0
+		if ( registered != (dimm_mask & ((1<<DIMM_SOCKETS)-1)) ) {
+			dimm_mask &= (registered | (registered << DIMM_SOCKETS) ); //disable unbuffed dimm
+	//		die("Mixed buffered and registered dimms not supported");
+		}
+		//By yhlu for debug M2, s1g1 can do dual channel, but it use unbuffer DIMM
+		if (!registered) {
+			die("Unbuffered Dimms not supported on Opteron");
+		}
+#endif
+	}
+
+
 	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~DCL_UnBuffDimm;
 	meminfo->is_registered = 1;
@@ -1852,7 +1656,6 @@ static struct spd_set_memclk_result spd_
 		if (latencies < 0) goto hw_error;
 		if (latencies == 0) {
 			continue;
-//			goto dimm_err;
 		}
 
 		/* Compute the lowest cas latency supported */
@@ -1966,23 +1769,6 @@ static int update_dimm_Trfc(const struct
 	uint32_t dth;
 	int value;
 
-#if 0
-	int value2;
-
-	value = spd_read_byte(ctrl->channel0[i], SPD_TRFC);
-	if (value < 0) return -1;
-
-        value2 = spd_read_byte(ctrl->channel0[i], SPD_TRC -1);
-	if(value2 & 1) value += 256;
-        value <<= 2;
-        value += convert_to_1_4(value2>>1);
-
-	if (value == 0) {
-		value = param->tRFC;
-	}
-	value *= 10;
-	clocks = (value + param->divisor - 1)/param->divisor;
-#endif
 	//get the cs_size --> logic dimm size
 	value = spd_read_byte(ctrl->channel0[i], SPD_PRI_WIDTH);
         if (value < 0) {
@@ -1997,7 +1783,6 @@ static int update_dimm_Trfc(const struct
 
 	old_clocks = ((dth >> (DTH_TRFC0_SHIFT+i*3)) & DTH_TRFC_MASK);
 	if (old_clocks >= clocks) { // some one did it?
-//		clocks = old_clocks;
 		return 1;
 	}
 	dth &= ~(DTH_TRFC_MASK << (DTH_TRFC0_SHIFT+i*3));
@@ -2072,7 +1857,6 @@ static int update_dimm_Tras(const struct
 	dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
 	old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
 	if (old_clocks >= clocks) { // someone did it?
-//		clocks = old_clocks;
 		return 1;
 	}
 	dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
@@ -2397,6 +2181,7 @@ static void set_max_async_latency(const 
 	dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
 	dch &= ~(DCH_MaxAsyncLat_MASK << DCH_MaxAsyncLat_SHIFT);
 
+	//FIXME: We need to use Max of DqsRcvEnDelay + 6ns here: After trainning and get that from index reg 0x10, 0x13, 0x16, 0x19, 0x30, 0x33, 0x36, 0x39
 	async_lat = 6+6;
 	
 	
@@ -2684,7 +2469,6 @@ static void sdram_set_spd_registers(cons
 	long dimm_mask;
 #if 1
 	if (!sysinfo->ctrl_present[ctrl->node_id]) {
-//		print_debug("No memory controller present\r\n");
 		return;
 	}
 #endif
@@ -2852,6 +2636,7 @@ static void sdram_enable(int controllers
 
 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
         unsigned cpu_f0_f1[8];
+	/* FIXME: How about 32 node machine later? */
 	tsc_t tsc, tsc0[8];
 	
 	print_debug_addr("sdram_enable: tsc0[8]: ", &tsc0[0]);
@@ -2886,6 +2671,14 @@ static void sdram_enable(int controllers
 
 	/* We need to wait a mimmium of 20 MEMCLKS to enable the  InitDram */
 	memreset(controllers, ctrl);
+#if 0
+	print_debug("prepare to InitDram:");
+	for(i=0; i<10; i++) {
+		print_debug_hex32(i);
+		print_debug("\b\b\b\b\b\b\b\b");
+	}
+	print_debug("\r\n");
+#endif
 
 	for(i = 0; i < controllers; i++) {
 		uint32_t dcl, dch;
@@ -3016,10 +2809,6 @@ static void sdram_enable(int controllers
                 sysinfo->mem_trained[i] = 0x80; // mem need to be trained
         }
 
-#if 0
-        dump_pci_devices();
-        dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
-#endif
 
 #if MEM_TRAIN_SEQ ==  0
    #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
@@ -3056,11 +2845,6 @@ static void sdram_enable(int controllers
 	wait_all_core0_mem_trained(sysinfo);
 #endif
 
-#if 0
-        dump_pci_devices();
-        dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98);
-#endif
-
 }
 static void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, const uint16_t *spd_addr)
 {
Index: src/northbridge/amd/amdk8/raminit_f_dqs.c
===================================================================
--- src/northbridge/amd/amdk8/raminit_f_dqs.c.orig
+++ src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -107,15 +107,6 @@ static unsigned Get_MCTSysAddr(const str
 
 static unsigned Get_RcvrSysAddr(const struct mem_controller * ctrl, unsigned channel, unsigned cs_idx, struct sys_info *sysinfo)
 {
-#if 0
-	//get SB_64MuxedMode
-	uint32_t dword;
-	dword = pci_read_config32(ctrl->f2, DRAM_CTRL_MISC);
-	if((dword & DCM_Mode64BitMux) == DCM_Mode64BitMux) {
-		if(channel) cs_idx += 4; // translate Receiver number to Chipsel
-	}
-#endif
-	
 	return Get_MCTSysAddr(ctrl, cs_idx, sysinfo);
 
 }
@@ -181,43 +172,6 @@ static void set_FSBASE(uint32_t addr_hi)
 
 }
 
-#if 0
-static void write_mem(uint32_t addr_hi, uint32_t addr_lo, uint32_t value) 
-{
-	if(addr_hi == 0) {
-		*((uint32_t *)addr_lo) = value;
-		return;
-	} 
-
-	set_FSBASE(addr_hi);
-
-        __asm__ volatile (
-		"movl %1, %%fs:(%0)\n\t"
-                :: "a" (addr_lo), "b" (value) 
-        );
-	
-}
-
-static uint32_t read_mem(uint32_t addr_hi, uint32_t addr_lo)
-{
-	unsigned value;
-        if(addr_hi == 0) {
-                value = *((uint32_t *)addr_lo);
-		return value; 
-        }
-
-	set_FSBASE(addr_hi);
-
-        __asm__ volatile (
-                "movl %%fs:(%1), %0\n\t"
-                :"=b"(value): "a" (addr_lo)
-        );
-	
-	return value;
-
-}
-#endif
-
 static unsigned ChipSelPresent(const struct mem_controller *ctrl, unsigned cs_idx, struct sys_info *sysinfo)
 {
         unsigned enabled;
@@ -233,6 +187,7 @@ static unsigned ChipSelPresent(const str
 
 static unsigned RcvrRankEnabled(const struct mem_controller *ctrl, int channel, int cs_idx, unsigned is_Width128, struct sys_info *sysinfo)
 {
+	/* FIXME: process 64Muxed */
         if(!is_Width128) {
         	if(channel) return 0; // no channel b
         }
@@ -701,6 +656,7 @@ static unsigned TrainRcvrEn(const struct
 
 				/* Program current Receiver enable delay */
 				pci_write_config32_index_wait(ctrl->f2, 0x98, index, RcvrEnDly);
+				/* FIXME: 64bit MUX */
 	
 				if(is_Width128) {
 					/* Program current Receiver enable delay chaannel b */
@@ -1164,6 +1120,7 @@ static unsigned TrainDQSPos(const struct
 
 	for(ChipSel = 0; ChipSel < 8; ChipSel++) { //logical register chipselects 0..7
 		print_debug_dqs("\t\t\t\tTrainDQSPos: 11 ChipSel ", ChipSel, 4); 
+		//FIXME: process 64MUXedMode
 		if(!ChipSelPresent(ctrl, ChipSel, sysinfo)) continue;
 		BanksPresent  = 1;
 
@@ -1454,6 +1411,7 @@ static unsigned TrainDQSRdWrPos(const st
 		}
 		channel++;
 		if(!is_Width128){
+			//FIXME: 64MuxMode??	
 			channel++; // skip channel if 64-bit mode
 		}
 	}
@@ -2030,11 +1988,15 @@ static inline void train_ram_on_node(uns
 	wait_till_sysinfo_in_ram(); // use pci to get it
 
 	if(sysinfox->mem_trained[nodeid] == 0x80) {
+	#if 0
 		sysinfo->tom_k = sysinfox->tom_k;
 		sysinfo->tom2_k = sysinfox->tom2_k;
 		sysinfo->meminfo[nodeid].is_Width128 = sysinfox->meminfo[nodeid].is_Width128;
 		sysinfo->mem_trained[nodeid] = sysinfox->mem_trained[nodeid];
 		memcpy(&sysinfo->ctrl[nodeid], &sysinfox->ctrl[nodeid], sizeof(struct mem_controller));
+	#else
+		memcpy(sysinfo, sysinfox, DCACHE_RAM_GLOBAL_VAR_SIZE);
+	#endif
 		set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's
 	#if CONFIG_AP_CODE_IN_CAR == 0
 		print_debug("CODE IN ROM AND RUN ON NODE:"); print_debug_hex8(nodeid); print_debug("\r\n");
Index: src/northbridge/amd/amdk8/incoherent_ht.c
===================================================================
--- src/northbridge/amd/amdk8/incoherent_ht.c.orig
+++ src/northbridge/amd/amdk8/incoherent_ht.c
@@ -162,6 +162,24 @@ static uint16_t ht_read_freq_cap(device_
 
 	return freq_cap;
 }
+static uint8_t ht_read_width_cap(device_t dev, uint8_t pos)
+{
+	uint8_t width_cap = pci_read_config8(dev, pos);
+
+	uint32_t id;
+
+	id = pci_read_config32(dev, 0);
+
+	/* netlogic micro cap doesn't support 16 bit yet */
+	if (id == (0x184e | (0x0001 << 16))) {
+		if((width_cap & 0x77) == 0x11) {
+			width_cap &= 0x88;
+		}
+	}
+	
+	return width_cap;
+	
+}
 #define LINK_OFFS(CTRL, WIDTH,FREQ,FREQ_CAP) \
       (((CTRL & 0xff) << 24) | ((WIDTH & 0xff) << 16) | ((FREQ & 0xff) << 8) | (FREQ_CAP & 0xFF))
 
@@ -223,8 +241,8 @@ static int ht_optimize_link(
 	pci_write_config8(dev2, pos2 + LINK_FREQ(offs2), freq);
 
 	/* Get the width capabilities */
-	width_cap1 = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1));
-	width_cap2 = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2));
+	width_cap1 = ht_read_width_cap(dev1, pos1 + LINK_WIDTH(offs1));
+	width_cap2 = ht_read_width_cap(dev2, pos2 + LINK_WIDTH(offs2));
 
 	/* Calculate dev1's input width */
 	ln_width1 = link_width_to_pow2[width_cap1 & 7];
@@ -402,6 +420,8 @@ static int ht_setup_chainx(device_t udev
 
 	uint8_t next_unitid, last_unitid;
 	unsigned uoffs;
+	uint8_t temp_unitid;
+	unsigned not_use_count;
 
 #if RAMINIT_SYSINFO == 0
 	int reset_needed = 0;
@@ -473,24 +493,34 @@ static int ht_setup_chainx(device_t udev
 
 		/* Update the Unitid of the current device */
 		flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
-		flags &= ~0x1f; /* mask out the bse Unit ID */
-		flags |= next_unitid & 0x1f;
-		pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
-
-		/* Note the change in device number */
-		dev = PCI_DEV(bus, next_unitid, 0);
-
                 /* Compute the number of unitids consumed */
                 count = (flags >> 5) & 0x1f;
+		flags &= ~0x1f; /* mask out the base Unit ID */
+
+		not_use_count = 0;
+		temp_unitid = next_unitid;
 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
 		if(offset_unitid) {
-	                real_last_unitid = next_unitid;
+			if( (next_unitid + count) >= 0x20) {
+		                temp_unitid = HT_CHAIN_END_UNITID_BASE;
+				// keep to use the old next_unitid
+				not_use_count = 1;
+			} 
         	        real_last_pos = pos;
+			real_last_unitid = temp_unitid;
 			ht_dev_num++;
-		}
+		} 
 #endif
 
-                next_unitid += count;
+		flags |= temp_unitid & 0x1f;
+		pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
+
+		/* Note the change in device number */
+		dev = PCI_DEV(bus, temp_unitid, 0);
+
+		if(!not_use_count) 
+	                next_unitid += count;
+
 
 		/* Find which side of the ht link we are on,
 		 * by reading which direction our last write to PCI_CAP_FLAGS
@@ -525,7 +555,7 @@ static int ht_setup_chainx(device_t udev
 end_of_chain: ;
 	
 #if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
-        if(offset_unitid && (ht_dev_num>0)  ) {
+        if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != HT_CHAIN_END_UNITID_BASE) ) {
                 uint16_t flags;
 		int i;
                 flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
@@ -690,14 +720,7 @@ static int set_ht_link_buffer_counts_cha
                 uint32_t reg;
                 uint8_t nodeid, linkn;
                 uint8_t busn;
-                unsigned devn = 1;
-
-        #if HT_CHAIN_UNITID_BASE != 1
-                #if SB_HT_CHAIN_UNITID_OFFSET_ONLY == 1
-                if(i==0) // to check if it is sb ht chain
-                #endif
-                        devn = HT_CHAIN_UNITID_BASE;
-        #endif
+                unsigned devn;
 
                 reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
                 if((reg & 3) != 3) continue; // not enabled
@@ -706,10 +729,13 @@ static int set_ht_link_buffer_counts_cha
                 linkn = ((reg & 0xf00)>>8); // link n
                 busn = (reg & 0xff0000)>>16; //busn
 
-                reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1?
-                if ( (reg & 0xffff) == vendorid ) {
-                        reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val);
-                }
+		for(devn = 0; devn < 0x20; devn++) {
+	                reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1?
+        	        if ( (reg & 0xffff) == vendorid ) {
+                	        reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val);
+				break;
+                	}
+		}
         }
 
         return reset_needed;
Index: src/arch/i386/boot/linuxbios_table.c
===================================================================
--- src/arch/i386/boot/linuxbios_table.c.orig
+++ src/arch/i386/boot/linuxbios_table.c
@@ -365,6 +365,16 @@ unsigned long write_linuxbios_table( 
 		low_table_end = (unsigned long)head;
 	}
 
+	printk_debug("Adjust low_table_end from 0x%08x to ", low_table_end);
+	low_table_end += 0xfff; // 4K align
+	low_table_end &= ~0xfff;
+	printk_debug("0x%08x \n", low_table_end);
+	/* kernel assume this position is reserved */
+	printk_debug("Adjust rom_table_end from 0x%08x to ", rom_table_end);
+	rom_table_end += 0xffff; // 64K align
+	rom_table_end &= ~0xffff;
+	printk_debug("0x%08x \n", rom_table_end);
+
 	if (HAVE_OPTION_TABLE == 1) {
 		struct lb_record *rec_dest, *rec_src;
 		/* Write the option config table... */
Index: src/arch/i386/boot/tables.c
===================================================================
--- src/arch/i386/boot/tables.c.orig
+++ src/arch/i386/boot/tables.c
@@ -10,38 +10,12 @@
 #include <arch/acpi.h>
 #include "linuxbios_table.h"
 
-// Global Descriptor Table, defined in c_start.S
-extern uint8_t gdt;
-extern uint8_t gdt_end;
-
-/* i386 lgdt argument */
-struct gdtarg {
-	unsigned short limit;
-	unsigned int base;
-} __attribute__((packed));
-
-// Copy GDT to new location and reload it
-// 2003-07 by SONE Takeshi
-// Ported from Etherboot to LinuxBIOS 2005-08 by Steve Magnani
-void move_gdt(unsigned long newgdt)
-{
-	uint16_t num_gdt_bytes = &gdt_end - &gdt;
-	struct gdtarg gdtarg;
-
-	printk_debug("Moving GDT to %#lx...", newgdt);
-	memcpy((void*)newgdt, &gdt, num_gdt_bytes);
-	gdtarg.base = newgdt;
-	gdtarg.limit = num_gdt_bytes - 1;
-	__asm__ __volatile__ ("lgdt %0\n\t" : : "m" (gdtarg));
-	printk_debug("ok\n");
-}
-
 struct lb_memory *write_tables(void)
 {
 	unsigned long low_table_start, low_table_end, new_low_table_end;
 	unsigned long rom_table_start, rom_table_end;
 
-	rom_table_start = 0xf0000;
+	rom_table_start = 0xf0000; 
 	rom_table_end =   0xf0000;
 	/* Start low addr at 16 bytes instead of 0 because of a buglet
 	 * in the generic linux unzip code, as it tests for the a20 line.
@@ -59,55 +33,48 @@ struct lb_memory *write_tables(void)
 	/* write them in the rom area because DSDT can be large (8K on epia-m) which
 	 * pushes linuxbios table out of first 4K if set up in low table area 
          */
-
 	rom_table_end = write_acpi_tables(rom_table_end);
 	rom_table_end = (rom_table_end+1023) & ~1023;
 
-	/* copy the smp block to address 0 */
-	post_code(0x96);
+        /* copy the smp block to address 0 */
+        post_code(0x96);
 
-	/* The smp table must be in 0-1K, 639K-640K, or 960K-1M */
-	new_low_table_end = write_smp_table(low_table_end);
+        /* The smp table must be in 0-1K, 639K-640K, or 960K-1M */
+        new_low_table_end = write_smp_table(low_table_end); // low_table_end is 0x10 at this point
 
-#if HAVE_MP_TABLE==1
+#if HAVE_MP_TABLE
         /* Don't write anything in the traditional x86 BIOS data segment,
          * for example the linux kernel smp need to use 0x467 to pass reset vector
          */
-        if(new_low_table_end>0x467){
-                unsigned mptable_size = new_low_table_end - low_table_end - SMP_FLOATING_TABLE_LEN;
-                /* We can not put mptable here, we need to copy them to somewhere else*/
-                if((rom_table_end+mptable_size)<0x100000) {
-                        /* We can copy mptable on rom_table, and leave low space for lbtable  */
-                        printk_debug("move mptable to 0x%0x\n", rom_table_end);
-                        memcpy((unsigned char *)rom_table_end, (unsigned char *)(low_table_end+SMP_FLOATING_TABLE_LEN), mptable_size);
-                        memset((unsigned char *)low_table_end, '\0', mptable_size + SMP_FLOATING_TABLE_LEN);
-                        smp_write_floating_table_physaddr(low_table_end, rom_table_end);
-                        low_table_end += SMP_FLOATING_TABLE_LEN;
-                        rom_table_end += mptable_size;
-                        rom_table_end = (rom_table_end+1023) & ~1023;
-                } else {
-                        /* We can need to put mptable low and from 0x500 */
-                        printk_debug("move mptable to 0x%0x\n", 0x500);
-                        memcpy((unsigned char *)0x500, (unsigned char *)(low_table_end+SMP_FLOATING_TABLE_LEN), mptable_size);
-                        memset((unsigned char *)low_table_end, '\0', 0x500-low_table_end);
-                        smp_write_floating_table_physaddr(low_table_end, 0x500);
-                        low_table_end = 0x500 + mptable_size;
-                }
-        }
-#endif 
-
-	/* Don't write anything in the traditional x86 BIOS data segment */
-	if (low_table_end < 0x500) {
+	if(new_low_table_end>0x467){
+		unsigned mptable_size;
+		unsigned mpc_start;
+		low_table_end += SMP_FLOATING_TABLE_LEN; /* keep the mpf in 1k low, so kernel can find it */
+		mptable_size = new_low_table_end - low_table_end;
+		/* We can not put mptable low, we need to copy them to somewhere else*/
+		if((rom_table_end+mptable_size)<0x100000) {
+			/* We can copy mptable on rom_table  */
+			mpc_start = rom_table_end;
+			rom_table_end += mptable_size;
+			rom_table_end = (rom_table_end+1023) & ~1023;
+		} else {
+			/* We can need to put mptable before rom_table */
+			mpc_start = rom_table_start - mptable_size;
+			mpc_start &= ~1023;
+			rom_table_start = mpc_start;
+		}
+		printk_debug("move mptable from 0x%0x to 0x%0x, size 0x%0x\n", low_table_end, mpc_start, mptable_size);
+		memcpy((unsigned char *)mpc_start, (unsigned char *)low_table_end, mptable_size);
+		smp_write_floating_table_physaddr(low_table_end - SMP_FLOATING_TABLE_LEN, mpc_start);
+		memset((unsigned char *)low_table_end, '\0', mptable_size);
+	}
+#endif
+	if(low_table_end<0x500) {
 		low_table_end = 0x500;
 	}
 
-	// Relocate the GDT to reserved memory, so it won't get clobbered
-	move_gdt(low_table_end);
-	low_table_end += &gdt_end - &gdt;
-
 	/* The linuxbios table must be in 0-4K or 960K-1M */
-	write_linuxbios_table(
-			      low_table_start, low_table_end,
+	write_linuxbios_table(low_table_start, low_table_end,
 			      rom_table_start, rom_table_end);
 
 	return get_lb_mem();
Index: src/arch/i386/include/stdint.h
===================================================================
--- src/arch/i386/include/stdint.h.orig
+++ src/arch/i386/include/stdint.h
@@ -67,5 +67,9 @@ typedef unsigned long int  uintmax_t;
 
 #undef __HAVE_LONG_LONG__
 
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+
 
 #endif /* I386_STDINT_H */
Index: src/arch/i386/include/arch/acpi.h
===================================================================
--- src/arch/i386/include/arch/acpi.h.orig
+++ src/arch/i386/include/arch/acpi.h
@@ -17,9 +17,6 @@
 
 #if HAVE_ACPI_TABLES==1
 
-typedef unsigned char u8;
-typedef unsigned short u16;
-typedef unsigned int u32;
 typedef unsigned long long u64;
 
 #define RSDP_SIG              "RSD PTR "  /* RSDT Pointer signature */
@@ -83,7 +80,7 @@ typedef struct acpi_table_header        
 /* RSDT */
 typedef struct acpi_rsdt {
 	struct acpi_table_header header;
-	u32 entry[6+ACPI_SSDTX_NUM]; /* HPET, FADT, SRAT, SLIT, MADT(APIC), SSDT, SSDTX*/
+	u32 entry[6+ACPI_SSDTX_NUM+CONFIG_MAX_CPUS]; /* HPET, FADT, SRAT, SLIT, MADT(APIC), SSDT, SSDTX, and SSDT for CPU pstate*/
 } __attribute__ ((packed)) acpi_rsdt_t;
 
 /* XSDT */
Index: src/arch/i386/lib/c_start.S
===================================================================
--- src/arch/i386/lib/c_start.S.orig
+++ src/arch/i386/lib/c_start.S
@@ -263,9 +263,9 @@ gdt:
 	.word	0x0000, 0x0000		/* dummy */
 	.byte	0x00, 0x00, 0x00, 0x00
 
-	/* selgdt 0x10, flat code segment */
+	/* selgdt 0x10, flat code segment */ 
 	.word	0xffff, 0x0000		
-	.byte	0x00, 0x9b, 0xcf, 0x00	
+	.byte	0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */	
 
 	/* selgdt 0x18, flat data segment */
 	.word	0xffff, 0x0000		
Index: src/arch/i386/lib/cpu.c
===================================================================
--- src/arch/i386/lib/cpu.c.orig
+++ src/arch/i386/lib/cpu.c
@@ -207,7 +207,6 @@ static void set_cpu_ops(struct device *c
 			}
 		}
 	}
-	die("Unknown cpu");
 	return;
  found:
 	cpu->ops = driver->ops;
@@ -223,7 +222,7 @@ void cpu_initialize(void)
 	struct device *cpu;
 	struct cpu_info *info;
 	struct cpuinfo_x86 c;
-
+	
 	info = cpu_info();
 
 	printk_notice("Initializing CPU #%d\n", info->index);
@@ -233,41 +232,37 @@ void cpu_initialize(void)
 		die("CPU: missing cpu device structure");
 	}
 
-	// Check that we haven't been passed bad information as the result of a race 
-	// (i.e. BSP timed out while waiting for us to load secondary_stack)
-
-#if CONFIG_SMP  || CONFIG_IOPIC 
-	if (cpu->path.u.apic.apic_id != lapicid()) {
-		printk_err("CPU #%d Initialization FAILED: APIC ID mismatch (%u != %u)\n",
-				   info->index, cpu->path.u.apic.apic_id, lapicid());
-		// return without setting initialized flag
-	} else {
-#endif
-		/* Find what type of cpu we are dealing with */
-		identify_cpu(cpu);
-		printk_debug("CPU: vendor %s device %x\n",
-			cpu_vendor_name(cpu->vendor), cpu->device);
-
-	        get_fms(&c, cpu->device);
-
-	        printk_debug("CPU: family %02x, model %02x, stepping %02x\n", c.x86, c.x86_model, c.x86_mask);
-
-			
-		/* Lookup the cpu's operations */
+	/* Find what type of cpu we are dealing with */
+	identify_cpu(cpu);
+	printk_debug("CPU: vendor %s device %x\n",
+		cpu_vendor_name(cpu->vendor), cpu->device);
+
+	get_fms(&c, cpu->device);
+
+	printk_debug("CPU: family %02x, model %02x, stepping %02x\n", c.x86, c.x86_model, c.x86_mask);
+	
+	/* Lookup the cpu's operations */
+	set_cpu_ops(cpu);
+
+	if(!cpu->ops) { 
+		/* mask out the stepping and try again */
+		cpu->device -= c.x86_mask;
 		set_cpu_ops(cpu);
+		cpu->device += c.x86_mask;
+		if(!cpu->ops) die("Unknown cpu");
+		printk_debug("Using stepping 0 ops instead\n");
+	}
+	
 
-		/* Initialize the cpu */
-		if (cpu->ops && cpu->ops->init) {
-			cpu->enabled = 1;
-			cpu->initialized = 1;
-			cpu->ops->init(cpu);
-		}
+	/* Initialize the cpu */
+	if (cpu->ops && cpu->ops->init) {
+		cpu->enabled = 1;
+		cpu->initialized = 1;
+		cpu->ops->init(cpu);
+	}
 
-		printk_info("CPU #%d Initialized\n", info->index);
-#if CONFIG_SMP  || CONFIG_IOPIC 
+	printk_info("CPU #%d Initialized\n", info->index);
 
-	}
-#endif
 	return;
 }
 
Index: src/drivers/generic/debug/debug_dev.c
===================================================================
--- src/drivers/generic/debug/debug_dev.c.orig
+++ src/drivers/generic/debug/debug_dev.c
@@ -5,6 +5,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <cpu/x86/msr.h>
+#include <arch/io.h>
 #include "chip.h"
 
 static void print_pci_regs(struct device *dev)
@@ -21,17 +22,53 @@ static void print_pci_regs(struct device
       printk_debug("\n");
 }
 
-static void print_mem(void)
+static void print_mem(unsigned start, unsigned size)
 {
         unsigned int i;
-	unsigned int start = 0xfffff000;
-	for(i=start;i<0xffffffff;i++) {
-             if((i & 0xf)==0) printk_debug("\n %08x:",i);
+	unsigned int end = start + size;
+	for(i=start; i<end; i++) {
+             if((i & 0xf)==0) printk_debug("\n%08x:",i);
              printk_debug(" %02x",(unsigned char)*((unsigned char *)i));
-             }
-	printk_debug(" %02x\n",(unsigned char)*((unsigned char *)i));
+	}
+	printk_debug("\n");
+
+}
+
+static void print_io(unsigned port)
+{
+
+        int i;
+        printk_debug("%04x:\n", port);
+        for(i=0;i<256;i++) {
+                uint8_t val;
+                if ((i & 0x0f) == 0) {
+                        printk_debug("%02x:", i);
+                }
+                val = inb(port);
+                printk_debug(" %02x",val);
+                if ((i & 0x0f) == 0x0f) {
+                        print_debug("\n");
+                }
+                port++;
+        }
+}
+
+static void print_io_mcp55(void)
+{
+	device_t dev;
+	struct resource *res;
+	int i;
+	dev= dev_find_slot(0, PCI_DEVFN(1, 1));
+	if(dev) {
+		for(i=0x68; i>0x60; i-=4) {
+			res = find_resource(dev, i);
+			if(res) {
+				print_io(res->base);
+			}
+		}
+	}
+}
 
- }
 static void print_pci_regs_all(void)
 {
         struct device *dev;
@@ -57,6 +94,60 @@ static void print_pci_regs_all(void)
 	}
 }
 
+static void print_pci_regs_index(struct device *dev, unsigned index_reg, unsigned type, unsigned length)
+{
+        int i;
+        printk_debug("%s\n", dev_path(dev));
+
+        printk_debug(" index reg: %04x type: %02x\n", index_reg, type);
+
+        type<<=28;
+
+        for(i = 0; i < length; i++) {
+                uint32_t val;
+                if ((i & 0x0f) == 0) {
+                        printk_debug("\n%02x:",i);
+                }
+	        pci_write_config32(dev, index_reg, i|type);
+	        val = pci_read_config32(dev, index_reg+0x4);
+
+                printk_debug(" %08x", val);
+        }
+        print_debug("\n");
+}
+#if 0
+static  void print_pci_regs_index_all_k9(void)
+{
+	int nodes = 64;
+	int i;
+	
+	device_t dev[64];
+	
+	for(i=0; i<nodes; i++) {
+		dev[i] = get_node_pci(i, 1);
+	}
+	printk_debug("MMIO:\n");
+	//MMIO
+	for(i=0; i<nodes; i++) {
+		if(!dev[i]) break;
+		print_pci_regs_index(dev[i], 0x110,2, 64);  
+		print_pci_regs_index(dev[i], 0x110,3, 64);  
+	}
+	//IO
+	printk_debug("MMIO:\n");
+	for(i=0; i<nodes; i++) {
+		if(!dev[i]) break;
+		print_pci_regs_index(dev[i], 0x110,4, 64);  
+	}
+	//DRAM
+	printk_debug("DRAM:\n");
+	for(i=0; i<nodes; i++) {
+		if(!dev[i]) break;
+		print_pci_regs_index(dev[i], 0x110,0, 64);  
+		print_pci_regs_index(dev[i], 0x110,1, 64);  
+	}
+}
+#endif
 static void print_cpuid()
 {
 	msr_t msr;
@@ -251,7 +342,13 @@ static void debug_init(device_t dev)
 		print_pci_regs_all();
 		break;
 	case 2: 
-		print_mem();
+		print_mem(0xffe00000, 0x100);
+		print_mem(0xfff00000, 0x100);
+		print_mem(0xfff80000, 0x100);
+		print_mem(0xfff90000, 0x100);
+		print_mem(0xfffa0000, 0x100);
+		print_mem(0xfffb0000, 0x100);
+		print_mem(0xfffc0000, 0x100);
 		break;
 	case 3:
 		print_cpuid();
@@ -271,6 +368,12 @@ static void debug_init(device_t dev)
 	case 8: 
 		hard_reset();
 		break;
+	case 9: 
+		print_io_mcp55();
+		break;
+	case 10: 
+	//	print_pci_regs_index_all_k9();
+		break;
 	}
 }
 
Index: src/arch/i386/lib/console.c
===================================================================
--- src/arch/i386/lib/console.c.orig
+++ src/arch/i386/lib/console.c
@@ -9,11 +9,15 @@ static void __console_tx_byte(unsigned c
 #include "console_print.c"
 
 #else  
-/* CONFIG_USE_INIT == 1 */
+/* CONFIG_USE_PRINTK_IN_CAR == 1 */
 
 #include "console_printk.c"
 
-#endif /* CONFIG_USE_INIT */
+// do_printk
+#include "../../../console/vtxprintf.c"
+#include "printk_init.c"
+
+#endif /* CONFIG_USE_PRINTK_IN_CAR */
 
 #ifndef LINUXBIOS_EXTRA_VERSION
 #define LINUXBIOS_EXTRA_VERSION ""
Index: src/cpu/amd/model_fxx/processor_name.c
===================================================================
--- src/cpu/amd/model_fxx/processor_name.c.orig
+++ src/cpu/amd/model_fxx/processor_name.c
@@ -20,8 +20,6 @@
 #include <string.h>
 #include <cpu/x86/msr.h>
 
-typedef unsigned int u32;
-
 /* The maximum length of CPU names is 48 bytes, including the final NULL byte.
  * If you change these names your BIOS will _NOT_ pass the AMD validation and
  * your mainboard will not be posted on the AMD Recommended Motherboard Website
Index: src/pc80/serial.c
===================================================================
--- src/pc80/serial.c.orig
+++ src/pc80/serial.c
@@ -24,7 +24,7 @@
 #define UART_LCS	TTYS0_LCS
 
 
-#if CONFIG_USE_INIT == 0
+#if CONFIG_USE_PRINTK_IN_CAR == 0
 
 /* Data */
 #define UART_RBR 0x00
@@ -92,6 +92,7 @@ static void uart_init(void)
 	outb(UART_LCS, TTYS0_BASE + UART_LCR);
 }
 #else
+#include "../lib/uart8250.c"
 extern void uart8250_init(unsigned base_port, unsigned divisor, unsigned lcs);
 static void uart_init(void)
 {
Index: src/mainboard/gigabyte/m57sli/Options.lb
===================================================================
--- src/mainboard/gigabyte/m57sli/Options.lb.orig
+++ src/mainboard/gigabyte/m57sli/Options.lb
@@ -213,7 +213,7 @@ default K8_HT_FREQ_1G_SUPPORT=1
 default CONFIG_CONSOLE_VGA=1
 default CONFIG_PCI_ROM_RUN=1
 
-default CONFIG_USBDEBUG_DIRECT=1
+#default CONFIG_USBDEBUG_DIRECT=1
 
 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
 default HT_CHAIN_UNITID_BASE=0
Index: util/abuild/abuild
===================================================================
--- util/abuild/abuild.orig
+++ util/abuild/abuild
@@ -142,14 +142,14 @@ EOF
 			cat <<EOF
 romimage "normal"
 	option USE_FALLBACK_IMAGE=0
-	option ROM_IMAGE_SIZE=0x16000
+	option ROM_IMAGE_SIZE=0x17000
 	option LINUXBIOS_EXTRA_VERSION=".0-normal"
 	payload PAYLOAD
 end
 
 romimage "fallback" 
 	option USE_FALLBACK_IMAGE=1
-	option ROM_IMAGE_SIZE=0x16000
+	option ROM_IMAGE_SIZE=0x17000
 	option LINUXBIOS_EXTRA_VERSION=".0-fallback"
 	payload PAYLOAD
 end
