coreboot-4.0-4742-g553fe1c Sun Oct 20 19:33:38 CEST 2013 starting...
now booting... romstage


coreboot-4.0-4742-g553fe1c Sun Oct 20 19:33:38 CEST 2013 starting...
now booting... real_main
Enabling routing table for node 00 done.
Enabling UP settings
coherent_ht_finalize
done
core0 started: 
now booting... Core0 started
started ap apicid: * AP 01started

SBLink=00
NC node|link=00
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0x6e, unfiltered freq_cap=0x75
pos=0x6e, filtered freq_cap=0x75
freq_cap1=0x75, freq_cap2=0x75
dev1 old_freq=0x0, freq=0x6, needs_reset=0x1
dev2 old_freq=0x0, freq=0x6, needs_reset=0x1
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x1
after optimize_link_read_pointers_chain, reset_needed=0x1
K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06 VIA HT caps: 0075
ht reset -
soft r

coreboot-4.0-4742-g553fe1c Sun Oct 20 19:33:38 CEST 2013 starting...
now booting... romstage


coreboot-4.0-4742-g553fe1c Sun Oct 20 19:33:38 CEST 2013 starting...
now booting... real_main
Enabling routing table for node 00 done.
Enabling UP settings
coherent_ht_finalize
done
core0 started: 
now booting... Core0 started
started ap apicid: * AP 01started

SBLink=00
NC node|link=00
entering optimize_link_incoherent_ht
sysinfo->link_pair_num=0x1
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0x6e, unfiltered freq_cap=0x75
pos=0x6e, filtered freq_cap=0x75
freq_cap1=0x75, freq_cap2=0x75
dev1 old_freq=0x6, freq=0x6, needs_reset=0x0
dev2 old_freq=0x6, freq=0x6, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
after ht_optimize_link for link pair 0, reset_needed=0x0
after optimize_link_read_pointers_chain, reset_needed=0x0
K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 06 VIA HT caps: 0075
Current fid_cur: 0x10, fid_max: 0x10
Requested fid_new: 0x10
Ram1.00
setting up CPU00 northbridge registers
done.
Ram2.00
Device error
Device error
Enabling dual channel memory
Registered
200MHz
Interleaved
RAM end at 0x00200000 kB
Lower RAM end at 0x00200000 kB
Ram3
ECC enabled
Initializing memory:  done
Ram4
v_esp=000cff08
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Clearing initial memory region: Done
Loading image.
CBFS: CBFS_HEADER_ROM_ADDRESS: 0xfffffc00/0x80000
CBFS: CBFS location: 0x0~0x7fc20, align: 64
CBFS: Looking for 'fallback/coreboot_ram' starting from 0x0.
CBFS:  - load entry 0x0 file name (16 bytes)...
CBFS:  (unmatched file @0x0: cmos_layout.bin)
CBFS:  - load entry 0x740 file name (32 bytes)...
CBFS:  (unmatched file @0x740: fallback/romstage)
CBFS:  - load entry 0xb200 file name (32 bytes)...
CBFS: Found file (offset=0xb238, len=60432).
CBFS: loading stage fallback/coreboot_ram @ 0x100000 (516152 bytes), entry @ 0x100000
CBFS: stage loaded.
Jumping to image.