Index: src/include/device/pci_ids.h
===================================================================
--- src/include/device/pci_ids.h	(revision 4264)
+++ src/include/device/pci_ids.h	(working copy)
@@ -1866,6 +1866,7 @@
 #define PCI_DEVICE_ID_INTEL_80960_RP	0x1960
 #define PCI_DEVICE_ID_INTEL_82437VX	0x7030
 #define PCI_DEVICE_ID_INTEL_82439TX	0x7100
+#define PCI_DEVICE_ID_INTEL_82810E_IG	0x7125
 
 /* Intel 82371FB (PIIX) */
 #define PCI_DEVICE_ID_INTEL_82371FB_ISA		0x122e
Index: src/northbridge/intel/i82810/Config.lb
===================================================================
--- src/northbridge/intel/i82810/Config.lb	(revision 4264)
+++ src/northbridge/intel/i82810/Config.lb	(working copy)
@@ -18,10 +18,10 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-uses HAVE_HIGH_TABLES
+#uses HAVE_HIGH_TABLES
 
 config chip.h
 
 driver northbridge.o
 
-default HAVE_HIGH_TABLES=1
+#default HAVE_HIGH_TABLES=1
Index: src/northbridge/intel/i82810/raminit.c
===================================================================
--- src/northbridge/intel/i82810/raminit.c	(revision 4264)
+++ src/northbridge/intel/i82810/raminit.c	(working copy)
@@ -276,9 +276,117 @@
  * 0x4445   384MB   0xfd   128MB single-sided   256MB dual-sided
  * 0x0001   512MB   0xff   256MB dual-sided     256MB dual-sided
  */
+
+struct dimm_info {
+	u8 dual;
+	u8 single;
+	u8 size;
+};
+
 static void set_dram_buffer_strength(void)
 {
-	pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, 0x77da);
+	struct dimm_info dimm0, dimm1;
+	u16 buff_sc;
+
+	/* check 1st slot */
+	if (smbus_read_byte(DIMM_SPD_BASE, 2) == 4) {
+		dimm0.size = smbus_read_byte(DIMM_SPD_BASE, 31);
+		dimm0.dual = (smbus_read_byte(DIMM_SPD_BASE, 5) > 1);
+		dimm0.single = !dimm0.dual;
+	} else {
+		dimm0.size = dimm0.dual = dimm0.single = 0;
+	}
+
+	/* check 2nd slot */
+	if (smbus_read_byte(DIMM_SPD_BASE + 1, 2) == 4) {
+		dimm1.size = smbus_read_byte(DIMM_SPD_BASE + 1, 31);
+		dimm1.dual = (smbus_read_byte(DIMM_SPD_BASE + 1, 5) > 1);
+		dimm1.single = !dimm1.dual;
+	} else {
+		dimm1.size = dimm1.dual = dimm1.single = 0;
+	}
+	
+	buff_sc = 0;
+	/* tame the beast... */
+	if ( (dimm0.dual && dimm1.dual) || 
+		(dimm0.dual && dimm1.single) || 
+		(dimm0.single && dimm1.dual) ) {
+		buff_sc |= 1;
+	}
+	if ( (dimm0.size && !dimm1.size) || 
+		(!dimm0.size && dimm1.size) || 
+		(dimm0.single && dimm1.single) ) {
+		buff_sc |= 1 << 1;
+	}
+	if ( (dimm0.dual && !dimm1.size) || 
+		(!dimm0.size && dimm1.dual) || 
+		(dimm0.single && dimm1.single) ||
+		(dimm0.dual && dimm1.single) ||
+		(dimm0.single && dimm1.dual) ) {
+		buff_sc |= 1 << 2;
+	}
+	if ( (dimm0.single && !dimm1.size) || 
+		(!dimm0.size && dimm1.single) ) {
+		buff_sc |= 1 << 3;
+	}
+	if ( (dimm0.size && !dimm1.size) || 
+		(!dimm0.size && dimm1.size) ) {
+		buff_sc |= 1 << 4;
+	}
+	if ( (dimm0.dual && !dimm1.size) || 
+		(!dimm0.size && dimm1.dual) || 
+		(dimm0.dual && dimm1.single) || 
+		(dimm0.single && dimm1.dual) ) {
+		buff_sc |= 1 << 6;
+	}
+	if ( (dimm0.single && !dimm1.size) || 
+		(!dimm0.size && dimm1.single) || 
+		(dimm0.single && dimm1.single) ) {
+		buff_sc |= 3 << 6;
+	}
+	if ( (!dimm0.size && dimm1.single) || 
+		(dimm0.dual && dimm1.single) || 
+		(dimm0.single && dimm1.single) ) {
+		buff_sc |= 1 << 8;
+	}
+	if (dimm0.size && !dimm1.size) {
+		buff_sc |= 3 << 8;
+	}
+	if ( (dimm0.single && !dimm1.size) || 
+		(dimm0.single && dimm1.single) || 
+		(dimm0.single && dimm1.dual) ) {
+		buff_sc |= 1 << 10;
+	}
+	if (!dimm0.size && dimm1.size) {
+		buff_sc |= 3 << 10;
+	}
+	if ( (dimm0.size && !dimm1.size) || 
+		(dimm0.single && !dimm1.size) || 
+		(!dimm0.size && dimm1.single) ||
+		(dimm0.single && dimm1.single) ||
+		(dimm0.dual && dimm1.single) ) {
+		buff_sc |= 1 << 12;
+	}
+	if (dimm0.size && !dimm1.size) {
+		buff_sc |= 1 << 13;
+	}
+	if ( (!dimm0.size && dimm1.size) || 
+		(dimm0.single && !dimm1.size) || 
+		(dimm0.single && dimm1.single) ||
+		(dimm0.single && dimm1.dual) ) {
+		buff_sc |= 1 << 14;
+	}
+	if (!dimm0.size && dimm1.size) {
+		buff_sc |= 1 << 15;
+	}
+	
+	print_debug("BUFF_SC calculated to 0x");
+	print_debug_hex16(buff_sc);
+	print_debug("\r\n");
+
+
+	/* go a head and set the BUFF_SC */
+	pci_write_config16(PCI_DEV(0, 0, 0), BUFF_SC, buff_sc);
 }
 
 /*-----------------------------------------------------------------------------
@@ -287,10 +395,15 @@
 
 static void sdram_set_registers(void)
 {
+	u8 value;
 	unsigned long val;
 
-	/* TODO */
-	pci_write_config8(PCI_DEV(0, 0, 0), GMCHCFG, 0x60);
+	value = pci_read_config8(PCI_DEV(0, 0, 0), GMCHCFG);
+	/* Preserve reserved bits. */
+	val &= 0xa4;
+	/* set the GMCH to prechange all during the service of a page miss */
+	val |= 0x28;
+	pci_write_config8(PCI_DEV(0, 0, 0), GMCHCFG, val);
 
 	/* PAMR: Programmable Attributes Register
 	 * Every pair of bits controls an address range:
@@ -308,24 +421,51 @@
 
 	/* Ideally, this should be R/W for as many ranges as possible. */
 	pci_write_config8(PCI_DEV(0, 0, 0), PAM, 0xff);
-
-	/* Enabling the VGA Framebuffer currently screws up the rest of the boot.
-	 * Disable for now */
+	/* or we can use sane defaults, but VGA won't work for unknown reason */
+	//pci_write_config8(PCI_DEV(0, 0, 0), PAM, 0x41);
 	
-	/* Enable 1MB framebuffer. */
-	//pci_write_config8(PCI_DEV(0, 0, 0), SMRAM, 0xC0);
+	/* set System Management RAM Control Register / Graphics Mode Select */
+	value = pci_read_config8(PCI_DEV(0, 0, 0), SMRAM);
+	/* Set size for Onboard-VGA framebuffer. */
+#ifdef CONFIG_VIDEO_MB
+	switch (CONFIG_VIDEO_MB) {
+	case 512: /* 512K of memory */
+		value |= 2 << 6;
+		break;
+	case 1: /* 1M of memory */
+		value |= 3 << 6;
+		break;
+	default: /* No VGA memory */
+		/* Preserve bits except for GMS */
+		value &= 0x3f;
+		break;
+	}
+#endif
+	/* set AB segment Enabled as SMM RAM */
+	value |= 0x0C;
+	pci_write_config8(PCI_DEV(0, 0, 0), SMRAM, value);
 
-	//val = pci_read_config16(PCI_DEV(0, 0, 0), MISSC);
+	/* Set the value for Fixed DRAM Hole Control Register */
+	pci_write_config8(PCI_DEV(0, 0, 0), FDHC, 0x00);
+
+	val = pci_read_config16(PCI_DEV(0, 0, 0), MISSC);
 	/* Preserve reserved bits. */
-	//val &= 0xff06;
-	/* Set graphics cache window to 32MB, no power throttling. */
+	val &= 0xff06;
+	/* Set graphics cache window to 32MB, no power throttling. 0 for 64MB.*/
 	//val |= 0x0001;
-	//pci_write_config16(PCI_DEV(0, 0, 0), MISSC, val);
+	pci_write_config16(PCI_DEV(0, 0, 0), MISSC, val);
 
-	//val = pci_read_config8(PCI_DEV(0, 0, 0), MISSC2);
+	val = 0;
+	val = pci_read_config8(PCI_DEV(0, 0, 0), MISSC2);
+	/* Preserve reserved bits. */
+	val &= 0xf9;
 	/* Enable graphics palettes and clock gating (not optional!) */
-	//val |= 0x06;
-	//pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, val);
+	val |= 0x06;
+	
+	val |= 0xc6;
+	pci_write_config8(PCI_DEV(0, 0, 0), MISSC2, val);
+
+	print_debug("i810 Initial registers have been set.\r\n");
 }
 
 static void sdram_set_spd_registers(void)
@@ -341,6 +481,7 @@
 static void sdram_enable(void)
 {
 	int i;
+	u8 reg8;
 
 	/* 1. Apply NOP. */
 	PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
@@ -369,6 +510,17 @@
 	do_ram_command(RAM_COMMAND_NORMAL);
 	udelay(1);
 
-	PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
-	DUMPNORTH();
+	/* 6. Enable refresh */
+	PRINT_DEBUG("RAM Enable 6: Enable Refresh\r\n");
+	reg8 = pci_read_config8(PCI_DEV(0, 0, 0), DRAMT);
+	/* set SDRAM Mode Select for Normal Operation, refresh 15.6usec */
+	reg8 |= 0x20;
+	pci_write_config8(PCI_DEV(0, 0, 0), DRAMT, reg8);
+
+	/* Intel reserved, which seems to be needed */
+	pci_write_config8(PCI_DEV(0, 0, 0), 0x81, 0x78);
+	pci_write_config8(PCI_DEV(0, 0, 0), 0x82, 0x1d);
+
+	//PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
+	//DUMPNORTH();
 }
Index: src/northbridge/intel/i82810/northbridge.c
===================================================================
--- src/northbridge/intel/i82810/northbridge.c	(revision 4264)
+++ src/northbridge/intel/i82810/northbridge.c	(working copy)
@@ -37,21 +37,43 @@
 	printk_spew("Northbridge init\n");
 }
 
+static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	u32 pci_id;
+
+	printk_debug("Setting PCI bridge subsystem ID\n");
+	pci_id = pci_read_config32(dev, 0);
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, pci_id );
+}
+
+static struct pci_operations intel_pci_ops = {
+	.set_subsystem    = intel_set_subsystem,
+};
+
 static struct device_operations northbridge_operations = {
 	.read_resources		= pci_dev_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= northbridge_init,
 	.enable			= 0,
-	.ops_pci		= 0,
+	.ops_pci		= &intel_pci_ops,
 };
 
-static const struct pci_driver northbridge_driver __pci_driver = {
+/* structure for 82810 */
+static const struct pci_driver i810_northbridge_driver __pci_driver = {
 	.ops	= &northbridge_operations,
 	.vendor	= PCI_VENDOR_ID_INTEL,
 	.device	= 0x7120,
 };
 
+/* structure for 82810e */
+static const struct pci_driver i810e_northbridge_driver __pci_driver = {
+	.ops    = &northbridge_operations,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x7124,
+};
+
+
 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
 
 static void pci_domain_read_resources(device_t dev)
@@ -160,6 +182,22 @@
 		/* Convert tomk from MB to KB. */
 		tomk = tomk << 10;
 
+#ifdef CONFIG_VIDEO_MB
+		/* check for VGA reserved memory
+		* possible CONFIG_VIDEO_MB values are 512(kb) and 1(mb)
+		*/
+		if (CONFIG_VIDEO_MB == 512) {
+			tomk -= 512;
+			printk_debug("Allocating 512KB of RAM for VGA\n");
+		} else if (CONFIG_VIDEO_MB == 1) {
+			tomk -= 1024 ;
+			printk_debug("Allocating 1MB of RAM for VGA\n");
+		} else {
+			/* assume no vga if incorrect value */
+			tomk == tomk;
+		}
+#endif
+
 		/* Compute the top of Low memory. */
 		tolmk = pci_tolm >> 10;
 		if (tolmk >= tomk) {
