Author: uwe Date: Fri Oct 1 01:15:36 2010 New Revision: 5888 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5888
Log: Various cosmetic and coding style fixes in CAR code (trivial).
Also, whitespace fixes, consistency fixes, and drop some of the less useful comments.
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: trunk/src/cpu/amd/car/cache_as_ram.inc trunk/src/cpu/intel/car/cache_as_ram.inc trunk/src/cpu/via/car/cache_as_ram.inc
Modified: trunk/src/cpu/amd/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/car/cache_as_ram.inc Thu Sep 30 23:22:40 2010 (r5887) +++ trunk/src/cpu/amd/car/cache_as_ram.inc Fri Oct 1 01:15:36 2010 (r5888) @@ -18,76 +18,82 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#define CacheSize CONFIG_DCACHE_RAM_SIZE -#define CacheBase (0xd0000 - CacheSize) +#include <cpu/x86/mtrr.h> +#include <cpu/amd/mtrr.h> + +#define CacheSize CONFIG_DCACHE_RAM_SIZE +#define CacheBase (0xd0000 - CacheSize)
-/* leave some space for global variable to pass to RAM stage */ -#define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE +/* Leave some space for global variable to pass to RAM stage. */ +#define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-/* for CAR with FAM10 */ -#define CacheSizeAPStack 0x400 /* 1K */ +/* For CAR with Fam10h. */ +#define CacheSizeAPStack 0x400 /* 1K */
-#define MSR_MCFG_BASE 0xC0010058 -#define MSR_FAM10 0xC001102A +#define MSR_MCFG_BASE 0xC0010058 +#define MSR_FAM10 0xC001102A
-#define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x +#define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x
-#define CPUID_MASK 0x0ff00f00 +#define CPUID_MASK 0x0ff00f00 #define CPUID_VAL_FAM10_ROTATED 0x0f000010
-#include <cpu/x86/mtrr.h> -#include <cpu/amd/mtrr.h> /* * XMM map: - * xmm1: cpu family - * xmm2: fam10 comparison value - * xmm3: backup ebx + * xmm1: CPU family + * xmm2: Fam10h comparison value + * xmm3: Backup EBX */
- /* Save the BIST result */ + /* Save the BIST result. */ movl %eax, %ebp
- /* for normal part %ebx already contain cpu_init_detected from fallback call */ + /* + * For normal part %ebx already contain cpu_init_detected + * from fallback call. + */
cache_as_ram_setup: post_code(0xa0)
- /* enable SSE */ - movl %cr4, %eax - orl $(3<<9), %eax - movl %eax, %cr4 + /* Enable SSE. */ + movl %cr4, %eax + orl $(3 << 9), %eax + movl %eax, %cr4
- /* figure out cpu family */ + /* Figure out the CPU family. */ cvtsi2sd %ebx, %xmm3 movl $0x01, %eax cpuid - /* base family is bits 8..11, extended family is bits 20..27 */ + /* Base family is bits 8..11, extended family is bits 20..27. */ andl $CPUID_MASK, %eax - /* reorder bits for easier comparison by value */ + /* Reorder bits for easier comparison by value. */ roll $0x10, %eax cvtsi2sd %eax, %xmm1 movl $CPUID_VAL_FAM10_ROTATED, %eax cvtsi2sd %eax, %xmm2 cvtsd2si %xmm3, %ebx
- /* check if cpu_init_detected */ + /* Check if cpu_init_detected. */ movl $MTRRdefType_MSR, %ecx rdmsr andl $(1 << 11), %eax - movl %eax, %ebx /* We store the status */ + movl %eax, %ebx /* We store the status. */
jmp_if_k8(CAR_FAM10_out_post_errata)
- /* for GH, CAR need to set DRAM Base/Limit Registers to direct that to node0 */ - - /* Only BSP needed, for other nodes set during HT/memory init. */ - /* So we need to check if it is BSP */ + /* + * For GH, CAR need to set DRAM Base/Limit registers to direct that + * to node0. + * Only BSP needed, for other nodes set during HT/memory init. + * So we need to check if it is BSP. + */ movl $0x1b, %ecx rdmsr - bt $8, %eax /*BSC */ + bt $8, %eax /* BSC */ jnc CAR_FAM10_out
- /* Enable RT tables on BSP */ + /* Enable RT tables on BSP. */ movl $0x8000c06c, %eax movw $0xcf8, %dx outl %eax, %dx @@ -96,7 +102,7 @@ btr $0, %eax outl %eax, %dx
- /* Setup temporary DRAM map: [0,16M) bit 0-23 */ + /* Setup temporary DRAM map: [0,16M) bit 0-23. */ movl $0x8000c144, %eax movw $0xcf8, %dx outl %eax, %dx @@ -113,8 +119,9 @@
CAR_FAM10_out:
- /* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM. - * Re-enable it in after RAM is initialized and before CAR is disabled + /* + * Errata 193: Disable clean copybacks to L3 cache to allow cached ROM. + * Re-enable it in after RAM is initialized and before CAR is disabled. */ movl $MSR_FAM10, %ecx rdmsr @@ -122,23 +129,13 @@ wrmsr
/* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */ - - /* read-address has to be stored in the ecx register */ movl $MSR_FAM10, %ecx - - /* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */ rdmsr - - /* Set bit 35 to 1 in EAX:EDX */ - bts $35-32, %edx - - /* write back the modified register EDX:EAX to the MSR specified in ECX */ + bts $35-32, %edx /* Set bit 35 in EDX:EAX (bit 3 in EDX). */ wrmsr
- /* Erratum 343 end */ - #if CONFIG_MMCONF_SUPPORT - /* Set MMIO Config space BAR */ + /* Set MMIO Config space BAR. */ movl $MSR_MCFG_BASE, %ecx rdmsr
@@ -152,7 +149,7 @@
CAR_FAM10_out_post_errata:
- /* Set MtrrFixDramModEn for clear fixed mtrr */ + /* Set MtrrFixDramModEn for clear fixed MTRR. */ enable_fixed_mtrr_dram_modify: movl $SYSCFG_MSR, %ecx rdmsr @@ -160,7 +157,7 @@ orl $SYSCFG_MSR_MtrrFixDramModEn, %eax wrmsr
- /* Clear all MTRRs */ + /* Clear all MTRRs. */ xorl %edx, %edx movl $fixed_mtrr_msr, %esi
@@ -176,59 +173,63 @@ jmp clear_fixed_var_mtrr clear_fixed_var_mtrr_out:
-/* 0x06 is the WB IO type for a given 4k segment. +/* + * 0x06 is the WB IO type for a given 4k segment. * 0x1e is the MEM IO type for a given 4k segment (K10 and above). * segs is the number of 4k segments in the area of the particular - * register we want to use for CAR. + * register we want to use for CAR. * reg is the register where the IO type should be stored. */ .macro extractmask segs, reg .if \segs <= 0 - /* The xorl here is superfluous because at the point of first execution + /* + * The xorl here is superfluous because at the point of first execution * of this macro, %eax and %edx are cleared. Later invocations of this * macro will have a monotonically increasing segs parameter. */ - xorl \reg, \reg + xorl \reg, \reg .else jmp_if_k8(1f)
.if \segs == 1 - movl $0x1e000000, \reg /* WB MEM type */ + movl $0x1e000000, \reg /* WB MEM type */ .elseif \segs == 2 - movl $0x1e1e0000, \reg /* WB MEM type */ + movl $0x1e1e0000, \reg /* WB MEM type */ .elseif \segs == 3 - movl $0x1e1e1e00, \reg /* WB MEM type */ + movl $0x1e1e1e00, \reg /* WB MEM type */ .elseif \segs >= 4 - movl $0x1e1e1e1e, \reg /* WB MEM type */ + movl $0x1e1e1e1e, \reg /* WB MEM type */ .endif jmp 2f 1: .if \segs == 1 - movl $0x06000000, \reg /* WB IO type */ + movl $0x06000000, \reg /* WB IO type */ .elseif \segs == 2 - movl $0x06060000, \reg /* WB IO type */ + movl $0x06060000, \reg /* WB IO type */ .elseif \segs == 3 - movl $0x06060600, \reg /* WB IO type */ + movl $0x06060600, \reg /* WB IO type */ .elseif \segs >= 4 - movl $0x06060606, \reg /* WB IO type */ + movl $0x06060606, \reg /* WB IO type */ .endif 2: .endif /* if \segs <= 0 */ .endm
-/* size is the cache size in bytes we want to use for CAR. - * windowoffset is the 32k-aligned window into CAR size +/* + * size is the cache size in bytes we want to use for CAR. + * windowoffset is the 32k-aligned window into CAR size. */ .macro simplemask carsize, windowoffset .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4) extractmask gas_bug_workaround, %eax .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000)) extractmask gas_bug_workaround, %edx -/* Without the gas bug workaround, the entire macro would consist only of the - * two lines below. - extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax - extractmask (((\carsize - \windowoffset) / 0x1000)), %edx - */ + /* + * Without the gas bug workaround, the entire macro would consist + * only of the two lines below: + * extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax + * extractmask (((\carsize - \windowoffset) / 0x1000)), %edx + */ .endm
#if CacheSize > 0x10000 @@ -242,18 +243,18 @@ #endif
#if CacheSize > 0x8000 - /* enable caching for 32K-64K using fixed mtrr */ + /* Enable caching for 32K-64K using fixed MTRR. */ movl $MTRRfix4K_C0000_MSR, %ecx simplemask CacheSize, 0x8000 wrmsr #endif
- /* enable caching for 0-32K using fixed mtrr */ + /* Enable caching for 0-32K using fixed MTRR. */ movl $MTRRfix4K_C8000_MSR, %ecx simplemask CacheSize, 0 wrmsr
- /* enable memory access for first MBs using top_mem */ + /* Enable memory access for first MBs using top_mem. */ movl $TOP_MEM, %ecx xorl %edx, %edx movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax @@ -267,13 +268,13 @@ #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #endif
- /* enable write base caching so we can do execute in place - * on the flash rom. + /* Enable write base caching so we can do execute in place (XIP) + * on the flash ROM. */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx - movl $REAL_XIP_ROM_BASE, %eax - orl $MTRR_TYPE_WRBACK, %eax + movl $REAL_XIP_ROM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax wrmsr
movl $MTRRphysMask_MSR(1), %ecx @@ -285,14 +286,13 @@ wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
- /* Set the default memory type and enable fixed and variable MTRRs */ + /* Set the default memory type and enable fixed and variable MTRRs. */ movl $MTRRdefType_MSR, %ecx xorl %edx, %edx - /* Enable Variable and Fixed MTRRs */ - movl $0x00000c00, %eax + movl $0x00000c00, %eax /* Enable variable and fixed MTRRs. */ wrmsr
- /* Enable the MTRRs and IORRs in SYSCFG */ + /* Enable the MTRRs and IORRs in SYSCFG. */ movl $SYSCFG_MSR, %ecx rdmsr orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax @@ -300,35 +300,35 @@
post_code(0xa1)
- /* enable cache */ + /* Enable cache. */ movl %cr0, %eax andl $0x9fffffff, %eax movl %eax, %cr0
jmp_if_k8(fam10_end_part1)
- /* So we need to check if it is BSP */ + /* So we need to check if it is BSP. */ movl $0x1b, %ecx rdmsr - bt $8, %eax /*BSC */ + bt $8, %eax /* BSC */ jnc CAR_FAM10_ap fam10_end_part1:
post_code(0xa2)
- /* Read the range with lodsl*/ + /* Read the range with lodsl. */ cld movl $CacheBase, %esi movl $(CacheSize >> 2), %ecx rep lodsl
- /* Clear the range */ + /* Clear the range. */ movl $CacheBase, %edi movl $(CacheSize >> 2), %ecx xorl %eax, %eax rep stosl
- /* set up the stack pointer */ + /* Set up the stack pointer. */ movl $(CacheBase + CacheSize - GlobalVarSize), %eax movl %eax, %esp
@@ -336,42 +336,47 @@
jmp CAR_FAM10_ap_out CAR_FAM10_ap: - /* need to set stack pointer for AP */ - /* it will be from CacheBase + (CacheSize - GlobalVarSize)/2 - (NodeID<<CoreIDbits + CoreID) * CacheSizeAPStack*/ - /* So need to get the NodeID and CoreID at first */ - /* If NB_CFG bit 54 is set just use initial apicid, otherwise need to reverse it */ + /* + * Need to set stack pointer for AP. + * It will be from: + * CacheBase + (CacheSize - GlobalVarSize) / 2 + * - (NodeID << CoreIDbits + CoreID) * CacheSizeAPStack + * So need to get the NodeID and CoreID at first. + * If NB_CFG bit 54 is set just use initial APIC ID, otherwise need + * to reverse it. + */
- /* store our init detected */ + /* Store our init detected. */ movl %ebx, %esi
- /* get the coreid bits at first */ + /* Get the coreid bits at first. */ movl $0x80000008, %eax cpuid shrl $12, %ecx andl $0x0f, %ecx movl %ecx, %edi
- /* get the initial apic id */ + /* Get the initial APIC ID. */ movl $1, %eax cpuid shrl $24, %ebx
- /* get the nb cfg bit 54 */ - movl $0xc001001f, %ecx /* NB_CFG_MSR */ + /* Get the nb cfg bit 54. */ + movl $0xc001001f, %ecx /* NB_CFG_MSR */ rdmsr - movl %edi, %ecx /* CoreID bits */ + movl %edi, %ecx /* CoreID bits */ bt $(54-32), %edx jc roll_cfg rolb %cl, %bl roll_cfg:
- /* calculate stack pointer */ + /* Calculate stack pointer. */ movl $CacheSizeAPStack, %eax mull %ebx - movl $(CacheBase + (CacheSize - GlobalVarSize)/2), %esp + movl $(CacheBase + (CacheSize - GlobalVarSize) / 2), %esp subl %eax, %esp
- /* retrive init detected */ + /* Retrive init detected. */ movl %esi, %ebx
post_code(0xa4) @@ -380,35 +385,38 @@
post_code(0xa5)
- /* disable SSE */ - movl %cr4, %eax - andl $~(3<<9), %eax - movl %eax, %cr4 + /* Disable SSE. */ + movl %cr4, %eax + andl $~(3 << 9), %eax + movl %eax, %cr4
- /* Restore the BIST result */ + /* Restore the BIST result. */ movl %ebp, %eax
- /* We need to set ebp ? No need */ + /* We need to set EBP? No need. */ movl %esp, %ebp - pushl %ebx /* init detected */ - pushl %eax /* bist */ + pushl %ebx /* Init detected. */ + pushl %eax /* BIST */ call cache_as_ram_main - /* We will not go back */ + /* We will not go back. */
- post_code(0xaf) /* Should never see this postcode */ + post_code(0xaf) /* Should never see this POST code. */
fixed_mtrr_msr: .long 0x250, 0x258, 0x259 .long 0x268, 0x269, 0x26A .long 0x26B, 0x26C, 0x26D .long 0x26E, 0x26F + var_mtrr_msr: .long 0x200, 0x201, 0x202, 0x203 .long 0x204, 0x205, 0x206, 0x207 .long 0x208, 0x209, 0x20A, 0x20B .long 0x20C, 0x20D, 0x20E, 0x20F + var_iorr_msr: .long 0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019 + mem_top: .long 0xC001001A, 0xC001001D .long 0x000 /* NULL, end of table */
Modified: trunk/src/cpu/intel/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/car/cache_as_ram.inc Thu Sep 30 23:22:40 2010 (r5887) +++ trunk/src/cpu/intel/car/cache_as_ram.inc Fri Oct 1 01:15:36 2010 (r5888) @@ -21,18 +21,18 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#define CacheSize CONFIG_DCACHE_RAM_SIZE -#define CacheBase (0xd0000 - CacheSize) - #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/lapic_def.h>
- /* Save the BIST result */ +#define CacheSize CONFIG_DCACHE_RAM_SIZE +#define CacheBase (0xd0000 - CacheSize) + + /* Save the BIST result. */ movl %eax, %ebp
CacheAsRam: - // Check whether the processor has HT capability + /* Check whether the processor has HT capability. */ movl $01, %eax cpuid btl $28, %edx @@ -41,20 +41,26 @@ cmpb $01, %bh jbe NotHtProcessor
- // It is a HT processor; Send SIPI to the other logical processor - // within this processor so that the CAR related common system - // registers are programmed accordingly. + /* + * It is a HT processor. Send SIPI to the other logical processor + * within this processor so that the CAR related common system + * registers are programmed accordingly. + */
- // Use some register that is common to both logical processors - // as semaphore. Refer Appendix B, Vol.3 + /* + * Use some register that is common to both logical processors + * as semaphore. Refer Appendix B, Vol.3. + */ xorl %eax, %eax xorl %edx, %edx movl $MTRRfix64K_00000_MSR, %ecx wrmsr
- // Figure out the logical AP's APIC ID; the following logic will - // work only for processors with 2 threads. - // Refer to Vol 3. Table 7-1 for details about this logic + /* + * Figure out the logical AP's APIC ID; the following logic will + * work only for processors with 2 threads. + * Refer to Vol 3. Table 7-1 for details about this logic. + */ movl $0xFEE00020, %esi movl (%esi), %ebx andl $0xFF000000, %ebx @@ -66,17 +72,19 @@ LogicalAP0: orb $0x01, %bl Send_SIPI: - bswapl %ebx // ebx - logical AP's APIC ID + bswapl %ebx /* EBX - logical AP's APIC ID. */
- // Fill up the IPI command registers in the Local APIC mapped to - // default address and issue SIPI to the other logical processor - // within this processor die. + /* + * Fill up the IPI command registers in the Local APIC mapped to + * default address and issue SIPI to the other logical processor + * within this processor die. + */ Retry_SIPI: movl %ebx, %eax movl $0xFEE00310, %esi movl %eax, (%esi)
- // SIPI vector - F900:0000 + /* SIPI vector - F900:0000 */ movl $0x000006F9, %eax movl $0xFEE00300, %esi movl %eax, (%esi) @@ -91,7 +99,7 @@ andl $0x00001000, %eax jnz Retry_SIPI
- // Wait for the Logical AP to complete initialization + /* Wait for the Logical AP to complete initialization. */ LogicalAP_SIPINotdone: movl $MTRRfix64K_00000_MSR, %ecx rdmsr @@ -99,14 +107,13 @@ jz LogicalAP_SIPINotdone
NotHtProcessor: - /* Set the default memory type and enable fixed and variable MTRRs */ + /* Set the default memory type and enable fixed and variable MTRRs. */ movl $MTRRdefType_MSR, %ecx xorl %edx, %edx - /* Enable Variable and Fixed MTRRs */ - movl $0x00000c00, %eax + movl $0x00000c00, %eax /* Enable variable and fixed MTRRs. */ wrmsr
- /* Clear all MTRRs */ + /* Clear all MTRRs. */ xorl %edx, %edx movl $fixed_mtrr_msr, %esi
@@ -126,6 +133,7 @@ .long 0x268, 0x269, 0x26A .long 0x26B, 0x26C, 0x26D .long 0x26E, 0x26F + var_mtrr_msr: .long 0x200, 0x201, 0x202, 0x203 .long 0x204, 0x205, 0x206, 0x207 @@ -135,14 +143,16 @@
clear_fixed_var_mtrr_out:
-/* 0x06 is the WB IO type for a given 4k segment. +/* + * 0x06 is the WB IO type for a given 4k segment. * segs is the number of 4k segments in the area of the particular * register we want to use for CAR. * reg is the register where the IO type should be stored. */ .macro extractmask segs, reg .if \segs <= 0 - /* The xorl here is superfluous because at the point of first execution + /* + * The xorl here is superfluous because at the point of first execution * of this macro, %eax and %edx are cleared. Later invocations of this * macro will have a monotonically increasing segs parameter. */ @@ -158,19 +168,21 @@ .endif .endm
-/* size is the cache size in bytes we want to use for CAR. - * windowoffset is the 32k-aligned window into CAR size +/* + * size is the cache size in bytes we want to use for CAR. + * windowoffset is the 32k-aligned window into CAR size. */ .macro simplemask carsize, windowoffset .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000) - 4) extractmask gas_bug_workaround, %eax .set gas_bug_workaround,(((\carsize - \windowoffset) / 0x1000)) extractmask gas_bug_workaround, %edx -/* Without the gas bug workaround, the entire macro would consist only of the - * two lines below. - extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax - extractmask (((\carsize - \windowoffset) / 0x1000)), %edx - */ + /* + * Without the gas bug workaround, the entire macro would consist + * only of the two lines below: + * extractmask (((\carsize - \windowoffset) / 0x1000) - 4), %eax + * extractmask (((\carsize - \windowoffset) / 0x1000)), %edx + */ .endm
#if CacheSize > 0x10000 @@ -184,13 +196,13 @@ #endif
#if CacheSize > 0x8000 - /* enable caching for 32K-64K using fixed mtrr */ + /* Enable caching for 32K-64K using fixed MTRR. */ movl $MTRRfix4K_C0000_MSR, %ecx simplemask CacheSize, 0x8000 wrmsr #endif
- /* enable caching for 0-32K using fixed mtrr */ + /* Enable caching for 0-32K using fixed MTRR. */ movl $MTRRfix4K_C8000_MSR, %ecx simplemask CacheSize, 0 wrmsr @@ -203,8 +215,9 @@ #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #endif
- /* enable write base caching so we can do execute in place - * on the flash rom. + /* + * Enable write base caching so we can do execute in place (XIP) + * on the flash ROM. */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx @@ -218,27 +231,27 @@ wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
- /* enable cache */ + /* Enable cache. */ movl %cr0, %eax andl $0x9fffffff, %eax movl %eax, %cr0
- /* Read the range with lodsl*/ + /* Read the range with lodsl. */ movl $CacheBase, %esi cld movl $(CacheSize >> 2), %ecx rep lodsl
- /* Clear the range */ + /* Clear the range. */ movl $CacheBase, %edi movl $(CacheSize >> 2), %ecx xorl %eax, %eax rep stosl
#if 0 - /* check the cache as ram */ + /* Check the cache as ram. */ movl $CacheBase, %esi - movl $(CacheSize>>2), %ecx + movl $(CacheSize >> 2), %ecx .xin1: movl %esi, %eax movl %eax, (%esi) @@ -249,29 +262,30 @@ .xout1:
movl $CacheBase, %esi -// movl $(CacheSize>>2), %ecx - movl $4, %ecx + // movl $(CacheSize >> 2), %ecx + movl $4, %ecx .xin1x: movl %esi, %eax
movl $0x4000, %edx movb %ah, %al .testx1: - outb %al, $0x80 + outb %al, $0x80 decl %edx - jnz .testx1 + jnz .testx1
movl (%esi), %eax - cmpb 0xff, %al - je .xin2 /* dont show */ + cmpb 0xff, %al + je .xin2 /* Don't show. */
movl $0x4000, %edx .testx2: - outb %al, $0x80 + outb %al, $0x80 decl %edx - jnz .testx2 + jnz .testx2
-.xin2: decl %ecx +.xin2: + decl %ecx je .xout1x add $4, %esi jmp .xin1x @@ -281,21 +295,22 @@ movl $(CacheBase + CacheSize - 4), %eax movl %eax, %esp lout: - /* Restore the BIST result */ + /* Restore the BIST result. */ movl %ebp, %eax
- /* We need to set ebp ? No need */ + /* We need to set EBP? No need. */ movl %esp, %ebp - pushl %eax /* bist */ + pushl %eax /* BIST */ call main
- /* We don't need cache as ram for now on */ - /* disable cache */ + /* We don't need CAR for now on. */ + + /* Disable cache. */ movl %cr0, %eax - orl $(0x1<<30),%eax + orl $(1 << 30), %eax movl %eax, %cr0
- /* clear sth */ + /* Clear sth. */ movl $MTRRfix4K_C8000_MSR, %ecx xorl %edx, %edx xorl %eax, %eax @@ -306,25 +321,25 @@ wrmsr #endif
- /* Set the default memory type and disable fixed - * and enable variable MTRRs + /* + * Set the default memory type and disable fixed + * and enable variable MTRRs. */ movl $MTRRdefType_MSR, %ecx xorl %edx, %edx - /* Enable Variable and Disable Fixed MTRRs */ - movl $0x00000800, %eax + movl $0x00000800, %eax /* Enable variable and disable fixed MTRRs. */ wrmsr
- /* enable cache */ + /* Enable cache. */ movl %cr0, %eax - andl $0x9fffffff,%eax + andl $0x9fffffff, %eax movl %eax, %cr0
- /* clear boot_complete flag */ + /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: post_code(0x11) - cld /* clear direction flag */ + cld /* Clear direction flag. */
movl %ebp, %esi
Modified: trunk/src/cpu/via/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.inc Thu Sep 30 23:22:40 2010 (r5887) +++ trunk/src/cpu/via/car/cache_as_ram.inc Fri Oct 1 01:15:36 2010 (r5888) @@ -25,31 +25,30 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#define CacheSize CONFIG_DCACHE_RAM_SIZE -#define CacheBase CONFIG_DCACHE_RAM_BASE - #include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h>
- /* Save the BIST result */ +#define CacheSize CONFIG_DCACHE_RAM_SIZE +#define CacheBase CONFIG_DCACHE_RAM_BASE + + /* Save the BIST result. */ movl %eax, %ebp
CacheAsRam:
- /* disable cache */ + /* Disable cache. */ movl %cr0, %eax - orl $(0x1<<30),%eax - movl %eax,%cr0 + orl $(1 << 30), %eax + movl %eax, %cr0 invd
- /* Set the default memory type and enable fixed and variable MTRRs */ + /* Set the default memory type and enable fixed and variable MTRRs. */ movl $MTRRdefType_MSR, %ecx xorl %edx, %edx - /* Enable Variable and Fixed MTRRs */ - movl $0x00000c00, %eax + movl $0x00000c00, %eax /* Enable variable and fixed MTRRs. */ wrmsr
- /* Clear all MTRRs */ + /* Clear all MTRRs. */ xorl %edx, %edx movl $fixed_mtrr_msr, %esi
@@ -80,13 +79,13 @@ clear_fixed_var_mtrr_out: movl $MTRRphysBase_MSR(0), %ecx xorl %edx, %edx - movl $(CacheBase|MTRR_TYPE_WRBACK),%eax + movl $(CacheBase | MTRR_TYPE_WRBACK), %eax wrmsr
movl $MTRRphysMask_MSR(0), %ecx /* This assumes we never access addresses above 2^36 in CAR. */ - movl $0x0000000f,%edx - movl $(~(CacheSize-1)|0x800),%eax + movl $0x0000000f, %edx + movl $(~(CacheSize - 1) | 0x800), %eax wrmsr
#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK @@ -95,13 +94,14 @@ #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE #endif
- /* enable write base caching so we can do execute in place - * on the flash rom. + /* + * Enable write base caching so we can do execute in place (XIP) + * on the flash ROM. */ movl $MTRRphysBase_MSR(1), %ecx xorl %edx, %edx - movl $REAL_XIP_ROM_BASE, %eax - orl $MTRR_TYPE_WRBACK, %eax + movl $REAL_XIP_ROM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax wrmsr
movl $MTRRphysMask_MSR(1), %ecx @@ -111,39 +111,41 @@
movl $MTRRdefType_MSR, %ecx xorl %edx, %edx - /* Enable Variable and Fixed MTRRs */ - movl $0x00000800, %eax + movl $0x00000800, %eax /* Enable variable and fixed MTRRs. */ wrmsr
movl %cr0, %eax andl $0x9fffffff, %eax movl %eax, %cr0
- /* Read the range with lodsl*/ + /* Read the range with lodsl. */ cld movl $CacheBase, %esi movl %esi, %edi - movl $(CacheSize>>2), %ecx + movl $(CacheSize >> 2), %ecx rep lodsl
movl $CacheBase, %esi movl %esi, %edi movl $(CacheSize >> 2), %ecx
- /* 0x5c5c5c5c is a memory test pattern. - * TODO: Check if everything works with the zero pattern as well. */ - /*xorl %eax, %eax*/ - xorl $0x5c5c5c5c,%eax + /* + * 0x5c5c5c5c is a memory test pattern. + * TODO: Check if everything works with the zero pattern as well. + */ + /* xorl %eax, %eax */ + xorl $0x5c5c5c5c, %eax rep stosl
#ifdef CARTEST movl REAL_XIP_ROM_BASE, %esi movl %esi, %edi - movl $(CONFIG_XIP_ROM_SIZE>>2), %ecx + movl $(CONFIG_XIP_ROM_SIZE >> 2), %ecx rep lodsl #endif
- /* The key point of this CAR code is C7 cache does not turn into + /* + * The key point of this CAR code is C7 cache does not turn into * "no fill" mode, which is not compatible with general CAR code. */
@@ -155,27 +157,27 @@ post_code(0x40) xorl %edx, %edx xorl %eax, %eax - movl $0x5c5c,%edx - pushl %edx - pushl %edx - pushl %edx - pushl %edx - pushl %edx + movl $0x5c5c, %edx + pushl %edx + pushl %edx + pushl %edx + pushl %edx + pushl %edx popl %esi popl %esi popl %eax popl %eax popl %eax - cmpl %edx,%eax - jne stackerr + cmpl %edx, %eax + jne stackerr #endif
- /* Restore the BIST result */ + /* Restore the BIST result. */ movl %ebp, %eax
- /* We need to set ebp ? No need */ + /* We need to set EBP? No need. */ movl %esp, %ebp - pushl %eax /* bist */ + pushl %eax /* BIST */ call main
/* @@ -184,94 +186,96 @@ * want to go back. */
- /* We don't need cache as ram for now on */ - /* disable cache */ - movl %cr0, %eax - orl $(0x1<<30),%eax - movl %eax, %cr0 - + /* We don't need CAR for now on. */
- /* Set the default memory type and disable fixed and enable variable MTRRs */ - movl $MTRRdefType_MSR, %ecx - xorl %edx, %edx + /* Disable cache. */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0
- /* Enable Variable and Disable Fixed MTRRs */ - movl $0x00000800, %eax + /* + * Set the default memory type and disable fixed and enable + * variable MTRRs. + */ + movl $MTRRdefType_MSR, %ecx + xorl %edx, %edx + movl $0x00000800, %eax /* Enable variable & disable fixed MTRRs. */ wrmsr
- /* enable caching for first 1M using variable mtrr */ + /* Enable caching for first 1M using variable MTRR. */ movl $MTRRphysBase_MSR(0), %ecx - xorl %edx, %edx - movl $(0 | 6), %eax - //movl $(0 | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + movl $(0 | 6), %eax + // movl $(0 | MTRR_TYPE_WRBACK), %eax wrmsr
- /* enable cache for 0-7ffff, 80000-9ffff, e0000-fffff; + /* + * Enable cache for 0-7ffff, 80000-9ffff, e0000-fffff; * If 1M cacheable, then when S3 resume, there is stange color on - * screen for 2 sec. suppose problem of a0000-dfffff and cache. + * screen for 2 sec. Suppose problem of a0000-dfffff and cache. * And in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable. */
movl $MTRRphysMask_MSR(0), %ecx - movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ - movl $((~(( 0 + 0x80000) - 1)) | 0x800), %eax + movl $0x0000000f, %edx /* AMD 40 bit 0xff */ + movl $((~((0 + 0x80000) - 1)) | 0x800), %eax wrmsr
movl $MTRRphysBase_MSR(1), %ecx - xorl %edx, %edx - movl $(0x80000 | 6), %eax - orl $(0 | 6), %eax + xorl %edx, %edx + movl $(0x80000 | 6), %eax + orl $(0 | 6), %eax wrmsr
movl $MTRRphysMask_MSR(1), %ecx - movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ - movl $((~(( 0 + 0x20000) - 1)) | 0x800), %eax + movl $0x0000000f, %edx /* AMD 40 bit 0xff */ + movl $((~((0 + 0x20000) - 1)) | 0x800), %eax wrmsr
movl $MTRRphysBase_MSR(2), %ecx - xorl %edx, %edx - movl $(0xc0000 | 6), %eax - orl $(0 | 6), %eax + xorl %edx, %edx + movl $(0xc0000 | 6), %eax + orl $(0 | 6), %eax wrmsr
movl $MTRRphysMask_MSR(2), %ecx - movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ - movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax + movl $0x0000000f, %edx /* AMD 40 bit 0xff */ + movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax wrmsr
- /* cache XIP_ROM_BASE-SIZE to speedup coreboot code */ + /* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */ movl $MTRRphysBase_MSR(3), %ecx - xorl %edx, %edx - movl $REAL_XIP_ROM_BASE,%eax - orl $(0 | 6), %eax + xorl %edx, %edx + movl $REAL_XIP_ROM_BASE,%eax + orl $(0 | 6), %eax wrmsr
movl $MTRRphysMask_MSR(3), %ecx - xorl %edx, %edx - movl $CONFIG_XIP_ROM_SIZE,%eax + xorl %edx, %edx + movl $CONFIG_XIP_ROM_SIZE, %eax decl %eax notl %eax - orl $(0 | 0x800), %eax + orl $(0 | 0x800), %eax wrmsr
- /* enable cache */ - movl %cr0, %eax - andl $0x9fffffff,%eax - movl %eax, %cr0 + /* Enable cache. */ + movl %cr0, %eax + andl $0x9fffffff, %eax + movl %eax, %cr0 invd
- /* clear boot_complete flag */ + /* Clear boot_complete flag. */ xorl %ebp, %ebp __main: post_code(0x11) - cld /* clear direction flag */ + cld /* Clear direction flag. */
movl %ebp, %esi
- movl $ROMSTAGE_STACK, %esp + movl $ROMSTAGE_STACK, %esp movl %esp, %ebp - pushl %esi - call copy_and_run + pushl %esi + call copy_and_run
.Lhlt: post_code(0xee)