diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h
index ca3b3c5..d980827 100644
--- a/src/commonlib/include/commonlib/helpers.h
+++ b/src/commonlib/include/commonlib/helpers.h
@@ -50,10 +50,10 @@
 #endif
 
 #ifndef MIN
-#define MIN(a, b) __CMP(a, b, <)
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
 #endif
 #ifndef MAX
-#define MAX(a, b) __CMP(a, b, >)
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
 #endif
 
 #ifndef ABS
diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c
index e983690..d3c5225 100644
--- a/src/mainboard/amd/bettong/BiosCallOuts.c
+++ b/src/mainboard/amd/bettong/BiosCallOuts.c
@@ -18,18 +18,17 @@
 #include <device/device.h>
 #include <AGESA.h>
 #include <northbridge/amd/agesa/BiosCallOuts.h>
+#include <northbridge/amd/agesa/state_machine.h>
 #include <northbridge/amd/pi/00660F01/chip.h>
 #include <FchPlatform.h>
 #include <stdlib.h>
 #include <string.h>
 #include <northbridge/amd/pi/dimmSpd.h>
-#include <northbridge/amd/pi/agesawrapper.h>
 #include <boardid.h>
 
 #include "imc.h"
 #include "hudson.h"
 
-static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr);
 static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr);
 
 const BIOS_CALLOUT_STRUCT BiosCallouts[] =
@@ -41,7 +40,6 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] =
 	{AGESA_GET_IDS_INIT_DATA,        agesa_EmptyIdsInitData },
 	{AGESA_HOOKBEFORE_DQS_TRAINING,  agesa_NoopSuccess },
 	{AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess },
-	{AGESA_FCH_OEM_CALLOUT,          Fch_Oem_config },
 	{AGESA_GNB_GFX_GET_VBIOS_IMAGE,  agesa_GfxGetVbiosImage }
 };
 const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts);
@@ -70,49 +68,54 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
 	memset(&FchParams->Imc.EcStruct, 0, sizeof(FCH_EC));
 }
 
-/**
- * Fch Oem setting callback
- *
- *  Configure platform specific Hudson device,
- *   such as Azalia, SATA, IMC etc.
- */
-AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
+void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams)
 {
-	AMD_CONFIG_PARAMS *StdHeader = ConfigPtr;
-
-	if (StdHeader->Func == AMD_INIT_RESET) {
-		FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
-		printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
+	printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
+	//FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE);
+	FchParams->FchReset.SataEnable = hudson_sata_enable();
+	FchParams->FchReset.IdeEnable = hudson_ide_enable();
+	FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
+	FchParams->FchReset.Xhci1Enable = FALSE;
+	FchParams->EarlyOemGpioTable = oem_bettong_gpio;
+	printk(BIOS_DEBUG, "Done\n");
+}
 
-		FchParams_reset->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
-		FchParams_reset->FchReset.Xhci1Enable = FALSE;
-		FchParams_reset->EarlyOemGpioTable = oem_bettong_gpio;
-	} else if (StdHeader->Func == AMD_INIT_ENV) {
-		FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData;
-		printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
+void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams)
+{
+	printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");
 
 		if (CONFIG(HUDSON_IMC_FWM))
-			oem_fan_control(FchParams_env);
+		oem_fan_control(FchParams);
 
 		/* XHCI configuration */
-		if (CONFIG(HUDSON_XHCI_ENABLE))
-			FchParams_env->Usb.Xhci0Enable = TRUE;
-		else
-			FchParams_env->Usb.Xhci0Enable = FALSE;
-
-		FchParams_env->Usb.Xhci1Enable = FALSE;
-		FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */
-
-		/* sata configuration */
-		/* SD configuration */
-		/* Rev F has an on-board eMMC, which only supports SD 2.0 */
-		if (board_id() == 'F') {
-			FchParams_env->Sd.SdConfig = SdVer2;
-		}
+	FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE);
+	FchParams->Usb.Xhci1Enable = FALSE;
+
+	/* 8: If USB3 port is unremoveable. */
+	FchParams->Usb.USB30PortInit = 8;
+
+	/* SATA configuration */
+	FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE;
+	switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) {
+	case SataRaid:
+	case SataAhci:
+	case SataAhci7804:
+	case SataLegacyIde:
+		FchParams->Sata.SataIdeMode = FALSE;
+		break;
+	case SataIde2Ahci:
+	case SataIde2Ahci7804:
+	default: /* SataNativeIde */
+		FchParams->Sata.SataIdeMode = TRUE;
+		break;
 	}
-	printk(BIOS_DEBUG, "Done\n");
 
-	return AGESA_SUCCESS;
+	/* SD configuration */
+	/* Rev F has an on-board eMMC, which only supports SD 2.0 */
+	if (board_id() == 'F') {
+		FchParams->Sd.SdConfig = SdVer2;
+	}
+	printk(BIOS_DEBUG, "Done\n");
 }
 
 static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr)
diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig
index 5f26e87..d30c087 100644
--- a/src/mainboard/amd/bettong/Kconfig
+++ b/src/mainboard/amd/bettong/Kconfig
@@ -17,7 +17,7 @@ if BOARD_AMD_BETTONG
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
-	select BINARYPI_LEGACY_WRAPPER
+	#select BINARYPI_LEGACY_WRAPPER
 	select CPU_AMD_PI_00660F01
 	select NORTHBRIDGE_AMD_PI_00660F01
 	select SOUTHBRIDGE_AMD_PI_KERN
diff --git a/src/mainboard/amd/bettong/OemCustomize.c b/src/mainboard/amd/bettong/OemCustomize.c
index 4843b2a..0fedc2c 100644
--- a/src/mainboard/amd/bettong/OemCustomize.c
+++ b/src/mainboard/amd/bettong/OemCustomize.c
@@ -14,7 +14,7 @@
  */
 
 #include <AGESA.h>
-#include <northbridge/amd/pi/agesawrapper.h>
+#include <northbridge/amd/agesa/state_machine.h>
 #include <PlatformMemoryConfiguration.h>
 #include <boardid.h>
 
@@ -112,25 +112,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
 	.DdiLinkList  = DdiList
 };
 
-/*---------------------------------------------------------------------------------------*/
-/**
- *  OemCustomizeInitEarly
- *
- *  Description:
- *    This is the stub function will call the host environment through the binary block
- *    interface (call-out port) to provide a user hook opportunity
- *
- *  Parameters:
- *    @param[in]      **PeiServices
- *    @param[in]      *InitEarly
- *
- *    @retval         VOID
- *
- **/
-/*---------------------------------------------------------------------------------------*/
-VOID OemCustomizeInitEarly (
-	IN  OUT AMD_EARLY_PARAMS    *InitEarly
-	)
+void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
 {
 	InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
 }
@@ -147,9 +129,9 @@ static const PSO_ENTRY DDR4PlatformMemoryConfiguration[] = {
 	PSO_END
 };
 
-void OemPostParams(AMD_POST_PARAMS *PostParams)
+void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
 {
 	if (board_id() == 'F') {
-		PostParams->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
+		InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)DDR4PlatformMemoryConfiguration;
 	}
 }
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
index 5201fa3..01c6d44 100644
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -21,54 +21,29 @@
 #include <cpu/x86/bist.h>
 #include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/state_machine.h>
-#include <northbridge/amd/pi/agesawrapper.h>
-#include <northbridge/amd/pi/agesawrapper_call.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
 
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-	u32 val;
-
-	hudson_lpc_port80();
+/* Mask BIST bit 31. One result of Silicon Observation
+ * report_bist_failure(bist & 0x7FFFFFFF);
+ */
 
-	if (!cpu_init_detectedx && boot_cpu()) {
-		post_code(0x30);
+void board_BeforeAgesa(struct sysinfo *cb)
+{
+	post_code(0x30);
 
 #if CONFIG(HUDSON_UART)
-		configure_hudson_uart();
+	configure_hudson_uart();
 #endif
-		post_code(0x31);
-		console_init();
-	}
+	post_code(0x31);
+	console_init();
 
 	/* Halt if there was a built in self test failure */
 	post_code(0x34);
-	report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */
-
-	/* Load MPB */
-	val = cpuid_eax(1);
-	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
-	printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
-	post_code(0x37);
-	AGESAWRAPPER(amdinitreset);
-	post_code(0x38);
-	printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n");
-
-	post_code(0x39);
-	AGESAWRAPPER(amdinitearly);
-
-	post_code(0x40);
-	AGESAWRAPPER(amdinitpost);
-}
-
-void agesa_postcar(struct sysinfo *cb)
-{
-	post_code(0x41);
-	AGESAWRAPPER(amdinitenv);
+	//report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */
 
+	/* After AMD_INIT_ENV -> move to ramstage ? */
 	if (acpi_is_wakeup_s4()) {
-		outb(0xEE, PM_INDEX);
+		outb(0xee, PM_INDEX);
 		outb(0x8, PM_DATA);
 	}
 }
diff --git a/src/northbridge/amd/pi/00660F01/Makefile.inc b/src/northbridge/amd/pi/00660F01/Makefile.inc
index 7107d84..2419dc3 100644
--- a/src/northbridge/amd/pi/00660F01/Makefile.inc
+++ b/src/northbridge/amd/pi/00660F01/Makefile.inc
@@ -16,3 +16,8 @@
 romstage-y += dimmSpd.c
 
 ramstage-y += northbridge.c
+
+ifneq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y)
+romstage-y += state_machine.c
+ramstage-y += state_machine.c
+endif
\ No newline at end of file
diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc
index 33f59c7..f8a28e5 100644
--- a/src/southbridge/amd/pi/hudson/Makefile.inc
+++ b/src/southbridge/amd/pi/hudson/Makefile.inc
@@ -60,6 +60,8 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
 ramstage-$(CONFIG_HUDSON_UART) += uart.c
 ramstage-y += usb.c
 
+postcar-$(CONFIG_HUDSON_UART) += uart.c
+
 smm-y += smihandler.c
 smm-y += smi_util.c
 
diff --git a/src/vendorcode/amd/pi/00660F01/AMD.h b/src/vendorcode/amd/pi/00660F01/AMD.h
index 990261b..1b4a055 100644
--- a/src/vendorcode/amd/pi/00660F01/AMD.h
+++ b/src/vendorcode/amd/pi/00660F01/AMD.h
@@ -145,7 +145,7 @@ typedef enum {
   AMD_INIT_RESUME            = 0x00029000,                                          ///< AmdInitResume entry point handle
   AMD_RELEASE_STRUCT         = 0x0002A000,                                       ///< AmdReleaseStruct handle
   AMD_S3LATE_RESTORE         = 0x0002B000,                                       ///< AmdS3LateRestore entry point handle
-#if 0
+#if 1
   /* This was removed, shifting everything else up.*/
   AMD_S3_SAVE                = 0x0002C000,
 #endif
