coreboot-4.7-443-gbcf9a0a7ab Sat Mar 3 15:19:38 UTC 2018 romstage starting... MSR GLCP_SYS_RSTPLL (4c000014) value is 0000059c:0000182e Configuring PLL. coreboot-4.7-443-gbcf9a0a7ab Sat Mar 3 15:19:38 UTC 2018 romstage starting... MSR GLCP_SYS_RSTPLL (4c000014) value is 0000059c:07de002e PLL configured. Castle 2.0 BTM periodic sync period. Enable Quack for fewer re-RAS on the MC GLIU port active enable Set the Delay Control in GLCP spd_read_byte dev 50 addr 0d returns 08 spd_read_byte dev 50 addr 05 returns 01 spd_read_byte dev 51 returns 0xff Enable RSDC FPU imprecise exceptions bit Enable Suspend on HLT & PAUSE instructions Enable SUSP and allow TSC to run in Suspend Setup throttling delays to proper mode Done cpuRegInit Ram1.00 Ram2.00 * sdram_set_spd_register spd_read_byte dev 50 addr 15 returns ff * Check DIMM 0 * Check DIMM 1 spd_read_byte dev 51 returns 0xff * Check DDR MAX spd_read_byte dev 50 addr 09 returns 0a spd_read_byte dev 51 returns 0xff * AUTOSIZE DIMM 0 * Check present spd_read_byte dev 50 addr 02 returns 07 * MODBANKS spd_read_byte dev 50 addr 05 returns 01 * FIELDBANKS spd_read_byte dev 50 addr 11 returns 04 * SPDNUMROWS spd_read_byte dev 50 addr 03 returns 03 spd_read_byte dev 50 addr 04 returns 0a * SPDBANKDENSITY spd_read_byte dev 50 addr 1f returns 40 * DIMMSIZE * BEFORT CTZ * TEST DIMM SIZE > 8 * PAGESIZE spd_read_byte dev 50 addr 04 returns 0a * MAXCOLADDR * >12address test * RDMSR CF07 * WRMSR CF07 * ALL DONE * AUTOSIZE DIMM 1 * Check present spd_read_byte dev 51 returns 0xff * set cas latency spd_read_byte dev 50 addr 12 returns 10 spd_read_byte dev 50 addr 17 returns 3c spd_read_byte dev 50 addr 19 returns 4b spd_read_byte dev 51 returns 0xff * set all latency spd_read_byte dev 50 addr 1e returns 28 spd_read_byte dev 51 returns 0xff spd_read_byte dev 50 addr 1b returns 0f spd_read_byte dev 51 returns 0xff spd_read_byte dev 50 addr 1d returns 0f spd_read_byte dev 51 returns 0xff spd_read_byte dev 50 addr 1c returns 0a spd_read_byte dev 51 returns 0xff spd_read_byte dev 50 addr 2a returns 46 spd_read_byte dev 51 returns 0xff * set emrs spd_read_byte dev 50 addr 16 returns ff spd_read_byte dev 51 returns 0xff * set ref rate spd_read_byte dev 50 addr 0c returns 3a spd_read_byte dev 51 returns 0xff Ram3 * DRAM controller init done. RAM DLL lock Ram4 POST 02