In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__.
http://www.coreboot.org/pipermail/coreboot/2007-September/024665.html

It's about time we follow this advice.

Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


Index: Makefile.inc
===================================================================
--- Makefile.inc	(revision 6481)
+++ Makefile.inc	(working copy)
@@ -50,10 +50,10 @@
 # Add source classes and their build options
 classes-y := ramstage romstage driver smm
 
-ramstage-S-ccopts:=-DASSEMBLY
+ramstage-S-ccopts:=
 romstage-c-ccopts:=-D__PRE_RAM__
-romstage-S-ccopts:=-DASSEMBLY -D__PRE_RAM__
-driver-S-ccopts:=-DASSEMBLY
+romstage-S-ccopts:=-D__PRE_RAM__
+driver-S-ccopts:=
 
 ramstage-c-deps:=$$(OPTION_TABLE_H)
 romstage-c-deps:=$$(OPTION_TABLE_H)
Index: src/southbridge/amd/cs5535/cs5535.h
===================================================================
--- src/southbridge/amd/cs5535/cs5535.h	(revision 6481)
+++ src/southbridge/amd/cs5535/cs5535.h	(working copy)
@@ -115,7 +115,7 @@
 /* Flash Memory Mask values */
 #define FLASH_MEM_4K		0xFFFFF000
 
-#if !defined(ASSEMBLY) && !defined(__ROMCC__)
+#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
 #if defined(__PRE_RAM__)
 void cs5535_disable_internal_uart(void);
 #else
Index: src/southbridge/amd/cs5536/cs5536.h
===================================================================
--- src/southbridge/amd/cs5536/cs5536.h	(revision 6481)
+++ src/southbridge/amd/cs5536/cs5536.h	(working copy)
@@ -442,7 +442,7 @@
 #define FLASH_IO_128B		0x0000FF80
 #define FLASH_IO_256B		0x0000FF00
 
-#if !defined(ASSEMBLY) && !defined(__ROMCC__)
+#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
 #if defined(__PRE_RAM__)
 void cs5536_setup_onchipuart(int uart);
 void cs5536_disable_internal_uart(void);
Index: src/southbridge/intel/i82371eb/i82371eb.h
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb.h	(revision 6481)
+++ src/southbridge/intel/i82371eb/i82371eb.h	(working copy)
@@ -21,7 +21,7 @@
 #ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
 #define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
 
-#if !defined(ASSEMBLY)
+#if !defined(__ASSEMBLER__)
 #if !defined(__PRE_RAM__)
 #if !defined(__ACPI__) /* dsdt include */
 
Index: src/southbridge/intel/i82801gx/i82801gx.h
===================================================================
--- src/southbridge/intel/i82801gx/i82801gx.h	(revision 6481)
+++ src/southbridge/intel/i82801gx/i82801gx.h	(working copy)
@@ -38,7 +38,7 @@
 #ifndef __ACPI__
 #define DEBUG_PERIODIC_SMIS 0
 
-#if !defined(ASSEMBLY) && !defined(__ROMCC__)
+#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
 #if !defined(__PRE_RAM__)
 #include "chip.h"
 extern void i82801gx_enable(device_t dev);
Index: src/include/fallback.h
===================================================================
--- src/include/fallback.h	(revision 6481)
+++ src/include/fallback.h	(working copy)
@@ -1,12 +1,12 @@
 #ifndef FALLBACK_H
 #define FALLBACK_H
 
-#if !defined(ASSEMBLY) && !defined(__PRE_RAM__)
+#if !defined(__ASSEMBLER__) && !defined(__PRE_RAM__)
 
 void set_boot_successful(void);
 void boot_successful(void);
 
-#endif /* ASSEMBLY */
+#endif /* __ASSEMBLER__ */
 
 #define RTC_BOOT_BYTE	48
 
Index: src/include/cpu/amd/lxdef.h
===================================================================
--- src/include/cpu/amd/lxdef.h	(revision 6481)
+++ src/include/cpu/amd/lxdef.h	(working copy)
@@ -630,7 +630,7 @@
 #define DELAY_UPPER_DISABLE_CLK135	(1 << 23)
 #define DELAY_LOWER_STATUS_MASK		0x7C0
 
-#if !defined(__ROMCC__)  && !defined(ASSEMBLY)
+#if !defined(__ROMCC__)  && !defined(__ASSEMBLER__)
 #if defined(__PRE_RAM__)
 void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated);
 void SystemPreInit(void);
Index: src/include/cpu/amd/gx2def.h
===================================================================
--- src/include/cpu/amd/gx2def.h	(revision 6481)
+++ src/include/cpu/amd/gx2def.h	(working copy)
@@ -511,7 +511,7 @@
 #define PMLogic_BASE		(0x9D00)
 
 
-#if !defined(__ROMCC__)  && !defined(ASSEMBLY)
+#if !defined(__ROMCC__)  && !defined(__ASSEMBLER__)
 #if defined(__PRE_RAM__)
 void cpuRegInit(void);
 void SystemPreInit(void);
Index: src/include/cpu/amd/mtrr.h
===================================================================
--- src/include/cpu/amd/mtrr.h	(revision 6481)
+++ src/include/cpu/amd/mtrr.h	(working copy)
@@ -33,7 +33,7 @@
 #define TOP_MEM_MASK			0x007fffff
 #define TOP_MEM_MASK_KB			(TOP_MEM_MASK >> 10)
 
-#if !defined(__PRE_RAM__) && !defined(ASSEMBLY)
+#if !defined(__PRE_RAM__) && !defined(__ASSEMBLER__)
 void amd_setup_mtrrs(void);
 #endif
 
Index: src/include/cpu/x86/mtrr.h
===================================================================
--- src/include/cpu/x86/mtrr.h	(revision 6481)
+++ src/include/cpu/x86/mtrr.h	(working copy)
@@ -36,7 +36,7 @@
 #define MTRRfix4K_F0000_MSR 0x26e
 #define MTRRfix4K_F8000_MSR 0x26f
 
-#if !defined (ASSEMBLY) && !defined(__PRE_RAM__)
+#if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__)
 #include <device/device.h>
 void enable_fixed_mtrr(void);
 void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb);
@@ -69,7 +69,7 @@
 #endif
 
 
-#if !defined (ASSEMBLY)
+#if !defined (__ASSEMBLER__)
 #if defined(CONFIG_XIP_ROM_SIZE)
 # if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
    extern unsigned long AUTO_XIP_ROM_BASE;
Index: src/mainboard/supermicro/h8dmr/ap_romstage.c
===================================================================
--- src/mainboard/supermicro/h8dmr/ap_romstage.c	(revision 6481)
+++ src/mainboard/supermicro/h8dmr/ap_romstage.c	(working copy)
@@ -19,7 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
 #define __PRE_RAM__
 
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
Index: src/mainboard/supermicro/h8dme/ap_romstage.c
===================================================================
--- src/mainboard/supermicro/h8dme/ap_romstage.c	(revision 6481)
+++ src/mainboard/supermicro/h8dme/ap_romstage.c	(working copy)
@@ -19,7 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
 #define __PRE_RAM__
 
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
Index: src/mainboard/gigabyte/m57sli/ap_romstage.c
===================================================================
--- src/mainboard/gigabyte/m57sli/ap_romstage.c	(revision 6481)
+++ src/mainboard/gigabyte/m57sli/ap_romstage.c	(working copy)
@@ -19,7 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
 #define __PRE_RAM__
 
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
Index: src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c
===================================================================
--- src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c	(revision 6481)
+++ src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c	(working copy)
@@ -21,7 +21,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
 #define __PRE_RAM__
 
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
Index: src/mainboard/amd/serengeti_cheetah/ap_romstage.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah/ap_romstage.c	(revision 6481)
+++ src/mainboard/amd/serengeti_cheetah/ap_romstage.c	(working copy)
@@ -1,4 +1,3 @@
-#define ASSEMBLY 1
 #define __PRE_RAM__
 
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
Index: src/mainboard/tyan/s2912/ap_romstage.c
===================================================================
--- src/mainboard/tyan/s2912/ap_romstage.c	(revision 6481)
+++ src/mainboard/tyan/s2912/ap_romstage.c	(working copy)
@@ -19,7 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
 #define __PRE_RAM__
 
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
Index: src/mainboard/msi/ms7260/ap_romstage.c
===================================================================
--- src/mainboard/msi/ms7260/ap_romstage.c	(revision 6481)
+++ src/mainboard/msi/ms7260/ap_romstage.c	(working copy)
@@ -19,8 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
-
 #define __PRE_RAM__
 
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
Index: src/mainboard/nvidia/l1_2pvv/ap_romstage.c
===================================================================
--- src/mainboard/nvidia/l1_2pvv/ap_romstage.c	(revision 6481)
+++ src/mainboard/nvidia/l1_2pvv/ap_romstage.c	(working copy)
@@ -19,7 +19,6 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#define ASSEMBLY 1
 #define __PRE_RAM__
 
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
Index: src/arch/x86/Makefile.bootblock.inc
===================================================================
--- src/arch/x86/Makefile.bootblock.inc	(revision 6481)
+++ src/arch/x86/Makefile.bootblock.inc	(working copy)
@@ -55,7 +55,7 @@
 
 $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.S
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC) -MMD -DASSEMBLY -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@
+	$(CC) -MMD -x assembler-with-cpp -D__ASSEMBLER__ -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@
 
 $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/x86/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H)
 	@printf "    ROMCC      $(subst $(obj)/,,$(@))\n"
@@ -105,5 +105,5 @@
 
 $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $< -o $@
+	$(CC) -MMD -x assembler-with-cpp -D__ASSEMBLER__ -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $< -o $@
 
Index: src/arch/x86/Makefile.bigbootblock.inc
===================================================================
--- src/arch/x86/Makefile.bigbootblock.inc	(revision 6481)
+++ src/arch/x86/Makefile.bigbootblock.inc	(working copy)
@@ -26,7 +26,7 @@
 
 $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/crt0.S
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
-	$(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< -o $@
+	$(CC) -MMD -x assembler-with-cpp -D__ASSEMBLER__ -E -I$(src)/include -I$(src)/arch/x86/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< -o $@
 
 $(obj)/coreboot: $$(romstage-objs) $(obj)/ldscript.ld
 	@printf "    LINK       $(subst $(obj)/,,$(@))\n"
Index: Makefile
===================================================================
--- Makefile	(revision 6481)
+++ Makefile	(working copy)
@@ -64,7 +64,7 @@
 endif
 endif
 
-CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E
+CPP:= $(CC) -x assembler-with-cpp -D__ASSEMBLER__ -E
 HOSTCC = gcc
 HOSTCXX = g++
 HOSTCFLAGS := -I$(srck) -I$(objk) -g
