Index: src/mainboard/sunw/ultra40/Config.lb
===================================================================
--- src/mainboard/sunw/ultra40/Config.lb	(revision 2542)
+++ src/mainboard/sunw/ultra40/Config.lb	(working copy)
@@ -14,9 +14,9 @@ end
 ## Compute the start location and size size of
 ## The linuxBIOS bootloader.
 ##
-default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default PAYLOAD_SIZE             = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-default CONFIG_ROM_PAYLOAD     = 1
+default CONFIG_ROM_PAYLOAD       = 1
 
 ##
 ## Compute where this copy of linuxBIOS will start in the boot rom
@@ -33,7 +33,7 @@ default _ROMBASE      = ( CONFIG_ROM_PAY
 default XIP_ROM_SIZE=65536
 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
 
-arch i386 end 
+arch i386 end
 
 
 ##
@@ -49,7 +49,7 @@ if HAVE_PIRQ_TABLE object irq_tables.o e
 #object reset.o
 if USE_DCACHE_RAM
 
-	if CONFIG_USE_INIT	
+	if CONFIG_USE_INIT
 		makerule ./auto.o
 		        depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
         		action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
@@ -113,12 +113,12 @@ end
 ##
 ## Build our reset vector (This is where linuxBIOS is entered)
 ##
-if USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
+if USE_FALLBACK_IMAGE
+	mainboardinit cpu/x86/16bit/reset16.inc
+	ldscript /cpu/x86/16bit/reset16.lds
 else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
+	mainboardinit cpu/x86/32bit/reset32.inc
+	ldscript /cpu/x86/32bit/reset32.lds
 end
 
 if USE_DCACHE_RAM
@@ -151,7 +151,7 @@ if USE_DCACHE_RAM
 end
 
 ###
-### This is the early phase of linuxBIOS startup 
+### This is the early phase of linuxBIOS startup
 ### Things are delicate and we test to see if we should
 ### failover to another image.
 ###
@@ -186,7 +186,7 @@ else
 end
 
 ##
-## Include the secondary Configuration files 
+## Include the secondary Configuration files
 ##
 if CONFIG_CHIP_NAME
 	config chip.h
@@ -194,157 +194,185 @@ end
 
 # sample config for tyan/s2895
 chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_940
-                        device apic 0 on end
-                end
-        end
+	device apic_cluster 0 on
+		chip cpu/amd/socket_940
+			device apic 0 on end
+		end
+	end
 	device pci_domain 0 on
-		chip northbridge/amd/amdk8 #mc0
-			device pci 18.0 on end # link 0
-			device pci 18.0 on # link1 
-				#  devices on link 0, link 0 == LDT 0 
-			        chip southbridge/nvidia/ck804 
+		chip northbridge/amd/amdk8 #CPU0
+			device pci 18.0 on		# link0
+#				chip southbridge/nvidia/ck804
+#					device pci 0.0 on  end # HT
+#					device pci 1.0 off end # LPC
+#					device pci 1.1 off end # SM
+#					device pci 2.0 off end # USB 1.1
+#					device pci 2.1 off end # USB 2
+#					device pci 4.0 off end # ACI
+#					device pci 4.1 off end # MCI
+#					device pci 6.0 off end # IDE
+#					device pci 7.0 off end # SATA 1
+#					device pci 8.0 off end # SATA 0
+#					device pci 9.0 off end # PCI
+#					device pci a.0 off end # NIC
+#					device pci b.0 off end # PCI E 3
+#					device pci c.0 off end # PCI E 2
+#					device pci d.0 off end # PCI E 1
+#					device pci e.0 off end # PCI E 0
+#				end
+			end
+			device pci 18.0 on # link1
+				chip southbridge/nvidia/ck804
 					device pci 0.0 on end   # HT
-                			device pci 1.0 on # LPC
-                	                        chip superio/smsc/lpc47m10x
-                        	                        device pnp 2e.0 off #  Floppy
-                                	                         io 0x60 = 0x3f0
-                                        	                irq 0x70 = 6
-                                                	        drq 0x74 = 2
-	                                                end
-        	                                        device pnp 2e.3 off #  Parallel Port
-                	                                         io 0x60 = 0x378
-                        	                                irq 0x70 = 7
-                                	                end
-                                        	        device pnp 2e.4 on #  Com1
-                                                	        io 0x60 = 0x3f8
-	                                                        irq 0x70 = 4
-        	                                        end
-                	                                device pnp 2e.5 off #  Com2
-                        	                                io 0x60 = 0x2f8
-                                	                        irq 0x70 = 3
-                                        	        end
-	                                                device pnp 2e.7 off #  Keyboard
-        	                                                io 0x60 = 0x60
-                	                                        io 0x62 = 0x64
-                        	                                irq 0x70 = 1
-                                	                        irq 0x72 = 12
-                                        	        end
-                        	                end
-					end
-			                device pci 1.1 on # SM 0
-                                                chip drivers/generic/generic #dimm 0-0-0
-                                                        device i2c 50 on end  
-                                                end              
-                                                chip drivers/generic/generic #dimm 0-0-1
-                                                        device i2c 51 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 0-1-0
-                                                        device i2c 52 on end
-                                                end             
-                                                chip drivers/generic/generic #dimm 0-1-1
-                                                        device i2c 53 on end
-                                                end              
-                                                chip drivers/generic/generic #dimm 1-0-0
-                                                        device i2c 54 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-0-1
-                                                        device i2c 55 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-1-0
-                                                        device i2c 56 on end
-                                                end     
-                                                chip drivers/generic/generic #dimm 1-1-1
-                                                        device i2c 57 on end
-                                                end 
+						device pci 1.0 on # LPC
+							chip superio/smsc/lpc47m10x
+								device pnp 2e.0 off #  Floppy
+									io 0x60 = 0x3f0
+									irq 0x70 = 6
+									drq 0x74 = 2
+								end
+								device pnp 2e.3 off #  Parallel Port
+									io 0x60 = 0x378
+									irq 0x70 = 7
+								end
+								device pnp 2e.4 on #  Com1
+									io 0x60 = 0x3f8
+									irq 0x70 = 4
+								end
+								device pnp 2e.5 off #  Com2
+									io 0x60 = 0x2f8
+									irq 0x70 = 3
+								end
+								device pnp 2e.7 off #  Keyboard
+									io 0x60 = 0x60
+									io 0x62 = 0x64
+									irq 0x70 = 1
+									irq 0x72 = 12
+								end
+							end
+						end
+						device pci 1.1 on # SM 0
+							chip drivers/generic/generic #dimm 0-0-0
+								device i2c 50 on end
+							end
+							chip drivers/generic/generic #dimm 0-0-1
+								device i2c 51 on end
+							end
+							chip drivers/generic/generic #dimm 0-1-0
+								device i2c 52 on end
+							end
+							chip drivers/generic/generic #dimm 0-1-1
+								device i2c 53 on end
+							end
+							chip drivers/generic/generic #dimm 1-0-0
+								device i2c 54 on end
+							end
+							chip drivers/generic/generic #dimm 1-0-1
+								device i2c 55 on end
+							end
+							chip drivers/generic/generic #dimm 1-1-0
+								device i2c 56 on end
+							end
+							chip drivers/generic/generic #dimm 1-1-1
+								device i2c 57 on end
+							end
+					end # SM
+					device pci 1.1 on # SM 1
+						#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
+						#chip drivers/generic/generic #PCI-E x16
+						#	device i2c ?? on end
+						#end
+						#chip drivers/generic/generic #PCI-E x4
+						#	device i2c ?? on end
+						#end
+						#chip drivers/generic/generic #PCI-E x16
+						#	device i2c ?? on end
+						#end
+						#chip drivers/generic/generic #PCI-E x4
+						#	device i2c ?? on end
+						#end
+						#chip drivers/generic/generic #PCI Slot
+						#	device i2c ?? on end
+						#end
+						#chip drivers/generic/generic #PCI Slot
+						#	device i2c ?? on end
+						#end
+						chip drivers/generic/generic #MAC EEPROM
+							device i2c 51 on end
+						end
+						chip drivers/generic/generic #SATA's FRU
+							device i2c 53 on end
+						end
+						chip drivers/generic/generic #MB's FRU
+							device i2c 55 on end
+						end
+						chip drivers/generic/generic #Power's FRU
+							device i2c 57 on end
+						end
+						chip drivers/generic/generic #HW Monitor
+							device i2c 5d on end
+						end
+						chip drivers/generic/generic #Super IO
+							device i2c 5e on end
+						end
 					end # SM
-                                        device pci 1.1 on # SM 1
-#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
-#                                                chip drivers/generic/generic #PCIXA Slot1
-#                                                        device i2c 50 on end
-#                                                end
-#                                                chip drivers/generic/generic #PCIXB Slot1
-#                                                        device i2c 51 on end
-#                                                end     
-#                                                chip drivers/generic/generic #PCIXB Slot2
-#                                                        device i2c 52 on end
-#                                                end             
-#                                                chip drivers/generic/generic #PCI Slot1
-#                                                        device i2c 53 on end
-#                                                end              
-#                                                chip drivers/generic/generic #Master CK804 PCI-E
-#                                                        device i2c 54 on end
-#                                                end     
-#                                                chip drivers/generic/generic #Slave CK804 PCI-E
-#                                                        device i2c 55 on end
-#                                                end             
-                                                chip drivers/generic/generic #MAC EEPROM
-                                                        device i2c 51 on end
-                                                end 
-
-                                        end # SM 
-	                		device pci 2.0 on end # USB 1.1
-        	        		device pci 2.1 on end # USB 2
-	                		device pci 4.0 on end # ACI
-        	        		device pci 4.1 off end # MCI
-                			device pci 6.0 on end # IDE
-	                		device pci 7.0 on end # SATA 1
-        	        		device pci 8.0 on end # SATA 0
-                			device pci 9.0 on end # PCI
-	                		device pci a.0 on end # NIC
-        	       			device pci b.0 off end # PCI E 3
-                			device pci c.0 off end # PCI E 2
-                			device pci d.0 off end # PCI E 1
-                			device pci e.0 on end # PCI E 0
-	                                register "ide0_enable" = "1"
-        	                        register "ide1_enable" = "1"
-                	                register "sata0_enable" = "1"
-                        	        register "sata1_enable" = "1"
-#					register "nic_rom_address" = "0xfff80000" # 64k
-#					register "raid_rom_address" = "0xfff90000"
+					device pci 2.0 on end # USB 1.1
+					device pci 2.1 on end # USB 2
+					device pci 4.0 on end # ACI
+					device pci 4.1 off end # MCI
+					device pci 6.0 on end # IDE
+					device pci 7.0 on end # SATA 1
+					device pci 8.0 on end # SATA 0
+					device pci 9.0 on end # PCI
+					device pci a.0 on end # NIC
+					device pci b.0 off end # PCI E 3
+					device pci c.0 off end # PCI E 2
+					device pci d.0 on end # PCI E 1
+					device pci e.0 on end # PCI E 0
+					register "usb1_hc_reset"="1"
+					register "ide0_enable" = "1"
+					register "ide1_enable" = "1"
+					register "sata0_enable" = "1"
+					register "sata1_enable" = "1"
 					register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 					register "mac_eeprom_addr" = "0x51"
-				end
-			end #  device pci 18.0 
+				end #chip southbridge/nvidia/ck804
+			end #  device pci 18.0
 			device pci 18.0 on end # link 2
 			device pci 18.1 on end
 			device pci 18.2 on end
 			device pci 18.3 on end
 		end # mc0
-		
-		chip northbridge/amd/amdk8
-                	device pci 19.0 on end # link 0
-		device pci 19.0 on   
-                        	#  devices on link 1, link 1 == LDT 1
-                        	chip southbridge/nvidia/ck804 
-                                	device pci 0.0 on end   # HT
-                                	device pci 1.0 on end   # LPC
-                                	device pci 1.1 off end # SM
-                                	device pci 2.0 off end # USB 1.1
-                                	device pci 2.1 off end # USB 2
-                                	device pci 4.0 off end # ACI
-                                	device pci 4.1 off end # MCI
-                                	device pci 6.0 off end # IDE
-                                	device pci 7.0 off end # SATA 1
-                                	device pci 8.0 off end # SATA 0
-                                	device pci 9.0 off end # PCI
-                                	device pci a.0 on end # NIC
-                                	device pci b.0 off end # PCI E 3
-                                	device pci c.0 off end # PCI E 2
-                                	device pci d.0 off end # PCI E 1
-                                	device pci e.0 on end # PCI E 0
-#					register "nic_rom_address" = "0xfff80000" # 64k
-                                        register "mac_eeprom_smbus" = "3"
-                                        register "mac_eeprom_addr" = "0x51"
-                        	end
-                	end #  device pci 19.0 
-			
-			device pci 19.0 on end
+
+		chip northbridge/amd/amdk8 #CPU1
+			device pci 19.0 on end # link 0
+			device pci 19.0 on		# link 1
+				chip southbridge/nvidia/ck804
+					device pci 0.0 off end  # HT
+					device pci 1.0 off end # LPC
+					device pci 1.1 off end # SM
+					device pci 2.0 off end # USB 1.1
+					device pci 2.1 off end # USB 2
+					device pci 4.0 off end # ACI
+					device pci 4.1 off end # MCI
+					device pci 6.0 off end # IDE
+					device pci 7.0 off end # SATA 1
+					device pci 8.0 off end # SATA 0
+					device pci 9.0 off end # PCI
+					device pci a.0 off end # NIC
+					device pci b.0 off end # PCI E 3
+					device pci c.0 off end # PCI E 2
+					device pci d.0 off end # PCI E 1
+					device pci e.0 off end # PCI E 0
+					register "mac_eeprom_smbus" = "3"
+					register "mac_eeprom_addr" = "0x51"
+				end
+			end #  device pci 19.0
+			device pci 19.0 on end	#link 2
 			device pci 19.1 on end
 			device pci 19.2 on end
 			device pci 19.3 on end
 		end
 	end # PCI domain
-	
+
 end #root_complex
Index: src/mainboard/sunw/ultra40/mptable.c
===================================================================
--- src/mainboard/sunw/ultra40/mptable.c	(revision 2542)
+++ src/mainboard/sunw/ultra40/mptable.c	(working copy)
@@ -3,228 +3,200 @@
 #include <device/pci.h>
 #include <string.h>
 #include <stdint.h>
-
-extern  unsigned char bus_isa;
-extern  unsigned char bus_ck804_0; //1
-extern  unsigned char bus_ck804_1; //2
-extern  unsigned char bus_ck804_2; //3
-extern  unsigned char bus_ck804_3; //4
-extern  unsigned char bus_ck804_4; //5
-extern  unsigned char bus_ck804_5; //6
-extern  unsigned char bus_8131_0;  //7
-extern  unsigned char bus_8131_1;  //8
-extern  unsigned char bus_8131_2;  //9
-extern  unsigned char bus_ck804b_0;//a
-extern  unsigned char bus_ck804b_1;//b
-extern  unsigned char bus_ck804b_2;//c
-extern  unsigned char bus_ck804b_3;//d
-extern  unsigned char bus_ck804b_4;//e
-extern  unsigned char bus_ck804b_5;//f
-extern  unsigned apicid_ck804;
-extern  unsigned apicid_8131_1;
-extern  unsigned apicid_8131_2;
-extern  unsigned apicid_ck804b;
-
-extern unsigned pci1234[];
-
-extern  unsigned sbdn;
-extern  unsigned hcdn[];
-extern  unsigned sbdn3;
-extern  unsigned sbdnb;
+#include "mb_conf.h"
 
 void *smp_write_config_table(void *v)
 {
-        static const char sig[4] = "PCMP";
-        static const char oem[8] = "SUNW    ";
-        static const char productid[12] = "ultra40     ";
-        struct mp_config_table *mc;
+	static const char sig[4] = "PCMP";
+	static const char oem[8] = "SUNW    ";
+	static const char productid[12] = "ultra40     ";
+	struct mp_config_table *mc;
+	mb_conf_t const* const bc=get_bus_conf();
 
-        unsigned char bus_num;
+	unsigned char bus_num;
 	int i;
 
-        mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
-        memset(mc, 0, sizeof(*mc));
+	mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+	memset(mc, 0, sizeof(*mc));
 
-        memcpy(mc->mpc_signature, sig, sizeof(sig));
-        mc->mpc_length = sizeof(*mc); /* initially just the header */
-        mc->mpc_spec = 0x04;
-        mc->mpc_checksum = 0; /* not yet computed */
-        memcpy(mc->mpc_oem, oem, sizeof(oem));
-        memcpy(mc->mpc_productid, productid, sizeof(productid));
-        mc->mpc_oemptr = 0;
-        mc->mpc_oemsize = 0;
-        mc->mpc_entry_count = 0; /* No entries yet... */
-        mc->mpc_lapic = LAPIC_ADDR;
-        mc->mpe_length = 0;
-        mc->mpe_checksum = 0;
-        mc->reserved = 0;
-
-        smp_write_processors(mc);
-
-	get_bus_conf();
-
-/*Bus:		Bus ID	Type*/
-       /* define bus and isa numbers */
-        for(bus_num = 0; bus_num < bus_isa; bus_num++) {
-                smp_write_bus(mc, bus_num, "PCI   ");
-        }
-        smp_write_bus(mc, bus_isa, "ISA   ");
+	memcpy(mc->mpc_signature, sig, sizeof(sig));
+	mc->mpc_length = sizeof(*mc); /* initially just the header */
+	mc->mpc_spec = 0x04;
+	mc->mpc_checksum = 0; /* not yet computed */
+	memcpy(mc->mpc_oem, oem, sizeof(oem));
+	memcpy(mc->mpc_productid, productid, sizeof(productid));
+	mc->mpc_oemptr = 0;
+	mc->mpc_oemsize = 0;
+	mc->mpc_entry_count = 0; /* No entries yet... */
+	mc->mpc_lapic = LAPIC_ADDR;
+	mc->mpe_length = 0;
+	mc->mpe_checksum = 0;
+	mc->reserved = 0;
+
+	smp_write_processors(mc);
+
+	/*Bus:		Bus ID	Type*/
+	/* define bus and isa numbers */
+	for(bus_num = 0; bus_num < bc->bus_isa; bus_num++) {
+		smp_write_bus(mc, bus_num, (unsigned char*)"PCI   ");
+	}
+	smp_write_bus(mc, bc->bus_isa, (unsigned char*)"ISA   ");
 
 /*I/O APICs:	APIC ID	Version	State		Address*/
-        {
-                device_t dev;
+	{
 		struct resource *res;
+		device_t dev;
 		uint32_t dword;
 
-                dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
-                if (dev) {
+		dev = dev_find_slot(bc->bus_ck804_0, PCI_DEVFN(bc->sbdn+ 0x1,0));
+		if (dev) {
 			res = find_resource(dev, PCI_BASE_ADDRESS_1);
-			if (res) {
-				smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
-			}
-
+			if (res) smp_write_ioapic(mc, bc->apicid_ck804, 0x11, res->base);
 
 			dword = 0x0000d218;
-	        	pci_write_config32(dev, 0x7c, dword);
-
-		        dword = 0x12008a00;
-		        pci_write_config32(dev, 0x80, dword);
-
-	        	dword = 0x00080d7d;
-		        pci_write_config32(dev, 0x84, dword);
+			pci_write_config32(dev, 0x7c, dword);
 
-                }
+			dword = 0x12008a00;
+			pci_write_config32(dev, 0x80, dword);
 
-                dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
-                if (dev) {
+			dword = 0x00080d7d;
+			pci_write_config32(dev, 0x84, dword);
+		}
+
+#if 0
+		dev = dev_find_slot(bc->bus_8131_0, PCI_DEVFN(bc->sbdn3,1));
+		if (dev) {
 			res = find_resource(dev, PCI_BASE_ADDRESS_0);
-			if (res) {
-				smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
-			}
-                }
-                dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
-                if (dev) {
+			if (res) smp_write_ioapic(mc, bc->apicid_8131_1, 0x11, res->base);
+		}
+		dev = dev_find_slot(bc->bus_8131_0, PCI_DEVFN(bc->sbdn3+1,1));
+		if (dev) {
 			res = find_resource(dev, PCI_BASE_ADDRESS_0);
-			if (res) {
-				smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
-			}
-                }
-
-	    if(pci1234[2] & 0xf) {
-                dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0));
-                if (dev) {
-			res = find_resource(dev, PCI_BASE_ADDRESS_1);
-			if (res) {
-				smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base);
+			if (res) smp_write_ioapic(mc, bc->apicid_8131_2, 0x11, res->base);
+		}
+#endif
+
+#if 0
+		if(sysconf.pci1234[2] & 0xf) {
+			dev = dev_find_slot(bc->bus_ck804b_0, PCI_DEVFN(bc->sbdnb + 0x1,0));
+			if (dev) {
+				res = find_resource(dev, PCI_BASE_ADDRESS_1);
+				if (res) smp_write_ioapic(mc, bc->apicid_ck804b, 0x11, res->base);
 			}
 
 			dword = 0x0000d218;
-                        pci_write_config32(dev, 0x7c, dword);
-
-                        dword = 0x00000000;
-                        pci_write_config32(dev, 0x80, dword);
-
-                        dword = 0x00000d00;
-                        pci_write_config32(dev, 0x84, dword);
+			pci_write_config32(dev, 0x7c, dword);
 
-                }
-	    }
+			dword = 0x00000000;
+			pci_write_config32(dev, 0x80, dword);
 
+			dword = 0x00000d00;
+			pci_write_config32(dev, 0x84, dword);
+		}
+#endif
 	}
-  
+
 /*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#
-*/	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_ck804, 0x0);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, apicid_ck804, 0x1);
-	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x0, apicid_ck804, 0x2);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x3, apicid_ck804, 0x3);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x4, apicid_ck804, 0x4);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x6, apicid_ck804, 0x6);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x7, apicid_ck804, 0x7);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x8, apicid_ck804, 0x8);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xc, apicid_ck804, 0xc);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xd, apicid_ck804, 0xd);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xe, apicid_ck804, 0xe);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xf, apicid_ck804, 0xf);
+*/	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bc->bus_isa, 0x0, bc->apicid_ck804, 0x0);
+	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bc->bus_isa, 0x1, bc->apicid_ck804, 0x1);
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bc->bus_isa, 0x0, bc->apicid_ck804, 0x0);
+	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bc->bus_isa, 0x3, bc->apicid_ck804, 0x3);
+	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bc->bus_isa, 0x4, bc->apicid_ck804, 0x4);
+	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bc->bus_isa, 0x6, bc->apicid_ck804, 0x6);
+	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bc->bus_isa, 0x7, bc->apicid_ck804, 0x7);
+	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bc->bus_isa, 0x8, bc->apicid_ck804, 0x8);
+	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bc->bus_isa, 0xc, bc->apicid_ck804, 0xc);
+	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bc->bus_isa, 0xd, bc->apicid_ck804, 0xd);
+	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bc->bus_isa, 0xe, bc->apicid_ck804, 0xe);
+	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bc->bus_isa, 0xf, bc->apicid_ck804, 0xf);
 
 // Onboard ck804 smbus
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
-// 10
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bc->bus_ck804_0, ((bc->sbdn+1)<<2)|1, bc->apicid_ck804, 0xa); // 10
 
 // Onboard ck804 USB 1.1
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bc->bus_ck804_0, ((bc->sbdn+2)<<2)|0, bc->apicid_ck804, 0x15); // 21
 
 // Onboard ck804 USB 2
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bc->bus_ck804_0, ((bc->sbdn+2)<<2)|1, bc->apicid_ck804, 0x14); // 20
 
 // Onboard ck804 Audio
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bc->bus_ck804_0, ((bc->sbdn+4)<<2)|0, bc->apicid_ck804, 0x14); // 20
 
 // Onboard ck804 SATA 0
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bc->bus_ck804_0, ((bc->sbdn +7)<<2)|0, bc->apicid_ck804, 0x17); // 23
 
 // Onboard ck804 SATA 1
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bc->bus_ck804_0, ((bc->sbdn +8)<<2)|0, bc->apicid_ck804, 0x16); // 22
 
 // Onboard ck804 NIC
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bc->bus_ck804_0, ((bc->sbdn +0x0a)<<2)|0, bc->apicid_ck804, 0x15); // 21
+
+//Slot 0 PCIe x4
+	for (i=0; i!=4; ++i) {
+		smp_write_intsrc(mc,mp_INT,MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,bc->bus_pcie_x4,(0<<2)|i,bc->apicid_ck804,0x10+(3+i-bc->sbdn)%4u);
+	}
 
 //Slot 1 PCIE x16
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
-        }
+	for(i=0;i<4;i++) {
+		smp_write_intsrc(mc,mp_INT,MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,bc->bus_pcie_x16,(0<<2)|i,bc->apicid_ck804,0x10+(2+i-bc->sbdn)%4u);
+	}
 
 //Onboard Firewire
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19
+	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bc->bus_pci, (0x05<<2)|0, bc->apicid_ck804, 0x13); // 19
 
 //Slot 2 PCI 32
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4);
-        }
+	for(i=0;i<4;i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bc->bus_pci, (0x04<<2)|i, bc->apicid_ck804, 0x10 + (0+i)%4);
+	}
 
-	if(pci1234[2] & 0xf) {
+#if 0
+	if(sysconf.pci1234[2] & 0xf) {
 //Onboard ck804b NIC
-        smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bc->bus_ck804b_0, ((bc->sbdnb+0x0a)<<2)|0, bc->apicid_ck804b, 0x15);//24+4+4+21=53
 
 //Slot 3 PCIE x16
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4);
-        }
+		for(i=0;i<4;i++) {
+			smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bc->bus_ck804b_5, (0x00<<2)|i, bc->apicid_ck804b, 0x10 + (2+i+4-bc->sbdnb%4)%4);
+		}
 	}
+#endif
 
+#if 0
 //Channel B of 8131
 
 //Slot 4 PCI-X 100/66
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4);
-        }
+	for(i=0;i<4;i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4);
+	}
 
 //Slot 5 PCIX 100/66
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29
-        }
+	for(i=0;i<4;i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29
+	}
 
 //OnBoard LSI SCSI
-        for(i=0;i<2;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30
-        }
+	for(i=0;i<2;i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30
+	}
 
 //Channel A of 8131
 
-//Slot 6 PCIX 133/100/66       
-        for(i=0;i<4;i++) {
-                smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24
-        }
-
-/*Local Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#*/
-	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
-	smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
+//Slot 6 PCIX 133/100/66
+	for(i=0;i<4;i++) {
+		smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24
+	}
+#endif
+
+/*	Local Ints:			 Type		Polarity			Trigger					Bus ID	   IRQ	APIC ID		 PIN# */
+	smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bc->bus_isa, 0x0, MP_APIC_ALL, 0x0);
+	smp_write_intsrc(mc, mp_NMI,	MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bc->bus_isa, 0x0, MP_APIC_ALL, 0x1);
 	/* There is no extension information... */
 
 	/* Compute the checksums */
 	mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 	mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
-	printk_debug("Wrote the mp table end at: %p - %p\n",
-		mc, smp_next_mpe_entry(mc));
+	printk_debug("Wrote the mp table end at: %p - %p\n",mc, smp_next_mpe_entry(mc));
+
 	return smp_next_mpe_entry(mc);
 }
 
Index: src/mainboard/sunw/ultra40/irq_tables.c
===================================================================
--- src/mainboard/sunw/ultra40/irq_tables.c	(revision 2542)
+++ src/mainboard/sunw/ultra40/irq_tables.c	(working copy)
@@ -1,4 +1,4 @@
-/* This file was generated by getpir.c, do not modify! 
+/* This file was generated by getpir.c, do not modify!
    (but if you do, please run checkpir on it to verify)
    Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
 
@@ -9,12 +9,13 @@
 #include <string.h>
 #include <stdint.h>
 #include <arch/pirq_routing.h>
+#include "mb_conf.h"
 
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, 
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
 		uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
 		uint8_t slot, uint8_t rfu)
 {
-        pirq_info->bus = bus; 
+        pirq_info->bus = bus;
         pirq_info->devfn = devfn;
                 pirq_info->irq[0].link = link0;
                 pirq_info->irq[0].bitmap = bitmap0;
@@ -28,60 +29,36 @@ static void write_pirq_info(struct irq_i
         pirq_info->rfu = rfu;
 }
 
-extern  unsigned char bus_ck804_0; //1
-extern  unsigned char bus_ck804_1; //2
-extern  unsigned char bus_ck804_2; //3
-extern  unsigned char bus_ck804_3; //4
-extern  unsigned char bus_ck804_4; //5
-extern  unsigned char bus_ck804_5; //6
-extern  unsigned char bus_8131_0;  //7
-extern  unsigned char bus_8131_1;  //8
-extern  unsigned char bus_8131_2;  //9
-extern  unsigned char bus_ck804b_0;//a
-extern  unsigned char bus_ck804b_1;//b
-extern  unsigned char bus_ck804b_2;//c
-extern  unsigned char bus_ck804b_3;//d
-extern  unsigned char bus_ck804b_4;//e
-extern  unsigned char bus_ck804b_5;//f
-
-extern unsigned pci1234[];
-
-extern  unsigned sbdn;
-extern  unsigned hcdn[];
-extern  unsigned sbdn3;
-extern  unsigned sbdnb;
-
 unsigned long write_pirq_routing_table(unsigned long addr)
 {
-
 	struct irq_routing_table *pirq;
 	struct irq_info *pirq_info;
 	unsigned slot_num;
 	uint8_t *v;
 
-        uint8_t sum=0;
-        int i;
+	uint8_t sum=0;
+	int i;
 
-        get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+	mb_conf_t const* const bc=get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
 
-        /* Align the table to be 16 byte aligned. */
-        addr += 15;
-        addr &= ~15;
+	/* Align the table to be 16 byte aligned. */
+	addr += 15;
+	addr &= ~15;
 
-        /* This table must be betweeen 0xf0000 & 0x100000 */
-        printk_info("Writing IRQ routing tables to 0x%x...", addr);
+	/* This table must be betweeen 0xf0000 & 0x100000 */
+	printk_info("Writing IRQ routing tables to 0x%x...", addr);
 
 	pirq = (void *)(addr);
 	v = (uint8_t *)(addr);
-	
+
 	pirq->signature = PIRQ_SIGNATURE;
 	pirq->version  = PIRQ_VERSION;
-	
-	pirq->rtr_bus = bus_ck804_0;
-	pirq->rtr_devfn = ((sbdn+9)<<3)|0;
+
+	pirq->rtr_bus = bc->bus_ck804_0;
+	pirq->rtr_devfn = ((bc->sbdn+9)<<3)|0;
 
 	pirq->exclusive_irqs = 0;
-	
+
 	pirq->rtr_vendor = 0x10de;
 	pirq->rtr_device = 0x005c;
 
@@ -91,88 +68,94 @@ unsigned long write_pirq_routing_table(u
 
 	pirq_info = (void *) ( &pirq->checksum + 1);
 	slot_num = 0;
+
 //pci bridge
-	write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+	write_pirq_info(pirq_info, bc->bus_ck804_0, ((bc->sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
 	pirq_info++; slot_num++;
+
+#if 0
 //pcix bridge
-        write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+	write_pirq_info(pirq_info, bc->bus_8131_0, (bc->sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
         pirq_info++; slot_num++;
-        
-	if(pci1234[2] & 0xf) {     
-	//second pci beidge   
-        	write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0);
-	        pirq_info++; slot_num++;
+
+	if(sysconf.pci1234[2] & 0xf) {
+	//second pci beidge
+		write_pirq_info(pirq_info, bc->bus_ck804b_0, ((bc->sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0);
+		pirq_info++; slot_num++;
 	}
-#if 0
+#endif
+
+	if (bc->coproc_plugged) {
+		write_pirq_info(pirq_info, bc->coproc_busN, (bc->coproc_devN<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+		pirq_info++; slot_num++;
+	}
+
 //smbus
-	write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
-        pirq_info++; slot_num++;
+	write_pirq_info(pirq_info, bc->bus_ck804_0, ((bc->sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+	pirq_info++; slot_num++;
 
 //usb
-	write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
-        pirq_info++; slot_num++;
+	write_pirq_info(pirq_info, bc->bus_ck804_0, ((bc->sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
+	pirq_info++; slot_num++;
 
 //audio
-	write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
-        pirq_info++; slot_num++;
+	write_pirq_info(pirq_info, bc->bus_ck804_0, ((bc->sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+	pirq_info++; slot_num++;
+
 //sata
-	write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
-        pirq_info++; slot_num++;
+	write_pirq_info(pirq_info, bc->bus_ck804_0, ((bc->sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+	pirq_info++; slot_num++;
+
 //sata
-        write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
-        pirq_info++; slot_num++;
+	write_pirq_info(pirq_info, bc->bus_ck804_0, ((bc->sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+	pirq_info++; slot_num++;
+
 //nic
-        write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
-        pirq_info++; slot_num++;
+	write_pirq_info(pirq_info, bc->bus_ck804_0, ((bc->sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+	pirq_info++; slot_num++;
 
-//Slot1 PCIE x16
-        write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
-        pirq_info++; slot_num++;
+//Slot1 - PCIE x16
+	write_pirq_info(pirq_info, bc->bus_pcie_x16, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
+	pirq_info++; slot_num++;
 
 //firewire
-        write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
-        pirq_info++; slot_num++;
+	write_pirq_info(pirq_info, bc->bus_pci, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+	pirq_info++; slot_num++;
 
-//Slot2 pci
-        write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
-        pirq_info++; slot_num++;
-//nic   
-        write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
-        pirq_info++; slot_num++;
-//Slot3 PCIE x16 
-        write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
-        pirq_info++; slot_num++;
+//Slot2 - pci
+	write_pirq_info(pirq_info, bc->bus_pci, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
+	pirq_info++; slot_num++;
+
+//Second nic
+//	write_pirq_info(pirq_info, bc->bus_ck804b_0, ((bc->sbdnb+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
+//	pirq_info++; slot_num++;
 
+//Slot0 - PCIE x4
+	write_pirq_info(pirq_info, bc->bus_pcie_x4, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
+	pirq_info++; slot_num++;
+
+#if 0
 //Slot4 PCIX
-        write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0);
-        pirq_info++; slot_num++;
+	write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0);
+	pirq_info++; slot_num++;
 
 //Slot5 PCIX
-        write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0);
-        pirq_info++; slot_num++;
+	write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0);
+	pirq_info++; slot_num++;
 
 //onboard scsi
-        write_pirq_info(pirq_info, bus_8131_2, (6<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0);
-        pirq_info++; slot_num++;
+	write_pirq_info(pirq_info, bus_8131_2, (6<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0);
+	pirq_info++; slot_num++;
 
 //Slot6 PCIX
-        write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
-        pirq_info++; slot_num++;
+	write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
+	pirq_info++; slot_num++;
 #endif
-                
-	pirq->size = 32 + 16 * slot_num; 
-
-        for (i = 0; i < pirq->size; i++)
-                sum += v[i];	
 
+	pirq->size = 32 + 16 * slot_num;
+	for (i = 0; i < pirq->size; i++) sum += v[i];
 	sum = pirq->checksum - sum;
-
-        if (sum != pirq->checksum) {
-                pirq->checksum = sum;
-        }
-
+	pirq->checksum = sum;
 	printk_info("done.\n");
-
-	return	(unsigned long) pirq_info;
-
+	return (unsigned long)pirq_info;
 }
Index: src/mainboard/sunw/ultra40/resourcemap.c
===================================================================
--- src/mainboard/sunw/ultra40/resourcemap.c	(revision 2542)
+++ src/mainboard/sunw/ultra40/resourcemap.c	(working copy)
@@ -1,8 +1,3 @@
-/*
- * needs a different resource map
- *
- */
-
 static void setup_ultra40_resource_map(void)
 {
 	static const unsigned int register_values[] = {
@@ -145,7 +140,7 @@ static void setup_ultra40_resource_map(v
 		 *	   1 = base/limit registers i are read-only
 		 * [ 7: 4] Reserved
 		 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
-		 *	   This field defines the upper address bits of a 40bit address 
+		 *	   This field defines the upper address bits of a 40bit address
 		 *	   that defines the start of memory-mapped I/O region i
 		 */
 		PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
@@ -182,8 +177,8 @@ static void setup_ultra40_resource_map(v
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
-		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001, 
+		PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007010,
+		PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff011,
 		PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
 
@@ -201,7 +196,7 @@ static void setup_ultra40_resource_map(v
 		 * [ 3: 2] Reserved
 		 * [ 4: 4] VGA Enable
 		 *	   0 = VGA matches Disabled
-		 *	   1 = matches all address < 64K and where A[9:0] is in the 
+		 *	   1 = matches all address < 64K and where A[9:0] is in the
 		 *	       range 3B0-3BB or 3C0-3DF independen of the base & limit registers
 		 * [ 5: 5] ISA Enable
 		 *	   0 = ISA matches Disabled
@@ -209,11 +204,11 @@ static void setup_ultra40_resource_map(v
 		 *	       from matching agains this base/limit pair
 		 * [11: 6] Reserved
 		 * [24:12] PCI I/O Base i
-		 *	   This field defines the start of PCI I/O region n 
+		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
-		PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00008033,
+		PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00001023,
+		PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00008013,
 		PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
 		PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
 
@@ -263,4 +258,3 @@ static void setup_ultra40_resource_map(v
 	max = sizeof(register_values)/sizeof(register_values[0]);
 	setup_resource_map(register_values, max);
 }
-
Index: src/mainboard/sunw/ultra40/Options.lb
===================================================================
--- src/mainboard/sunw/ultra40/Options.lb	(revision 2542)
+++ src/mainboard/sunw/ultra40/Options.lb	(working copy)
@@ -18,6 +18,7 @@ uses ROM_SECTION_SIZE
 uses ROM_SECTION_OFFSET
 uses CONFIG_ROM_PAYLOAD
 uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_PRECOMPRESSED_PAYLOAD
 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
 uses PAYLOAD_SIZE
 uses _ROMBASE
Index: src/mainboard/sunw/ultra40/auto.c
===================================================================
--- src/mainboard/sunw/ultra40/auto.c	(revision 2542)
+++ src/mainboard/sunw/ultra40/auto.c	(working copy)
@@ -1,5 +1,5 @@
 #define ASSEMBLY 1
- 
+
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -64,23 +64,8 @@ static void memreset(int controllers, co
 }
 
 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-        
 #define SUPERIO_GPIO_IO_BASE 0x400
 
-static void sio_gpio_setup(void){
-
-	unsigned value;
-
-//	lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c
-
-#if 1
-	lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L 
-	value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
-	lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
-#endif
-	
-}
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 	/* nothing to do */
@@ -125,8 +110,9 @@ static inline int spd_read_byte(unsigned
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
-		
+                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/  \
+				RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xe4),~(1<<16|1<<17),1<<18|1<<19, /* PCI-E controller 0,1 enable; 2,3 - disable */
+
 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
 
 
@@ -168,7 +154,7 @@ static void main(unsigned long bist)
         lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
         uart_init();
         console_init();
-	
+
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
@@ -180,7 +166,7 @@ static void main(unsigned long bist)
 
         needs_reset |= ht_setup_chains_x();
 
-	needs_reset |= ck804_early_setup_x();	
+	needs_reset |= ck804_early_setup_x();
 
        	if (needs_reset) {
                	print_info("ht reset -\r\n");
Index: src/mainboard/sunw/ultra40/mb_conf.h
===================================================================
--- src/mainboard/sunw/ultra40/mb_conf.h	(revision 0)
+++ src/mainboard/sunw/ultra40/mb_conf.h	(revision 0)
@@ -0,0 +1,44 @@
+#if !defined(__MB_CONF__H__)
+#define __MB_CONF__H__
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+typedef struct {
+	// Variables for MB layouts.
+	// These will be shared by irqtable mptable and acpi_tables
+	unsigned char bus_isa;
+	unsigned char bus_ck804_0;	// CK804 HT bus
+	unsigned char bus_pci;		// PCI bus; CK804 -> device 9 (P2P bridge) -> secondary bus number
+//	unsigned char bus_ck804_2;
+//	unsigned char bus_ck804_3;
+//	unsigned char bus_ck804_4;
+	unsigned char bus_pcie_x4;	//PCI-E bus, CK804 -> device D (P2P bridge) -> secondary bus number
+	unsigned char bus_pcie_x16;	// PCI-E bus, CK804 -> device E (P2P bridge) -> secondary bus number
+//	unsigned char bus_8131_0;	//
+//	unsigned char bus_8131_1;	//
+//	unsigned char bus_8131_2;	//
+//	unsigned char bus_ck804b_0;	// IO4 HT bus
+//	unsigned char bus_ck804b_1;	//
+//	unsigned char bus_ck804b_2;	//
+//	unsigned char bus_ck804b_3;	//
+//	unsigned char bus_ck804b_4;	//
+//	unsigned char bus_ck804b_5;	// PCI-E bus, IO4 -> device E (P2P bridge) -> secondary bus number
+
+	unsigned apicid_ck804;
+//	unsigned apicid_8131_1;
+//	unsigned apicid_8131_2;
+//	unsigned apicid_ck804b;
+
+	//unsigned sblk;
+	unsigned sbdn;		//CK804 Unit ID == its first device number
+	//unsigned sbdn3;
+	//unsigned sbdnb;	//IO04 Unit ID == its first device number
+
+	int coproc_busN;
+	int coproc_devN;
+	int coproc_plugged;
+} mb_conf_t;
+
+mb_conf_t const* get_bus_conf(void);
+
+#endif //!defined(__MB_CONF__H__)
Index: src/mainboard/sunw/ultra40/cache_as_ram_auto.c
===================================================================
--- src/mainboard/sunw/ultra40/cache_as_ram_auto.c	(revision 2542)
+++ src/mainboard/sunw/ultra40/cache_as_ram_auto.c	(working copy)
@@ -12,7 +12,7 @@
 #define SET_NB_CFG_54 1
 #endif
 
- 
+
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
@@ -59,20 +59,8 @@ static void memreset(int controllers, co
 }
 
 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-
 #define SUPERIO_GPIO_IO_BASE 0x400
 
-static void sio_gpio_setup(void){
-
-        unsigned value;
-
-        /*Enable onboard scsi*/
-        lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L 
-        value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
-        lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
-
-}
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
 	/* nothing to do */
@@ -89,7 +77,7 @@ static inline int spd_read_byte(unsigned
 #include "sdram/generic_sdram.c"
 
  /* tyan does not want the default */
-#include "resourcemap.c" 
+#include "resourcemap.c"
 
 #include "cpu/amd/dualcore/dualcore.c"
 
@@ -106,7 +94,8 @@ static inline int spd_read_byte(unsigned
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
-                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
+                RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/  \
+				RES_PCI_IO, PCI_ADDR(0,CK804_DEVN_BASE+1,0,0xe4),~(1<<16|1<<17),1<<18|1<<19, /* PCI-E controller 0,1 enable; 2,3 - disable */
 
 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
 
@@ -130,22 +119,22 @@ static void sio_setup(void)
         uint32_t dword;
         uint8_t byte;
 
-        
+
         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
-        
+
         byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
-        byte |= 0x20; 
+        byte |= 0x20;
         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
-        
+
         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
         dword |= (1<<29)|(1<<0);
         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
-        
-#if  1  
+
+#if  1
         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
-                
+
         value =  lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
-        value &= 0xbf; 
+        value &= 0xbf;
         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 #endif
 
@@ -232,7 +221,7 @@ void real_main(unsigned long bist, unsig
 	lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
         uart_init();
         console_init();
-	
+
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
Index: src/mainboard/sunw/ultra40/get_bus_conf.c
===================================================================
--- src/mainboard/sunw/ultra40/get_bus_conf.c	(revision 2542)
+++ src/mainboard/sunw/ultra40/get_bus_conf.c	(working copy)
@@ -6,266 +6,115 @@
 #if CONFIG_LOGICAL_CPUS==1
 #include <cpu/amd/dualcore.h>
 #endif
+#include "mb_conf.h"
 
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-//busnum is default
-        unsigned char bus_isa;
-        unsigned char bus_ck804_0; //1
-        unsigned char bus_ck804_1; //2
-        unsigned char bus_ck804_2; //3
-        unsigned char bus_ck804_3; //4
-        unsigned char bus_ck804_4; //5
-        unsigned char bus_ck804_5; //6
-        unsigned char bus_8131_0;  //7
-        unsigned char bus_8131_1;  //8
-        unsigned char bus_8131_2;  //9
-        unsigned char bus_ck804b_0;//a
-        unsigned char bus_ck804b_1;//b
-        unsigned char bus_ck804b_2;//c
-        unsigned char bus_ck804b_3;//d
-        unsigned char bus_ck804b_4;//e
-        unsigned char bus_ck804b_5;//f
-        unsigned apicid_ck804;
-        unsigned apicid_8131_1;
-        unsigned apicid_8131_2;
-        unsigned apicid_ck804b;
-
-unsigned sblk;
-unsigned pci1234[] = 
-{        //Here you only need to set value in pci1234 for HT-IO that could be installed or not
-	 //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
-        0x0000ff0,
-        0x0000ff0,
-        0x0000ff0,
-//        0x0000ff0,
-//        0x0000ff0,
-//        0x0000ff0,
-//        0x0000ff0,
-//        0x0000ff0
+static unsigned const pci1234x[] =
+{	//Here you only need to set value in pci1234 for HT-IO that could be installed or not
+	//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+	0x0000ff0,
+	0x0000ff0,
+	0x0000ff0,
+//	0x0000ff0,
+//	0x0000ff0,
+//	0x0000ff0,
+//	0x0000ff0,
+//	0x0000ff0
 };
-unsigned hc_possible_num;
-unsigned sbdn;
-unsigned hcdn[] = 
-{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
+//static unsigned const  _hc_possible_num=sizeof(_pci1234)/sizeof(_pci1234[0]);
+static unsigned const hcdnx[] =
+{	//HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
+	0x20202020,
 	0x20202020,
 	0x20202020,
-        0x20202020,
-//        0x20202020,
-//        0x20202020,
-//        0x20202020,
-//        0x20202020,
-//        0x20202020,
+//	0x20202020,
+//	0x20202020,
+//	0x20202020,
+//	0x20202020,
+//	0x20202020,
 };
-unsigned sbdn3;
-unsigned sbdnb;
 
 extern void get_sblk_pci1234(void);
 
-static unsigned get_bus_conf_done = 0;
-
-void get_bus_conf(void)
+mb_conf_t const* get_bus_conf(void)
 {
-
 	unsigned apicid_base;
-
-        device_t dev;
-
-	if(get_bus_conf_done==1) return; //do it only once
-
-	get_bus_conf_done = 1;
-
-	hc_possible_num = sizeof(pci1234)/sizeof(pci1234[0]);	
-	
+	device_t dev;
+	unsigned i;
+	static mb_conf_t bc;
+	static mb_conf_t* ret=0;
+
+	if (ret!=0) return ret; //do it only once
+
+	sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+	for (i=0; i!=sizeof(pci1234x)/sizeof(pci1234x[0]); ++i) {
+		sysconf.pci1234[i]=pci1234x[i];
+		sysconf.hcdn[i]=hcdnx[i];
+	}
 	get_sblk_pci1234();
-	
-	sbdn = (hcdn[0] & 0xff); // first byte of first chain
-
-	sbdn3 = (hcdn[1] & 0xff);
-
-	sbdnb = (hcdn[2] & 0xff); // first byte of second chain
 
-//	bus_ck804_0 = node_link_to_bus(0, sblk);
-	bus_ck804_0 = (pci1234[0] >> 16) & 0xff;
-
-                /* CK804 */
-                dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0));
-                if (dev) {
-                        bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if 0
-                        bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-                        bus_ck804_2++;
-#else
-                        bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-                        bus_ck804_5++;
-#endif
-                }
-                else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
-
-                        bus_ck804_1 = 2;
-#if 0
-                        bus_ck804_2 = 3;
-#else
-                        bus_ck804_5 = 3;
-#endif
-
-                }
-#if 0
-                dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b,0));
-                if (dev) {
-                        bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-                        bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-                        bus_ck804_3++;
-                }
-                else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0b);
-
-                        bus_ck804_3 = bus_ck804_2+1;
-                }
-
-                dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c,0));
-                if (dev) {
-                        bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-                        bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-                        bus_ck804_4++;
-                }
-                else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0c);
-
-                        bus_ck804_4 = bus_ck804_3+1;
-                }
-
-
-                dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0));
-                if (dev) {
-                        bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-                        bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-                        bus_ck804_5++;
-                }
-                else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",sbdn + 0x0d);
-
-                        bus_ck804_5 = bus_ck804_4+1;
-                }
-#endif
-
-                dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0));
-                if (dev) {
-                        bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-                }
-                else {
-                        printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
-                }
-
-		bus_8131_0 = (pci1234[1] >> 16) & 0xff;
-                /* 8131-1 */
-                dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
-                if (dev) {
-                        bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-                        bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-                        bus_8131_2++;
-                }
-                else {
-                        printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
-
-                        bus_8131_1 = bus_8131_0+1;
-                        bus_8131_2 = bus_8131_0+2;
-                }
-                /* 8131-2 */
-                dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
-                if (dev) {
-                        bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-                        bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-                        bus_isa++;
-                }
-                else {
-                        printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
-
-                        bus_8131_2 = bus_8131_1+1;
-                }
-
-                /* CK804b */
-
-	if(pci1234[2] & 0xf) { //if the second cpu is installed
-		bus_ck804b_0 = (pci1234[2]>>16) & 0xff;
-#if 0
-                dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x09,0));
-                if (dev) {
-                        bus_ck804b_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-                        bus_ck804b_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-                        bus_ck804b_2++;
-                }
-                else {
-                        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x09);
-
-                        bus_ck804b_1 = bus_ck804b_0+1;
-                        bus_ck804b_2 = bus_ck804b_0+2;
-                }
-
-                dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0b,0));
-                if (dev) {
-                        bus_ck804b_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-                        bus_ck804b_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-                        bus_ck804b_3++;
-                }
-                else {
-                        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0b);
-
-                        bus_ck804b_2 = bus_ck804b_0+1;
-                        bus_ck804b_3 = bus_ck804b_0+2;
-                }
-
-                dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0c,0));
-                if (dev) {
-                        bus_ck804b_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-                        bus_ck804b_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-                        bus_ck804b_4++;
-                }
-                else {
-                        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0c);
-
-                        bus_ck804b_4 = bus_ck804b_3+1;
-                }
-                dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0d,0));
-                if (dev) {
-                        bus_ck804b_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-                        bus_ck804b_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-                        bus_ck804b_5++;
-                }
-                else {
-                        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0d);
-
-                        bus_ck804b_5 = bus_ck804b_4+1;
-                }
-#endif
+	bc.sbdn  = (sysconf.hcdn[0] & 0xff); // device number of CK804
+//	bc.sbdn3 = (sysconf.hcdn[1] & 0xff);
+//	bc.sbdnb = (sysconf.hcdn[2] & 0xff);
+
+	bc.bus_ck804_0 = (sysconf.pci1234[0] >> 16) & 0xff;
+
+	/* CK804 */
+	dev = dev_find_slot(bc.bus_ck804_0, PCI_DEVFN(bc.sbdn + 0x09,0));
+	if (!dev) {
+		printk_emerg("ERROR - cannot find CK804's device 9 - PCI-to-PCI bridge\n");
+		while (1) continue;
+	}
+	bc.bus_pci = pci_read_config8(dev, PCI_SECONDARY_BUS);
+//	bc.bus_isa = 1 + pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 
-                dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0e,0));
-                if (dev) {
-                        bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-                        bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-                        bus_isa++;
-                }
-                else {
-                        printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0e);
-#if 1
-                        bus_ck804b_5 = bus_ck804b_4+1;
-#endif
+	dev=dev_find_slot(bc.bus_ck804_0,PCI_DEVFN(bc.sbdn+0x0d,0));
+	if (!dev) {
+		printk_emerg("ERROR - cannot find CK804's device D - PCI-to-PCIe bridge\n");
+		while (1) continue;
+	}
+	bc.bus_pcie_x4=pci_read_config8(dev,PCI_SECONDARY_BUS);
 
-                        bus_isa = bus_ck804b_5+1;
-                }
+	dev = dev_find_slot(bc.bus_ck804_0, PCI_DEVFN(bc.sbdn+ 0x0e,0));
+	if (!dev) {
+		printk_emerg("ERROR - cannot find CK804's device E - PCI-to-PCI bridge\n", bc.sbdn+ 0x0e);
+		while (1) continue;
 	}
+	bc.bus_pcie_x16 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+	bc.bus_isa=bc.bus_pcie_x16+1;
 
+//	/* IO04 */
+//	if(sysconf.pci1234[2] & 0xf) { //if the second cpu is installed
+//		bc.bus_ck804b_0 = (sysconf.pci1234[2]>>16) & 0xff;
+//		dev = dev_find_slot(bc.bus_ck804b_0, PCI_DEVFN(bc.sbdnb + 0x0e,0));
+//		if (!dev) {
+//			printk_emerg("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bc.bus_ck804b_0,bc.sbdnb+0x0e);
+//			while (1) continue;
+//		}
+//		bc.bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+//		bc.bus_isa = 1 + pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+//	}
+
+	if (sysconf.pci1234[1] & 0xf) { //if another HT chain is present
+		unsigned busN=sysconf.pci1234[1]>>16 & 0xff;
+		unsigned devN=sysconf.hcdn[1] & 0xff;
+		dev=dev_find_slot(busN,PCI_DEVFN(devN,0));
+		if (dev && pci_read_config16(dev,0)!=PCI_VENDOR_ID_NVIDIA) {
+			bc.coproc_busN=busN;
+			bc.coproc_devN=devN;
+			bc.coproc_plugged=1;
+			printk_debug("Coprocessor installed, bus=%02x, dev=%02x\n",busN,devN);
+		}
+	}
 
 /*I/O APICs:	APIC ID	Version	State		Address*/
 #if CONFIG_LOGICAL_CPUS==1
 	apicid_base = get_apicid_base(4);
-#else 
-	apicid_base = CONFIG_MAX_PHYSICAL_CPUS; 
+#else
+	apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
 #endif
-	apicid_ck804 = apicid_base+0;
-        apicid_8131_1 = apicid_base+1;
-        apicid_8131_2 = apicid_base+2;
-        apicid_ck804b = apicid_base+3;
-
+	bc.apicid_ck804 = apicid_base+0;
+//	bc.apicid_8131_1 = apicid_base+1;
+//	bc.apicid_8131_2 = apicid_base+2;
+//	bc.apicid_ck804b = apicid_base+3;
+	return ret=&bc;
 }
Index: targets/sunw/ultra40/Config.kernel.lb
===================================================================
--- targets/sunw/ultra40/Config.kernel.lb	(revision 0)
+++ targets/sunw/ultra40/Config.kernel.lb	(revision 0)
@@ -0,0 +1,24 @@
+# Sample config file for
+# the sunw ultra40
+# This will make a target directory of ./ultra40
+
+target ultra40
+mainboard sunw/ultra40
+
+option ROM_SIZE=1024*1024
+option DEFAULT_CONSOLE_LOGLEVEL=11
+option MAXIMUM_CONSOLE_LOGLEVEL=11
+option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
+option CONFIG_PRECOMPRESSED_PAYLOAD=1
+option HT_CHAIN_UNITID_BASE=0
+option SB_HT_CHAIN_UNITID_OFFSET_ONLY=1
+
+romimage "fallback"
+	option USE_FALLBACK_IMAGE=1
+	option FALLBACK_SIZE=1024*1024
+	option ROM_IMAGE_SIZE=128*1024
+	option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+	payload ../payload.zelf
+end
+
+buildrom ./linuxbios.rom ROM_SIZE  "fallback"




