I’m trying to bring up an Intel Rangeley based prototype board using coreboot and Intel FSP. During FspInitEntry, FSP prints:

Err[24]: GetSet Value exceeds limits

to serial debug and halts. Does anyone know what this means?

I’m using the Memory Down option in the FSP and filling in the MEM_DOWN_DIMM_CONFIG structure in mainboard/…/romstage.c

I can see that the FSP is reading and validating this structure, as changing the ram speed has an effect on memory clock frequency, and if I put in invalid values the FSP will complain. I’ve tried reducing memory speed, disabling ECC, disabling channel 1 but I always get the same error.

Does anyone else have any experience with Memory Down on Rangeley?

Andy Knowles