coreboot-4.0-r6298M Wed Jan 26 15:55:08 EST 2011 starting... Enabling routing table for node 00 done. Enabling SMP settings 01 nodes initialized. Enabling UP settings coherent_ht_finalize done core0 started: started ap apicid: * AP 01started SBLink=01 NC node|link=01 entering ht_optimize_link pos=0xaa, unfiltered freq_cap=0x8075 pos=0xaa, filtered freq_cap=0x75 pos=0x52, unfiltered freq_cap=0x807f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x75, freq_cap2=0x7f dev1 old_freq=0x0, freq=0x6, needs_reset=0x1 dev2 old_freq=0x0, freq=0x6, needs_reset=0x1 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 ht reset - coreboot-4.0-r6298M Wed Jan 26 15:55:08 EST 2011 starting... Enabling routing table for node 00 done. Enabling SMP settings 01 nodes initialized. Enabling UP settings coherent_ht_finalize done core0 started: started ap apicid: * AP 01started SBLink=01 NC node|link=01 entering ht_optimize_link pos=0xaa, unfiltered freq_cap=0x8075 pos=0xaa, filtered freq_cap=0x75 pos=0x52, unfiltered freq_cap=0x807f pos=0x52, filtered freq_cap=0x7f freq_cap1=0x75, freq_cap2=0x7f dev1 old_freq=0x6, freq=0x6, needs_reset=0x0 dev2 old_freq=0x6, freq=0x6, needs_reset=0x0 width_cap1=0x11, width_cap2=0x11 dev1 input ln_width1=0x4, ln_width2=0x4 dev1 input width=0x1 dev1 output ln_width1=0x4, ln_width2=0x4 dev1 input|output width=0x11 old dev1 input|output width=0x11 dev2 input|output width=0x11 old dev2 input|output width=0x11 SMBus controller enabled Ram1.00 setting up CPU00 northbridge registers done. Ram2.00 Enabling dual channel memory Registered 200Mhz dtl= 0x12623541 latency= 0x00000001 mtype= 0x00000000 lat= 0x00000000 clocks= 0x00000000 Interleaved RAM end at 0x00200000 kB Lower RAM end at 0x00200000 kB Ram3 ECC enabled Initializing memory: done Handling memory hole at 0x00300000 (default) Ram4 v_esp=000cee08 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Loading image. Check CBFS header at fffffcfe magic is 4f524243 Found CBFS header at fffffcfe Check cmos_layout.bin CBFS: follow chain: fff00000 + 28 + 6f3 + align -> fff00740 Check fallback/romstage CBFS: follow chain: fff00740 + 38 + 790e + align -> fff080c0 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (344064 bytes), entry @ 0x10000 Stage: done loading. Jumping to image. coreboot-4.0-r6298M Wed Jan 26 15:55:08 EST 2011 booting... Enumerating buses... Show all devs...Before device enumeration. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.7: enabled 1 PNP: 002e.8: enabled 1 PNP: 002e.9: enabled 1 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 0 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:04.0: enabled 0 PCI: 00:04.1: enabled 0 PCI: 00:06.0: enabled 1 PCI: 00:07.0: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 0 PCI: 00:0b.0: enabled 1 PCI: 00:0c.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:0e.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 Compare with tree... Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.7: enabled 1 PNP: 002e.8: enabled 1 PNP: 002e.9: enabled 1 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 0 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:04.0: enabled 0 PCI: 00:04.1: enabled 0 PCI: 00:06.0: enabled 1 PCI: 00:07.0: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 0 PCI: 00:0b.0: enabled 1 PCI: 00:0c.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:0e.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 scan_static_bus for Root Device APIC_CLUSTER: 0 enabled PCI_DOMAIN: 0000 enabled APIC_CLUSTER: 0 scanning... PCI: 00:18.3 siblings=1 CPU: APIC: 00 enabled CPU: APIC: 01 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] bus ops PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] ops PCI: 00:18.3 [1022/1103] enabled PCI: pci_scan_bus returning with max=000 PCI_DOMAIN: 0000 passpw: enabled scan_static_bus for Root Device done done Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 APIC_CLUSTER: 0 read_resources bus 0 link: 0 APIC: 00 missing read_resources APIC: 01 missing read_resources APIC_CLUSTER: 0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:18.0 read_resources bus 0 link: 0 PCI: 00:00.0 missing read_resources PCI: 00:01.0 missing read_resources PCI: 00:01.1 missing read_resources PCI: 00:02.0 missing read_resources PCI: 00:02.1 missing read_resources PCI: 00:06.0 missing read_resources PCI: 00:07.0 missing read_resources PCI: 00:08.0 missing read_resources PCI: 00:09.0 missing read_resources PCI: 00:0b.0 missing read_resources PCI: 00:0c.0 missing read_resources PCI: 00:0d.0 missing read_resources PCI: 00:0e.0 missing read_resources PCI: 00:18.0 read_resources bus 0 link: 0 done PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 0 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 801000 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags2 PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81 PCI: 00:00.0 PCI: 00:01.0 child on link 0 PNP: 002e.0 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 0 PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 4 PNP: 002e.1 PNP: 002e.1 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 PNP: 002e.1 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 0 PNP: 002e.1 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000800 4 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 0 align 0 gran 0 limit 0 flags c0000100 PNP: 002e.2 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000400 0 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 0 align 0 gran 0 limit 0 flags c0000100 PNP: 002e.3 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000400 0 PNP: 002e.5 PNP: 002e.5 resource base 60 size 0 align 0 gran 0 limit 0 flags c00001000 PNP: 002e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags c00001002 PNP: 002e.5 resource base 1 size 0 align 0 gran 0 limit 0 flags c0000400 0 PNP: 002e.5 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 2 PNP: 002e.7 PNP: 002e.7 resource base 330 size 0 align 0 gran 0 limit 0 flags c0000102 PNP: 002e.7 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 0 PNP: 002e.8 PNP: 002e.9 PNP: 002e.9 resource base 7f size 0 align 0 gran 0 limit 0 flags c00004000 PNP: 002e.9 resource base cb size 0 align 0 gran 0 limit 0 flags c00004001 PNP: 002e.a PNP: 002e.b PCI: 00:01.1 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:04.0 PCI: 00:04.1 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 PCI: 00:0a.0 PCI: 00:0b.0 PCI: 00:0c.0 PCI: 00:0d.0 PCI: 00:0e.0 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base 0 size 4000000 align 26 gran 26 limit ffffffff f4 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit:f PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ff PCI: 00:18.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: fe PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit:e PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limitf PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limf PCI: 00:18.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 lime PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: f PCI: 00:18.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: e PCI: 00:18.3 94 * [0x0 - 0x3ffffff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 4000000 size: 4000000 align: 26 e avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:18.0 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PNP: 002e.0 skipping PNP: 002e.0@60 fixed resource, size=0! skipping PNP: 002e.0@70 fixed resource, size=0! skipping PNP: 002e.0@74 fixed resource, size=0! constrain_resources: PNP: 002e.1 skipping PNP: 002e.1@60 fixed resource, size=0! skipping PNP: 002e.1@70 fixed resource, size=0! skipping PNP: 002e.1@74 fixed resource, size=0! constrain_resources: PNP: 002e.2 skipping PNP: 002e.2@60 fixed resource, size=0! skipping PNP: 002e.2@70 fixed resource, size=0! constrain_resources: PNP: 002e.3 skipping PNP: 002e.3@60 fixed resource, size=0! skipping PNP: 002e.3@70 fixed resource, size=0! constrain_resources: PNP: 002e.5 skipping PNP: 002e.5@60 fixed resource, size=0! skipping PNP: 002e.5@62 fixed resource, size=0! skipping PNP: 002e.5@70 fixed resource, size=0! skipping PNP: 002e.5@72 fixed resource, size=0! constrain_resources: PNP: 002e.7 skipping PNP: 002e.7@62 fixed resource, size=0! skipping PNP: 002e.7@70 fixed resource, size=0! constrain_resources: PNP: 002e.8 constrain_resources: PNP: 002e.9 skipping PNP: 002e.9@f0 fixed resource, size=0! skipping PNP: 002e.9@f1 fixed resource, size=0! constrain_resources: PCI: 00:01.1 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:02.1 constrain_resources: PCI: 00:06.0 constrain_resources: PCI: 00:07.0 constrain_resources: PCI: 00:08.0 constrain_resources: PCI: 00:09.0 constrain_resources: PCI: 00:0b.0 constrain_resources: PCI: 00:0c.0 constrain_resources: PCI: 00:0d.0 constrain_resources: PCI: 00:0e.0 constrain_resources: PCI: 00:18.1 constrain_resources: PCI: 00:18.2 constrain_resources: PCI: 00:18.3 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00000000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit ffffffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:0 size:0 align:0 gran:0 limit:ffff PCI_DOMAIN: 0000 allocate_resources_io: next_base: 0 size: 0 align: 0 gran: 0 e PCI: 00:18.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:fff PCI: 00:18.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12e PCI_DOMAIN: 0000 allocate_resources_mem: base:fc000000 size:4000000 align:26 gf Assigned: PCI: 00:18.3 94 * [0xfc000000 - 0xffffffff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: 100000000 size: 4000000 ale PCI: 00:18.0 allocate_resources_prefmem: base:ffffffff size:0 align:20 gran:20f PCI: 00:18.0 allocate_resources_prefmem: next_base: ffffffff size: 0 align: 20e PCI: 00:18.0 allocate_resources_mem: base:ffffffff size:0 align:20 gran:20 limf PCI: 00:18.0 allocate_resources_mem: next_base: ffffffff size: 0 align: 20 grae Root Device assign_resources, bus 0 link: 0 0: mmio_basek=003f0000, basek=00000300, limitk=00200000 PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.0 assign_resources, bus 0 link: 0 PCI: 00:18.3 94 <- [0x00fc000000 - 0x00ffffffff] size 0x04000000 gran 0x1a mem> PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 APIC_CLUSTER: 0 APIC_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 PCI_DOMAIN: 0000 child on link 0 PCI: 00:18.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040 PCI_DOMAIN: 0000 resource base fc000000 size 4000000 align 26 gran 0 limit f0 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e000 PCI_DOMAIN: 0000 resource base c0000 size 7ff40000 align 0 gran 0 limit 0 fl0 PCI: 00:18.0 child on link 0 PCI: 00:00.0 PCI: 00:18.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 400 PCI: 00:18.0 resource base ffffffff size 0 align 20 gran 20 limit ffffffff 2 PCI: 00:18.0 resource base ffffffff size 0 align 20 gran 20 limit ffffffff 1 PCI: 00:00.0 PCI: 00:01.0 child on link 0 PNP: 002e.0 PNP: 002e.0 PNP: 002e.0 resource base 3f0 size 0 align 0 gran 0 limit 0 flags c0000100 PNP: 002e.0 resource base 6 size 0 align 0 gran 0 limit 0 flags c0000400 0 PNP: 002e.0 resource base 2 size 0 align 0 gran 0 limit 0 flags c0000800 4 PNP: 002e.1 PNP: 002e.1 resource base 378 size 0 align 0 gran 0 limit 0 flags c0000100 PNP: 002e.1 resource base 7 size 0 align 0 gran 0 limit 0 flags c0000400 0 PNP: 002e.1 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000800 4 PNP: 002e.2 PNP: 002e.2 resource base 3f8 size 0 align 0 gran 0 limit 0 flags c0000100 PNP: 002e.2 resource base 4 size 0 align 0 gran 0 limit 0 flags c0000400 0 PNP: 002e.3 PNP: 002e.3 resource base 2f8 size 0 align 0 gran 0 limit 0 flags c0000100 PNP: 002e.3 resource base 3 size 0 align 0 gran 0 limit 0 flags c0000400 0 PNP: 002e.5 PNP: 002e.5 resource base 60 size 0 align 0 gran 0 limit 0 flags c00001000 PNP: 002e.5 resource base 64 size 0 align 0 gran 0 limit 0 flags c00001002 PNP: 002e.5 resource base 1 size 0 align 0 gran 0 limit 0 flags c0000400 0 PNP: 002e.5 resource base c size 0 align 0 gran 0 limit 0 flags c0000400 2 PNP: 002e.7 PNP: 002e.7 resource base 330 size 0 align 0 gran 0 limit 0 flags c0000102 PNP: 002e.7 resource base 9 size 0 align 0 gran 0 limit 0 flags c0000400 0 PNP: 002e.8 PNP: 002e.9 PNP: 002e.9 resource base 7f size 0 align 0 gran 0 limit 0 flags c00004000 PNP: 002e.9 resource base cb size 0 align 0 gran 0 limit 0 flags c00004001 PNP: 002e.a PNP: 002e.b PCI: 00:01.1 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:04.0 PCI: 00:04.1 PCI: 00:06.0 PCI: 00:07.0 PCI: 00:08.0 PCI: 00:09.0 PCI: 00:0a.0 PCI: 00:0b.0 PCI: 00:0c.0 PCI: 00:0d.0 PCI: 00:0e.0 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.3 resource base fc000000 size 4000000 align 26 gran 26 limit fff4 Done allocating resources. Enabling resources... PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1043/8162 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1043/8162 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 cmd <- 00 done. Initializing devices... Root Device init APIC_CLUSTER: 0 init start_eip=0x0000b000, offset=0x00100000, code_size=0x0000005b Initializing CPU #0 CPU: vendor AMD device 20f12 CPU: family 0f, model 21, stepping 02 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB ADDRESS_MASK_HIGH=0xff Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled microcode: equivalent rev id = 0x0210, current patch id = 0x00000000 microcode: rev id (4a) does not match this patch. microcode: Not updated! Fix microcode_updates[] microcode: rev id (150) does not match this patch. microcode: Not updated! Fix microcode_updates[] microcode: patch id to apply = 0x0000004d microcode: updated to patch id = 0x0000004d success CPU model Dual Core AMD Opteron(tm) Processor 275 Setting up local apic... apic_id: 0x00 done. Clearing memory 2048K - 2097152K: ------------------------------- done CPU #0 initialized Asserting INIT. Waiting for send to finish... +Deasserting INIT. Waiting for send to finish... +#startup loops: 2. Sending STARTUP #1 to 1. After apic_write. Startup point 1. Waiting for send to finish... +Sending STARTUP #2 to 1. After apic_write. Startup point 1. Waiting for send to finish... +After Startup. Initializing CPU #1 Waiting for 1 CPUS to stop CPU: vendor AMD device 20f12 CPU: family 0f, model 21, stepping 02 Enabling cache Setting fixed MTRRs(0-88) type: UC Setting fixed MTRRs(0-16) Type: WB, RdMEM, WrMEM Setting fixed MTRRs(24-88) Type: WB, RdMEM, WrMEM DONE fixed MTRRs Setting variable MTRR 0, base: 0MB, range: 2048MB, type WB ADDRESS_MASK_HIGH=0xff Zero-sized MTRR range @0KB DONE variable MTRRs Clear out the extra MTRR's call enable_var_mtrr() Leave x86_setup_var_mtrrs MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled microcode: equivalent rev id = 0x0210, current patch id = 0x00000000 microcode: rev id (4a) does not match this patch. microcode: Not updated! Fix microcode_updates[] microcode: rev id (150) does not match this patch. microcode: Not updated! Fix microcode_updates[] microcode: patch id to apply = 0x0000004d microcode: updated to patch id = 0x0000004d success CPU model Dual Core AMD Opteron(tm) Processor 275 Setting up local apic... apic_id: 0x01 done. CPU #1 initialized All AP CPUs stopped PCI: 00:18.0 init PCI: 00:18.1 init Check CBFS header at fffffcfe magic is 4f524243 Found CBFS header at fffffcfe Check cmos_layout.bin CBFS: follow chain: fff00000 + 28 + 6f3 + align -> fff00740 Check fallback/romstage CBFS: follow chain: fff00740 + 38 + 790e + align -> fff080c0 Check fallback/coreboot_ram CBFS: follow chain: fff080c0 + 38 + a989 + align -> fff12ac0 Check fallback/payload CBFS: follow chain: fff12ac0 + 38 + b6e8 + align -> fff1e200 Check CBFS: follow chain: fff1e200 + 28 + e1ad6 + align -> fffffd00 CBFS: Could not find file pci1022,1101.rom PCI: 00:18.2 init Check CBFS header at fffffcfe magic is 4f524243 Found CBFS header at fffffcfe Check cmos_layout.bin CBFS: follow chain: fff00000 + 28 + 6f3 + align -> fff00740 Check fallback/romstage CBFS: follow chain: fff00740 + 38 + 790e + align -> fff080c0 Check fallback/coreboot_ram CBFS: follow chain: fff080c0 + 38 + a989 + align -> fff12ac0 Check fallback/payload CBFS: follow chain: fff12ac0 + 38 + b6e8 + align -> fff1e200 Check CBFS: follow chain: fff1e200 + 28 + e1ad6 + align -> fffffd00 CBFS: Could not find file pci1022,1102.rom PCI: 00:18.3 init NB: Function 3 Misc Control.. done. Devices initialized Show all devs...After init. Root Device: enabled 1 APIC_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 PCI_DOMAIN: 0000: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:01.0: enabled 1 PNP: 002e.0: enabled 1 PNP: 002e.1: enabled 1 PNP: 002e.2: enabled 1 PNP: 002e.3: enabled 1 PNP: 002e.5: enabled 1 PNP: 002e.7: enabled 1 PNP: 002e.8: enabled 1 PNP: 002e.9: enabled 1 PNP: 002e.a: enabled 0 PNP: 002e.b: enabled 0 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:04.0: enabled 0 PCI: 00:04.1: enabled 0 PCI: 00:06.0: enabled 1 PCI: 00:07.0: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:0a.0: enabled 0 PCI: 00:0b.0: enabled 1 PCI: 00:0c.0: enabled 1 PCI: 00:0d.0: enabled 1 PCI: 00:0e.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 APIC: 01: enabled 1 Initializing CBMEM area to 0x7fff0000 (65536 bytes) Adding CBMEM entry as no. 1 Moving GDT to 7fff0200...ok High Tables Base is 7fff0000. PCI: Using configuration type 1 Writing IRQ routing tables to 0xf0000...done. Adding CBMEM entry as no. 2 Writing IRQ routing tables to 0x7fff0400...done. PIRQ table: 256 bytes. PCI: 00:01.0 missing resource: 14