Please, try to do the following exercise:

[1] WR 0x1000 to SC_GP_LVL, then RD the value out of it: what it is?

[2] WR 0x2000 to SC_GP_LVL, then RD the value out of it: what it is?

[3] WR 0x4000 to SC_GP_LVL, then RD the value out of it: what it is?

If you have all 0x0, most likely it does mean that Rangeley's SC_GP_LVL register isd WR ONLY (when you read it, all 0s).

To verify this, you should fetch the following document:

http://www.intel.com/content/www/us/en/processors/atom/atom-c2000-microserver-datasheet.html

And read Chapter 25 - General Purpose I/O (GPIO).

Best Regards,

Zoran

On Wed, Jul 13, 2016 at 6:39 AM, 김유석 <poplinux0@gmail.com> wrote:

Dear Sir.

I want to control the GPIO pin that pin number is 12, 13, 14

DataSheet(P 1909) and coreboot source code(src/southbridge/intel/fsp_rangeley/gpio.c, gpio.h) is said to me that "It is very easy"

If i want to set the HIGH to 12, 13, 14

Just setup the some register, is see below.

SC_USE_SEL = 0x7000(b0111 0000 0000 0000)

    Is mean, the 12, 13, 14 is config to GPIO mode.(enable GPIO)

SC_IO_SEL = 0x00(b0000 0000 0000 0000)

    Is mean, the 12, 13, 14 is output mode

SC_GP_LVL = 0x7000(b0111 0000 0000 0000)

    Is mean, the 12, 13, 14 is set to HIGH level(1)

src/southbridge/intel/fsp_rangeley/gpio.h

/* Core GPIO */
const struct soc_gpio soc_gpio_mode = {
.gpio12 = GPIO_MODE_GPIO, /* Board ID GPIO */
    .gpio13 = GPIO_MODE_GPIO, /* Board ID GPIO */
    .gpio14 = GPIO_MODE_GPIO, /* Board ID GPIO */
};

const struct soc_gpio soc_gpio_direction = {
.gpio12 = GPIO_DIR_OUTPUT,
.gpio13 = GPIO_DIR_OUTPUT,
.gpio14 = GPIO_DIR_OUTPUT,
};

const struct soc_gpio soc_gpio_level = {
.gpio12 = GPIO_LEVEL_HIGH,
.gpio13 = GPIO_LEVEL_HIGH,
.gpio14 = GPIO_LEVEL_HIGH,
};

Yes, It is perfectley running.

The 12, 13, 14 PIN is goto active-HIGH.(I was check this pin use by oscilloscope.)

And I'm try to read the SC_GP_LVL register for check current status/config of gpio pins

I was respected the read value is 0x7000, because i was writed the 0x7000 to SC_GP_LVL.

But, every time readed the 0x00 from SC_GP_LVL register.

When write 0x7000 write to SC_USE_SEL, Can read the 0x7000 from SC_USE_SEL.

When write 0x00 write to SC_IO_SEL, Can read the 0x00 from SC_IO_SEL.

But,

When write 0x7000 write to SC_GP_LVL, Can read the 0x00 from SC_GP_LVL. everytime.

I don't understand this sistuation.

Please advise to me.

Thank you.

--
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot