Index: src/southbridge/via/vt8237r/vt8237r_early_smbus.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_early_smbus.c	(revision 3942)
+++ src/southbridge/via/vt8237r/vt8237r_early_smbus.c	(working copy)
@@ -39,17 +39,17 @@
 		return;
 
 	if (loops >= SMBUS_TIMEOUT)
-		print_err("SMBus timeout\r\n");
+		print_err("SMBus timeout\n");
 	if (host_status & (1 << 4))
-		print_err("Interrupt/SMI# was Failed Bus Transaction\r\n");
+		print_err("Interrupt/SMI# was Failed Bus Transaction\n");
 	if (host_status & (1 << 3))
-		print_err("Bus error\r\n");
+		print_err("Bus error\n");
 	if (host_status & (1 << 2))
-		print_err("Device error\r\n");
+		print_err("Device error\n");
 	if (host_status & (1 << 1))
-		print_debug("Interrupt/SMI# completed successfully\r\n");
+		print_debug("Interrupt/SMI# completed successfully\n");
 	if (host_status & (1 << 0))
-		print_err("Host busy\r\n");
+		print_err("Host busy\n");
 }
 
 /**
@@ -59,7 +59,7 @@
 {
 	int loops;
 
-	PRINT_DEBUG("Waiting until SMBus ready\r\n");
+	PRINT_DEBUG("Waiting until SMBus ready\n");
 
 	loops = 0;
 	/* Yes, this is a mess, but it's the easiest way to do it. */
@@ -81,7 +81,7 @@
 
 	PRINT_DEBUG("After reset status: ");
 	PRINT_DEBUG_HEX16(inb(SMBHSTSTAT));
-	PRINT_DEBUG("\r\n");
+	PRINT_DEBUG("\n");
 }
 
 /**
@@ -98,7 +98,7 @@
 	PRINT_DEBUG_HEX16(dimm);
 	PRINT_DEBUG(" OFFSET ");
 	PRINT_DEBUG_HEX16(offset);
-	PRINT_DEBUG("\r\n");
+	PRINT_DEBUG("\n");
 
 	smbus_reset();
 
@@ -121,7 +121,7 @@
 	val = inb(SMBHSTDAT0);
 	PRINT_DEBUG("Read: ");
 	PRINT_DEBUG_HEX16(val);
-	PRINT_DEBUG("\r\n");
+	PRINT_DEBUG("\n");
 
 	/* Probably don't have to do this, but it can't hurt. */
 	smbus_reset();
@@ -144,7 +144,7 @@
 		dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
 					PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
 		if (dev == PCI_DEV_INVALID)
-			die("Power management controller not found\r\n");
+			die("Power management controller not found\n");
 	}
 
 	/*
@@ -189,7 +189,7 @@
 
 	ram_slots = ARRAY_SIZE(ctrl->channel0);
 	if (!ram_slots) {
-		print_err("smbus_fixup() thinks there are no RAM slots!\r\n");
+		print_err("smbus_fixup() thinks there are no RAM slots!\n");
 		return;
 	}
 
@@ -213,9 +213,9 @@
 	}
 
 	if (i >= SMBUS_TIMEOUT)
-		print_err("SMBus timed out while warming up\r\n");
+		print_err("SMBus timed out while warming up\n");
 	else
-		PRINT_DEBUG("Done\r\n");
+		PRINT_DEBUG("Done\n");
 }
 
 /* FIXME: Better separate the NB and SB, will be done once it works. */
@@ -306,7 +306,7 @@
 				       PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
 
 	if (dev == PCI_DEV_INVALID)
-		die("SB not found\r\n");
+		die("SB not found\n");
 
 	/* Put SPI base 20 d0 fe. */
 	tmp = pci_read_config32(dev, 0xbc);
Index: src/southbridge/via/vt8231/vt8231_early_serial.c
===================================================================
--- src/southbridge/via/vt8231/vt8231_early_serial.c	(revision 3942)
+++ src/southbridge/via/vt8231/vt8231_early_serial.c	(working copy)
@@ -39,7 +39,7 @@
 	
 	if (dev == PCI_DEV_INVALID) {
 		outb(7, 0x80);
-		die("Serial controller not found\r\n");
+		die("Serial controller not found\n");
 	}
 	
 	/* first, you have to enable the superio and superio config. 
Index: src/southbridge/via/vt8231/vt8231_early_smbus.c
===================================================================
--- src/southbridge/via/vt8231/vt8231_early_smbus.c	(revision 3942)
+++ src/southbridge/via/vt8231/vt8231_early_smbus.c	(working copy)
@@ -30,7 +30,7 @@
 	dev = pci_locate_device(PCI_ID(0x1106, 0x8235), 0);
 
 	if (dev == PCI_DEV_INVALID) {
-		die("SMBUS controller not found\r\n");
+		die("SMBUS controller not found\n");
 	}
 	// set IO base address to SMBUS_IO_BASE
 	pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
@@ -47,9 +47,9 @@
 	c |= 1;
 	pci_write_config8(dev, 4, c);
 	print_debug_hex8(c);
-	print_debug(" is the comm register\r\n");
+	print_debug(" is the comm register\n");
 
-	print_debug("SMBus controller enabled\r\n");
+	print_debug("SMBus controller enabled\n");
 }
 
 
@@ -117,7 +117,7 @@
 	smbus_wait_until_ready();
 	print_debug("After reset status ");
 	print_debug_hex8(inb(SMBUS_IO_BASE + SMBHSTSTAT));
-	print_debug("\r\n");
+	print_debug("\n");
 }
 
 static void smbus_print_error(unsigned char host_status_register)
@@ -125,21 +125,21 @@
 
 	print_err("smbus_error: ");
 	print_err_hex8(host_status_register);
-	print_err("\r\n");
+	print_err("\n");
 	if (host_status_register & (1 << 4)) {
-		print_err("Interrup/SMI# was Failed Bus Transaction\r\n");
+		print_err("Interrup/SMI# was Failed Bus Transaction\n");
 	}
 	if (host_status_register & (1 << 3)) {
-		print_err("Bus Error\r\n");
+		print_err("Bus Error\n");
 	}
 	if (host_status_register & (1 << 2)) {
-		print_err("Device Error\r\n");
+		print_err("Device Error\n");
 	}
 	if (host_status_register & (1 << 1)) {
-		print_err("Interrupt/SMI# was Successful Completion\r\n");
+		print_err("Interrupt/SMI# was Successful Completion\n");
 	}
 	if (host_status_register & (1 << 0)) {
-		print_err("Host Busy\r\n");
+		print_err("Host Busy\n");
 	}
 }
 
Index: src/southbridge/via/vt82c686/vt82c686_early_serial.c
===================================================================
--- src/southbridge/via/vt82c686/vt82c686_early_serial.c	(revision 3942)
+++ src/southbridge/via/vt82c686/vt82c686_early_serial.c	(working copy)
@@ -65,7 +65,7 @@
 	if (sbdev == PCI_DEV_INVALID) {
 		/* Serial output is not yet working at this point, but
 		 * die() emits the POST code 0xff and halts the CPU, too. */
-		die("Southbridge not found.\r\n");
+		die("Southbridge not found.\n");
 	}
 
 	/* Enable Super-I/O (bit 0) and Super-I/O Configuration (bit 1). */
Index: src/southbridge/via/vt8235/vt8235_early_smbus.c
===================================================================
--- src/southbridge/via/vt8235/vt8235_early_smbus.c	(revision 3942)
+++ src/southbridge/via/vt8235/vt8235_early_smbus.c	(working copy)
@@ -36,7 +36,7 @@
 				PCI_DEVICE_ID_VIA_8235), 0);
 	
 	if (dev == PCI_DEV_INVALID) {
-		die("SMBUS controller not found\r\n");
+		die("SMBUS controller not found\n");
 	}		
 
 	// set IO base address to SMBUS_IO_BASE
@@ -91,7 +91,7 @@
 		while((c & 1) == 1) {
 			print_debug("c is ");
 			print_debug_hex8(c);
-			print_debug("\r\n");
+			print_debug("\n");
 			c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
 			/* nop */ 
 		}
@@ -110,7 +110,7 @@
 	smbus_wait_until_ready();
 	print_debug("After reset status ");
 	print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT));
-	print_debug("\r\n");
+	print_debug("\n");
 }
   
 
@@ -137,21 +137,21 @@
 
 	print_err("smbus_error: ");
 	print_err_hex8(host_status_register);
-	print_err("\r\n");
+	print_err("\n");
 	if (host_status_register & (1 << 4)) {
-		print_err("Interrup/SMI# was Failed Bus Transaction\r\n");
+		print_err("Interrup/SMI# was Failed Bus Transaction\n");
 	}
 	if (host_status_register & (1 << 3)) {
-		print_err("Bus Error\r\n");
+		print_err("Bus Error\n");
 	}
 	if (host_status_register & (1 << 2)) {
-		print_err("Device Error\r\n");
+		print_err("Device Error\n");
 	}
 	if (host_status_register & (1 << 1)) {
-		print_err("Interrupt/SMI# was Successful Completion\r\n");
+		print_err("Interrupt/SMI# was Successful Completion\n");
 	}
 	if (host_status_register & (1 << 0)) {
-		print_err("Host Busy\r\n");
+		print_err("Host Busy\n");
 	}
 }
 
Index: src/southbridge/amd/cs5535/cs5535_early_setup.c
===================================================================
--- src/southbridge/amd/cs5535/cs5535_early_setup.c	(revision 3942)
+++ src/southbridge/amd/cs5535/cs5535_early_setup.c	(working copy)
@@ -167,16 +167,16 @@
 		print_debug("reboot from BIOS reset\n\r");
 		return;
 	}
-	print_debug("Setup idsel\r\n");
+	print_debug("Setup idsel\n");
 	cs5535_setup_idsel();
-	print_debug("Setup iobase\r\n");
+	print_debug("Setup iobase\n");
 	cs5535_usb_swapsif();
 	cs5535_setup_iobase();
-	print_debug("Setup gpio\r\n");
+	print_debug("Setup gpio\n");
 	cs5535_setup_gpio();
-	print_debug("Setup cis_mode\r\n");
+	print_debug("Setup cis_mode\n");
 	cs5535_setup_cis_mode();
-	print_debug("Setup smbus\r\n");
+	print_debug("Setup smbus\n");
 	cs5535_enable_smbus();
 	dummy();
 }
Index: src/southbridge/amd/cs5536/cs5536_early_setup.c
===================================================================
--- src/southbridge/amd/cs5536/cs5536_early_setup.c	(revision 3942)
+++ src/southbridge/amd/cs5536/cs5536_early_setup.c	(working copy)
@@ -210,15 +210,15 @@
 		//print_debug("reboot from BIOS reset\n\r");
 		return;
 	}
-	//print_debug("Setup idsel\r\n");
+	//print_debug("Setup idsel\n");
 	cs5536_setup_idsel();
-	//print_debug("Setup iobase\r\n");
+	//print_debug("Setup iobase\n");
 	cs5536_usb_swapsif();
 	cs5536_setup_iobase();
-	//print_debug("Setup gpio\r\n");
+	//print_debug("Setup gpio\n");
 	cs5536_setup_gpio();
-	//print_debug("Setup smbus\r\n");
+	//print_debug("Setup smbus\n");
 	cs5536_enable_smbus();
-	//print_debug("Setup power button\r\n");
+	//print_debug("Setup power button\n");
 	cs5536_setup_power_button();
 }
Index: src/southbridge/amd/cs5536/cs5536_early_smbus.c
===================================================================
--- src/southbridge/amd/cs5536/cs5536_early_smbus.c	(revision 3942)
+++ src/southbridge/amd/cs5536/cs5536_early_smbus.c	(working copy)
@@ -199,7 +199,7 @@
 	print_debug_hex8(error);
 	print_debug(" device:");
 	print_debug_hex8(device);
-	print_debug("\r\n");
+	print_debug("\n");
 	/* stop, clean up the error, and leave */
 	smbus_stop_condition(smbus_io_base);
 	outb(inb(smbus_io_base + SMB_STS), smbus_io_base + SMB_STS);
Index: src/southbridge/amd/sb600/sb600_early_setup.c
===================================================================
--- src/southbridge/amd/sb600/sb600_early_setup.c	(revision 3942)
+++ src/southbridge/amd/sb600/sb600_early_setup.c	(working copy)
@@ -44,7 +44,7 @@
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
 
 	if (dev == PCI_DEV_INVALID) {
-		die("SMBUS controller not found\r\n");
+		die("SMBUS controller not found\n");
 		/* NOT REACHED */
 	}
 	return pci_read_config8(dev, 0x08);
@@ -286,10 +286,10 @@
 	dev = pci_locate_device(PCI_ID(0x1002, 0x4385), 0);
 
 	if (dev == PCI_DEV_INVALID) {
-		die("SMBUS controller not found\r\n");
+		die("SMBUS controller not found\n");
 		/* NOT REACHED */
 	}
-	printk_info("SMBus controller enabled, sb revision is 0x%x\r\n",
+	printk_info("SMBus controller enabled, sb revision is 0x%x\n",
 		    get_sb600_revision());
 
 	/* sbPorAtStartOfTblCfg */
Index: src/southbridge/amd/amd8111/amd8111_early_smbus.c
===================================================================
--- src/southbridge/amd/amd8111/amd8111_early_smbus.c	(revision 3942)
+++ src/southbridge/amd/amd8111/amd8111_early_smbus.c	(working copy)
@@ -9,7 +9,7 @@
 
 	dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0);
 	if (dev == PCI_DEV_INVALID) {
-		die("SMBUS controller not found\r\n");
+		die("SMBUS controller not found\n");
 	}
 
 	pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1);
@@ -23,7 +23,7 @@
 
 	/* clear any lingering errors, so the transaction will run */
 	outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
-	print_spew("SMBus controller enabled\r\n");
+	print_spew("SMBus controller enabled\n");
 }
 
 static int smbus_recv_byte(unsigned device)
Index: src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c
===================================================================
--- src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c	(revision 3942)
+++ src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c	(working copy)
@@ -13,10 +13,10 @@
 	dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201?
 
 	if (dev == PCI_DEV_INVALID) {
-		die("SMBUS controller not found\r\n");
+		die("SMBUS controller not found\n");
 	}
 	
-	print_debug("SMBus controller enabled\r\n");
+	print_debug("SMBus controller enabled\n");
 	/* set smbus iobase */
 	pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
 	/* Set smbus iospace enable */ 
Index: src/southbridge/broadcom/bcm5785/bcm5785_sata.c
===================================================================
--- src/southbridge/broadcom/bcm5785/bcm5785_sata.c	(revision 3942)
+++ src/southbridge/broadcom/bcm5785/bcm5785_sata.c	(working copy)
@@ -53,13 +53,13 @@
 		for(i=0; i<4; i++) {
 			mmio = base + 0x100 * i; 
 			byte = readb(mmio + 0x40);
-			printk_debug("port %d PHY status = %02x\r\n", i, byte);
+			printk_debug("port %d PHY status = %02x\n", i, byte);
 			if(byte & 0x4) {// bit 2 is set
 				byte = readb(mmio+0x48);
 				writeb(byte | 1, mmio + 0x48);
 				writeb(byte & (~1), mmio + 0x48);
 	                        byte = readb(mmio + 0x40);
-	                        printk_debug("after reset port %d PHY status = %02x\r\n", i, byte);
+	                        printk_debug("after reset port %d PHY status = %02x\n", i, byte);
 			}
 		}
 		
Index: src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
===================================================================
--- src/southbridge/broadcom/bcm5785/bcm5785_lpc.c	(revision 3942)
+++ src/southbridge/broadcom/bcm5785/bcm5785_lpc.c	(working copy)
@@ -77,7 +77,7 @@
 					if(!(res->flags & IORESOURCE_IO)) continue;
 		        	        base = res->base;
                 			end = resource_end(res);
-					printk_debug("bcm5785lpc decode:%s, base=0x%08x, end=0x%08x\r\n",dev_path(child),base, end);
+					printk_debug("bcm5785lpc decode:%s, base=0x%08x, end=0x%08x\n",dev_path(child),base, end);
 					switch(base) {
 					case 0x60: //KBC
 					case 0x64:
Index: src/southbridge/nvidia/ck804/ck804_early_smbus.c
===================================================================
--- src/southbridge/nvidia/ck804/ck804_early_smbus.c	(revision 3942)
+++ src/southbridge/nvidia/ck804/ck804_early_smbus.c	(working copy)
@@ -12,9 +12,9 @@
 	device_t dev;
 	dev = pci_locate_device(PCI_ID(0x10de, 0x0052), 0);
 	if (dev == PCI_DEV_INVALID)
-		die("SMBus controller not found\r\n");
+		die("SMBus controller not found\n");
 
-	print_debug("SMBus controller enabled\r\n");
+	print_debug("SMBus controller enabled\n");
 
 	/* Set SMBus I/O base. */
 	pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
Index: src/southbridge/nvidia/ck804/ck804_sata.c
===================================================================
--- src/southbridge/nvidia/ck804/ck804_sata.c	(revision 3942)
+++ src/southbridge/nvidia/ck804/ck804_sata.c	(working copy)
@@ -47,7 +47,7 @@
 		return;
 
 	dword = *(base + 0);
-	printk_debug("*(base+0)=%08x\r\n", dword);
+	printk_debug("*(base+0)=%08x\n", dword);
 	if (dword == 0x113) {
 		loop = 200000;	// 2
 		do {
@@ -56,11 +56,11 @@
 				break;
 			udelay(10);
 		} while (--loop > 0);
-		printk_debug("loop=%d, *(base+4)=%08x\r\n", loop, dword);
+		printk_debug("loop=%d, *(base+4)=%08x\n", loop, dword);
 	}
 
 	dword = *(base + 0x40);
-	printk_debug("*(base+0x40)=%08x\r\n", dword);
+	printk_debug("*(base+0x40)=%08x\n", dword);
 	if (dword == 0x113) {
 		loop = 200000;	//2
 		do {
@@ -69,7 +69,7 @@
 				break;
 			udelay(10);
 		} while (--loop > 0);
-		printk_debug("loop=%d, *(base+0x44)=%08x\r\n", loop, dword);
+		printk_debug("loop=%d, *(base+0x44)=%08x\n", loop, dword);
 	}
 }
 #endif
Index: src/southbridge/nvidia/ck804/ck804_lpc.c
===================================================================
--- src/southbridge/nvidia/ck804/ck804_lpc.c	(revision 3942)
+++ src/southbridge/nvidia/ck804/ck804_lpc.c	(working copy)
@@ -314,7 +314,7 @@
 						continue;
 					base = res->base;
 					end = resource_end(res);
-					printk_debug("ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\r\n", dev_path(child), base, end);
+					printk_debug("ck804 lpc decode:%s, base=0x%08lx, end=0x%08lx\n", dev_path(child), base, end);
 					switch (base) {
 					case 0x3f8:	// COM1
 						reg |= (1 << 0);
Index: src/southbridge/nvidia/mcp55/mcp55_early_smbus.c
===================================================================
--- src/southbridge/nvidia/mcp55/mcp55_early_smbus.c	(revision 3942)
+++ src/southbridge/nvidia/mcp55/mcp55_early_smbus.c	(working copy)
@@ -33,10 +33,10 @@
 	dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0);
 #if 0
 	if (dev == PCI_DEV_INVALID) {
-		die("SMBUS controller not found\r\n");
+		die("SMBUS controller not found\n");
 	}
 
-	print_debug("SMBus controller enabled\r\n");
+	print_debug("SMBus controller enabled\n");
 #endif
 	/* set smbus iobase */
 	pci_write_config32(dev, 0x20, SMBUS0_IO_BASE | 1);
Index: src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
===================================================================
--- src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c	(revision 3942)
+++ src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c	(working copy)
@@ -410,7 +410,7 @@
 	}
 
 out:
-	print_debug("mcp55_num:"); print_debug_hex8(mcp55_num); print_debug("\r\n");
+	print_debug("mcp55_num:"); print_debug_hex8(mcp55_num); print_debug("\n");
 
 	mcp55_early_set_port(mcp55_num, busn, devn, io_base);
 	mcp55_early_setup(mcp55_num, busn, devn, io_base, pci_e_x);
Index: src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
===================================================================
--- src/southbridge/intel/i82801ca/i82801ca_early_smbus.c	(revision 3942)
+++ src/southbridge/intel/i82801ca/i82801ca_early_smbus.c	(working copy)
@@ -5,7 +5,7 @@
 {
 	device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
 
-	print_debug("SMBus controller enabled\r\n");
+	print_debug("SMBus controller enabled\n");
 	/* set smbus iobase */
 	pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
 	/* Set smbus enable */
Index: src/southbridge/intel/esb6300/esb6300_early_smbus.c
===================================================================
--- src/southbridge/intel/esb6300/esb6300_early_smbus.c	(revision 3942)
+++ src/southbridge/intel/esb6300/esb6300_early_smbus.c	(working copy)
@@ -6,7 +6,7 @@
 {
 	device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
 
-	print_spew("SMBus controller enabled\r\n");
+	print_spew("SMBus controller enabled\n");
 	pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
 	pci_write_config8(dev, 0x40, 1);
 	pci_write_config8(dev, 0x4, 1);
@@ -92,7 +92,7 @@
 				SMBUS_IO_BASE + SMBHSTSTAT);
 	}
 
-	print_debug("SMBUS Block complete\r\n");
+	print_debug("SMBUS Block complete\n");
 	return 0;
 }
 
Index: src/southbridge/intel/i82801er/i82801er_watchdog.c
===================================================================
--- src/southbridge/intel/i82801er/i82801er_watchdog.c	(revision 3942)
+++ src/southbridge/intel/i82801er/i82801er_watchdog.c	(working copy)
@@ -23,6 +23,6 @@
         /* Clear TCO timeout status */
         outw(0x0008, base + 0x04);
         outw(0x0002, base + 0x06);
-        printk_debug("Watchdog ICH5 disabled\r\n");
+        printk_debug("Watchdog ICH5 disabled\n");
 }
 
Index: src/southbridge/intel/i82801er/i82801er_early_smbus.c
===================================================================
--- src/southbridge/intel/i82801er/i82801er_early_smbus.c	(revision 3942)
+++ src/southbridge/intel/i82801er/i82801er_early_smbus.c	(working copy)
@@ -6,7 +6,7 @@
 {
 	device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
 
-	print_spew("SMBus controller enabled\r\n");
+	print_spew("SMBus controller enabled\n");
 
 	pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
 	/* Set smbus enable */
@@ -34,7 +34,7 @@
 		return;
 	}
 	
-	print_debug("Unimplemented smbus_write_byte() called.\r\n");
+	print_debug("Unimplemented smbus_write_byte() called.\n");
 
 #if 0
 	/* setup transaction */
@@ -124,7 +124,7 @@
 				SMBUS_IO_BASE + SMBHSTSTAT);
 	}
 
-	print_debug("SMBUS Block complete\r\n");
+	print_debug("SMBUS Block complete\n");
 	return 0;
 }
 
Index: src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
===================================================================
--- src/southbridge/intel/i82371eb/i82371eb_early_smbus.c	(revision 3942)
+++ src/southbridge/intel/i82371eb/i82371eb_early_smbus.c	(working copy)
@@ -38,9 +38,9 @@
 				PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0);
 
 	if (dev == PCI_DEV_INVALID)
-		die("SMBus controller not found\r\n");
+		die("SMBus controller not found\n");
 
-	print_spew("SMBus controller enabled\r\n");
+	print_spew("SMBus controller enabled\n");
 
 	/* Set the SMBus I/O base. */
 	pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1);
Index: src/southbridge/intel/i82801gx/i82801gx_early_smbus.c
===================================================================
--- src/southbridge/intel/i82801gx/i82801gx_early_smbus.c	(revision 3942)
+++ src/southbridge/intel/i82801gx/i82801gx_early_smbus.c	(working copy)
@@ -49,7 +49,7 @@
 
 	/* Clear any lingering errors, so transactions can run. */
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-	print_debug("SMBus controller enabled.\r\n");
+	print_debug("SMBus controller enabled.\n");
 }
 
 static inline int smbus_read_byte(unsigned device, unsigned address)
Index: src/southbridge/intel/i82801gx/i82801gx_watchdog.c
===================================================================
--- src/southbridge/intel/i82801gx/i82801gx_watchdog.c	(revision 3942)
+++ src/southbridge/intel/i82801gx/i82801gx_watchdog.c	(working copy)
@@ -48,5 +48,5 @@
 	outw(0x0008, base + 0x04);
 	outw(0x0002, base + 0x06);
 
-	printk_debug("ICH7 watchdog disabled\r\n");
+	printk_debug("ICH7 watchdog disabled\n");
 }
Index: src/southbridge/intel/i82801xx/i82801xx_early_smbus.c
===================================================================
--- src/southbridge/intel/i82801xx/i82801xx_early_smbus.c	(revision 3942)
+++ src/southbridge/intel/i82801xx/i82801xx_early_smbus.c	(working copy)
@@ -58,7 +58,7 @@
 	/* Clear any lingering errors, so transactions can run. */
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
 
-	print_debug("SMBus controller enabled\r\n");
+	print_debug("SMBus controller enabled\n");
 }
 
 static inline int smbus_read_byte(unsigned device, unsigned address)
@@ -69,7 +69,7 @@
 static void smbus_write_byte(unsigned device, unsigned address,
 			     unsigned char val)
 {
-	print_err("Unimplemented smbus_write_byte() called\r\n");
+	print_err("Unimplemented smbus_write_byte() called\n");
 	return;
 }
 
Index: src/southbridge/intel/i82801xx/i82801xx_watchdog.c
===================================================================
--- src/southbridge/intel/i82801xx/i82801xx_watchdog.c	(revision 3942)
+++ src/southbridge/intel/i82801xx/i82801xx_watchdog.c	(working copy)
@@ -50,5 +50,5 @@
 	outw(0x0008, base + 0x04);
 	outw(0x0002, base + 0x06);
 
-	printk_debug("ICH Watchdog disabled\r\n");
+	printk_debug("ICH Watchdog disabled\n");
 }
Index: src/southbridge/intel/i3100/i3100_early_smbus.c
===================================================================
--- src/southbridge/intel/i3100/i3100_early_smbus.c	(revision 3942)
+++ src/southbridge/intel/i3100/i3100_early_smbus.c	(working copy)
@@ -26,7 +26,7 @@
 {
 	device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
 
-	print_spew("SMBus controller enabled\r\n");
+	print_spew("SMBus controller enabled\n");
 	pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
 	pci_write_config8(dev, 0x40, 1);
 	pci_write_config8(dev, 0x4, 1);
Index: src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c
===================================================================
--- src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c	(revision 3942)
+++ src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c	(working copy)
@@ -23,7 +23,7 @@
 {
 	device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
 
-	print_debug("SMBus controller enabled\r\n");
+	print_debug("SMBus controller enabled\n");
 	/* set smbus iobase */
 	pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
 	/* Set smbus enable */
@@ -101,7 +101,7 @@
 	unsigned char global_status_register;
 	unsigned char byte;
 
-	/*print_err("smbus_read_byte\r\n");*/
+	/*print_err("smbus_read_byte\n");*/
 	if (smbus_wait_until_ready() < 0) {
 		print_err_hex8(-2);
 		return -2;
@@ -149,7 +149,7 @@
 /*
         print_err("smbus_read_byte: ");
 	print_err_hex32(device); print_err(" ad "); print_err_hex32(address);
-	print_err("value "); print_err_hex8(byte); print_err("\r\n");
+	print_err("value "); print_err_hex8(byte); print_err("\n");
  */
 	return byte;
 }
Index: src/southbridge/sis/sis966/sis966_aza.c
===================================================================
--- src/southbridge/sis/sis966/sis966_aza.c	(revision 3942)
+++ src/southbridge/sis/sis966/sis966_aza.c	(working copy)
@@ -277,14 +277,14 @@
 
         for(i=0;i<0xff;i+=4){
                 if((i%16)==0){
-                        print_debug("\r\n");
+                        print_debug("\n");
                         print_debug_hex8(i);
                         print_debug(": ");
                 }
                 print_debug_hex32(pci_read_config32(dev,i));
                 print_debug("  ");
         }
-        print_debug("\r\n");
+        print_debug("\n");
 }
 #endif
 
Index: src/southbridge/sis/sis966/sis966_usb2.c
===================================================================
--- src/southbridge/sis/sis966/sis966_usb2.c	(revision 3942)
+++ src/southbridge/sis/sis966/sis966_usb2.c	(working copy)
@@ -108,14 +108,14 @@
 
         for(i=0;i<0xff;i+=4){
                 if((i%16)==0){
-                        print_debug("\r\n");
+                        print_debug("\n");
                         print_debug_hex8(i);
                         print_debug(": ");
                 }
                 print_debug_hex32(pci_read_config32(dev,i));
                 print_debug("  ");
         }
-        print_debug("\r\n");
+        print_debug("\n");
 }
 #endif
         print_debug("USB 2.0 INIT:<----------\n");
Index: src/southbridge/sis/sis966/sis966_sata.c
===================================================================
--- src/southbridge/sis/sis966/sis966_sata.c	(revision 3942)
+++ src/southbridge/sis/sis966/sis966_sata.c	(working copy)
@@ -156,14 +156,14 @@
 
         for(i=0;i<0xff;i+=4){
                 if((i%16)==0){
-                        print_debug("\r\n");
+                        print_debug("\n");
                         print_debug_hex8(i);
                         print_debug(": ");
                 }
                 print_debug_hex32(pci_read_config32(dev,i));
                 print_debug("  ");
         }
-        print_debug("\r\n");
+        print_debug("\n");
 }
 #endif
 
Index: src/southbridge/sis/sis966/sis966_usb.c
===================================================================
--- src/southbridge/sis/sis966/sis966_usb.c	(revision 3942)
+++ src/southbridge/sis/sis966/sis966_usb.c	(working copy)
@@ -81,14 +81,14 @@
 
         for(i=0;i<0xff;i+=4){
                 if((i%16)==0){
-                        print_debug("\r\n");
+                        print_debug("\n");
                         print_debug_hex8(i);
                         print_debug(": ");
                 }
                 print_debug_hex32(pci_read_config32(dev,i));
                 print_debug("  ");
         }
-        print_debug("\r\n");
+        print_debug("\n");
 }
 #endif
         print_debug("USB 1.1 INIT:<----------\n");
Index: src/southbridge/sis/sis966/sis966_ide.c
===================================================================
--- src/southbridge/sis/sis966/sis966_ide.c	(revision 3942)
+++ src/southbridge/sis/sis966/sis966_ide.c	(working copy)
@@ -156,14 +156,14 @@
 
         for(i=0;i<0xff;i+=4){
                 if((i%16)==0){
-                        print_debug("\r\n");
+                        print_debug("\n");
                         print_debug_hex8(i);
                         print_debug(": ");
                 }
                 print_debug_hex32(pci_read_config32(dev,i));
                 print_debug("  ");
         }
-        print_debug("\r\n");
+        print_debug("\n");
 }
 #endif
 print_debug("IDE_INIT:<----------\n");
Index: src/southbridge/sis/sis966/sis966_nic.c
===================================================================
--- src/southbridge/sis/sis966/sis966_nic.c	(revision 3942)
+++ src/southbridge/sis/sis966/sis966_nic.c	(working copy)
@@ -270,7 +270,7 @@
 
 	if(!res)
 	{
-		printk_debug("NIC Cannot find resource..\r\n");
+		printk_debug("NIC Cannot find resource..\n");
 		return;
 	}
 	base = res->base;
@@ -278,7 +278,7 @@
 
 	if(!(val=phy_detect(base,&PhyAddr)))
 	{
-	       printk_debug("PHY detect fail !!!!\r\n");
+	       printk_debug("PHY detect fail !!!!\n");
 		return;
 	}
 
@@ -321,14 +321,14 @@
 
         for(i=0;i<0xff;i+=4){
                 if((i%16)==0){
-                        print_debug("\r\n");
+                        print_debug("\n");
                         print_debug_hex8(i);
                         print_debug(": ");
                 }
                 print_debug_hex32(pci_read_config32(dev,i));
                 print_debug("  ");
         }
-        print_debug("\r\n");
+        print_debug("\n");
 }
 
 
Index: src/ram/ramtest.c
===================================================================
--- src/ram/ramtest.c	(revision 3942)
+++ src/ram/ramtest.c	(working copy)
@@ -30,13 +30,13 @@
 	 * Fill.
 	 */
 #if CONFIG_USE_PRINTK_IN_CAR
-	printk_debug("DRAM fill: 0x%08x-0x%08x\r\n", start, stop);
+	printk_debug("DRAM fill: 0x%08x-0x%08x\n", start, stop);
 #else
 	print_debug("DRAM fill: ");
 	print_debug_hex32(start);
 	print_debug("-");
 	print_debug_hex32(stop);
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 	for(addr = start; addr < stop ; addr += 4) {
 		/* Display address being filled */
@@ -52,10 +52,10 @@
 	};
 	/* Display final address */
 #if CONFIG_USE_PRINTK_IN_CAR
-	printk_debug("%08x\r\nDRAM filled\r\n", addr);
+	printk_debug("%08x\nDRAM filled\n", addr);
 #else
 	print_debug_hex32(addr);
-	print_debug("\r\nDRAM filled\r\n");
+	print_debug("\nDRAM filled\n");
 #endif
 }
 
@@ -67,13 +67,13 @@
 	 * Verify.
 	 */
 #if CONFIG_USE_PRINTK_IN_CAR
-	printk_debug("DRAM verify: 0x%08x-0x%08x\r\n", start, stop);
+	printk_debug("DRAM verify: 0x%08x-0x%08x\n", start, stop);
 #else
 	print_debug("DRAM verify: ");
 	print_debug_hex32(start);
 	print_debug_char('-');
 	print_debug_hex32(stop);
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 	for(addr = start; addr < stop ; addr += 4) {
 		unsigned long value;
@@ -90,13 +90,13 @@
 		if (value != addr) {
 			/* Display address with error */
 #if CONFIG_USE_PRINTK_IN_CAR
-			printk_err("Fail: @0x%08x Read value=0x%08x\r\n", addr, value);
+			printk_err("Fail: @0x%08x Read value=0x%08x\n", addr, value);
 #else
 			print_err("Fail: @0x");
 			print_err_hex32(addr);
 			print_err(" Read value=0x");
 			print_err_hex32(value);
-			print_err("\r\n");
+			print_err("\n");
 #endif
 			i++;
 			if(i>256) {
@@ -118,17 +118,17 @@
 
 	if (i) {
 #if CONFIG_USE_PRINTK_IN_CAR
-		printk_debug("\r\nDRAM did _NOT_ verify!\r\n");
+		printk_debug("\nDRAM did _NOT_ verify!\n");
 #else
-		print_debug("\r\nDRAM did _NOT_ verify!\r\n");
+		print_debug("\nDRAM did _NOT_ verify!\n");
 #endif
 		die("DRAM ERROR");
 	}
 	else {
 #if CONFIG_USE_PRINTK_IN_CAR
-		printk_debug("\r\nDRAM range verified.\r\n");
+		printk_debug("\nDRAM range verified.\n");
 #else
-		print_debug("\r\nDRAM range verified.\r\n");
+		print_debug("\nDRAM range verified.\n");
 #endif
 	}
 }
@@ -142,20 +142,20 @@
 	 * are tested.   -Tyson
 	 */
 #if CONFIG_USE_PRINTK_IN_CAR
-	printk_debug("Testing DRAM : %08x - %08x\r\n", start, stop);
+	printk_debug("Testing DRAM : %08x - %08x\n", start, stop);
 #else
 	print_debug("Testing DRAM : ");
 	print_debug_hex32(start);
 	print_debug("-");	
 	print_debug_hex32(stop);
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 	ram_fill(start, stop);
 	ram_verify(start, stop);
 #if CONFIG_USE_PRINTK_IN_CAR
-	printk_debug("Done.\r\n");
+	printk_debug("Done.\n");
 #else
-	print_debug("Done.\r\n");
+	print_debug("Done.\n");
 #endif
 }
 
Index: src/superio/winbond/w83627ehg/superio.c
===================================================================
--- src/superio/winbond/w83627ehg/superio.c	(revision 3942)
+++ src/superio/winbond/w83627ehg/superio.c	(working copy)
@@ -99,7 +99,7 @@
 		value = pnp_read_index(base, reg);
 		value &= 0xff & (~(hwm_reg_values[i + 1]));
 		value |= 0xff & hwm_reg_values[i + 2];
-		// printk_debug("base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value);
+		// printk_debug("base = 0x%04x, reg = 0x%02x, value = 0x%02x\n", base, reg,value);
 		pnp_write_index(base, reg, value);
 	}
 }
Index: src/superio/winbond/w83627hf/superio.c
===================================================================
--- src/superio/winbond/w83627hf/superio.c	(revision 3942)
+++ src/superio/winbond/w83627hf/superio.c	(working copy)
@@ -90,7 +90,7 @@
 		value &= 0xff & hwm_reg_values[i+1];
 		value |= 0xff & hwm_reg_values[i+2];
 #if 0
-		printk_debug("base = 0x%04x, reg = 0x%02x, value = 0x%02x\r\n", base, reg,value);
+		printk_debug("base = 0x%04x, reg = 0x%02x, value = 0x%02x\n", base, reg,value);
 #endif
 		pnp_write_index(base, reg, value);
 	}
Index: src/superio/ite/it8716f/superio.c
===================================================================
--- src/superio/ite/it8716f/superio.c	(revision 3942)
+++ src/superio/ite/it8716f/superio.c	(working copy)
@@ -72,13 +72,13 @@
 
 	/* Read out current value of FAN_CTL control register (0x14). */
 	value = pnp_read_index(base, 0x14);
-	printk_debug("FAN_CTL: reg = 0x%04x, read value = 0x%02x\r\n",
+	printk_debug("FAN_CTL: reg = 0x%04x, read value = 0x%02x\n",
 		     base + 0x14, value);
 
 	/* Set FAN_CTL control register (0x14) polarity to high, and
 	   activate fans 1, 2 and 3. */
 	pnp_write_index(base, 0x14, value | 0x87);
-	printk_debug("FAN_CTL: reg = 0x%04x, writing value = 0x%02x\r\n",
+	printk_debug("FAN_CTL: reg = 0x%04x, writing value = 0x%02x\n",
 		     base + 0x14, value | 0x87);
 }
 #endif
Index: src/superio/smsc/lpc47m10x/superio.c
===================================================================
--- src/superio/smsc/lpc47m10x/superio.c	(revision 3942)
+++ src/superio/smsc/lpc47m10x/superio.c	(working copy)
@@ -195,7 +195,7 @@
 static void dump_pnp_device(device_t dev)
 {
     int register_index;
-    print_debug("\r\n");
+    print_debug("\n");
 
     for(register_index = 0; register_index <= LPC47M10X2_MAX_CONFIG_REGISTER; register_index++) {
         uint8_t register_value;
@@ -214,10 +214,10 @@
         print_debug_char(' ');
         print_debug_hex8(register_value);
         if ((register_index & 0x0f) == 0x0f) {
-        	print_debug("\r\n");
+        	print_debug("\n");
         }
     }
 
-   	print_debug("\r\n");
+   	print_debug("\n");
 }
 #endif
Index: src/superio/smsc/lpc47n217/superio.c
===================================================================
--- src/superio/smsc/lpc47n217/superio.c	(revision 3942)
+++ src/superio/smsc/lpc47n217/superio.c	(working copy)
@@ -360,7 +360,7 @@
 static void dump_pnp_device(device_t dev)
 {
     int register_index;
-    print_debug("\r\n");
+    print_debug("\n");
 
     for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) {
         uint8_t register_value;
@@ -379,10 +379,10 @@
         print_debug_char(' ');
         print_debug_hex8(register_value);
         if ((register_index & 0x0f) == 0x0f) {
-        	print_debug("\r\n");
+        	print_debug("\n");
         }
     }
 
-   	print_debug("\r\n");
+   	print_debug("\n");
 }
 #endif
Index: src/superio/smsc/lpc47b272/superio.c
===================================================================
--- src/superio/smsc/lpc47b272/superio.c	(revision 3942)
+++ src/superio/smsc/lpc47b272/superio.c	(working copy)
@@ -197,7 +197,7 @@
 static void dump_pnp_device(device_t dev)
 {
     int register_index;
-    print_debug("\r\n");
+    print_debug("\n");
 
     for(register_index = 0; register_index <= LPC47B272_MAX_CONFIG_REGISTER; register_index++) {
         uint8_t register_value;
@@ -216,10 +216,10 @@
         print_debug_char(' ');
         print_debug_hex8(register_value);
         if ((register_index & 0x0f) == 0x0f) {
-        	print_debug("\r\n");
+        	print_debug("\n");
         }
     }
 
-   	print_debug("\r\n");
+   	print_debug("\n");
 }
 #endif
Index: src/superio/smsc/lpc47b397/superio.c
===================================================================
--- src/superio/smsc/lpc47b397/superio.c	(revision 3942)
+++ src/superio/smsc/lpc47b397/superio.c	(working copy)
@@ -98,7 +98,7 @@
 
 	switch(dev->path.u.pnp.device) {
 	case LPC47B397_HWM:
-		printk_debug("lpc47b397 SensorBus Register Access enabled\r\n");
+		printk_debug("lpc47b397 SensorBus Register Access enabled\n");
 		pnp_set_logical_device(dev);
 		enable_hwm_smbus(dev);
 		break;
Index: src/cpu/amd/model_fxx/fidvid.c
===================================================================
--- src/cpu/amd/model_fxx/fidvid.c	(revision 3942)
+++ src/cpu/amd/model_fxx/fidvid.c	(working copy)
@@ -16,9 +16,9 @@
 {
 #if K8_SET_FIDVID_DEBUG == 1
 	#if CONFIG_USE_PRINTK_IN_CAR
-		printk_debug("%s%x\r\n", str, val);
+		printk_debug("%s%x\n", str, val);
 	#else
-		print_debug(str); print_debug_hex32(val); print_debug("\r\n");
+		print_debug(str); print_debug_hex32(val); print_debug("\n");
 	#endif
 #endif
 }
@@ -27,9 +27,9 @@
 {
 #if K8_SET_FIDVID_DEBUG == 1
 	#if CONFIG_USE_PRINTK_IN_CAR
-		printk_debug("%s%02x\r\n", str, val);
+		printk_debug("%s%02x\n", str, val);
 	#else
-		print_debug(str); print_debug_hex8(val); print_debug("\r\n");
+		print_debug(str); print_debug_hex8(val); print_debug("\n");
 	#endif
 #endif
 }
@@ -38,9 +38,9 @@
 {
 #if K8_SET_FIDVID_DEBUG == 1
 	#if CONFIG_USE_PRINTK_IN_CAR
-		printk_debug("%s%x%x\r\n", str, val, val2);
+		printk_debug("%s%x%x\n", str, val, val2);
 	#else
-		print_debug(str); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\r\n");
+		print_debug(str); print_debug_hex32(val); print_debug_hex32(val2); print_debug("\n");
 	#endif
 #endif
 }
@@ -140,9 +140,9 @@
 
 	if (apicid != apicidx) {
 #if CONFIG_USE_PRINTK_IN_CAR
-		printk_err("wrong apicid, we want change %x, but it is %x\r\n", apicid, apicidx);
+		printk_err("wrong apicid, we want change %x, but it is %x\n", apicid, apicidx);
 #else
-		print_err("wrong apicid, we want change "); print_err_hex8(apicid); print_err(" but it is "); print_err_hex8(apicidx); print_err("\r\n");
+		print_err("wrong apicid, we want change "); print_err_hex8(apicid); print_err(" but it is "); print_err_hex8(apicidx); print_err("\n");
 #endif
 		return fidvid;
 	}
@@ -340,10 +340,10 @@
 
 	if (showmessage) {
 		if (vid_new != vid_cur) {
-			print_err("set vid failed for apicid ="); print_err_hex8(apicidx);  print_err("\r\n");
+			print_err("set vid failed for apicid ="); print_err_hex8(apicidx);  print_err("\n");
 		}
 		if (fid_new != fid_cur) {
-			print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\r\n");
+			print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\n");
 		}
 	}
 
Index: src/cpu/amd/model_fxx/init_cpus.c
===================================================================
--- src/cpu/amd/model_fxx/init_cpus.c	(revision 3942)
+++ src/cpu/amd/model_fxx/init_cpus.c	(working copy)
@@ -17,9 +17,9 @@
 static inline void print_initcpu8 (const char *strval, unsigned val)
 {
 #if CONFIG_USE_PRINTK_IN_CAR
-        printk_debug("%s%02x\r\n", strval, val);
+        printk_debug("%s%02x\n", strval, val);
 #else
-        print_debug(strval); print_debug_hex8(val); print_debug("\r\n");
+        print_debug(strval); print_debug_hex8(val); print_debug("\n");
 #endif
 }
 
@@ -36,18 +36,18 @@
 static inline void print_initcpu16 (const char *strval, unsigned val)
 {
 #if CONFIG_USE_PRINTK_IN_CAR
-        printk_debug("%s%04x\r\n", strval, val);
+        printk_debug("%s%04x\n", strval, val);
 #else
-        print_debug(strval); print_debug_hex16(val); print_debug("\r\n");
+        print_debug(strval); print_debug_hex16(val); print_debug("\n");
 #endif
 }
 
 static inline void print_initcpu(const char *strval, unsigned val)
 {
 #if CONFIG_USE_PRINTK_IN_CAR
-        printk_debug("%s%08x\r\n", strval, val);
+        printk_debug("%s%08x\n", strval, val);
 #else
-        print_debug(strval); print_debug_hex32(val); print_debug("\r\n");
+        print_debug(strval); print_debug_hex32(val); print_debug("\n");
 #endif
 }
 
@@ -172,12 +172,12 @@
 static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id, const char *str)
 {
 	#if CONFIG_USE_PRINTK_IN_CAR
-                printk_debug("%s --- {  APICID = %02x NODEID = %02x COREID = %02x} ---\r\n", str, apicid, id.nodeid, id.coreid);
+                printk_debug("%s --- {  APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, apicid, id.nodeid, id.coreid);
 	#else
 		print_debug(str);
         	print_debug(" ---- {APICID = "); print_debug_hex8(apicid);
 		print_debug(" NODEID = "), print_debug_hex8(id.nodeid); print_debug(" COREID = "), print_debug_hex8(id.coreid);
-	        print_debug("} --- \r\n");
+	        print_debug("} --- \n");
         #endif
 }
 
@@ -224,7 +224,7 @@
 {
         print_debug("started ap apicid: ");
         for_each_ap(bsp_apicid, 2 , wait_ap_started, (void *)0);
-        print_debug("\r\n");
+        print_debug("\n");
 }
 
 static void allow_all_aps_stop(unsigned bsp_apicid)
@@ -314,8 +314,8 @@
 #endif
 
                 if (cpu_init_detectedx) {
-                        print_apicid_nodeid_coreid(apicid, id, "\r\n\r\n\r\nINIT detected from ");
-                        print_debug("\r\nIssuing SOFT_RESET...\r\n");
+                        print_apicid_nodeid_coreid(apicid, id, "\n\n\nINIT detected from ");
+                        print_debug("\nIssuing SOFT_RESET...\n");
                         soft_reset();
                 }
 
@@ -378,7 +378,7 @@
                 while(!is_core0_started(i)) {}
                 print_initcpu8_nocr(" ", i);
         }
-        print_debug("\r\n");
+        print_debug("\n");
 
 }
 
Index: src/cpu/amd/sc520/raminit.c
===================================================================
--- src/cpu/amd/sc520/raminit.c	(revision 3942)
+++ src/cpu/amd/sc520/raminit.c	(working copy)
@@ -248,14 +248,14 @@
 
 
 static void dumpram(void){
-  print_err("ctl "); print_err_hex8(*drcctl); print_err("\r\n");
-  print_err("mctl "); print_err_hex8(*drcmctl); print_err("\r\n");
-  print_err("cfg "); print_err_hex8(*drccfg); print_err("\r\n");
+  print_err("ctl "); print_err_hex8(*drcctl); print_err("\n");
+  print_err("mctl "); print_err_hex8(*drcmctl); print_err("\n");
+  print_err("cfg "); print_err_hex8(*drccfg); print_err("\n");
 
-  print_err("bendadr0 "); print_err_hex8(*drcbendadr); print_err("\r\n");
-  print_err("bendadr1 "); print_err_hex8(*drcbendadr); print_err("\r\n");
-  print_err("bendadr2 "); print_err_hex8(*drcbendadr); print_err("\r\n");
-  print_err("bendadr3"); print_err_hex8(*drcbendadr); print_err("\r\n");
+  print_err("bendadr0 "); print_err_hex8(*drcbendadr); print_err("\n");
+  print_err("bendadr1 "); print_err_hex8(*drcbendadr); print_err("\n");
+  print_err("bendadr2 "); print_err_hex8(*drcbendadr); print_err("\n");
+  print_err("bendadr3"); print_err_hex8(*drcbendadr); print_err("\n");
 }
 
 /* there is a lot of silliness in the amd code, and it is 
@@ -311,11 +311,11 @@
 	print_err("NOP\n");
 	/* 100? 200? */
 	udelay(100);
-	print_err("after sc520_udelay\r\n");
+	print_err("after sc520_udelay\n");
 
 	/* issue all banks precharge */
 	*drcctl=0x02;
-	print_err("set *drcctl to 2 \r\n");
+	print_err("set *drcctl to 2 \n");
 	dummy_write();
 	print_err("PRE\n");
 
@@ -334,7 +334,7 @@
 	*drcctl=0x04;
 	for (i=0; i<8; i++) /* refresh 8 times */{
 		dummy_write();
-		print_err("dummy write\r\n");
+		print_err("dummy write\n");
 	}
 	print_err("8 dummy writes\n");
 
@@ -342,18 +342,18 @@
 	*drcctl=0x00;
 	print_err("normal\n");
 
-	print_err("HI done normal\r\n");
+	print_err("HI done normal\n");
 
 	print_err("sizemem\n");
 	for(bank = 3; bank >= 0; bank--) {
-	  print_err("Try to assign to l\r\n");
+	  print_err("Try to assign to l\n");
 	  *lp = 0xdeadbeef;
-	  print_err("assigned l ... \r\n");
+	  print_err("assigned l ... \n");
 	  if (*lp != 0xdeadbeef) {
 	    print_err(" no memory at bank "); 
 	    // print_err_hex8(bank); 
 	    //   print_err(" value "); print_err_hex32(*lp);
-	    print_err("\r\n"); 
+	    print_err("\n"); 
 	    //	    continue;
 	  }
 	  *drcctl = 2;
@@ -362,7 +362,7 @@
 	  l = *drcbendadr;
 	  l >>= 8; 
 	  *drcbendadr = l;
-	  print_err("loop around\r\n");
+	  print_err("loop around\n");
 	  *drcctl = 0;
 	  dummy_write();
 	}
@@ -386,11 +386,11 @@
 	print_err("NOP\n");
 	/* 100? 200? */
 	//sc520_udelay(100);
-	print_err("after sc520_udelay\r\n");
+	print_err("after sc520_udelay\n");
 
 	/* issue all banks precharge */
 	*drcctl=0x02;
-	print_err("set *drcctl to 2 \r\n");
+	print_err("set *drcctl to 2 \n");
 	dummy_write();
 	print_err("PRE\n");
 
@@ -409,7 +409,7 @@
 	*drcctl=0x04;
 	for (i=0; i<8; i++) /* refresh 8 times */{
 		dummy_write();
-		print_err("dummy write\r\n");
+		print_err("dummy write\n");
 	}
 	print_err("8 dummy writes\n");
 
@@ -417,7 +417,7 @@
 	*drcctl=0x00;
 	print_err("normal\n");
 
-	print_err("HI done normal\r\n");
+	print_err("HI done normal\n");
 	bank = 3;
 
 
@@ -558,7 +558,7 @@
 	al -= i&3;
 	*drcbendaddr = rows >> al;
 	print_err("computed ending_adr = "); print_err_hex8(ending_adr); 
-	print_err("\r\n");
+	print_err("\n");
 	
 */
 bad_reinit:
@@ -592,7 +592,7 @@
 	return bank;
 	
 bad_ram:
-	print_info("bad ram!\r\n");
+	print_info("bad ram!\n");
 	/* you are here because the read-after-write failed, 
 	 * in most cases because: no ram in that bank! 
 	 * set badbank to 1 and go to reinit
@@ -600,7 +600,7 @@
 	ending_adr = 0;
 	goto bad_reinit;
 	while(1)
-	print_err("DONE NEXTBANK\r\n");
+	print_err("DONE NEXTBANK\n");
 #endif
 }	
 
@@ -628,27 +628,27 @@
 	/* two autorefreshes */
 	*drcctl = 4;
 	*zero = 0;
-	print_debug("one zero out on refresh\r\n");
+	print_debug("one zero out on refresh\n");
 	*zero = 0;
-	print_debug("two zero out on refresh\r\n");
+	print_debug("two zero out on refresh\n");
 
 	/* load mode register */
 	*drcctl = 3;
 	*zero = 0;
-	print_debug("DONE the load mode reg\r\n");
+	print_debug("DONE the load mode reg\n");
 	
 	/* normal mode */
 	*drcctl = 0x0;
 	*zero = 0;
-	print_debug("DONE one last write and then turn on refresh etc\r\n");
+	print_debug("DONE one last write and then turn on refresh etc\n");
 	*drcctl = 0x18;
 	*zero = 0;
-	print_debug("DONE the normal\r\n");
+	print_debug("DONE the normal\n");
 	*zero = 0xdeadbeef;
 	if (*zero != 0xdeadbeef) 
-	  print_debug("NO LUCK\r\n");
+	  print_debug("NO LUCK\n");
 	else
-	  print_debug("did a store and load ...\r\n");
+	  print_debug("did a store and load ...\n");
 	//print_err_hex32(*zero);
-	//	print_err(" zero is now "); print_err_hex32(*zero); print_err("\r\n");
+	//	print_err(" zero is now "); print_err_hex32(*zero); print_err("\n");
 }
Index: src/cpu/amd/dualcore/amd_sibling.c
===================================================================
--- src/cpu/amd/dualcore/amd_sibling.c	(revision 3942)
+++ src/cpu/amd/dualcore/amd_sibling.c	(working copy)
@@ -113,7 +113,7 @@
 
 	if((apicid_base+ioapic_num-1)>0xf) {
 		// We need to enable APIC EXT ID
-		printk_info("if the IO APIC device doesn't support 256 apic id, \r\n you need to set ENABLE_APIC_EXT_ID in auto.c so you can spare 16 id for ioapic\r\n");
+		printk_info("if the IO APIC device doesn't support 256 apic id, \n you need to set ENABLE_APIC_EXT_ID in auto.c so you can spare 16 id for ioapic\n");
 		enable_apic_ext_id(nodes);
 	}
 	
Index: src/cpu/amd/quadcore/amd_sibling.c
===================================================================
--- src/cpu/amd/quadcore/amd_sibling.c	(revision 3942)
+++ src/cpu/amd/quadcore/amd_sibling.c	(working copy)
@@ -114,7 +114,7 @@
 
 	if((apicid_base+ioapic_num-1)>0xf) {
 		// We need to enable APIC EXT ID
-		printk_spew("if the IO APIC device doesn't support 256 apic id, \r\n you need to set ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n");
+		printk_spew("if the IO APIC device doesn't support 256 apic id, \n you need to set ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\n");
 		enable_apic_ext_id(sysconf.nodes);
 	}
 
Index: src/cpu/amd/model_lx/cpureginit.c
===================================================================
--- src/cpu/amd/model_lx/cpureginit.c	(revision 3942)
+++ src/cpu/amd/model_lx/cpureginit.c	(working copy)
@@ -209,9 +209,9 @@
 	print_debug_hex32(msr.hi);
 	print_debug(" and lo ");
 	print_debug_hex32(msr.lo);
-	print_debug("\r\n");
+	print_debug("\n");
 	wrmsr(GLCP_DELAY_CONTROLS, msr);
-	print_debug("SetDelayControl done\r\n");
+	print_debug("SetDelayControl done\n");
 	return;
 }
 
@@ -225,7 +225,7 @@
 
 	/* Castle 2.0 BTM periodic sync period. */
 	/*      [40:37] 1 sync record per 256 bytes */
-	print_debug("Castle 2.0 BTM periodic sync period.\r\n");
+	print_debug("Castle 2.0 BTM periodic sync period.\n");
 	msrnum = CPU_PF_CONF;
 	msr = rdmsr(msrnum);
 	msr.hi |= (0x8 << 5);
@@ -235,7 +235,7 @@
 	 * LX performance setting.
 	 * Enable Quack for fewer re-RAS on the MC
 	 */
-	print_debug("Enable Quack for fewer re-RAS on the MC\r\n");
+	print_debug("Enable Quack for fewer re-RAS on the MC\n");
 	msrnum = GLIU0_ARB;
 	msr = rdmsr(msrnum);
 	msr.hi &= ~ARB_UPPER_DACK_EN_SET;
@@ -251,25 +251,25 @@
 	/* GLIU port active enable, limit south pole masters 
 	 * (AES and PCI) to one outstanding transaction. 
 	 */
-	print_debug(" GLIU port active enable\r\n");
+	print_debug(" GLIU port active enable\n");
 	msrnum = GLIU1_PORT_ACTIVE;
 	msr = rdmsr(msrnum);
 	msr.lo &= ~0x880;
 	wrmsr(msrnum, msr);
 
 	/* Set the Delay Control in GLCP */
-	print_debug("Set the Delay Control in GLCP\r\n");
+	print_debug("Set the Delay Control in GLCP\n");
 	SetDelayControl();
 
 	/*  Enable RSDC */
-	print_debug("Enable RSDC\r\n");
+	print_debug("Enable RSDC\n");
 	msrnum = CPU_AC_SMM_CTL;
 	msr = rdmsr(msrnum);
 	msr.lo |= SMM_INST_EN_SET;
 	wrmsr(msrnum, msr);
 
 	/* FPU imprecise exceptions bit */
-	print_debug("FPU imprecise exceptions bit\r\n");
+	print_debug("FPU imprecise exceptions bit\n");
 	msrnum = CPU_FPU_MSR_MODE;
 	msr = rdmsr(msrnum);
 	msr.lo |= FPU_IE_SET;
@@ -277,14 +277,14 @@
 
 	/* Power Savers (Do after BIST) */
 	/* Enable Suspend on HLT & PAUSE instructions */
-	print_debug("Enable Suspend on HLT & PAUSE instructions\r\n");
+	print_debug("Enable Suspend on HLT & PAUSE instructions\n");
 	msrnum = CPU_XC_CONFIG;
 	msr = rdmsr(msrnum);
 	msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE;
 	wrmsr(msrnum, msr);
 
 	/* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */
-	print_debug("Enable SUSP and allow TSC to run in Suspend\r\n");
+	print_debug("Enable SUSP and allow TSC to run in Suspend\n");
 	msrnum = CPU_BC_CONF_0;
 	msr = rdmsr(msrnum);
 	msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
@@ -302,10 +302,10 @@
 #endif
 
 	/* Setup throttling delays to proper mode if it is ever enabled. */
-	print_debug("Setup throttling delays to proper mode\r\n");
+	print_debug("Setup throttling delays to proper mode\n");
 	msrnum = GLCP_TH_OD;
 	msr.hi = 0;
 	msr.lo = 0x00000603C;
 	wrmsr(msrnum, msr);
-	print_debug("Done cpuRegInit\r\n");
+	print_debug("Done cpuRegInit\n");
 }
Index: src/cpu/amd/car/copy_and_run.c
===================================================================
--- src/cpu/amd/car/copy_and_run.c	(revision 3942)
+++ src/cpu/amd/car/copy_and_run.c	(working copy)
@@ -5,9 +5,9 @@
 static inline void print_debug_cp_run(const char *strval, uint32_t val)
 {
 #if CONFIG_USE_PRINTK_IN_CAR
-        printk_debug("%s%08x\r\n", strval, val);
+        printk_debug("%s%08x\n", strval, val);
 #else
-        print_debug(strval); print_debug_hex32(val); print_debug("\r\n");
+        print_debug(strval); print_debug_hex32(val); print_debug("\n");
 #endif
 }
 
@@ -25,7 +25,7 @@
 
 
 #if !CONFIG_COMPRESS 
-	print_debug("Copying coreboot to RAM.\r\n");
+	print_debug("Copying coreboot to RAM.\n");
 	__asm__ volatile (
 		"leal _liseg, %0\n\t"
 		"leal _iseg, %1\n\t"
@@ -35,7 +35,7 @@
 	);
 	memcpy(dst, src, olen);
 #else 
-	print_debug("Uncompressing coreboot to RAM.\r\n");
+	print_debug("Uncompressing coreboot to RAM.\n");
 
         __asm__ volatile (
 	        "leal _liseg, %0\n\t"
@@ -56,7 +56,7 @@
 
 	print_debug_cp_run("coreboot_ram.bin   length = ", olen);
 
-	print_debug("Jumping to coreboot.\r\n");
+	print_debug("Jumping to coreboot.\n");
 
         __asm__ volatile (
                 "xorl %ebp, %ebp\n\t" /* cpu_reset for hardwaremain dummy */
@@ -74,7 +74,7 @@
         uint8_t *src, *dst;
         unsigned long ilen, olen;
 
-//        print_debug("Copying coreboot AP code to CAR.\r\n");
+//        print_debug("Copying coreboot AP code to CAR.\n");
 
 #if !CONFIG_COMPRESS
         __asm__ volatile (
@@ -106,7 +106,7 @@
 
 //        print_debug_cp_run("coreboot_apc.bin   length = ", olen);
 
-//        print_debug("Jumping to coreboot AP code in CAR.\r\n");
+//        print_debug("Jumping to coreboot AP code in CAR.\n");
 
         __asm__ volatile (
                 "movl %0, %%ebp\n\t" /* cpu_reset for hardwaremain dummy */
Index: src/cpu/amd/car/post_cache_as_ram.c
===================================================================
--- src/cpu/amd/car/post_cache_as_ram.c	(revision 3942)
+++ src/cpu/amd/car/post_cache_as_ram.c	(working copy)
@@ -8,9 +8,9 @@
 static inline void print_debug_pcar(const char *strval, uint32_t val)
 {
 #if CONFIG_USE_PRINTK_IN_CAR
-        printk_debug("%s%08x\r\n", strval, val);
+        printk_debug("%s%08x\n", strval, val);
 #else
-        print_debug(strval); print_debug_hex32(val); print_debug("\r\n");
+        print_debug(strval); print_debug_hex32(val); print_debug("\n");
 #endif
 }
 
@@ -81,15 +81,15 @@
 	/* We can put data to stack again */
 
         /* only global variable sysinfo in cache need to be offset */
-        print_debug("Done\r\n");
+        print_debug("Done\n");
         print_debug_pcar("testx = ", testx);
 
-	print_debug("Disabling cache as ram now \r\n");
+	print_debug("Disabling cache as ram now \n");
 	disable_cache_as_ram_bsp();  
 
         print_debug("Clearing initial memory region: ");
         clear_init_ram(); //except the range from [(CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_SIZE, (CONFIG_LB_MEM_TOPK<<10))
-        print_debug("Done\r\n");
+        print_debug("Done\n");
 
 //	dump_mem((CONFIG_LB_MEM_TOPK<<10) - 0x8000, (CONFIG_LB_MEM_TOPK<<10) - 0x7c00);
 
@@ -108,7 +108,7 @@
         copy_and_run();
         /* We will not return */
 
-        print_debug("should not be here -\r\n");
+        print_debug("should not be here -\n");
 
 }
 
Index: src/cpu/x86/car/copy_and_run.c
===================================================================
--- src/cpu/x86/car/copy_and_run.c	(revision 3942)
+++ src/cpu/x86/car/copy_and_run.c	(working copy)
@@ -19,7 +19,7 @@
 
 
 #if !CONFIG_COMPRESS 
-	print_debug("Copying coreboot to RAM.\r\n");
+	print_debug("Copying coreboot to RAM.\n");
 	__asm__ volatile (
 		"leal _liseg, %0\n\t"
 		"leal _iseg, %1\n\t"
@@ -29,7 +29,7 @@
 	);
 	memcpy(src, dst, dst_len);
 #else 
-	print_debug("Uncompressing coreboot to RAM.\r\n");
+	print_debug("Uncompressing coreboot to RAM.\n");
 
         __asm__ volatile (
 	        "leal _liseg, %0\n\t"
@@ -38,11 +38,11 @@
         );
 
 #if CONFIG_USE_INIT		
-	printk_spew("src=%08x\r\n",src); 
-	printk_spew("dst=%08x\r\n",dst);
+	printk_spew("src=%08x\n",src); 
+	printk_spew("dst=%08x\n",dst);
 #else
-        print_spew("src="); print_spew_hex32((uint32_t)src); print_spew("\r\n");
-        print_spew("dst="); print_spew_hex32((uint32_t)dst); print_spew("\r\n");
+        print_spew("src="); print_spew_hex32((uint32_t)src); print_spew("\n");
+        print_spew("dst="); print_spew_hex32((uint32_t)dst); print_spew("\n");
 #endif
 	
 //	dump_mem(src, src+0x100);
@@ -52,11 +52,11 @@
 #endif
 //	dump_mem(dst, dst+0x100);
 #if CONFIG_USE_INIT
-	printk_spew("coreboot_ram.bin length = %08x\r\n", olen);
+	printk_spew("coreboot_ram.bin length = %08x\n", olen);
 #else
-	print_spew("coreboot_ram.bin length = "); print_spew_hex32(olen); print_spew("\r\n");
+	print_spew("coreboot_ram.bin length = "); print_spew_hex32(olen); print_spew("\n");
 #endif
-	print_debug("Jumping to coreboot.\r\n");
+	print_debug("Jumping to coreboot.\n");
 
 	if(cpu_reset == 1 ) {
 		__asm__ volatile (
Index: src/cpu/intel/model_6ex/cache_as_ram_disable.c
===================================================================
--- src/cpu/intel/model_6ex/cache_as_ram_disable.c	(revision 3942)
+++ src/cpu/intel/model_6ex/cache_as_ram_disable.c	(working copy)
@@ -60,12 +60,12 @@
         	        "movl   %%esp, %0\n\t"
 	                : "=a" (v_esp)
 	        );
-	        printk_spew("v_esp=%08x\r\n", v_esp);
+	        printk_spew("v_esp=%08x\n", v_esp);
         }
 
 cpu_reset_x:
 
-        printk_spew("cpu_reset = %08x\r\n",cpu_reset);
+        printk_spew("cpu_reset = %08x\n",cpu_reset);
 
 	if(cpu_reset == 0) {
 	        print_spew("Clearing initial memory region: ");
@@ -107,5 +107,5 @@
 		/* We will not return */
 	}
 
-	print_debug("sorry. parachute did not open.\r\n");
+	print_debug("sorry. parachute did not open.\n");
 }
Index: src/cpu/intel/model_6fx/cache_as_ram_disable.c
===================================================================
--- src/cpu/intel/model_6fx/cache_as_ram_disable.c	(revision 3942)
+++ src/cpu/intel/model_6fx/cache_as_ram_disable.c	(working copy)
@@ -60,12 +60,12 @@
         	        "movl   %%esp, %0\n\t"
 	                : "=a" (v_esp)
 	        );
-	        printk_spew("v_esp=%08x\r\n", v_esp);
+	        printk_spew("v_esp=%08x\n", v_esp);
         }
 
 cpu_reset_x:
 
-        printk_spew("cpu_reset = %08x\r\n",cpu_reset);
+        printk_spew("cpu_reset = %08x\n",cpu_reset);
 
 	if(cpu_reset == 0) {
 	        print_spew("Clearing initial memory region: ");
@@ -107,5 +107,5 @@
 		/* We will not return */
 	}
 
-	print_debug("sorry. parachute did not open.\r\n");
+	print_debug("sorry. parachute did not open.\n");
 }
Index: src/cpu/intel/microcode/microcode.c
===================================================================
--- src/cpu/intel/microcode/microcode.c	(revision 3942)
+++ src/cpu/intel/microcode/microcode.c	(working copy)
@@ -82,7 +82,7 @@
 	print_debug_hex32(pf);
 	print_debug(" rev = 0x");
 	print_debug_hex32(rev);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	m = microcode_updates;
 	for(c = microcode_updates; m->hdrver;  m = (const struct microcode *)c) {
@@ -99,7 +99,7 @@
 			print_debug_hex32(new_rev);
 			print_debug(" from revision ");
 			print_debug_hex32(rev);
-			print_debug("\r\n");
+			print_debug("\n");
 			break;
 		}
 		if (m->total_size) {
Index: src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c
===================================================================
--- src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c	(working copy)
@@ -245,11 +245,11 @@
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
+        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\n");
 
         setup_mb_resource_map();
 
-	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
 #if MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram 
@@ -276,7 +276,7 @@
         {
                 msr_t msr;
 	        msr=rdmsr(0xc0010042);
-                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 
         }
 
@@ -290,7 +290,7 @@
         {
                 msr_t msr;
                	msr=rdmsr(0xc0010042);
-               	print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); 
+               	print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); 
 
         }
 #endif
@@ -300,7 +300,7 @@
 
         // fidvid change will issue one LDTSTOP and the HT change will be effective too
         if (needs_reset) {
-                print_info("ht reset -\r\n");
+                print_info("ht reset -\n");
                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
         }
 
Index: src/mainboard/iwill/dk8s2/auto.c
===================================================================
--- src/mainboard/iwill/dk8s2/auto.c	(revision 3942)
+++ src/mainboard/iwill/dk8s2/auto.c	(working copy)
@@ -135,7 +135,7 @@
 	needs_reset = setup_coherent_ht_domain();
 	needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
 	if (needs_reset) {
-		print_info("ht reset -\r\n");
+		print_info("ht reset -\n");
 		soft_reset();
 	}
 	
Index: src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
===================================================================
--- src/mainboard/iwill/dk8s2/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/iwill/dk8s2/cache_as_ram_auto.c	(working copy)
@@ -245,11 +245,11 @@
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
+        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\n");
 
         setup_default_resource_map();
 
-	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
 #if MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram 
@@ -276,7 +276,7 @@
         {
                 msr_t msr;
 	        msr=rdmsr(0xc0010042);
-                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 
         }
 
@@ -290,7 +290,7 @@
         {
                 msr_t msr;
                	msr=rdmsr(0xc0010042);
-               	print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); 
+               	print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); 
 
         }
 #endif
@@ -300,7 +300,7 @@
 
         // fidvid change will issue one LDTSTOP and the HT change will be effective too
         if (needs_reset) {
-                print_info("ht reset -\r\n");
+                print_info("ht reset -\n");
                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
         }
 
Index: src/mainboard/iwill/dk8x/auto.c
===================================================================
--- src/mainboard/iwill/dk8x/auto.c	(revision 3942)
+++ src/mainboard/iwill/dk8x/auto.c	(working copy)
@@ -136,7 +136,7 @@
 	needs_reset = setup_coherent_ht_domain();
 	needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
 	if (needs_reset) {
-		print_info("ht reset -\r\n");
+		print_info("ht reset -\n");
 		soft_reset();
 	}
 
@@ -165,7 +165,7 @@
 	print_debug("TOP_MEM: ");
 	print_debug_hex32(msr.hi);
 	print_debug_hex32(msr.lo);
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 #if 0
 	ram_check(0x00000000, msr.lo);
Index: src/mainboard/iwill/dk8x/cache_as_ram_auto.c
===================================================================
--- src/mainboard/iwill/dk8x/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/iwill/dk8x/cache_as_ram_auto.c	(working copy)
@@ -245,11 +245,11 @@
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
+        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\n");
 
         setup_default_resource_map();
 
-	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
 #if MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram 
@@ -276,7 +276,7 @@
         {
                 msr_t msr;
 	        msr=rdmsr(0xc0010042);
-                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 
         }
 
@@ -290,7 +290,7 @@
         {
                 msr_t msr;
                	msr=rdmsr(0xc0010042);
-               	print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); 
+               	print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); 
 
         }
 #endif
@@ -300,7 +300,7 @@
 
         // fidvid change will issue one LDTSTOP and the HT change will be effective too
         if (needs_reset) {
-                print_info("ht reset -\r\n");
+                print_info("ht reset -\n");
                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
         }
 
Index: src/mainboard/bcom/winnetp680/auto.c
===================================================================
--- src/mainboard/bcom/winnetp680/auto.c	(revision 3942)
+++ src/mainboard/bcom/winnetp680/auto.c	(working copy)
@@ -103,25 +103,25 @@
 	uart_init();
 	console_init();
 
-	print_spew("In auto.c:main()\r\n");
+	print_spew("In auto.c:main()\n");
 
 	enable_smbus();
 	smbus_fixup(&ctrl);
 
 	if (bist == 0) {
-		print_debug("doing early_mtrr\r\n");
+		print_debug("doing early_mtrr\n");
 		early_mtrr_init();
 	}
 
 	/* Halt if there was a built-in self test failure. */
 	report_bist_failure(bist);
 
-	print_debug("Enabling mainboard devices\r\n");
+	print_debug("Enabling mainboard devices\n");
 	enable_mainboard_devices();
 
 	ddr_ram_setup(&ctrl);
 
 	/* ram_check(0, 640 * 1024); */
 
-	print_spew("Leaving auto.c:main()\r\n");
+	print_spew("Leaving auto.c:main()\n");
 }
Index: src/mainboard/broadcom/blast/cache_as_ram_auto.c
===================================================================
--- src/mainboard/broadcom/blast/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/broadcom/blast/cache_as_ram_auto.c	(working copy)
@@ -79,9 +79,9 @@
 {
 #define SMBUS_HUB 0x71
 	int ret;
-        print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
+        print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
         ret = smbus_send_byte(SMBUS_HUB, device);
-        print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\r\n");
+        print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n");
 }
 #endif
 
@@ -211,7 +211,7 @@
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
         setup_blast_resource_map();
 	
@@ -234,7 +234,7 @@
 	bcm5785_early_setup();
 
        	if (needs_reset) {
-               	print_info("ht reset -\r\n");
+               	print_info("ht reset -\n");
                	soft_reset();
        	}
 
Index: src/mainboard/supermicro/x6dai_g/watchdog.c
===================================================================
--- src/mainboard/supermicro/x6dai_g/watchdog.c	(revision 3942)
+++ src/mainboard/supermicro/x6dai_g/watchdog.c	(working copy)
@@ -37,6 +37,6 @@
 static void disable_watchdogs(void)
 {
 	disable_esb6300_watchdog();
-	print_debug("Watchdogs disabled\r\n");
+	print_debug("Watchdogs disabled\n");
 }
 
Index: src/mainboard/supermicro/x6dai_g/debug.c
===================================================================
--- src/mainboard/supermicro/x6dai_g/debug.c	(revision 3942)
+++ src/mainboard/supermicro/x6dai_g/debug.c	(working copy)
@@ -12,7 +12,7 @@
 	print_debug_hex8(index);
 	print_debug(": 0x");
 	print_debug_hex8(data);
-	print_debug("\r\n");
+	print_debug("\n");
         return;
 }
         
@@ -49,52 +49,52 @@
         int i;
         unsigned char data;
        
-	 print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
+	 print_debug("\n*** SERVER I/O REGISTERS ***\n");
         for (i=0x10; i<=0x2d; i++) {
                 print_reg((unsigned char)i);
         }
 #if 0                                                                         
-        print_debug("\r\n*** XBUS REGISTERS ***\r\n");
+        print_debug("\n*** XBUS REGISTERS ***\n");
         setup_func(0x0f);
         for (i=0xf0; i<=0xff; i++) {
                 print_reg((unsigned char)i);
         }
                                                                                 
-        print_debug("\r\n***  SERIAL 1 CONFIG REGISTERS ***\r\n");
+        print_debug("\n***  SERIAL 1 CONFIG REGISTERS ***\n");
         setup_func(0x03);
         print_reg(0xf0);
                                                                                 
-        print_debug("\r\n***  SERIAL 2 CONFIG REGISTERS ***\r\n");
+        print_debug("\n***  SERIAL 2 CONFIG REGISTERS ***\n");
         setup_func(0x02);
         print_reg(0xf0);
 
 #endif
-        print_debug("\r\n***  GPIO REGISTERS ***\r\n");
+        print_debug("\n***  GPIO REGISTERS ***\n");
         setup_func(0x07);
         for (i=0xf0; i<=0xf8; i++) {
                 print_reg((unsigned char)i);
         }
-        print_debug("\r\n***  GPIO VALUES ***\r\n");
+        print_debug("\n***  GPIO VALUES ***\n");
         data = inb(0x68a);
-	print_debug("\r\nGPDO 4: 0x");
+	print_debug("\nGPDO 4: 0x");
 	print_debug_hex8(data);
         data = inb(0x68b);
-	print_debug("\r\nGPDI 4: 0x");
+	print_debug("\nGPDI 4: 0x");
 	print_debug_hex8(data);
-	print_debug("\r\n");
+	print_debug("\n");
 	
 #if 0                                                                                
                                                                                 
-        print_debug("\r\n***  WATCHDOG TIMER REGISTERS ***\r\n");
+        print_debug("\n***  WATCHDOG TIMER REGISTERS ***\n");
         setup_func(0x0a);
         print_reg(0xf0);
                                                                                 
-        print_debug("\r\n***  FAN CONTROL REGISTERS ***\r\n");
+        print_debug("\n***  FAN CONTROL REGISTERS ***\n");
         setup_func(0x09);
         print_reg(0xf0);
         print_reg(0xf1);
 
-        print_debug("\r\n***  RTC REGISTERS ***\r\n");
+        print_debug("\n***  RTC REGISTERS ***\n");
         setup_func(0x10);
         print_reg(0xf0);
         print_reg(0xf1);
@@ -104,7 +104,7 @@
         print_reg(0xfe);
         print_reg(0xff);
                                                                                 
-        print_debug("\r\n***  HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
+        print_debug("\n***  HEALTH MONITORING & CONTROL REGISTERS ***\n");
         setup_func(0x14);
         print_reg(0xf0);
 #endif                                                                           
@@ -135,7 +135,7 @@
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		print_debug("\r\n");
+		print_debug("\n");
 	}
 }
 
@@ -143,7 +143,7 @@
 {
 	int i;
 	print_debug_pci_dev(dev);
-	print_debug("\r\n");
+	print_debug("\n");
 	
 	for(i = 0; i <= 255; i++) {
 		unsigned char val;
@@ -155,7 +155,7 @@
 		print_debug_char(' ');
 		print_debug_hex8(val);
 		if ((i & 0x0f) == 0x0f) {
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -165,7 +165,7 @@
 	int i;
 	unsigned long bar;
 	
-	print_debug("BAR 14 Dump\r\n");
+	print_debug("BAR 14 Dump\n");
 	
 	bar = pci_read_config32(dev, 0x14);
 	for(i = 0; i <= 0x300; i+=4) {
@@ -178,14 +178,14 @@
 		val = pci_read_config8(dev, i);
 #endif		
 		if((i%4)==0) {
-		print_debug("\r\n");
+		print_debug("\n");
 		print_debug_hex16(i);
 		print_debug_char(' ');
 		}
 		print_debug_hex32(read32(bar + i));
 		print_debug_char(' ');
 	}
-	print_debug("\r\n");
+	print_debug("\n");
 }
 
 static void dump_pci_devices(void)
@@ -209,7 +209,7 @@
 static void dump_spd_registers(const struct mem_controller *ctrl)
 {
 	int i;
-	print_debug("\r\n");
+	print_debug("\n");
 	for(i = 0; i < 4; i++) {
 		unsigned device;
 		device = ctrl->channel0[i];
@@ -223,20 +223,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 		device = ctrl->channel1[i];
 		if (device) {
@@ -249,20 +249,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -275,14 +275,14 @@
         while(device <= SMBUS_MEM_DEVICE_END) {
                 int status = 0;
                 int i;
-        	print_debug("\r\n");
+        	print_debug("\n");
                 print_debug("dimm ");
 		print_debug_hex8(device);
 		
                 for(i = 0; (i < 256) ; i++) {
 	                unsigned char byte;
                         if ((i % 16) == 0) {
-				print_debug("\r\n");
+				print_debug("\n");
 				print_debug_hex8(i);
 				print_debug(": ");
                         }
@@ -290,7 +290,7 @@
                         if (status < 0) {
 			         print_debug("bad device: ");
 				 print_debug_hex8(-status);
-				 print_debug("\r\n");
+				 print_debug("\n");
 			         break; 
 			}
 			print_debug_hex8(status);
@@ -308,7 +308,7 @@
         while(device <= 0x42) {
                 int status = 0;
                 int i;
-        	print_debug("\r\n");
+        	print_debug("\n");
                 print_debug("ipmi ");
 		print_debug_hex8(device);
 		
@@ -318,7 +318,7 @@
                         if (status < 0) {
 			         print_debug("bad device: ");
 				 print_debug_hex8(-status);
-				 print_debug("\r\n");
+				 print_debug("\n");
 			         break; 
 			}
 			print_debug_hex8(status);
Index: src/mainboard/supermicro/h8dmr/apc_auto.c
===================================================================
--- src/mainboard/supermicro/h8dmr/apc_auto.c	(revision 3942)
+++ src/mainboard/supermicro/h8dmr/apc_auto.c	(working copy)
@@ -93,7 +93,7 @@
 
 	id = get_node_core_id_x();
 
-        print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+        print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
 
 	train_ram(id.nodeid, sysinfo, sysinfox);
 
Index: src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c
===================================================================
--- src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c	(working copy)
@@ -275,11 +275,11 @@
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
+        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\n");
 
         setup_mb_resource_map();
 
-        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
 #if MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@@ -305,7 +305,7 @@
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 
         }
 
@@ -319,7 +319,7 @@
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 
         }
 #endif
@@ -331,7 +331,7 @@
 
         // fidvid change will issue one LDTSTOP and the HT change will be effective too
         if (needs_reset) {
-                print_info("ht reset -\r\n");
+                print_info("ht reset -\n");
               	soft_reset();
         }
 #endif
Index: src/mainboard/supermicro/x6dhe_g/watchdog.c
===================================================================
--- src/mainboard/supermicro/x6dhe_g/watchdog.c	(revision 3942)
+++ src/mainboard/supermicro/x6dhe_g/watchdog.c	(working copy)
@@ -94,6 +94,6 @@
 //	disable_sio_watchdog(NSC_WD_DEV);
 	disable_esb6300_watchdog();
 //	disable_jarell_frb3();
-	print_debug("Watchdogs disabled\r\n");
+	print_debug("Watchdogs disabled\n");
 }
 
Index: src/mainboard/supermicro/x6dhe_g/debug.c
===================================================================
--- src/mainboard/supermicro/x6dhe_g/debug.c	(revision 3942)
+++ src/mainboard/supermicro/x6dhe_g/debug.c	(working copy)
@@ -12,7 +12,7 @@
 	print_debug_hex8(index);
 	print_debug(": 0x");
 	print_debug_hex8(data);
-	print_debug("\r\n");
+	print_debug("\n");
         return;
 }
         
@@ -49,52 +49,52 @@
         int i;
         unsigned char data;
        
-	 print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
+	 print_debug("\n*** SERVER I/O REGISTERS ***\n");
         for (i=0x10; i<=0x2d; i++) {
                 print_reg((unsigned char)i);
         }
 #if 0                                                                         
-        print_debug("\r\n*** XBUS REGISTERS ***\r\n");
+        print_debug("\n*** XBUS REGISTERS ***\n");
         setup_func(0x0f);
         for (i=0xf0; i<=0xff; i++) {
                 print_reg((unsigned char)i);
         }
                                                                                 
-        print_debug("\r\n***  SERIAL 1 CONFIG REGISTERS ***\r\n");
+        print_debug("\n***  SERIAL 1 CONFIG REGISTERS ***\n");
         setup_func(0x03);
         print_reg(0xf0);
                                                                                 
-        print_debug("\r\n***  SERIAL 2 CONFIG REGISTERS ***\r\n");
+        print_debug("\n***  SERIAL 2 CONFIG REGISTERS ***\n");
         setup_func(0x02);
         print_reg(0xf0);
 
 #endif
-        print_debug("\r\n***  GPIO REGISTERS ***\r\n");
+        print_debug("\n***  GPIO REGISTERS ***\n");
         setup_func(0x07);
         for (i=0xf0; i<=0xf8; i++) {
                 print_reg((unsigned char)i);
         }
-        print_debug("\r\n***  GPIO VALUES ***\r\n");
+        print_debug("\n***  GPIO VALUES ***\n");
         data = inb(0x68a);
-	print_debug("\r\nGPDO 4: 0x");
+	print_debug("\nGPDO 4: 0x");
 	print_debug_hex8(data);
         data = inb(0x68b);
-	print_debug("\r\nGPDI 4: 0x");
+	print_debug("\nGPDI 4: 0x");
 	print_debug_hex8(data);
-	print_debug("\r\n");
+	print_debug("\n");
 	
 #if 0                                                                                
                                                                                 
-        print_debug("\r\n***  WATCHDOG TIMER REGISTERS ***\r\n");
+        print_debug("\n***  WATCHDOG TIMER REGISTERS ***\n");
         setup_func(0x0a);
         print_reg(0xf0);
                                                                                 
-        print_debug("\r\n***  FAN CONTROL REGISTERS ***\r\n");
+        print_debug("\n***  FAN CONTROL REGISTERS ***\n");
         setup_func(0x09);
         print_reg(0xf0);
         print_reg(0xf1);
 
-        print_debug("\r\n***  RTC REGISTERS ***\r\n");
+        print_debug("\n***  RTC REGISTERS ***\n");
         setup_func(0x10);
         print_reg(0xf0);
         print_reg(0xf1);
@@ -104,7 +104,7 @@
         print_reg(0xfe);
         print_reg(0xff);
                                                                                 
-        print_debug("\r\n***  HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
+        print_debug("\n***  HEALTH MONITORING & CONTROL REGISTERS ***\n");
         setup_func(0x14);
         print_reg(0xf0);
 #endif                                                                           
@@ -135,7 +135,7 @@
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		print_debug("\r\n");
+		print_debug("\n");
 	}
 }
 
@@ -143,7 +143,7 @@
 {
 	int i;
 	print_debug_pci_dev(dev);
-	print_debug("\r\n");
+	print_debug("\n");
 	
 	for(i = 0; i <= 255; i++) {
 		unsigned char val;
@@ -155,7 +155,7 @@
 		print_debug_char(' ');
 		print_debug_hex8(val);
 		if ((i & 0x0f) == 0x0f) {
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -165,7 +165,7 @@
 	int i;
 	unsigned long bar;
 	
-	print_debug("BAR 14 Dump\r\n");
+	print_debug("BAR 14 Dump\n");
 	
 	bar = pci_read_config32(dev, 0x14);
 	for(i = 0; i <= 0x300; i+=4) {
@@ -178,14 +178,14 @@
 		val = pci_read_config8(dev, i);
 #endif		
 		if((i%4)==0) {
-		print_debug("\r\n");
+		print_debug("\n");
 		print_debug_hex16(i);
 		print_debug_char(' ');
 		}
 		print_debug_hex32(read32(bar + i));
 		print_debug_char(' ');
 	}
-	print_debug("\r\n");
+	print_debug("\n");
 }
 
 static void dump_pci_devices(void)
@@ -209,7 +209,7 @@
 static void dump_spd_registers(const struct mem_controller *ctrl)
 {
 	int i;
-	print_debug("\r\n");
+	print_debug("\n");
 	for(i = 0; i < 4; i++) {
 		unsigned device;
 		device = ctrl->channel0[i];
@@ -223,20 +223,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 		device = ctrl->channel1[i];
 		if (device) {
@@ -249,20 +249,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -275,14 +275,14 @@
         while(device <= SMBUS_MEM_DEVICE_END) {
                 int status = 0;
                 int i;
-        	print_debug("\r\n");
+        	print_debug("\n");
                 print_debug("dimm ");
 		print_debug_hex8(device);
 		
                 for(i = 0; (i < 256) ; i++) {
 	                unsigned char byte;
                         if ((i % 16) == 0) {
-				print_debug("\r\n");
+				print_debug("\n");
 				print_debug_hex8(i);
 				print_debug(": ");
                         }
@@ -290,7 +290,7 @@
                         if (status < 0) {
 			         print_debug("bad device: ");
 				 print_debug_hex8(-status);
-				 print_debug("\r\n");
+				 print_debug("\n");
 			         break; 
 			}
 			print_debug_hex8(status);
@@ -308,7 +308,7 @@
         while(device <= 0x42) {
                 int status = 0;
                 int i;
-        	print_debug("\r\n");
+        	print_debug("\n");
                 print_debug("ipmi ");
 		print_debug_hex8(device);
 		
@@ -318,7 +318,7 @@
                         if (status < 0) {
 			         print_debug("bad device: ");
 				 print_debug_hex8(-status);
-				 print_debug("\r\n");
+				 print_debug("\n");
 			         break; 
 			}
 			print_debug_hex8(status);
Index: src/mainboard/supermicro/x6dhe_g2/watchdog.c
===================================================================
--- src/mainboard/supermicro/x6dhe_g2/watchdog.c	(revision 3942)
+++ src/mainboard/supermicro/x6dhe_g2/watchdog.c	(working copy)
@@ -94,6 +94,6 @@
 //	disable_sio_watchdog(NSC_WD_DEV);
 	disable_esb6300_watchdog();
 //	disable_jarell_frb3();
-	print_debug("Watchdogs disabled\r\n");
+	print_debug("Watchdogs disabled\n");
 }
 
Index: src/mainboard/supermicro/x6dhe_g2/debug.c
===================================================================
--- src/mainboard/supermicro/x6dhe_g2/debug.c	(revision 3942)
+++ src/mainboard/supermicro/x6dhe_g2/debug.c	(working copy)
@@ -12,7 +12,7 @@
 	print_debug_hex8(index);
 	print_debug(": 0x");
 	print_debug_hex8(data);
-	print_debug("\r\n");
+	print_debug("\n");
         return;
 }
         
@@ -49,52 +49,52 @@
         int i;
         unsigned char data;
        
-	 print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
+	 print_debug("\n*** SERVER I/O REGISTERS ***\n");
         for (i=0x10; i<=0x2d; i++) {
                 print_reg((unsigned char)i);
         }
 #if 0                                                                         
-        print_debug("\r\n*** XBUS REGISTERS ***\r\n");
+        print_debug("\n*** XBUS REGISTERS ***\n");
         setup_func(0x0f);
         for (i=0xf0; i<=0xff; i++) {
                 print_reg((unsigned char)i);
         }
                                                                                 
-        print_debug("\r\n***  SERIAL 1 CONFIG REGISTERS ***\r\n");
+        print_debug("\n***  SERIAL 1 CONFIG REGISTERS ***\n");
         setup_func(0x03);
         print_reg(0xf0);
                                                                                 
-        print_debug("\r\n***  SERIAL 2 CONFIG REGISTERS ***\r\n");
+        print_debug("\n***  SERIAL 2 CONFIG REGISTERS ***\n");
         setup_func(0x02);
         print_reg(0xf0);
 
 #endif
-        print_debug("\r\n***  GPIO REGISTERS ***\r\n");
+        print_debug("\n***  GPIO REGISTERS ***\n");
         setup_func(0x07);
         for (i=0xf0; i<=0xf8; i++) {
                 print_reg((unsigned char)i);
         }
-        print_debug("\r\n***  GPIO VALUES ***\r\n");
+        print_debug("\n***  GPIO VALUES ***\n");
         data = inb(0x68a);
-	print_debug("\r\nGPDO 4: 0x");
+	print_debug("\nGPDO 4: 0x");
 	print_debug_hex8(data);
         data = inb(0x68b);
-	print_debug("\r\nGPDI 4: 0x");
+	print_debug("\nGPDI 4: 0x");
 	print_debug_hex8(data);
-	print_debug("\r\n");
+	print_debug("\n");
 	
 #if 0                                                                                
                                                                                 
-        print_debug("\r\n***  WATCHDOG TIMER REGISTERS ***\r\n");
+        print_debug("\n***  WATCHDOG TIMER REGISTERS ***\n");
         setup_func(0x0a);
         print_reg(0xf0);
                                                                                 
-        print_debug("\r\n***  FAN CONTROL REGISTERS ***\r\n");
+        print_debug("\n***  FAN CONTROL REGISTERS ***\n");
         setup_func(0x09);
         print_reg(0xf0);
         print_reg(0xf1);
 
-        print_debug("\r\n***  RTC REGISTERS ***\r\n");
+        print_debug("\n***  RTC REGISTERS ***\n");
         setup_func(0x10);
         print_reg(0xf0);
         print_reg(0xf1);
@@ -104,7 +104,7 @@
         print_reg(0xfe);
         print_reg(0xff);
                                                                                 
-        print_debug("\r\n***  HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
+        print_debug("\n***  HEALTH MONITORING & CONTROL REGISTERS ***\n");
         setup_func(0x14);
         print_reg(0xf0);
 #endif                                                                           
@@ -135,7 +135,7 @@
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		print_debug("\r\n");
+		print_debug("\n");
 	}
 }
 
@@ -143,7 +143,7 @@
 {
 	int i;
 	print_debug_pci_dev(dev);
-	print_debug("\r\n");
+	print_debug("\n");
 	
 	for(i = 0; i <= 255; i++) {
 		unsigned char val;
@@ -155,7 +155,7 @@
 		print_debug_char(' ');
 		print_debug_hex8(val);
 		if ((i & 0x0f) == 0x0f) {
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -165,7 +165,7 @@
 	int i;
 	unsigned long bar;
 	
-	print_debug("BAR 14 Dump\r\n");
+	print_debug("BAR 14 Dump\n");
 	
 	bar = pci_read_config32(dev, 0x14);
 	for(i = 0; i <= 0x300; i+=4) {
@@ -178,14 +178,14 @@
 		val = pci_read_config8(dev, i);
 #endif		
 		if((i%4)==0) {
-		print_debug("\r\n");
+		print_debug("\n");
 		print_debug_hex16(i);
 		print_debug_char(' ');
 		}
 		print_debug_hex32(read32(bar + i));
 		print_debug_char(' ');
 	}
-	print_debug("\r\n");
+	print_debug("\n");
 }
 
 static void dump_pci_devices(void)
@@ -209,7 +209,7 @@
 static void dump_spd_registers(const struct mem_controller *ctrl)
 {
 	int i;
-	print_debug("\r\n");
+	print_debug("\n");
 	for(i = 0; i < 4; i++) {
 		unsigned device;
 		device = ctrl->channel0[i];
@@ -223,20 +223,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 		device = ctrl->channel1[i];
 		if (device) {
@@ -249,20 +249,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -275,14 +275,14 @@
         while(device <= SMBUS_MEM_DEVICE_END) {
                 int status = 0;
                 int i;
-        	print_debug("\r\n");
+        	print_debug("\n");
                 print_debug("dimm ");
 		print_debug_hex8(device);
 		
                 for(i = 0; (i < 256) ; i++) {
 	                unsigned char byte;
                         if ((i % 16) == 0) {
-				print_debug("\r\n");
+				print_debug("\n");
 				print_debug_hex8(i);
 				print_debug(": ");
                         }
@@ -290,7 +290,7 @@
                         if (status < 0) {
 			         print_debug("bad device: ");
 				 print_debug_hex8(-status);
-				 print_debug("\r\n");
+				 print_debug("\n");
 			         break; 
 			}
 			print_debug_hex8(status);
@@ -308,7 +308,7 @@
         while(device <= 0x42) {
                 int status = 0;
                 int i;
-        	print_debug("\r\n");
+        	print_debug("\n");
                 print_debug("ipmi ");
 		print_debug_hex8(device);
 		
@@ -318,7 +318,7 @@
                         if (status < 0) {
 			         print_debug("bad device: ");
 				 print_debug_hex8(-status);
-				 print_debug("\r\n");
+				 print_debug("\n");
 			         break; 
 			}
 			print_debug_hex8(status);
Index: src/mainboard/supermicro/x6dhr_ig/watchdog.c
===================================================================
--- src/mainboard/supermicro/x6dhr_ig/watchdog.c	(revision 3942)
+++ src/mainboard/supermicro/x6dhr_ig/watchdog.c	(working copy)
@@ -94,6 +94,6 @@
 //	disable_sio_watchdog(NSC_WD_DEV);
 	disable_ich5_watchdog();
 //	disable_jarell_frb3();
-	print_debug("Watchdogs disabled\r\n");
+	print_debug("Watchdogs disabled\n");
 }
 
Index: src/mainboard/supermicro/x6dhr_ig/debug.c
===================================================================
--- src/mainboard/supermicro/x6dhr_ig/debug.c	(revision 3942)
+++ src/mainboard/supermicro/x6dhr_ig/debug.c	(working copy)
@@ -12,7 +12,7 @@
 	print_debug_hex8(index);
 	print_debug(": 0x");
 	print_debug_hex8(data);
-	print_debug("\r\n");
+	print_debug("\n");
         return;
 }
         
@@ -49,52 +49,52 @@
         int i;
         unsigned char data;
        
-	 print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
+	 print_debug("\n*** SERVER I/O REGISTERS ***\n");
         for (i=0x10; i<=0x2d; i++) {
                 print_reg((unsigned char)i);
         }
 #if 0                                                                         
-        print_debug("\r\n*** XBUS REGISTERS ***\r\n");
+        print_debug("\n*** XBUS REGISTERS ***\n");
         setup_func(0x0f);
         for (i=0xf0; i<=0xff; i++) {
                 print_reg((unsigned char)i);
         }
                                                                                 
-        print_debug("\r\n***  SERIAL 1 CONFIG REGISTERS ***\r\n");
+        print_debug("\n***  SERIAL 1 CONFIG REGISTERS ***\n");
         setup_func(0x03);
         print_reg(0xf0);
                                                                                 
-        print_debug("\r\n***  SERIAL 2 CONFIG REGISTERS ***\r\n");
+        print_debug("\n***  SERIAL 2 CONFIG REGISTERS ***\n");
         setup_func(0x02);
         print_reg(0xf0);
 
 #endif
-        print_debug("\r\n***  GPIO REGISTERS ***\r\n");
+        print_debug("\n***  GPIO REGISTERS ***\n");
         setup_func(0x07);
         for (i=0xf0; i<=0xf8; i++) {
                 print_reg((unsigned char)i);
         }
-        print_debug("\r\n***  GPIO VALUES ***\r\n");
+        print_debug("\n***  GPIO VALUES ***\n");
         data = inb(0x68a);
-	print_debug("\r\nGPDO 4: 0x");
+	print_debug("\nGPDO 4: 0x");
 	print_debug_hex8(data);
         data = inb(0x68b);
-	print_debug("\r\nGPDI 4: 0x");
+	print_debug("\nGPDI 4: 0x");
 	print_debug_hex8(data);
-	print_debug("\r\n");
+	print_debug("\n");
 	
 #if 0                                                                                
                                                                                 
-        print_debug("\r\n***  WATCHDOG TIMER REGISTERS ***\r\n");
+        print_debug("\n***  WATCHDOG TIMER REGISTERS ***\n");
         setup_func(0x0a);
         print_reg(0xf0);
                                                                                 
-        print_debug("\r\n***  FAN CONTROL REGISTERS ***\r\n");
+        print_debug("\n***  FAN CONTROL REGISTERS ***\n");
         setup_func(0x09);
         print_reg(0xf0);
         print_reg(0xf1);
 
-        print_debug("\r\n***  RTC REGISTERS ***\r\n");
+        print_debug("\n***  RTC REGISTERS ***\n");
         setup_func(0x10);
         print_reg(0xf0);
         print_reg(0xf1);
@@ -104,7 +104,7 @@
         print_reg(0xfe);
         print_reg(0xff);
                                                                                 
-        print_debug("\r\n***  HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
+        print_debug("\n***  HEALTH MONITORING & CONTROL REGISTERS ***\n");
         setup_func(0x14);
         print_reg(0xf0);
 #endif                                                                           
@@ -135,7 +135,7 @@
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		print_debug("\r\n");
+		print_debug("\n");
 	}
 }
 
@@ -143,7 +143,7 @@
 {
 	int i;
 	print_debug_pci_dev(dev);
-	print_debug("\r\n");
+	print_debug("\n");
 	
 	for(i = 0; i <= 255; i++) {
 		unsigned char val;
@@ -155,7 +155,7 @@
 		print_debug_char(' ');
 		print_debug_hex8(val);
 		if ((i & 0x0f) == 0x0f) {
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -165,7 +165,7 @@
 	int i;
 	unsigned long bar;
 	
-	print_debug("BAR 14 Dump\r\n");
+	print_debug("BAR 14 Dump\n");
 	
 	bar = pci_read_config32(dev, 0x14);
 	for(i = 0; i <= 0x300; i+=4) {
@@ -178,14 +178,14 @@
 		val = pci_read_config8(dev, i);
 #endif		
 		if((i%4)==0) {
-		print_debug("\r\n");
+		print_debug("\n");
 		print_debug_hex16(i);
 		print_debug_char(' ');
 		}
 		print_debug_hex32(read32(bar + i));
 		print_debug_char(' ');
 	}
-	print_debug("\r\n");
+	print_debug("\n");
 }
 
 static void dump_pci_devices(void)
@@ -209,7 +209,7 @@
 static void dump_spd_registers(const struct mem_controller *ctrl)
 {
 	int i;
-	print_debug("\r\n");
+	print_debug("\n");
 	for(i = 0; i < 4; i++) {
 		unsigned device;
 		device = ctrl->channel0[i];
@@ -223,20 +223,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 		device = ctrl->channel1[i];
 		if (device) {
@@ -249,20 +249,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -275,14 +275,14 @@
         while(device <= SMBUS_MEM_DEVICE_END) {
                 int status = 0;
                 int i;
-        	print_debug("\r\n");
+        	print_debug("\n");
                 print_debug("dimm ");
 		print_debug_hex8(device);
 		
                 for(i = 0; (i < 256) ; i++) {
 	                unsigned char byte;
                         if ((i % 16) == 0) {
-				print_debug("\r\n");
+				print_debug("\n");
 				print_debug_hex8(i);
 				print_debug(": ");
                         }
@@ -290,7 +290,7 @@
                         if (status < 0) {
 			         print_debug("bad device: ");
 				 print_debug_hex8(-status);
-				 print_debug("\r\n");
+				 print_debug("\n");
 			         break; 
 			}
 			print_debug_hex8(status);
@@ -308,7 +308,7 @@
         while(device <= 0x42) {
                 int status = 0;
                 int i;
-        	print_debug("\r\n");
+        	print_debug("\n");
                 print_debug("ipmi ");
 		print_debug_hex8(device);
 		
@@ -318,7 +318,7 @@
                         if (status < 0) {
 			         print_debug("bad device: ");
 				 print_debug_hex8(-status);
-				 print_debug("\r\n");
+				 print_debug("\n");
 			         break; 
 			}
 			print_debug_hex8(status);
Index: src/mainboard/supermicro/x6dhr_ig2/watchdog.c
===================================================================
--- src/mainboard/supermicro/x6dhr_ig2/watchdog.c	(revision 3942)
+++ src/mainboard/supermicro/x6dhr_ig2/watchdog.c	(working copy)
@@ -94,6 +94,6 @@
 //	disable_sio_watchdog(NSC_WD_DEV);
 	disable_ich5_watchdog();
 //	disable_jarell_frb3();
-	print_debug("Watchdogs disabled\r\n");
+	print_debug("Watchdogs disabled\n");
 }
 
Index: src/mainboard/supermicro/x6dhr_ig2/debug.c
===================================================================
--- src/mainboard/supermicro/x6dhr_ig2/debug.c	(revision 3942)
+++ src/mainboard/supermicro/x6dhr_ig2/debug.c	(working copy)
@@ -12,7 +12,7 @@
 	print_debug_hex8(index);
 	print_debug(": 0x");
 	print_debug_hex8(data);
-	print_debug("\r\n");
+	print_debug("\n");
         return;
 }
         
@@ -49,52 +49,52 @@
         int i;
         unsigned char data;
        
-	 print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
+	 print_debug("\n*** SERVER I/O REGISTERS ***\n");
         for (i=0x10; i<=0x2d; i++) {
                 print_reg((unsigned char)i);
         }
 #if 0                                                                         
-        print_debug("\r\n*** XBUS REGISTERS ***\r\n");
+        print_debug("\n*** XBUS REGISTERS ***\n");
         setup_func(0x0f);
         for (i=0xf0; i<=0xff; i++) {
                 print_reg((unsigned char)i);
         }
                                                                                 
-        print_debug("\r\n***  SERIAL 1 CONFIG REGISTERS ***\r\n");
+        print_debug("\n***  SERIAL 1 CONFIG REGISTERS ***\n");
         setup_func(0x03);
         print_reg(0xf0);
                                                                                 
-        print_debug("\r\n***  SERIAL 2 CONFIG REGISTERS ***\r\n");
+        print_debug("\n***  SERIAL 2 CONFIG REGISTERS ***\n");
         setup_func(0x02);
         print_reg(0xf0);
 
 #endif
-        print_debug("\r\n***  GPIO REGISTERS ***\r\n");
+        print_debug("\n***  GPIO REGISTERS ***\n");
         setup_func(0x07);
         for (i=0xf0; i<=0xf8; i++) {
                 print_reg((unsigned char)i);
         }
-        print_debug("\r\n***  GPIO VALUES ***\r\n");
+        print_debug("\n***  GPIO VALUES ***\n");
         data = inb(0x68a);
-	print_debug("\r\nGPDO 4: 0x");
+	print_debug("\nGPDO 4: 0x");
 	print_debug_hex8(data);
         data = inb(0x68b);
-	print_debug("\r\nGPDI 4: 0x");
+	print_debug("\nGPDI 4: 0x");
 	print_debug_hex8(data);
-	print_debug("\r\n");
+	print_debug("\n");
 	
 #if 0                                                                                
                                                                                 
-        print_debug("\r\n***  WATCHDOG TIMER REGISTERS ***\r\n");
+        print_debug("\n***  WATCHDOG TIMER REGISTERS ***\n");
         setup_func(0x0a);
         print_reg(0xf0);
                                                                                 
-        print_debug("\r\n***  FAN CONTROL REGISTERS ***\r\n");
+        print_debug("\n***  FAN CONTROL REGISTERS ***\n");
         setup_func(0x09);
         print_reg(0xf0);
         print_reg(0xf1);
 
-        print_debug("\r\n***  RTC REGISTERS ***\r\n");
+        print_debug("\n***  RTC REGISTERS ***\n");
         setup_func(0x10);
         print_reg(0xf0);
         print_reg(0xf1);
@@ -104,7 +104,7 @@
         print_reg(0xfe);
         print_reg(0xff);
                                                                                 
-        print_debug("\r\n***  HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
+        print_debug("\n***  HEALTH MONITORING & CONTROL REGISTERS ***\n");
         setup_func(0x14);
         print_reg(0xf0);
 #endif                                                                           
@@ -135,7 +135,7 @@
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		print_debug("\r\n");
+		print_debug("\n");
 	}
 }
 
@@ -143,7 +143,7 @@
 {
 	int i;
 	print_debug_pci_dev(dev);
-	print_debug("\r\n");
+	print_debug("\n");
 	
 	for(i = 0; i <= 255; i++) {
 		unsigned char val;
@@ -155,7 +155,7 @@
 		print_debug_char(' ');
 		print_debug_hex8(val);
 		if ((i & 0x0f) == 0x0f) {
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -165,7 +165,7 @@
 	int i;
 	unsigned long bar;
 	
-	print_debug("BAR 14 Dump\r\n");
+	print_debug("BAR 14 Dump\n");
 	
 	bar = pci_read_config32(dev, 0x14);
 	for(i = 0; i <= 0x300; i+=4) {
@@ -178,14 +178,14 @@
 		val = pci_read_config8(dev, i);
 #endif		
 		if((i%4)==0) {
-		print_debug("\r\n");
+		print_debug("\n");
 		print_debug_hex16(i);
 		print_debug_char(' ');
 		}
 		print_debug_hex32(read32(bar + i));
 		print_debug_char(' ');
 	}
-	print_debug("\r\n");
+	print_debug("\n");
 }
 
 static void dump_pci_devices(void)
@@ -209,7 +209,7 @@
 static void dump_spd_registers(const struct mem_controller *ctrl)
 {
 	int i;
-	print_debug("\r\n");
+	print_debug("\n");
 	for(i = 0; i < 4; i++) {
 		unsigned device;
 		device = ctrl->channel0[i];
@@ -223,20 +223,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 		device = ctrl->channel1[i];
 		if (device) {
@@ -249,20 +249,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -275,14 +275,14 @@
         while(device <= SMBUS_MEM_DEVICE_END) {
                 int status = 0;
                 int i;
-        	print_debug("\r\n");
+        	print_debug("\n");
                 print_debug("dimm ");
 		print_debug_hex8(device);
 		
                 for(i = 0; (i < 256) ; i++) {
 	                unsigned char byte;
                         if ((i % 16) == 0) {
-				print_debug("\r\n");
+				print_debug("\n");
 				print_debug_hex8(i);
 				print_debug(": ");
                         }
@@ -290,7 +290,7 @@
                         if (status < 0) {
 			         print_debug("bad device: ");
 				 print_debug_hex8(-status);
-				 print_debug("\r\n");
+				 print_debug("\n");
 			         break; 
 			}
 			print_debug_hex8(status);
@@ -308,7 +308,7 @@
         while(device <= 0x42) {
                 int status = 0;
                 int i;
-        	print_debug("\r\n");
+        	print_debug("\n");
                 print_debug("ipmi ");
 		print_debug_hex8(device);
 		
@@ -318,7 +318,7 @@
                         if (status < 0) {
 			         print_debug("bad device: ");
 				 print_debug_hex8(-status);
-				 print_debug("\r\n");
+				 print_debug("\n");
 			         break; 
 			}
 			print_debug_hex8(status);
Index: src/mainboard/kontron/986lcd-m/debug.c
===================================================================
--- src/mainboard/kontron/986lcd-m/debug.c	(revision 3942)
+++ src/mainboard/kontron/986lcd-m/debug.c	(working copy)
@@ -38,7 +38,7 @@
 		}
 		printk_debug("PCI: %02x:%02x.%02x", (dev >> 20) & 0xff,
 			(dev >> 15) & 0x1f, (dev >> 12) & 7);
-		printk_debug(" [%04x:%04x]\r\n", id &0xffff, id >> 16);
+		printk_debug(" [%04x:%04x]\n", id &0xffff, id >> 16);
 	}
 }
 
@@ -46,7 +46,7 @@
 {
 	int i;
 
-	printk_debug("PCI: %02x:%02x.%02x\r\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
+	printk_debug("PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
 
 	for(i = 0; i <= 255; i++) {
 		unsigned char val;
@@ -56,7 +56,7 @@
 		val = pci_read_config8(dev, i);
 		printk_debug(" %02x", val);
 		if ((i & 0x0f) == 0x0f) {
-			printk_debug("\r\n");
+			printk_debug("\n");
 		}
 	}
 }
@@ -85,21 +85,21 @@
         while(device <= SMBUS_MEM_DEVICE_END) {
                 int status = 0;
                 int i;
-        	printk_debug("\r\ndimm %02x", device);
+        	printk_debug("\ndimm %02x", device);
 		
                 for(i = 0; (i < 256) ; i++) {
                         if ((i % 16) == 0) {
-				printk_debug("\r\n%02x: ", i);
+				printk_debug("\n%02x: ", i);
                         }
 			status = smbus_read_byte(device, i);
                         if (status < 0) {
-			         printk_debug("bad device: %02x\r\n", -status);
+			         printk_debug("bad device: %02x\n", -status);
 			         break; 
 			}
 			printk_debug("%02x ", status);
 		}
 		device += SMBUS_MEM_DEVICE_INC;
-		printk_debug("\r\n");
+		printk_debug("\n");
 	}
 }
 
@@ -110,9 +110,9 @@
         for(i=start;i<end;i++) {
 		if((i & 0xf)==0) {
 #if CONFIG_USE_INIT
-			printk_debug("\r\n%08x:", i);
+			printk_debug("\n%08x:", i);
 #else	
-			print_debug("\r\n");
+			print_debug("\n");
 			print_debug_hex32(i);
 			print_debug(":");
 #endif
@@ -124,5 +124,5 @@
              	print_debug_hex8((unsigned char)*((unsigned char *)i));
 #endif
         }
-        print_debug("\r\n");
+        print_debug("\n");
  }
Index: src/mainboard/kontron/986lcd-m/power_reset_check.c
===================================================================
--- src/mainboard/kontron/986lcd-m/power_reset_check.c	(revision 3942)
+++ src/mainboard/kontron/986lcd-m/power_reset_check.c	(working copy)
@@ -25,7 +25,7 @@
 	uint8_t cmos;
 
 	cmos=cmos_read(RTC_BOOT_BYTE)>>4 ;
-	printk_debug("Boot byte = %x\r\n", cmos);
+	printk_debug("Boot byte = %x\n", cmos);
 
 	if((cmos>2)&&(cmos&1))  full_reset();
 }
Index: src/mainboard/gigabyte/m57sli/apc_auto.c
===================================================================
--- src/mainboard/gigabyte/m57sli/apc_auto.c	(revision 3942)
+++ src/mainboard/gigabyte/m57sli/apc_auto.c	(working copy)
@@ -94,7 +94,7 @@
 	id = get_node_core_id_x();
 
 	//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
-        print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+        print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
 
 	train_ram(id.nodeid, sysinfo, sysinfox);
 
Index: src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
===================================================================
--- src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c	(working copy)
@@ -303,9 +303,9 @@
 	early_usbdebug_direct_init();
 #endif
         console_init();
-        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
+        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\n");
 
-        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
 #if MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@@ -331,7 +331,7 @@
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 
         }
 
@@ -345,7 +345,7 @@
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 
         }
 #endif
@@ -356,7 +356,7 @@
 
         // fidvid change will issue one LDTSTOP and the HT change will be effective too
         if (needs_reset) {
-                print_info("ht reset -\r\n");
+                print_info("ht reset -\n");
               	soft_reset();
         }
         allow_all_aps_stop(bsp_apicid);
Index: src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c
===================================================================
--- src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c	(revision 3942)
+++ src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c	(working copy)
@@ -96,7 +96,7 @@
 	id = get_node_core_id_x();
 
 	//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
-        print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+        print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
 
 	train_ram(id.nodeid, sysinfo, sysinfox);
 
Index: src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c
===================================================================
--- src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c	(working copy)
@@ -291,9 +291,9 @@
 	early_usbdebug_direct_init();
 #endif
         console_init();
-        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
+        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\n");
 
-        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+        print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
 #if MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@@ -319,7 +319,7 @@
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 
         }
 
@@ -333,7 +333,7 @@
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 
         }
 #endif
@@ -343,7 +343,7 @@
 
         // fidvid change will issue one LDTSTOP and the HT change will be effective too
         if (needs_reset) {
-                print_info("ht reset -\r\n");
+                print_info("ht reset -\n");
               	soft_reset();
         }
         allow_all_aps_stop(bsp_apicid);
Index: src/mainboard/digitallogic/msm586seg/auto.c
===================================================================
--- src/mainboard/digitallogic/msm586seg/auto.c	(revision 3942)
+++ src/mainboard/digitallogic/msm586seg/auto.c	(working copy)
@@ -89,7 +89,7 @@
       print_err_hex8(c);
       print_err(" ");
     }
-    print_err("\r\n");
+    print_err("\n");
   }
 }
 
@@ -203,16 +203,16 @@
         uart_init();
         console_init();
 		for(i = 0; i < 100; i++)
-	  print_err("fill usart\r\n");
+	  print_err("fill usart\n");
 		//		while(1)
-		print_err("HI THERE!\r\n");
+		print_err("HI THERE!\n");
 		//			sizemem();
 	staticmem();
 	print_err("c60 is "); print_err_hex16(*(unsigned short *)0xfffefc60); 
 	print_err("\n");
 			
 	//			while(1)
-	print_err("STATIC MEM DONE\r\n");
+	print_err("STATIC MEM DONE\n");
 	outb(0xee, 0x80);
 	print_err("loop forever ...\n");
 
@@ -241,12 +241,12 @@
 #endif
 	
 #if 0
-	print_err("RAM CHECK!\r\n");
+	print_err("RAM CHECK!\n");
 	// Check 16MB of memory @ 0
 	ram_check(0x00000000, 0x01000000);
 #endif
 #if 0
-	print_err("RAM CHECK for 32 MB!\r\n");
+	print_err("RAM CHECK for 32 MB!\n");
 	// Check 32MB of memory @ 0
 	ram_check(0x00000000, 0x02000000);
 #endif
@@ -257,17 +257,17 @@
 	  for(i = 0; i < 0x20000; i++) {
 	    /*
 	      print_err("Set dst "); print_err_hex32((unsigned long) dst); 
-	      print_err(" to "); print_err_hex32(*src); print_err("\r\n");
+	      print_err(" to "); print_err_hex32(*src); print_err("\n");
 	    */
 	    *dst = *src;
-	    //print_err(" dst is now "); print_err_hex32(*dst); print_err("\r\n");
+	    //print_err(" dst is now "); print_err_hex32(*dst); print_err("\n");
 	    dst++, src++;
 	    outb((unsigned char)i, 0x80);
 	  }
 	}
 	dumpmem();
 	outb(0, 0x80);
-	print_err("loop forever\r\n");
+	print_err("loop forever\n");
 	outb(0xdd, 0x80);
         __asm__ volatile(
 			 "movl %0, %%edi\n\t"
@@ -276,7 +276,7 @@
 			 : "a" (0x4000)
 			 ); 
 	
-	print_err("FUCK\r\n");
+	print_err("FUCK\n");
 	
 	while(1);
 #endif
Index: src/mainboard/olpc/btest/auto.c
===================================================================
--- src/mainboard/olpc/btest/auto.c	(revision 3942)
+++ src/mainboard/olpc/btest/auto.c	(working copy)
@@ -95,7 +95,7 @@
 
 	print_debug("computed msr.hi ");
 	print_debug_hex32(msr.hi);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	/* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */
 	/* well, it may be close. It's about 200,000 ticks */
Index: src/mainboard/olpc/rev_a/auto.c
===================================================================
--- src/mainboard/olpc/rev_a/auto.c	(revision 3942)
+++ src/mainboard/olpc/rev_a/auto.c	(working copy)
@@ -95,7 +95,7 @@
 
 	print_debug("computed msr.hi ");
 	print_debug_hex32(msr.hi);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	/* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */
 	/* well, it may be close. It's about 200,000 ticks */
Index: src/mainboard/technologic/ts5300/auto.c
===================================================================
--- src/mainboard/technologic/ts5300/auto.c	(revision 3942)
+++ src/mainboard/technologic/ts5300/auto.c	(working copy)
@@ -57,18 +57,18 @@
 	
 	TS9500_LED_ON;
 
-	print_err("TS-9500 add-on found:\r\n");
+	print_err("TS-9500 add-on found:\n");
 	val=inb(0x19b);
 	for (i=0; i<8; i++) {
 		print_err("  DIP");
 		print_err_char(i+0x31);
 		print_err(": ");
 		if((val&(1<<i))!=0) 
-			print_err("on\r\n"); 
+			print_err("on\n"); 
 		else
-			print_err("off\r\n"); 
+			print_err("off\n"); 
 	}
-	print_err("\r\n");
+	print_err("\n");
 	
 	val=inb(0x19a);
 	
@@ -77,11 +77,11 @@
 		print_err_char(i+0x30-5);
 		print_err(": ");
 		if((val&(1<<i))!=0) 
-			print_err("on\r\n"); 
+			print_err("on\n"); 
 		else
-			print_err("off\r\n"); 
+			print_err("off\n"); 
 	}
-	print_err("\r\n");
+	print_err("\n");
 
 	TS9500_LED_OFF;
 }
@@ -93,29 +93,29 @@
 	print_err("Mainboard: ");
 	val=inb(0x74);
 	switch(val) {
-	case 0x50: print_err("TS-5300\r\n"); break;
-	case 0x40: print_err("TS-5400\r\n"); break;
-	case 0x60: print_err("TS-5500\r\n"); break;
-	case 0x20: print_err("TS-5600\r\n"); break;
-	case 0x70: print_err("TS-5700\r\n"); break;
-	default:   print_err("unknown\r\n"); break;
+	case 0x50: print_err("TS-5300\n"); break;
+	case 0x40: print_err("TS-5400\n"); break;
+	case 0x60: print_err("TS-5500\n"); break;
+	case 0x20: print_err("TS-5600\n"); break;
+	case 0x70: print_err("TS-5700\n"); break;
+	default:   print_err("unknown\n"); break;
 	}
 
 	val=inb(0x75);
 	print_err("  SRAM option:   ");
 	if((val&1)==0) print_err("not ");
-	print_err("installed\r\n");
+	print_err("installed\n");
 	
 	print_err("  RS-485 option: ");
 	if((val&2)==0) print_err("not ");
-	print_err("installed\r\n");
+	print_err("installed\n");
 
 	val=inb(0x76);
 	print_err("  Temp. range:   ");
-	if((val&2)==0) print_err("commercial\r\n"); 
-	else print_err("industrial\r\n");
+	if((val&2)==0) print_err("commercial\n"); 
+	else print_err("industrial\n");
 	
-	print_err("\r\n");
+	print_err("\n");
 	
 	val=inb(0x77);
 	for (i=1; i<8; i++) {
@@ -123,11 +123,11 @@
 		print_err_char(i+0x30);
 		print_err(": ");
 		if((val&(1<<i))!=0) 
-			print_err("on\r\n"); 
+			print_err("on\n"); 
 		else
-			print_err("off\r\n"); 
+			print_err("off\n"); 
 	}
-	print_err("\r\n");
+	print_err("\n");
 
 	/* Detect TS-9500 */
 	val=inb(0x19d);
@@ -158,9 +158,9 @@
         console_init();
 	
 	
-	print_err("Technologic Systems TS5300 - http://www.embeddedx86.com/\r\n");
+	print_err("Technologic Systems TS5300 - http://www.embeddedx86.com/\n");
 	staticmem();
-	print_err("Memory initialized: 32MB\r\n");
+	print_err("Memory initialized: 32MB\n");
 
 #if 1
 	identify_system();
@@ -168,7 +168,7 @@
 
 #if 0
 	// Check 32MB of memory @ 0 (very slow!)
-	print_err("Checking memory:\r\n");
+	print_err("Checking memory:\n");
 	ram_check(0x00000000, 0x000a0000);
 	ram_check(0x000b0000, 0x02000000);
 #endif
Index: src/mainboard/amd/pistachio/cache_as_ram_auto.c
===================================================================
--- src/mainboard/amd/pistachio/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/amd/pistachio/cache_as_ram_auto.c	(working copy)
@@ -230,7 +230,7 @@
 	post_code(0x06);
 
 	if (needs_reset) {
-		print_info("ht reset -\r\n");
+		print_info("ht reset -\n");
 		soft_reset();
 	}
 
Index: src/mainboard/amd/dbm690t/cache_as_ram_auto.c
===================================================================
--- src/mainboard/amd/dbm690t/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/amd/dbm690t/cache_as_ram_auto.c	(working copy)
@@ -226,7 +226,7 @@
 
 
 	if (needs_reset) {
-		print_info("ht reset -\r\n");
+		print_info("ht reset -\n");
 		soft_reset();
 	}
 
Index: src/mainboard/amd/rumba/auto.c
===================================================================
--- src/mainboard/amd/rumba/auto.c	(revision 3942)
+++ src/mainboard/amd/rumba/auto.c	(working copy)
@@ -52,7 +52,7 @@
 	/* get module banks (sides) per dimm, SPD byte 5 */
 	module_banks = spd_read_byte(0xA0, 5);
 	if (module_banks < 1 || module_banks > 2)
-		print_err("Module banks per dimm\r\n");
+		print_err("Module banks per dimm\n");
 	module_banks >>= 1;
 	msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
 	msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
@@ -60,7 +60,7 @@
 	/* get component banks per module bank, SPD byte 17 */
 	val = spd_read_byte(0xA0, 17);
 	if (val < 2 || val > 4)
-		print_err("Component banks per module bank\r\n");
+		print_err("Component banks per module bank\n");
 	val >>= 2;
 	msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
 	msr.hi |=  (val << CF07_UPPER_D0_CB_SHIFT);
@@ -80,7 +80,7 @@
 
 	print_debug("computed msr.hi ");
 	print_debug_hex32(msr.hi);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	msr.lo = 0x00003000;
 	wrmsr(MC_CF07_DATA, msr);
Index: src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c	(working copy)
@@ -105,14 +105,14 @@
 {
 #define SMBUS_HUB 0x18
         int ret, i;
-        print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n");
+        print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
         i=2;
         do {
                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
-                print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
+                print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
         } while ((ret!=0) && (i-->0));
         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
-        print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
+        print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
 }
 #endif
 
@@ -276,7 +276,7 @@
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
+        print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\n");
 
         setup_mb_resource_map();
 #if 0
@@ -284,7 +284,7 @@
 	dump_pci_device(PCI_DEV(0, 0x19, 0));
 #endif
 
-	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
 #if MEM_TRAIN_SEQ == 1
         set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram 
@@ -321,7 +321,7 @@
 		/* Read FIDVID_STATUS */
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 
         }
 
@@ -335,7 +335,7 @@
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); 
+                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); 
 
         }
 
@@ -351,7 +351,7 @@
 
         // fidvid change will issue one LDTSTOP and the HT change will be effective too
         if (needs_reset) {
-                print_info("ht reset -\r\n");
+                print_info("ht reset -\n");
                 soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
         }
 #endif
Index: src/mainboard/amd/serengeti_cheetah/apc_auto.c
===================================================================
--- src/mainboard/amd/serengeti_cheetah/apc_auto.c	(revision 3942)
+++ src/mainboard/amd/serengeti_cheetah/apc_auto.c	(working copy)
@@ -76,7 +76,7 @@
 #if CONFIG_USE_PRINTK_IN_CAR
         printk_debug("CODE IN CACHE ON NODE: %02x\n");
 #else
-        print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+        print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
 #endif
 
 	train_ram(id.nodeid, sysinfo, sysinfox);
Index: src/mainboard/pcengines/alix1c/cache_as_ram_auto.c
===================================================================
--- src/mainboard/pcengines/alix1c/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/pcengines/alix1c/cache_as_ram_auto.c	(working copy)
@@ -100,7 +100,7 @@
 	print_debug_hex8(address);
 	print_debug(" returns ");
 	print_debug_hex8(spdbytes[address]);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	return spdbytes[address];
 }
Index: src/mainboard/tyan/s2912/apc_auto.c
===================================================================
--- src/mainboard/tyan/s2912/apc_auto.c	(revision 3942)
+++ src/mainboard/tyan/s2912/apc_auto.c	(working copy)
@@ -83,7 +83,7 @@
 	id = get_node_core_id_x();
 
 	//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
-	print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+	print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
 
 	train_ram(id.nodeid, sysinfo, sysinfox);
 
Index: src/mainboard/tyan/s2912/cache_as_ram_auto.c
===================================================================
--- src/mainboard/tyan/s2912/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/tyan/s2912/cache_as_ram_auto.c	(working copy)
@@ -286,9 +286,9 @@
 	early_usbdebug_direct_init();
 #endif
 	console_init();
-	print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
+	print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\n");
 
-	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
 #if MEM_TRAIN_SEQ == 1
 	set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@@ -314,7 +314,7 @@
 	{
 		msr_t msr;
 		msr=rdmsr(0xc0010042);
-		print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+		print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 
 	}
 
@@ -328,7 +328,7 @@
 	{
 		msr_t msr;
 		msr=rdmsr(0xc0010042);
-		print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+		print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 
 	}
 #endif
@@ -339,7 +339,7 @@
 
 	// fidvid change will issue one LDTSTOP and the HT change will be effective too
 	if (needs_reset) {
-		print_info("ht reset -\r\n");
+		print_info("ht reset -\n");
 	      	soft_reset();
 	}
 
Index: src/mainboard/tyan/s2850/auto.c
===================================================================
--- src/mainboard/tyan/s2850/auto.c	(revision 3942)
+++ src/mainboard/tyan/s2850/auto.c	(working copy)
@@ -192,7 +192,7 @@
 #endif
 	needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
 	if (needs_reset) {
-		print_info("ht reset -\r\n");
+		print_info("ht reset -\n");
 		soft_reset();
 	}
 	enable_smbus();
Index: src/mainboard/tyan/s2850/cache_as_ram_auto.c
===================================================================
--- src/mainboard/tyan/s2850/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/tyan/s2850/cache_as_ram_auto.c	(working copy)
@@ -200,7 +200,7 @@
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\r\n");
+               	print_info("ht reset -\n");
                	soft_reset();
        	}
 
Index: src/mainboard/tyan/s2735/auto.c
===================================================================
--- src/mainboard/tyan/s2735/auto.c	(revision 3942)
+++ src/mainboard/tyan/s2735/auto.c	(working copy)
@@ -128,7 +128,7 @@
 	print_debug("TOP_MEM2: ");
 	print_debug_hex32(msr.hi);
 	print_debug_hex32(msr.lo);
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 
 #if 0
Index: src/mainboard/tyan/s2735/cache_as_ram_auto.c
===================================================================
--- src/mainboard/tyan/s2735/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/tyan/s2735/cache_as_ram_auto.c	(working copy)
@@ -193,9 +193,9 @@
 	                : "=a" (v_esp)
 	        );
 #if CONFIG_USE_INIT
-	        printk_debug("v_esp=%08x\r\n", v_esp);
+	        printk_debug("v_esp=%08x\n", v_esp);
 #else
-	        print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\r\n");
+	        print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\n");
 #endif
         }
 
@@ -205,9 +205,9 @@
 cpu_reset_x:
 
 #if CONFIG_USE_INIT
-        printk_debug("cpu_reset = %08x\r\n",cpu_reset);
+        printk_debug("cpu_reset = %08x\n",cpu_reset);
 #else
-        print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\r\n");
+        print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\n");
 #endif
 
 	if(cpu_reset == 0) {
@@ -248,15 +248,15 @@
 
                 /* We can not go back any more, we lost old stack data in cache as ram*/
                 if(new_cpu_reset==0) {
-                        print_debug("Use Ram as Stack now - done\r\n");
+                        print_debug("Use Ram as Stack now - done\n");
                 } else
                 {  
-                        print_debug("Use Ram as Stack now - \r\n");
+                        print_debug("Use Ram as Stack now - \n");
                 }
 #if CONFIG_USE_INIT
-                printk_debug("new_cpu_reset = %08x\r\n", new_cpu_reset);
+                printk_debug("new_cpu_reset = %08x\n", new_cpu_reset);
 #else
-                print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\r\n");
+                print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\n");
 #endif
 	
 		/*copy and execute coreboot_ram */
@@ -266,6 +266,6 @@
 #endif
 
 
-	print_debug("should not be here -\r\n");
+	print_debug("should not be here -\n");
 
 }
Index: src/mainboard/tyan/s2880/auto.c
===================================================================
--- src/mainboard/tyan/s2880/auto.c	(revision 3942)
+++ src/mainboard/tyan/s2880/auto.c	(working copy)
@@ -166,7 +166,7 @@
 
         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
         if (needs_reset) {
-                print_info("ht reset -\r\n");
+                print_info("ht reset -\n");
                 soft_reset();
         }
 	
Index: src/mainboard/tyan/s2880/cache_as_ram_auto.c
===================================================================
--- src/mainboard/tyan/s2880/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/tyan/s2880/cache_as_ram_auto.c	(working copy)
@@ -199,7 +199,7 @@
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\r\n");
+               	print_info("ht reset -\n");
                	soft_reset();
        	}
 
Index: src/mainboard/tyan/s2881/auto.c
===================================================================
--- src/mainboard/tyan/s2881/auto.c	(revision 3942)
+++ src/mainboard/tyan/s2881/auto.c	(working copy)
@@ -167,7 +167,7 @@
         // automatically set that for you, but you might meet tight space
         needs_reset |= ht_setup_chains_x();
         if (needs_reset) {
-                print_info("ht reset -\r\n");
+                print_info("ht reset -\n");
                 soft_reset();
         }
 	
Index: src/mainboard/tyan/s2881/cache_as_ram_auto.c
===================================================================
--- src/mainboard/tyan/s2881/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/tyan/s2881/cache_as_ram_auto.c	(working copy)
@@ -213,7 +213,7 @@
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\r\n");
+               	print_info("ht reset -\n");
                	soft_reset();
        	}
 
Index: src/mainboard/tyan/s4880/auto.c
===================================================================
--- src/mainboard/tyan/s4880/auto.c	(revision 3942)
+++ src/mainboard/tyan/s4880/auto.c	(working copy)
@@ -218,7 +218,7 @@
         needs_reset |= ht_setup_chains_x();
 	
         if (needs_reset) {
-                print_info("ht reset -\r\n");
+                print_info("ht reset -\n");
                 soft_reset();
         }
 	
Index: src/mainboard/tyan/s4880/cache_as_ram_auto.c
===================================================================
--- src/mainboard/tyan/s4880/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/tyan/s4880/cache_as_ram_auto.c	(working copy)
@@ -71,11 +71,11 @@
 {
 #define SMBUS_HUB 0x18
         int ret;
-        print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); 
+        print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); 
         ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
-        print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
+        print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
-        print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
+        print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
 }
 #endif
 
@@ -248,7 +248,7 @@
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\r\n");
+               	print_info("ht reset -\n");
                	soft_reset();
        	}
 
Index: src/mainboard/tyan/s2891/auto.c
===================================================================
--- src/mainboard/tyan/s2891/auto.c	(revision 3942)
+++ src/mainboard/tyan/s2891/auto.c	(working copy)
@@ -139,7 +139,7 @@
 	needs_reset |= ck804_early_setup_x();
 
 	if (needs_reset) {
-		print_info("ht reset -\r\n");
+		print_info("ht reset -\n");
 		soft_reset();
 	}
 
Index: src/mainboard/tyan/s2891/cache_as_ram_auto.c
===================================================================
--- src/mainboard/tyan/s2891/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/tyan/s2891/cache_as_ram_auto.c	(working copy)
@@ -224,7 +224,7 @@
 	needs_reset |= ck804_early_setup_x();
 
 	if (needs_reset) {
-		print_info("ht reset -\r\n");
+		print_info("ht reset -\n");
 	//	soft_reset();
 	}
 
Index: src/mainboard/tyan/s2882/auto.c
===================================================================
--- src/mainboard/tyan/s2882/auto.c	(revision 3942)
+++ src/mainboard/tyan/s2882/auto.c	(working copy)
@@ -171,7 +171,7 @@
         needs_reset = setup_coherent_ht_domain();
         needs_reset |= ht_setup_chains_x();
         if (needs_reset) {
-                print_info("ht reset -\r\n");
+                print_info("ht reset -\n");
                 soft_reset();
         }	
 	enable_smbus();
Index: src/mainboard/tyan/s2882/cache_as_ram_auto.c
===================================================================
--- src/mainboard/tyan/s2882/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/tyan/s2882/cache_as_ram_auto.c	(working copy)
@@ -202,7 +202,7 @@
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\r\n");
+               	print_info("ht reset -\n");
                	soft_reset();
        	}
 
Index: src/mainboard/tyan/s2892/auto.c
===================================================================
--- src/mainboard/tyan/s2892/auto.c	(revision 3942)
+++ src/mainboard/tyan/s2892/auto.c	(working copy)
@@ -141,7 +141,7 @@
 	needs_reset |= ck804_early_setup_x();
 
 	if (needs_reset) {
-		print_info("ht reset -\r\n");
+		print_info("ht reset -\n");
 		soft_reset();
 	}
 
Index: src/mainboard/tyan/s2892/cache_as_ram_auto.c
===================================================================
--- src/mainboard/tyan/s2892/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/tyan/s2892/cache_as_ram_auto.c	(working copy)
@@ -218,7 +218,7 @@
 	needs_reset |= ck804_early_setup_x();
 
 	if (needs_reset) {
-		print_info("ht reset -\r\n");
+		print_info("ht reset -\n");
 		soft_reset();
 	}
 
Index: src/mainboard/tyan/s4882/auto.c
===================================================================
--- src/mainboard/tyan/s4882/auto.c	(revision 3942)
+++ src/mainboard/tyan/s4882/auto.c	(working copy)
@@ -221,7 +221,7 @@
 
         needs_reset |= ht_setup_chains_x();
         if (needs_reset) {
-                print_info("ht reset -\r\n");
+                print_info("ht reset -\n");
                 soft_reset();
         }
 	
Index: src/mainboard/tyan/s4882/cache_as_ram_auto.c
===================================================================
--- src/mainboard/tyan/s4882/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/tyan/s4882/cache_as_ram_auto.c	(working copy)
@@ -76,14 +76,14 @@
 {
 #define SMBUS_HUB 0x18
         int ret, i;
-        print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); 
+        print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); 
         i=2;
         do {
                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
-                print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n");
+                print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
         } while ((ret!=0) && (i-->0));
         ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
-        print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n");
+        print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
 }
 #endif
 
@@ -231,7 +231,7 @@
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\r\n");
+               	print_info("ht reset -\n");
                	soft_reset();
        	}
 
Index: src/mainboard/tyan/s2875/auto.c
===================================================================
--- src/mainboard/tyan/s2875/auto.c	(revision 3942)
+++ src/mainboard/tyan/s2875/auto.c	(working copy)
@@ -162,7 +162,7 @@
 
         needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
         if (needs_reset) {
-                print_info("ht reset -\r\n");
+                print_info("ht reset -\n");
                 soft_reset();
         }
 
Index: src/mainboard/tyan/s2875/cache_as_ram_auto.c
===================================================================
--- src/mainboard/tyan/s2875/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/tyan/s2875/cache_as_ram_auto.c	(working copy)
@@ -197,7 +197,7 @@
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\r\n");
+               	print_info("ht reset -\n");
                	soft_reset();
        	}
 
Index: src/mainboard/tyan/s2885/auto.c
===================================================================
--- src/mainboard/tyan/s2885/auto.c	(revision 3942)
+++ src/mainboard/tyan/s2885/auto.c	(working copy)
@@ -173,7 +173,7 @@
         needs_reset |= ht_setup_chains_x();
 
         if (needs_reset) {
-                print_info("ht reset -\r\n");
+                print_info("ht reset -\n");
                 soft_reset();
         }
 
Index: src/mainboard/tyan/s2885/cache_as_ram_auto.c
===================================================================
--- src/mainboard/tyan/s2885/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/tyan/s2885/cache_as_ram_auto.c	(working copy)
@@ -215,7 +215,7 @@
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\r\n");
+               	print_info("ht reset -\n");
                	soft_reset();
        	}
 
Index: src/mainboard/tyan/s2895/auto.c
===================================================================
--- src/mainboard/tyan/s2895/auto.c	(revision 3942)
+++ src/mainboard/tyan/s2895/auto.c	(working copy)
@@ -166,7 +166,7 @@
 	needs_reset |= ck804_early_setup_x();
 
 	if (needs_reset) {
-		print_info("ht reset -\r\n");
+		print_info("ht reset -\n");
 		soft_reset();
 	}
 
Index: src/mainboard/tyan/s2895/cache_as_ram_auto.c
===================================================================
--- src/mainboard/tyan/s2895/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/tyan/s2895/cache_as_ram_auto.c	(working copy)
@@ -280,7 +280,7 @@
 	needs_reset |= ck804_early_setup_x();
 
 	if (needs_reset) {
-		print_info("ht reset -\r\n");
+		print_info("ht reset -\n");
 	//	soft_reset();
 	}
 
Index: src/mainboard/tyan/s2912_fam10/apc_auto.c
===================================================================
--- src/mainboard/tyan/s2912_fam10/apc_auto.c	(revision 3942)
+++ src/mainboard/tyan/s2912_fam10/apc_auto.c	(working copy)
@@ -83,7 +83,7 @@
 	id = get_node_core_id_x();
 
 	//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
-	print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+	print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
 
 	train_ram(id.nodeid, sysinfo, sysinfox);
 
Index: src/mainboard/lippert/frontrunner/auto.c
===================================================================
--- src/mainboard/lippert/frontrunner/auto.c	(revision 3942)
+++ src/mainboard/lippert/frontrunner/auto.c	(working copy)
@@ -26,7 +26,7 @@
 	msr_t msr;
 	/* 1. Initialize GLMC registers base on SPD values,
 	 * Hard coded as XpressROM for now */
-	//print_debug("sdram_enable step 1\r\n");
+	//print_debug("sdram_enable step 1\n");
 	msr = rdmsr(0x20000018);
 	msr.hi = 0x10076013;
 	msr.lo = 0x3400;
Index: src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c
===================================================================
--- src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/lippert/spacerunner-lx/cache_as_ram_auto.c	(working copy)
@@ -93,7 +93,7 @@
 	if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
 		print_err("ERROR: spd_read_byte(DIMM0, 0x");
 		print_err_hex8(address);
-		print_err(") returns 0xff\r\n");
+		print_err(") returns 0xff\n");
 	}
 #endif
 
@@ -224,7 +224,7 @@
 	if ((err = smc_send_config(SMC_CONFIG))) {
 		print_err("ERROR ");
 		print_err_char('0'+err);
-		print_err(" sending config data to SMC\r\n");
+		print_err(" sending config data to SMC\n");
 	}
 
 	sdram_initialize(1, memctrl);
Index: src/mainboard/via/epia-m/auto.c
===================================================================
--- src/mainboard/via/epia-m/auto.c	(revision 3942)
+++ src/mainboard/via/epia-m/auto.c	(working copy)
@@ -114,7 +114,7 @@
 
 	enable_smbus();
 
-	print_spew("In auto.c:main()\r\n");
+	print_spew("In auto.c:main()\n");
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
@@ -123,10 +123,10 @@
 
 	outb(5, 0x80);	
 
-	print_debug(" Enabling mainboard devices\r\n");
+	print_debug(" Enabling mainboard devices\n");
 	enable_mainboard_devices();
 
-	print_debug(" Enabling shadow ram\r\n");
+	print_debug(" Enabling shadow ram\n");
 	enable_shadow_ram();
 
 	ddr_ram_setup((const struct mem_controller *)0);
@@ -153,11 +153,11 @@
 #endif
 
 	if (bist == 0) {
-		print_debug(" Doing MTRR init.\r\n");
+		print_debug(" Doing MTRR init.\n");
 		early_mtrr_init();
 	}
 
 	//dump_pci_devices();
 	
-	print_spew("Leaving auto.c:main()\r\n");
+	print_spew("Leaving auto.c:main()\n");
 }
Index: src/mainboard/via/epia-cn/auto.c
===================================================================
--- src/mainboard/via/epia-cn/auto.c	(revision 3942)
+++ src/mainboard/via/epia-cn/auto.c	(working copy)
@@ -100,25 +100,25 @@
 	uart_init();
 	console_init();
 
-	print_spew("In auto.c:main()\r\n");
+	print_spew("In auto.c:main()\n");
 
 	enable_smbus();
 	smbus_fixup(&ctrl);
 
 	if (bist == 0) {
-		print_debug("doing early_mtrr\r\n");
+		print_debug("doing early_mtrr\n");
 		early_mtrr_init();
 	}
 
 	/* Halt if there was a built-in self test failure. */
 	report_bist_failure(bist);
 
-	print_debug("Enabling mainboard devices\r\n");
+	print_debug("Enabling mainboard devices\n");
 	enable_mainboard_devices();
 
 	ddr_ram_setup(&ctrl);
 
 	/* ram_check(0, 640 * 1024); */
 
-	print_spew("Leaving auto.c:main()\r\n");
+	print_spew("Leaving auto.c:main()\n");
 }
Index: src/mainboard/dell/s1850/watchdog.c
===================================================================
--- src/mainboard/dell/s1850/watchdog.c	(revision 3942)
+++ src/mainboard/dell/s1850/watchdog.c	(working copy)
@@ -52,6 +52,6 @@
 {
 //	disable_sio_watchdog(NSC_WD_DEV);
 	disable_ich5_watchdog();
-	print_debug("Watchdogs disabled\r\n");
+	print_debug("Watchdogs disabled\n");
 }
 
Index: src/mainboard/dell/s1850/debug.c
===================================================================
--- src/mainboard/dell/s1850/debug.c	(revision 3942)
+++ src/mainboard/dell/s1850/debug.c	(working copy)
@@ -12,7 +12,7 @@
 	print_debug_hex8(index);
 	print_debug(": 0x");
 	print_debug_hex8(data);
-	print_debug("\r\n");
+	print_debug("\n");
         return;
 }
         
@@ -49,52 +49,52 @@
         int i;
         unsigned char data;
        
-	 print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
+	 print_debug("\n*** SERVER I/O REGISTERS ***\n");
         for (i=0x10; i<=0x2d; i++) {
                 print_reg((unsigned char)i);
         }
 #if 0                                                                         
-        print_debug("\r\n*** XBUS REGISTERS ***\r\n");
+        print_debug("\n*** XBUS REGISTERS ***\n");
         setup_func(0x0f);
         for (i=0xf0; i<=0xff; i++) {
                 print_reg((unsigned char)i);
         }
                                                                                 
-        print_debug("\r\n***  SERIAL 1 CONFIG REGISTERS ***\r\n");
+        print_debug("\n***  SERIAL 1 CONFIG REGISTERS ***\n");
         setup_func(0x03);
         print_reg(0xf0);
                                                                                 
-        print_debug("\r\n***  SERIAL 2 CONFIG REGISTERS ***\r\n");
+        print_debug("\n***  SERIAL 2 CONFIG REGISTERS ***\n");
         setup_func(0x02);
         print_reg(0xf0);
 
 #endif
-        print_debug("\r\n***  GPIO REGISTERS ***\r\n");
+        print_debug("\n***  GPIO REGISTERS ***\n");
         setup_func(0x07);
         for (i=0xf0; i<=0xf8; i++) {
                 print_reg((unsigned char)i);
         }
-        print_debug("\r\n***  GPIO VALUES ***\r\n");
+        print_debug("\n***  GPIO VALUES ***\n");
         data = inb(0x68a);
-	print_debug("\r\nGPDO 4: 0x");
+	print_debug("\nGPDO 4: 0x");
 	print_debug_hex8(data);
         data = inb(0x68b);
-	print_debug("\r\nGPDI 4: 0x");
+	print_debug("\nGPDI 4: 0x");
 	print_debug_hex8(data);
-	print_debug("\r\n");
+	print_debug("\n");
 	
 #if 0                                                                                
                                                                                 
-        print_debug("\r\n***  WATCHDOG TIMER REGISTERS ***\r\n");
+        print_debug("\n***  WATCHDOG TIMER REGISTERS ***\n");
         setup_func(0x0a);
         print_reg(0xf0);
                                                                                 
-        print_debug("\r\n***  FAN CONTROL REGISTERS ***\r\n");
+        print_debug("\n***  FAN CONTROL REGISTERS ***\n");
         setup_func(0x09);
         print_reg(0xf0);
         print_reg(0xf1);
 
-        print_debug("\r\n***  RTC REGISTERS ***\r\n");
+        print_debug("\n***  RTC REGISTERS ***\n");
         setup_func(0x10);
         print_reg(0xf0);
         print_reg(0xf1);
@@ -104,7 +104,7 @@
         print_reg(0xfe);
         print_reg(0xff);
                                                                                 
-        print_debug("\r\n***  HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
+        print_debug("\n***  HEALTH MONITORING & CONTROL REGISTERS ***\n");
         setup_func(0x14);
         print_reg(0xf0);
 #endif                                                                           
@@ -135,7 +135,7 @@
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		print_debug("\r\n");
+		print_debug("\n");
 	}
 }
 
@@ -143,7 +143,7 @@
 {
 	int i;
 	print_debug_pci_dev(dev);
-	print_debug("\r\n");
+	print_debug("\n");
 	
 	for(i = 0; i <= 255; i++) {
 		unsigned char val;
@@ -155,7 +155,7 @@
 		print_debug_char(' ');
 		print_debug_hex8(val);
 		if ((i & 0x0f) == 0x0f) {
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -165,7 +165,7 @@
 	int i;
 	unsigned long bar;
 	
-	print_debug("BAR 14 Dump\r\n");
+	print_debug("BAR 14 Dump\n");
 	
 	bar = pci_read_config32(dev, 0x14);
 	for(i = 0; i <= 0x300; i+=4) {
@@ -178,14 +178,14 @@
 		val = pci_read_config8(dev, i);
 #endif		
 		if((i%4)==0) {
-		print_debug("\r\n");
+		print_debug("\n");
 		print_debug_hex16(i);
 		print_debug_char(' ');
 		}
 		print_debug_hex32(read32(bar + i));
 		print_debug_char(' ');
 	}
-	print_debug("\r\n");
+	print_debug("\n");
 }
 
 static void dump_pci_devices(void)
@@ -209,7 +209,7 @@
 static void dump_spd_registers(const struct mem_controller *ctrl)
 {
 	int i;
-	print_debug("\r\n");
+	print_debug("\n");
 	for(i = 0; i < 4; i++) {
 		unsigned device;
 		device = ctrl->channel0[i];
@@ -223,20 +223,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 		device = ctrl->channel1[i];
 		if (device) {
@@ -249,20 +249,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -275,14 +275,14 @@
         while(device <= SMBUS_MEM_DEVICE_END) {
                 int status = 0;
                 int i;
-        	print_debug("\r\n");
+        	print_debug("\n");
                 print_debug("dimm ");
 		print_debug_hex8(device);
 		
                 for(i = 0; (i < 256) ; i++) {
 	                unsigned char byte;
                         if ((i % 16) == 0) {
-				print_debug("\r\n");
+				print_debug("\n");
 				print_debug_hex8(i);
 				print_debug(": ");
                         }
@@ -290,7 +290,7 @@
                         if (status < 0) {
 			         print_debug("bad device: ");
 				 print_debug_hex8(-status);
-				 print_debug("\r\n");
+				 print_debug("\n");
 			         break; 
 			}
 			print_debug_hex8(status);
@@ -308,7 +308,7 @@
         while(device <= 0x42) {
                 int status = 0;
                 int i;
-        	print_debug("\r\n");
+        	print_debug("\n");
                 print_debug("ipmi ");
 		print_debug_hex8(device);
 		
@@ -318,7 +318,7 @@
                         if (status < 0) {
 			         print_debug("bad device: ");
 				 print_debug_hex8(-status);
-				 print_debug("\r\n");
+				 print_debug("\n");
 			         break; 
 			}
 			print_debug_hex8(status);
Index: src/mainboard/msi/ms7135/cache_as_ram_auto.c
===================================================================
--- src/mainboard/msi/ms7135/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/msi/ms7135/cache_as_ram_auto.c	(working copy)
@@ -246,7 +246,7 @@
 	needs_reset |= ck804_early_setup_x();
 
 	if (needs_reset) {
-		print_info("ht reset -\r\n");
+		print_info("ht reset -\n");
 		soft_reset();
 	}
 
Index: src/mainboard/msi/ms9282/cache_as_ram_auto.c
===================================================================
--- src/mainboard/msi/ms9282/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/msi/ms9282/cache_as_ram_auto.c	(working copy)
@@ -270,7 +270,7 @@
         needs_reset |= mcp55_early_setup_x();
 
                if (needs_reset) {
-                       print_info("ht reset -\r\n");
+                       print_info("ht reset -\n");
                        soft_reset();
                }
 
Index: src/mainboard/msi/ms9185/cache_as_ram_auto.c
===================================================================
--- src/mainboard/msi/ms9185/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/msi/ms9185/cache_as_ram_auto.c	(working copy)
@@ -259,7 +259,7 @@
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);
 
-       print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
+       print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\n");
 
        setup_ms9185_resource_map();
 #if 0
@@ -267,7 +267,7 @@
        dump_pci_device(PCI_DEV(0, 0x19, 0));
 #endif
 
-       print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+       print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
        setup_coherent_ht_domain();
 
@@ -299,7 +299,7 @@
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+                print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 
         }
 
@@ -313,7 +313,7 @@
         {
                 msr_t msr;
                 msr=rdmsr(0xc0010042);
-                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+                print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 
         }
 #endif
@@ -324,7 +324,7 @@
 
         // fidvid change will issue one LDTSTOP and the HT change will be effective too
         if (needs_reset) {
-                print_info("ht reset -\r\n");
+                print_info("ht reset -\n");
                 soft_reset();
         }
 #endif
Index: src/mainboard/msi/ms7260/apc_auto.c
===================================================================
--- src/mainboard/msi/ms7260/apc_auto.c	(revision 3942)
+++ src/mainboard/msi/ms7260/apc_auto.c	(working copy)
@@ -74,7 +74,7 @@
 	 */
 	print_debug("CODE IN CACHE ON NODE:");
 	print_debug_hex8(id.nodeid);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	train_ram(id.nodeid, sysinfo, sysinfox);
 
Index: src/mainboard/msi/ms7260/cache_as_ram_auto.c
===================================================================
--- src/mainboard/msi/ms7260/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/msi/ms7260/cache_as_ram_auto.c	(working copy)
@@ -264,11 +264,11 @@
 	print_debug_hex32(sysinfo);
 	print_debug(",");
 	print_debug_hex32((unsigned long)sysinfo + sizeof(struct sys_info));
-	print_debug(")\r\n");
+	print_debug(")\n");
 
 	print_debug("bsp_apicid=");
 	print_debug_hex8(bsp_apicid);
-	print_debug("\r\n");
+	print_debug("\n");
 
 #if MEM_TRAIN_SEQ == 1
 	/* In BSP so could hold all AP until sysinfo is in RAM. */
@@ -298,7 +298,7 @@
 		print_debug("begin msr fid, vid ");
 		print_debug_hex32(msr.hi);
 		print_debug_hex32(msr.lo);
-		print_debug("\r\n");
+		print_debug("\n");
 	}
 
 	enable_fid_change();
@@ -310,7 +310,7 @@
 		print_debug("end   msr fid, vid ");
 		print_debug_hex32(msr.hi);
 		print_debug_hex32(msr.lo);
-		print_debug("\r\n");
+		print_debug("\n");
 	}
 #endif
 
@@ -320,7 +320,7 @@
 
 	/* fidvid change will issue one LDTSTOP and the HT change will be effective too. */
 	if (needs_reset) {
-		print_info("ht reset -\r\n");
+		print_info("ht reset -\n");
 		soft_reset();
 	}
 	allow_all_aps_stop(bsp_apicid);
Index: src/mainboard/arima/hdama/debug.c
===================================================================
--- src/mainboard/arima/hdama/debug.c	(revision 3942)
+++ src/mainboard/arima/hdama/debug.c	(working copy)
@@ -23,7 +23,7 @@
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		print_debug("\r\n");
+		print_debug("\n");
 	}
 }
 
@@ -31,7 +31,7 @@
 {
 	int i;
 	print_debug_pci_dev(dev);
-	print_debug("\r\n");
+	print_debug("\n");
 	
 	for(i = 0; i <= 255; i++) {
 		unsigned char val;
@@ -43,7 +43,7 @@
 		print_debug_char(' ');
 		print_debug_hex8(val);
 		if ((i & 0x0f) == 0x0f) {
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -70,7 +70,7 @@
 	int n;
 	for(n = 0; n < controllers; n++) {
 		int i;
-		print_debug("\r\n");
+		print_debug("\n");
 		activate_spd_rom(&ctrl[n]);
 		for(i = 0; i < 4; i++) {
 			unsigned device;
@@ -87,13 +87,13 @@
 					int status;
 					unsigned char byte;
 					if ((j & 0xf) == 0) {
-						print_debug("\r\n");
+						print_debug("\n");
 						print_debug_hex8(j);
 						print_debug(": ");
 					}
 					status = spd_read_byte(device, j);
 					if (status < 0) {
-						print_debug("bad device\r\n");
+						print_debug("bad device\n");
 						break;
 					}
 #if 0
@@ -104,7 +104,7 @@
 #endif
 					print_debug_char(' ');
 				}
-				print_debug("\r\n");
+				print_debug("\n");
 			}
 			device = ctrl[n].channel1[i];
 			if (device) {
@@ -119,13 +119,13 @@
 					int status;
 					unsigned char byte;
 					if ((j & 0xf) == 0) {
-						print_debug("\r\n");
+						print_debug("\n");
 						print_debug_hex8(j);
 						print_debug(": ");
 					}
 					status = spd_read_byte(device, j);
 					if (status < 0) {
-						print_debug("bad device\r\n");
+						print_debug("bad device\n");
 						break;
 					}
 #if 0
@@ -136,7 +136,7 @@
 #endif
 					print_debug_char(' ');
 				}
-				print_debug("\r\n");
+				print_debug("\n");
 			}
 		}
 	}
Index: src/mainboard/arima/hdama/auto.c
===================================================================
--- src/mainboard/arima/hdama/auto.c	(revision 3942)
+++ src/mainboard/arima/hdama/auto.c	(working copy)
@@ -150,7 +150,7 @@
 	needs_reset = setup_coherent_ht_domain();
 	needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
 	if (needs_reset) {
-		print_info("ht reset -\r\n");
+		print_info("ht reset -\n");
 		soft_reset();
 	}
 #if 0
Index: src/mainboard/arima/hdama/cache_as_ram_auto.c
===================================================================
--- src/mainboard/arima/hdama/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/arima/hdama/cache_as_ram_auto.c	(working copy)
@@ -209,7 +209,7 @@
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\r\n");
+               	print_info("ht reset -\n");
                	soft_reset();
        	}
 
Index: src/mainboard/sunw/ultra40/auto.c
===================================================================
--- src/mainboard/sunw/ultra40/auto.c	(revision 3942)
+++ src/mainboard/sunw/ultra40/auto.c	(working copy)
@@ -184,7 +184,7 @@
 	needs_reset |= ck804_early_setup_x();	
 
        	if (needs_reset) {
-               	print_info("ht reset -\r\n");
+               	print_info("ht reset -\n");
                	soft_reset();
        	}
 
Index: src/mainboard/sunw/ultra40/cache_as_ram_auto.c
===================================================================
--- src/mainboard/sunw/ultra40/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/sunw/ultra40/cache_as_ram_auto.c	(working copy)
@@ -252,7 +252,7 @@
         needs_reset |= ck804_early_setup_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\r\n");
+               	print_info("ht reset -\n");
                	soft_reset();
        	}
 
Index: src/mainboard/newisys/khepri/auto.c
===================================================================
--- src/mainboard/newisys/khepri/auto.c	(revision 3942)
+++ src/mainboard/newisys/khepri/auto.c	(working copy)
@@ -128,7 +128,7 @@
 	needs_reset=ht_setup_chains_x();
 
 	if (needs_reset) {
-		print_info("ht reset -\r\n");
+		print_info("ht reset -\n");
 		soft_reset();
 	}
 #if 0
Index: src/mainboard/newisys/khepri/cache_as_ram_auto.c
===================================================================
--- src/mainboard/newisys/khepri/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/newisys/khepri/cache_as_ram_auto.c	(working copy)
@@ -224,7 +224,7 @@
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\r\n");
+               	print_info("ht reset -\n");
                	soft_reset();
        	}
 
Index: src/mainboard/jetway/j7f24/auto.c
===================================================================
--- src/mainboard/jetway/j7f24/auto.c	(revision 3942)
+++ src/mainboard/jetway/j7f24/auto.c	(working copy)
@@ -105,25 +105,25 @@
 	uart_init();
 	console_init();
 
-	print_spew("In auto.c:main()\r\n");
+	print_spew("In auto.c:main()\n");
 
 	enable_smbus();
 	smbus_fixup(&ctrl);
 
 	if (bist == 0) {
-		print_debug("doing early_mtrr\r\n");
+		print_debug("doing early_mtrr\n");
 		early_mtrr_init();
 	}
 
 	/* Halt if there was a built-in self test failure. */
 	report_bist_failure(bist);
 
-	print_debug("Enabling mainboard devices\r\n");
+	print_debug("Enabling mainboard devices\n");
 	enable_mainboard_devices();
 
 	ddr_ram_setup(&ctrl);
 
 	/* ram_check(0, 640 * 1024); */
 
-	print_spew("Leaving auto.c:main()\r\n");
+	print_spew("Leaving auto.c:main()\n");
 }
Index: src/mainboard/ibm/e326/auto.c
===================================================================
--- src/mainboard/ibm/e326/auto.c	(revision 3942)
+++ src/mainboard/ibm/e326/auto.c	(working copy)
@@ -149,7 +149,7 @@
 #endif
 
 	if (needs_reset) {
-		print_info("ht reset -\r\n");
+		print_info("ht reset -\n");
 		soft_reset();
 	}
 
Index: src/mainboard/ibm/e326/cache_as_ram_auto.c
===================================================================
--- src/mainboard/ibm/e326/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/ibm/e326/cache_as_ram_auto.c	(working copy)
@@ -205,7 +205,7 @@
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\r\n");
+               	print_info("ht reset -\n");
                	soft_reset();
        	}
 
Index: src/mainboard/ibm/e325/auto.c
===================================================================
--- src/mainboard/ibm/e325/auto.c	(revision 3942)
+++ src/mainboard/ibm/e325/auto.c	(working copy)
@@ -149,7 +149,7 @@
 #endif
 
 	if (needs_reset) {
-		print_info("ht reset -\r\n");
+		print_info("ht reset -\n");
 		soft_reset();
 	}
 
Index: src/mainboard/ibm/e325/cache_as_ram_auto.c
===================================================================
--- src/mainboard/ibm/e325/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/ibm/e325/cache_as_ram_auto.c	(working copy)
@@ -205,7 +205,7 @@
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\r\n");
+               	print_info("ht reset -\n");
                	soft_reset();
        	}
 
Index: src/mainboard/nvidia/l1_2pvv/apc_auto.c
===================================================================
--- src/mainboard/nvidia/l1_2pvv/apc_auto.c	(revision 3942)
+++ src/mainboard/nvidia/l1_2pvv/apc_auto.c	(working copy)
@@ -94,7 +94,7 @@
 	id = get_node_core_id_x();
 
 	//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
-	print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
+	print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\n");
 
 	train_ram(id.nodeid, sysinfo, sysinfox);
 
Index: src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c
===================================================================
--- src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c	(working copy)
@@ -290,9 +290,9 @@
 	early_usbdebug_direct_init();
 #endif
 	console_init();
-	print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
+	print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(",");  print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\n");
 
-	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+	print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
 
 #if MEM_TRAIN_SEQ == 1
 	set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
@@ -318,7 +318,7 @@
 	{
 		msr_t msr;
 		msr=rdmsr(0xc0010042);
-		print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+		print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 
 	}
 
@@ -332,7 +332,7 @@
 	{
 		msr_t msr;
 		msr=rdmsr(0xc0010042);
-		print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+		print_debug("end   msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
 
 	}
 #endif
@@ -343,7 +343,7 @@
 
 	// fidvid change will issue one LDTSTOP and the HT change will be effective too
 	if (needs_reset) {
-		print_info("ht reset -\r\n");
+		print_info("ht reset -\n");
 	      	soft_reset();
 	}
 	allow_all_aps_stop(bsp_apicid);
Index: src/mainboard/intel/xe7501devkit/auto.c
===================================================================
--- src/mainboard/intel/xe7501devkit/auto.c	(revision 3942)
+++ src/mainboard/intel/xe7501devkit/auto.c	(working copy)
@@ -89,5 +89,5 @@
 	
 	// NOTE: ROMCC dies with an internal compiler error
 	//		 if the following line is removed.
-	print_debug("SDRAM is up.\r\n");
+	print_debug("SDRAM is up.\n");
 }
Index: src/mainboard/intel/jarrell/watchdog.c
===================================================================
--- src/mainboard/intel/jarrell/watchdog.c	(revision 3942)
+++ src/mainboard/intel/jarrell/watchdog.c	(working copy)
@@ -91,7 +91,7 @@
 	disable_sio_watchdog(NSC_WD_DEV);
 	disable_ich5_watchdog();
 	disable_jarell_frb3();
-	print_debug("Watchdogs disabled\r\n");
+	print_debug("Watchdogs disabled\n");
 }
 
 static void ich5_watchdog_on(void)
@@ -134,5 +134,5 @@
 	value &= ~(1 << 11);
 	outw(value, base + 0x08);	
 
-	print_debug("Watchdog ICH5 enabled\r\n");
+	print_debug("Watchdog ICH5 enabled\n");
 }
Index: src/mainboard/intel/jarrell/debug.c
===================================================================
--- src/mainboard/intel/jarrell/debug.c	(revision 3942)
+++ src/mainboard/intel/jarrell/debug.c	(working copy)
@@ -12,7 +12,7 @@
 	print_debug_hex8(index);
 	print_debug(": 0x");
 	print_debug_hex8(data);
-	print_debug("\r\n");
+	print_debug("\n");
         return;
 }
         
@@ -49,52 +49,52 @@
         int i;
         unsigned char data;
        
-	 print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
+	 print_debug("\n*** SERVER I/O REGISTERS ***\n");
         for (i=0x10; i<=0x2d; i++) {
                 print_reg((unsigned char)i);
         }
 #if 0                                                                         
-        print_debug("\r\n*** XBUS REGISTERS ***\r\n");
+        print_debug("\n*** XBUS REGISTERS ***\n");
         setup_func(0x0f);
         for (i=0xf0; i<=0xff; i++) {
                 print_reg((unsigned char)i);
         }
                                                                                 
-        print_debug("\r\n***  SERIAL 1 CONFIG REGISTERS ***\r\n");
+        print_debug("\n***  SERIAL 1 CONFIG REGISTERS ***\n");
         setup_func(0x03);
         print_reg(0xf0);
                                                                                 
-        print_debug("\r\n***  SERIAL 2 CONFIG REGISTERS ***\r\n");
+        print_debug("\n***  SERIAL 2 CONFIG REGISTERS ***\n");
         setup_func(0x02);
         print_reg(0xf0);
 
 #endif
-        print_debug("\r\n***  GPIO REGISTERS ***\r\n");
+        print_debug("\n***  GPIO REGISTERS ***\n");
         setup_func(0x07);
         for (i=0xf0; i<=0xf8; i++) {
                 print_reg((unsigned char)i);
         }
-        print_debug("\r\n***  GPIO VALUES ***\r\n");
+        print_debug("\n***  GPIO VALUES ***\n");
         data = inb(0x68a);
-	print_debug("\r\nGPDO 4: 0x");
+	print_debug("\nGPDO 4: 0x");
 	print_debug_hex8(data);
         data = inb(0x68b);
-	print_debug("\r\nGPDI 4: 0x");
+	print_debug("\nGPDI 4: 0x");
 	print_debug_hex8(data);
-	print_debug("\r\n");
+	print_debug("\n");
 	
 #if 0                                                                                
                                                                                 
-        print_debug("\r\n***  WATCHDOG TIMER REGISTERS ***\r\n");
+        print_debug("\n***  WATCHDOG TIMER REGISTERS ***\n");
         setup_func(0x0a);
         print_reg(0xf0);
                                                                                 
-        print_debug("\r\n***  FAN CONTROL REGISTERS ***\r\n");
+        print_debug("\n***  FAN CONTROL REGISTERS ***\n");
         setup_func(0x09);
         print_reg(0xf0);
         print_reg(0xf1);
 
-        print_debug("\r\n***  RTC REGISTERS ***\r\n");
+        print_debug("\n***  RTC REGISTERS ***\n");
         setup_func(0x10);
         print_reg(0xf0);
         print_reg(0xf1);
@@ -104,7 +104,7 @@
         print_reg(0xfe);
         print_reg(0xff);
                                                                                 
-        print_debug("\r\n***  HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
+        print_debug("\n***  HEALTH MONITORING & CONTROL REGISTERS ***\n");
         setup_func(0x14);
         print_reg(0xf0);
 #endif                                                                           
@@ -135,7 +135,7 @@
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		print_debug("\r\n");
+		print_debug("\n");
 	}
 }
 
@@ -143,7 +143,7 @@
 {
 	int i;
 	print_debug_pci_dev(dev);
-	print_debug("\r\n");
+	print_debug("\n");
 	
 	for(i = 0; i <= 255; i++) {
 		unsigned char val;
@@ -155,7 +155,7 @@
 		print_debug_char(' ');
 		print_debug_hex8(val);
 		if ((i & 0x0f) == 0x0f) {
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -165,7 +165,7 @@
 	int i;
 	unsigned long bar;
 	
-	print_debug("BAR 14 Dump\r\n");
+	print_debug("BAR 14 Dump\n");
 	
 	bar = pci_read_config32(dev, 0x14);
 	for(i = 0; i <= 0x300; i+=4) {
@@ -178,14 +178,14 @@
 		val = pci_read_config8(dev, i);
 #endif		
 		if((i%4)==0) {
-		print_debug("\r\n");
+		print_debug("\n");
 		print_debug_hex16(i);
 		print_debug_char(' ');
 		}
 		print_debug_hex32(read32(bar + i));
 		print_debug_char(' ');
 	}
-	print_debug("\r\n");
+	print_debug("\n");
 }
 
 static void dump_pci_devices(void)
@@ -209,7 +209,7 @@
 static void dump_spd_registers(const struct mem_controller *ctrl)
 {
 	int i;
-	print_debug("\r\n");
+	print_debug("\n");
 	for(i = 0; i < 4; i++) {
 		unsigned device;
 		device = ctrl->channel0[i];
@@ -223,20 +223,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 		device = ctrl->channel1[i];
 		if (device) {
@@ -249,20 +249,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -275,14 +275,14 @@
         while(device <= SMBUS_MEM_DEVICE_END) {
                 int status = 0;
                 int i;
-        	print_debug("\r\n");
+        	print_debug("\n");
                 print_debug("dimm ");
 		print_debug_hex8(device);
 		
                 for(i = 0; (i < 256) ; i++) {
 	                unsigned char byte;
                         if ((i % 16) == 0) {
-				print_debug("\r\n");
+				print_debug("\n");
 				print_debug_hex8(i);
 				print_debug(": ");
                         }
@@ -290,7 +290,7 @@
                         if (status < 0) {
 			         print_debug("bad device: ");
 				 print_debug_hex8(-status);
-				 print_debug("\r\n");
+				 print_debug("\n");
 			         break; 
 			}
 			print_debug_hex8(status);
@@ -308,7 +308,7 @@
         while(device <= 0x42) {
                 int status = 0;
                 int i;
-        	print_debug("\r\n");
+        	print_debug("\n");
                 print_debug("ipmi ");
 		print_debug_hex8(device);
 		
@@ -318,7 +318,7 @@
                         if (status < 0) {
 			         print_debug("bad device: ");
 				 print_debug_hex8(-status);
-				 print_debug("\r\n");
+				 print_debug("\n");
 			         break; 
 			}
 			print_debug_hex8(status);
Index: src/mainboard/intel/jarrell/jarrell_fixups.c
===================================================================
--- src/mainboard/intel/jarrell/jarrell_fixups.c	(revision 3942)
+++ src/mainboard/intel/jarrell/jarrell_fixups.c	(working copy)
@@ -58,12 +58,12 @@
 	/* set gpio 42,44 signal levels */
 	data = inb(gpio_index + PC87427_GPDO_4);
 	if ((data & 0x14) == (0xff & (((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2))) {
-		print_debug("set_pllsel: correct settings detected!\r\n");
+		print_debug("set_pllsel: correct settings detected!\n");
 		return; /* settings already configured */
 	} else {
 		outb((data & 0xeb) | ((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2, gpio_index + PC87427_GPDO_4);
 		/* reset */
-		print_debug("set_pllsel: settings adjusted, now resetting...\r\n");
+		print_debug("set_pllsel: settings adjusted, now resetting...\n");
 	//	hard_reset(); /* should activate a PCI_RST, which should reset MCH, but it doesn't seem to work ???? */
 //		mch_reset();
 		full_reset();
Index: src/mainboard/intel/jarrell/power_reset_check.c
===================================================================
--- src/mainboard/intel/jarrell/power_reset_check.c	(revision 3942)
+++ src/mainboard/intel/jarrell/power_reset_check.c	(working copy)
@@ -6,7 +6,7 @@
 	cmos=cmos_read(RTC_BOOT_BYTE)>>4 ;
 	print_debug("Boot byte = ");
 	print_debug_hex8(cmos);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	if((cmos>2)&&(cmos&1))  full_reset();
 }
Index: src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
===================================================================
--- src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c	(working copy)
@@ -116,7 +116,7 @@
 	uint8_t tmp;
 
 	set_bios_reset();
-	print_debug("soft reset \r\n");
+	print_debug("soft reset \n");
 
 	/* PCI reset */
 	tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@ -194,7 +194,7 @@
 	console_init();
 	enable_rom_decode();
 
-	print_info("now booting... fallback\r\n");
+	print_info("now booting... fallback\n");
 
 	/* Is this a CPU only reset? Or is this a secondary CPU? */
 	if ((cpu_init_detectedx) || (!boot_cpu())) {
@@ -220,7 +220,7 @@
 	}
 
 normal_image:
-	/* print_info("JMP normal image\r\n"); */
+	/* print_info("JMP normal image\n"); */
 
 	__asm__ __volatile__("jmp __normal_image":
 			     :"a" (bist), "b" (cpu_init_detectedx));
@@ -262,7 +262,7 @@
 	console_init();
 	enable_rom_decode();
 
-	print_info("now booting... real_main\r\n");
+	print_info("now booting... real_main\n");
 
 	if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@@ -274,7 +274,7 @@
 	setup_coherent_ht_domain();
 	wait_all_core0_started();
 
-	print_info("now booting... Core0 started\r\n");
+	print_info("now booting... Core0 started\n");
 
 #if CONFIG_LOGICAL_CPUS==1
 	/* It is said that we should start core1 after all core0 launched. */
@@ -289,7 +289,7 @@
 	needs_reset |= k8t890_early_setup_ht();
 
 	if (needs_reset) {
-		print_debug("ht reset -\r\n");
+		print_debug("ht reset -\n");
 		soft_reset();
 	}
 
Index: src/mainboard/asus/a8n_e/cache_as_ram_auto.c
===================================================================
--- src/mainboard/asus/a8n_e/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/asus/a8n_e/cache_as_ram_auto.c	(working copy)
@@ -242,7 +242,7 @@
 	needs_reset |= ck804_early_setup_x();
 
 	if (needs_reset) {
-		print_info("ht reset -\r\n");
+		print_info("ht reset -\n");
 		soft_reset();
 	}
 
Index: src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
===================================================================
--- src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c	(working copy)
@@ -110,12 +110,12 @@
 /* this function might fail on some K8 CPUs with errata #181 */
 static void ldtstop_sb(void)
 {
-	print_debug("toggle LDTSTP#\r\n");
+	print_debug("toggle LDTSTP#\n");
 	u8 reg = inb (VT8237R_ACPI_IO_BASE + 0x5c);
 	reg = reg ^ (1 << 0);
 	outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);
 	reg = inb(VT8237R_ACPI_IO_BASE + 0x15);
-	print_debug("done\r\n");
+	print_debug("done\n");
 }
 
 
@@ -137,7 +137,7 @@
 	uint8_t tmp;
 
 	set_bios_reset();
-	print_debug("soft reset \r\n");
+	print_debug("soft reset \n");
 
 	/* PCI reset */
 	tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@ -180,7 +180,7 @@
 	console_init();
 	enable_rom_decode();
 
-	print_info("now booting... fallback\r\n");
+	print_info("now booting... fallback\n");
 
 	/* Is this a CPU only reset? Or is this a secondary CPU? */
 	if ((cpu_init_detectedx) || (!boot_cpu())) {
@@ -206,7 +206,7 @@
 	}
 
 normal_image:
-	/* print_info("JMP normal image\r\n"); */
+	/* print_info("JMP normal image\n"); */
 
 	__asm__ __volatile__("jmp __normal_image":
 			     :"a" (bist), "b" (cpu_init_detectedx));
@@ -250,7 +250,7 @@
 	console_init();
 	enable_rom_decode();
 
-	print_info("now booting... real_main\r\n");
+	print_info("now booting... real_main\n");
 
 
 	if (bist == 0)
@@ -262,7 +262,7 @@
 	setup_coherent_ht_domain();
 	wait_all_core0_started();
 
-	print_info("now booting... Core0 started\r\n");
+	print_info("now booting... Core0 started\n");
 
 #if CONFIG_LOGICAL_CPUS==1
 	/* It is said that we should start core1 after all core0 launched. */
@@ -285,9 +285,9 @@
 	if (needs_reset) {
 		print_debug_hex8(needs_reset);
 
-		print_debug("Xht reset -\r\n");
+		print_debug("Xht reset -\n");
 		soft_reset();
-		print_debug("NO reset\r\n");
+		print_debug("NO reset\n");
 
 	}
 
@@ -297,7 +297,7 @@
 	vt8237_sb_enable_fid_vid();
 
 	enable_fid_change();
-	print_debug("after enable_fid_change\r\n");
+	print_debug("after enable_fid_change\n");
 
 	init_fidvid_bsp(bsp_apicid);
 
Index: src/mainboard/agami/aruma/auto.c
===================================================================
--- src/mainboard/agami/aruma/auto.c	(revision 3942)
+++ src/mainboard/agami/aruma/auto.c	(working copy)
@@ -153,19 +153,19 @@
 //#if (ALLOW_HT_OVERCLOCKING==1) && (USE_FALLBACK_IMAGE==0)
 //	if(read_option(CMOS_VSTART_amdk8_1GHz, CMOS_VLEN_amdk8_1GHz, 0)) 
 //	{
-//		print_debug("AMDK8 allowed at 1GHz\r\n");
+//		print_debug("AMDK8 allowed at 1GHz\n");
 //	} else {
-//		print_debug("AMDK8 allowed at 800Hz only\r\n");
+//		print_debug("AMDK8 allowed at 800Hz only\n");
 //	}
 //	if(read_option(CMOS_VSTART_amd8131_800MHz, CMOS_VLEN_amd8131_800MHz, 0))
 //	{
-//		print_debug("AMD8131 allowed at 800MHz\r\n");
+//		print_debug("AMD8131 allowed at 800MHz\n");
 //	} else {
-//		print_debug("AMD8131 allowed at 600Hz only\r\n");
+//		print_debug("AMD8131 allowed at 600Hz only\n");
 //	}
 //#endif
 	if (needs_reset) {
-		print_info("HyperT reset -\r\n");
+		print_info("HyperT reset -\n");
 		soft_reset();
 	}
 
Index: src/mainboard/agami/aruma/cache_as_ram_auto.c
===================================================================
--- src/mainboard/agami/aruma/cache_as_ram_auto.c	(revision 3942)
+++ src/mainboard/agami/aruma/cache_as_ram_auto.c	(working copy)
@@ -243,7 +243,7 @@
         needs_reset |= ht_setup_chains_x();
 
        	if (needs_reset) {
-               	print_info("ht reset -\r\n");
+               	print_info("ht reset -\n");
                	soft_reset();
        	}
 
Index: src/sdram/generic_sdram.c
===================================================================
--- src/sdram/generic_sdram.c	(revision 3942)
+++ src/sdram/generic_sdram.c	(working copy)
@@ -6,15 +6,15 @@
 static inline void print_debug_sdram_8(const char *strval, uint32_t val)
 {
 #if CONFIG_USE_INIT
-        printk_debug("%s%02x\r\n", strval, val);
+        printk_debug("%s%02x\n", strval, val);
 #else
-        print_debug(strval); print_debug_hex8(val); print_debug("\r\n");
+        print_debug(strval); print_debug_hex8(val); print_debug("\n");
 #endif
 }
 
 void sdram_no_memory(void)
 {
-	print_err("No memory!!\r\n");
+	print_err("No memory!!\n");
 	while(1) { 
 		hlt(); 
 	}
@@ -55,7 +55,7 @@
 	 * Some chipsets do the work for us while on others 
 	 * we need to it by hand.
 	 */
-	print_debug("Ram3\r\n");
+	print_debug("Ram3\n");
 
 	#if RAMINIT_SYSINFO == 1
 	sdram_enable(controllers, ctrl, sysinfo);
@@ -63,5 +63,5 @@
 	sdram_enable(controllers, ctrl);
 	#endif
 
-	print_debug("Ram4\r\n");
+	print_debug("Ram4\n");
 }
Index: src/sdram/generic_dump_spd.c
===================================================================
--- src/sdram/generic_dump_spd.c	(revision 3942)
+++ src/sdram/generic_dump_spd.c	(working copy)
@@ -6,7 +6,7 @@
 static void dump_spd_registers(const struct mem_controller *ctrl)
 {
 	int i;
-	print_debug("\r\n");
+	print_debug("\n");
 	for(i = 0; i < 4; i++) {
 		unsigned device;
 		device = ctrl->channel0[i];
@@ -20,20 +20,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = spd_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 		device = ctrl->channel1[i];
 		if (device) {
@@ -46,20 +46,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = spd_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
Index: src/lib/debug.c
===================================================================
--- src/lib/debug.c	(revision 3942)
+++ src/lib/debug.c	(working copy)
@@ -23,7 +23,7 @@
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		print_debug("\r\n");
+		print_debug("\n");
 	}
 }
 
@@ -31,7 +31,7 @@
 {
 	int i;
 	print_debug_pci_dev(dev);
-	print_debug("\r\n");
+	print_debug("\n");
 	
 	for(i = 0; i <= 255; i++) {
 		unsigned char val;
@@ -43,7 +43,7 @@
 		print_debug_char(' ');
 		print_debug_hex8(val);
 		if ((i & 0x0f) == 0x0f) {
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
Index: src/northbridge/via/cn700/raminit.c
===================================================================
--- src/northbridge/via/cn700/raminit.c	(revision 3942)
+++ src/northbridge/via/cn700/raminit.c	(working copy)
@@ -56,7 +56,7 @@
 	PRINT_DEBUG_MEM_HEX8(reg);
 	PRINT_DEBUG_MEM(" to 0x");
 	PRINT_DEBUG_MEM_HEX32(0 + addr_offset);
-	PRINT_DEBUG_MEM("\r\n");
+	PRINT_DEBUG_MEM("\n");
 }
 
 /**
@@ -191,7 +191,7 @@
 	}
 
 	if (result == 0xff)
-		die("DRAM module size too big, not supported by CN700\r\n");
+		die("DRAM module size too big, not supported by CN700\n");
 
 	pci_write_config8(ctrl->d0f3, 0x40, result);
 	pci_write_config8(ctrl->d0f3, 0x48, 0x00);
@@ -397,30 +397,30 @@
 	u8 i;
 
 	/* 1. Apply NOP. */
-	PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\r\n");
+	PRINT_DEBUG_MEM("RAM Enable 1: Apply NOP\n");
 	do_ram_command(dev, RAM_COMMAND_NOP);
 	udelay(100);
 	read32(rank_address + 0x10);
 
 	/* 2. Precharge all. */
 	udelay(400);
-	PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n");
+	PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n");
 	do_ram_command(dev, RAM_COMMAND_PRECHARGE);
 	read32(rank_address + 0x10);
 
 	/* 3. Mode register set. */
-	PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
+	PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n");
 	do_ram_command(dev, RAM_COMMAND_MRS);
 	read32(rank_address + 0x120000);	/* EMRS DLL Enable */
 	read32(rank_address + 0x800);		/* MRS DLL Reset */
 
 	/* 4. Precharge all again. */
-	PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\r\n");
+	PRINT_DEBUG_MEM("RAM Enable 2: Precharge all\n");
 	do_ram_command(dev, RAM_COMMAND_PRECHARGE);
 	read32(rank_address + 0x0);
 
 	/* 5. Perform 8 refresh cycles. Wait tRC each time. */
-	PRINT_DEBUG_MEM("RAM Enable 3: CBR\r\n");
+	PRINT_DEBUG_MEM("RAM Enable 3: CBR\n");
 	do_ram_command(dev, RAM_COMMAND_CBR);
 	for (i = 0; i < 8; i++) {
 		read32(rank_address + 0x20);
@@ -428,7 +428,7 @@
 	}
 
 	/* 6. Mode register set. */
-	PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\r\n");
+	PRINT_DEBUG_MEM("RAM Enable 4: Mode register set\n");
 	/* Safe value for now, BL=8, WR=5, CAS=4 */
 	/*
 	 * (E)MRS values are from the BPG. No direct explanation is given, but 
@@ -441,7 +441,7 @@
 	read32(rank_address + 0x120020); /* EMRS OCD Calibration Mode Exit */
 
 	/* 8. Normal operation */
-	PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\r\n");
+	PRINT_DEBUG_MEM("RAM Enable 5: Normal operation\n");
 	do_ram_command(dev, RAM_COMMAND_NORMAL);
 	read32(rank_address + 0x30);
 }
Index: src/northbridge/via/vt8601/raminit.c
===================================================================
--- src/northbridge/via/vt8601/raminit.c	(revision 3942)
+++ src/northbridge/via/vt8601/raminit.c	(working copy)
@@ -76,7 +76,7 @@
 	print_debug_hex8(reg);
 	print_debug(" to ");
 	print_debug_hex8(val);
-	print_debug("\r\n");
+	print_debug("\n");
 	pci_write_config8(north, reg, val);
 }
 #else
@@ -93,7 +93,7 @@
 			print_debug_hex8(pci_read_config8(north, r + c));
 			print_debug(" ");
 		}
-		print_debug("\r\n");
+		print_debug("\n");
 		if (r >= 240)
 			break;
 	}
@@ -104,13 +104,13 @@
 	device_t north = (device_t) PCI_DEV(0, 0, 0);
 	uint8_t c, r;
 
-	print_err("vt8601 init starting\r\n");
+	print_err("vt8601 init starting\n");
 	print_debug_hex32(north);
 	print_debug(" is the north\n");
 	print_debug_hex16(pci_read_config16(north, 0));
 	print_debug(" ");
 	print_debug_hex16(pci_read_config16(north, 2));
-	print_debug("\r\n");
+	print_debug("\n");
 
 	/* All we are doing now is setting initial known-good values that will
 	 * be revised later as we read SPD
@@ -200,7 +200,7 @@
 	print_info("Slot ");
 	print_info_hex8(slot);
 	if (smbus_read_byte(module, 2) != 4) {
-		print_info(" is empty\r\n");
+		print_info(" is empty\n");
 		return 0;
 	}
 	print_info(" is SDRAM ");
@@ -225,7 +225,7 @@
 		print_info("x2");
 		value = (value << 16) | value;
 	}
-	print_info("\r\n");
+	print_info("\n");
 	return value;
 
 }
@@ -302,19 +302,19 @@
 
 	/* set NOP */
 	pci_write_config8(north, 0x6C, 0x01);
-	print_debug("NOP\r\n");
+	print_debug("NOP\n");
 	/* wait 200us */
 	// You need to do the memory reference. That causes the nop cycle. 
 	dimms_read(0);
 	udelay(400);
-	print_debug("PRECHARGE\r\n");
+	print_debug("PRECHARGE\n");
 	/* set precharge */
 	pci_write_config8(north, 0x6C, 0x02);
-	print_debug("DUMMY READS\r\n");
+	print_debug("DUMMY READS\n");
 	/* dummy reads */
 	dimms_read(0);
 	udelay(200);
-	print_debug("CBR\r\n");
+	print_debug("CBR\n");
 	/* set CBR */
 	pci_write_config8(north, 0x6C, 0x04);
 
@@ -335,7 +335,7 @@
 	udelay(200);
 	dimms_read(0);
 	udelay(200);
-	print_debug("MRS\r\n");
+	print_debug("MRS\n");
 	/* set MRS */
 	pci_write_config8(north, 0x6c, 0x03);
 #if DIMM_CL2
@@ -344,21 +344,21 @@
 	dimms_read(0x1d0);
 #endif
 	udelay(200);
-	print_debug("NORMAL\r\n");
+	print_debug("NORMAL\n");
 	/* set to normal mode */
 	pci_write_config8(north, 0x6C, 0x08);
 
 	dimms_write(0x55aa55aa);
 	dimms_read(0);
 	udelay(200);
-	print_debug("set ref. rate\r\n");
+	print_debug("set ref. rate\n");
 	// Set the refresh rate. 
 #if DIMM_PC133
 	pci_write_config8(north, 0x6A, 0x86);
 #else
 	pci_write_config8(north, 0x6A, 0x65);
 #endif
-	print_debug("enable multi-page open\r\n");
+	print_debug("enable multi-page open\n");
 	// enable multi-page open
 	pci_write_config8(north, 0x6B, 0x0d);
 
@@ -395,8 +395,8 @@
 		else /* 256MB or more per side */
 			ma = 0xe;
 		print_debug_hex16(ma);
-		print_debug(" is the MA type\r\n");
+		print_debug(" is the MA type\n");
 		set_ma_mapping(north, slot, ma);
 	}
-	print_err("vt8601 done\r\n");
+	print_err("vt8601 done\n");
 }
Index: src/northbridge/via/vt8623/raminit.c
===================================================================
--- src/northbridge/via/vt8623/raminit.c	(revision 3942)
+++ src/northbridge/via/vt8623/raminit.c	(working copy)
@@ -56,7 +56,7 @@
 			print_debug_hex8(pci_read_config8(north, r+c));
 			print_debug(" ");
 		}
-		print_debug("\r\n");
+		print_debug("\n");
   }
 }
 void print_val(char *str, int val)
@@ -72,7 +72,7 @@
 	uint16_t i,j;
 	unsigned long bank_address;
 
-	print_debug("vt8623 init starting\r\n");
+	print_debug("vt8623 init starting\n");
 	north = pci_locate_device(PCI_ID(0x1106, 0x3123), 0);
 	north = 0;
 	
@@ -102,7 +102,7 @@
 */
 	c = 0;
 	b = smbus_read_byte(0xa0,17);
-	print_val("Detecting Memory\r\nNumber of Banks ",b);
+	print_val("Detecting Memory\nNumber of Banks ",b);
 
 	if( b != 2 ){            // not 16 Mb type
 	
@@ -110,14 +110,14 @@
     Read SPD byte 3, Number of row addresses.
 */
 		b = smbus_read_byte(0xa0,3);
-		print_val("\r\nNumber of Rows ",b);
+		print_val("\nNumber of Rows ",b);
 		if( b >= 0x0d ){	// not 64/128Mb (rows <=12)
 
 /*
     Read SPD byte 13, Primary DRAM width.
 */
 			b = smbus_read_byte(0xa0,13);
-			print_val("\r\nPriamry DRAM width",b);
+			print_val("\nPriamry DRAM width",b);
 			if( b != 4 )   // mot 64/128Mb (x4)
 				c = 0x80;  // 256Mb
 		}
@@ -128,13 +128,13 @@
     Read SPD byte 4, Number of column addresses.
 */		
 		b = smbus_read_byte(0xa0,4);
-		print_val("\r\nNo Columns ",b);
+		print_val("\nNo Columns ",b);
 		if( b == 10 || b == 11 ) c |= 0x60;   // 10/11 bit col addr
 		if( b == 9 ) c |= 0x40;           // 9 bit col addr
 		if( b == 8 ) c |= 0x20;           // 8 bit col addr
 
 	}
-	print_val("\r\nMA type ",c);
+	print_val("\nMA type ",c);
 	pci_write_config8(north,0x58,c);
 
 /*
@@ -161,18 +161,18 @@
 	else c = 0x01;                   // Error, use default
 
 
-	print_val("\r\nBank 0 (*16 Mb) ",c);
+	print_val("\nBank 0 (*16 Mb) ",c);
 
 	// set bank zero size
 	pci_write_config8(north,0x5a,c);
 	// SPD byte 5  # of physical banks
 	b = smbus_read_byte(0xa0,5);
 
-	print_val("\r\nNo Physical Banks ",b);
+	print_val("\nNo Physical Banks ",b);
 	if( b == 2)
 		c <<=1;
 
-	print_val("\r\nTotal Memory (*16 Mb) ",c);
+	print_val("\nTotal Memory (*16 Mb) ",c);
 	// set banks 1,2,3
 	pci_write_config8(north,0x5b,c);
 	pci_write_config8(north,0x5c,c);
@@ -181,40 +181,40 @@
 
 	/* Read SPD byte 18 CAS Latency */
 	b = smbus_read_byte(0xa0,18);
-	print_debug("\r\nCAS Supported ");
+	print_debug("\nCAS Supported ");
 	if(b & 0x04)
 		print_debug("2 ");
 	if(b & 0x08)
 		print_debug("2.5 ");
 	if(b & 0x10)
 		print_debug("3");
-	print_val("\r\nCycle time at CL X     (nS)",smbus_read_byte(0xa0,9));
-	print_val("\r\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23));
-	print_val("\r\nCycle time at CL X-1   (nS)",smbus_read_byte(0xa0,25));
+	print_val("\nCycle time at CL X     (nS)",smbus_read_byte(0xa0,9));
+	print_val("\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23));
+	print_val("\nCycle time at CL X-1   (nS)",smbus_read_byte(0xa0,25));
 	
 
 	if( b & 0x10 ){             // DDR offering optional CAS 3
-		print_debug("\r\nStarting at CAS 3");
+		print_debug("\nStarting at CAS 3");
 		c = 0x30;
 		/* see if we can better it */
 		if( b & 0x08 ){     // DDR mandatory CAS 2.5
 			if( smbus_read_byte(0xa0,23) <= 0x75 ){ // we can manage 133Mhz at CAS 2.5
-				print_debug("\r\nWe can do CAS 2.5");
+				print_debug("\nWe can do CAS 2.5");
 				c = 0x20;
 			}
 		}
 		if( b & 0x04 ){     // DDR mandatory CAS 2
 			if( smbus_read_byte(0xa0,25) <= 0x75 ){ // we can manage 133Mhz at CAS 2
-				print_debug("\r\nWe can do CAS 2");
+				print_debug("\nWe can do CAS 2");
 				c = 0x10;
 			}
 		}
 	}else{                     // no optional CAS values just 2 & 2.5
-		print_debug("\r\nStarting at CAS 2.5");
+		print_debug("\nStarting at CAS 2.5");
 		c = 0x20;          // assume CAS 2.5
 		if( b & 0x04){      // Should always happen
 			if( smbus_read_byte(0xa0,23) <= 0x75){ // we can manage 133Mhz at CAS 2
-				print_debug("\r\nWe can do CAS 2");
+				print_debug("\nWe can do CAS 2");
 				c = 0x10;
 			}
 		}
@@ -254,7 +254,7 @@
 */
 
 	b = smbus_read_byte(0xa0,27);
-	print_val("\r\ntRP ",b);
+	print_val("\ntRP ",b);
 	if( b > 0x3c )           // set tRP = 3T
 		c |= 0x80;
 
@@ -266,7 +266,7 @@
 */
 
 	b = smbus_read_byte(0xa0,29);
-	print_val("\r\ntRCD ",b);
+	print_val("\ntRCD ",b);
 	if( b > 0x3c )           // set tRCD = 3T
 		c |= 0x04;
 
@@ -278,7 +278,7 @@
 */
 
 	b = smbus_read_byte(0xa0,30);
-	print_val("\r\ntRAS ",b);
+	print_val("\ntRAS ",b);
 	if( b > 0x25 )           // set tRAS = 6T
 		c |= 0x40;
 
@@ -500,7 +500,7 @@
 		break;
 		
 	}
-	print_val("\r\nLow Bond ",i);	
+	print_val("\nLow Bond ",i);	
 	if( i < 0xff ){ 
 		c = i++;
 		for(  ; i <0xff ; i++){
@@ -549,7 +549,7 @@
 		pci_write_config8(north,0x68,c);
 		pci_write_config8(north,0x68,0x42);
 	}else{
-		print_debug("Unable to determine low bond - Setting default\r\n");
+		print_debug("Unable to determine low bond - Setting default\n");
 		pci_write_config8(north,0x68,0x59);
 	}
 
@@ -608,10 +608,10 @@
 	pci_write_config8(north,0xac,0x2f);
 	pci_write_config8(north,0xae,0x04);
 
-        print_debug("vt8623 done\r\n");
+        print_debug("vt8623 done\n");
 	dumpnorth(north);
 
-	print_debug("AGP\r\n");
+	print_debug("AGP\n");
 	north = pci_locate_device(PCI_ID(0x1106, 0xb091), 0);
 	pci_write_config32(north,0x20,0xddf0dc00);
 	pci_write_config32(north,0x24,0xdbf0d800);
Index: src/northbridge/amd/gx1/raminit.c
===================================================================
--- src/northbridge/amd/gx1/raminit.c	(revision 3942)
+++ src/northbridge/amd/gx1/raminit.c	(working copy)
@@ -143,7 +143,7 @@
 #if 0
 	print_debug("MC_BANK_CFG = ");
 	print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG));
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 
 	/* retrieve the page size from the MC register */
@@ -152,7 +152,7 @@
 #if 0
 	print_debug("    page_size = ");
 	print_debug_hex32(page_size);
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 
 	comp_banks = (((getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_COMP_BNK << dimm_shift)) >> dimm_shift) >> 12);
@@ -169,7 +169,7 @@
 #if 0
 	print_debug("MC_BANK_CFG = ");
 	print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG));
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 	return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_MOD_BNK << dimm_shift));
 }
@@ -181,7 +181,7 @@
 #if 0
 	print_debug("MC_BANK_CFG = ");
 	print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG));
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 
 	page_size = page_size << (((getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_PG_SZ << dimm_shift)) >> dimm_shift) >> 4);
@@ -189,7 +189,7 @@
 #if 0
 	print_debug("    page_size = ");
 	print_debug_hex32(page_size);
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 
 	setGX1Mem(0, TEST_DATA1);
@@ -203,7 +203,7 @@
 #if 0
 	print_debug("MC_BANK_CFG = ");
 	print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG));
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 	return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_COMP_BNK << dimm_shift));
 }
@@ -225,7 +225,7 @@
 #if 0
 			print_debug("    Page size Config = ");
 			print_debug_hex32(page_size_config << dimm_shift);
-			print_debug("\r\n");
+			print_debug("\n");
 #endif
 			return(page_size_config << dimm_shift);
 			}
@@ -257,7 +257,7 @@
 
 	print_debug("Probing for DIMM");
 	print_debug_char((dimm_shift >> 4) + 0x30);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	setGX1Mem(0, TEST_DATA1);
 	setGX1Mem(0x100, 0);
@@ -269,7 +269,7 @@
 
 	print_debug("    Found DIMM");
 	print_debug_char((dimm_shift >> 4) + 0x30);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	return 1;
 }
@@ -285,7 +285,7 @@
 
 	print_debug("    Page Size:       ");
 	print_debug_hex32(0x400 << ((mem_config & (DIMM_PG_SZ << dimm_shift)) >> (dimm_shift + 4)));
-	print_debug("\r\n");
+	print_debug("\n");
 
 	/* Now do component banks detection */
 
@@ -294,7 +294,7 @@
 
 	print_debug("    Component Banks: ");
 	print_debug_char((((mem_config & (DIMM_COMP_BNK << dimm_shift)) >> (dimm_shift + 12)) ? 4 : 2) + 0x30);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	/* Now do module banks */
 
@@ -303,7 +303,7 @@
 	
 	print_debug("    Module Banks:    ");
 	print_debug_char((((mem_config & (DIMM_MOD_BNK << dimm_shift)) >> (dimm_shift + 14)) ? 2 : 1) + 0x30);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	mem_config &= (~(DIMM_SZ << dimm_shift));
 	mem_config |= (size_dimm(dimm_shift));
@@ -311,7 +311,7 @@
 	print_debug("    DIMM size:       ");
 	print_debug_hex32(1 << 
 		((mem_config & (DIMM_SZ << dimm_shift)) >> (dimm_shift + 8)) + 22);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	return (mem_config);
 }
@@ -320,7 +320,7 @@
 {
 unsigned int mem_config = 0x00700070;
 
-	print_debug("Setting up default parameters for memory\r\n");
+	print_debug("Setting up default parameters for memory\n");
 	outb(0x70, 0x80);
 
 	setGX1Mem(GX_BASE + MC_MEM_CNTRL2, 0x000007d8); /* Disable all CLKS, Shift = 3 */
@@ -335,7 +335,7 @@
 
 	enable_dimm();
 
-	print_debug("Sizing memory\r\n");
+	print_debug("Sizing memory\n");
 
 	setGX1Mem(GX_BASE + MC_BANK_CFG, 0x00705740);
 	do_refresh();
@@ -346,7 +346,7 @@
 
 	print_debug("MC_BANK_CFG = ");
 	print_debug_hex32(mem_config);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	setGX1Mem(GX_BASE + MC_BANK_CFG, mem_config);
 	enable_dimm();
Index: src/northbridge/amd/gx2/raminit.c
===================================================================
--- src/northbridge/amd/gx2/raminit.c	(revision 3942)
+++ src/northbridge/amd/gx2/raminit.c	(working copy)
@@ -21,13 +21,13 @@
 	msr = rdmsr(0x2000001a);
 	msr.lo = 0x0101;
 	wrmsr(0x2000001a, msr);
-	//print_debug("sdram_enable step 2\r\n");
+	//print_debug("sdram_enable step 2\n");
 
 	/* 3. release CKE mask to enable CKE */
 	msr = rdmsr(0x2000001d);
 	msr.lo &= ~(0x03 << 8);
 	wrmsr(0x2000201d, msr);
-	//print_debug("sdram_enable step 3\r\n");
+	//print_debug("sdram_enable step 3\n");
 
 	/* 4. set and clear REF_TST 16 times, more shouldn't hurt
 	 * why this is before EMRS and MRS ? */
@@ -38,7 +38,7 @@
 		msr.lo &= ~(0x01 << 3);
 		wrmsr(0x20000018, msr);
 	}
-	//print_debug("sdram_enable step 4\r\n");
+	//print_debug("sdram_enable step 4\n");
 
 	/* 5. set refresh interval */
 	msr = rdmsr(0x20000018);
@@ -50,7 +50,7 @@
 	msr.lo &= ~(0x03 << 6);
 	msr.lo |=  (0x00 << 6);
 	wrmsr(0x20000018, msr);
-	//print_debug("sdram_enable step 5\r\n");
+	//print_debug("sdram_enable step 5\n");
 
 	/* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */
 	msr = rdmsr(0x20000018);
@@ -58,7 +58,7 @@
 	wrmsr(0x20000018, msr);
 	msr.lo &= ~((0x01 << 28) | 0x01);
 	wrmsr(0x20000018, msr);
-	//print_debug("sdram_enable step 6\r\n");
+	//print_debug("sdram_enable step 6\n");
 
 	/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
 	 * it is documented in LX datasheet  */	
@@ -68,7 +68,7 @@
 	wrmsr(0x20000018, msr);
 	msr.lo &= ~((0x01 << 27) | 0x01);
 	wrmsr(0x20000018, msr);
-	//print_debug("sdram_enable step 7\r\n");
+	//print_debug("sdram_enable step 7\n");
 
 	/* 8. load Mode Register by set and clear PROG_DRAM */
 	msr = rdmsr(0x20000018);
@@ -76,7 +76,7 @@
 	wrmsr(0x20000018, msr);
 	msr.lo &= ~0x01;
 	wrmsr(0x20000018, msr);
-	//print_debug("sdram_enable step 8\r\n");
+	//print_debug("sdram_enable step 8\n");
 
 	/* wait 200 SDCLKs */
 	for (i = 0; i < 200; i++)
@@ -107,7 +107,7 @@
 	/* make sure there is nothing stale in the cache */
 	__asm__("wbinvd\n");
 
-	print_debug("RAM DLL lock\r\n");
+	print_debug("RAM DLL lock\n");
 	/* The RAM dll needs a write to lock on so generate a few dummy writes */
 	volatile unsigned long *ptr;
 	for (i=0;i<5;i++) {
Index: src/northbridge/amd/lx/raminit.c
===================================================================
--- src/northbridge/amd/lx/raminit.c	(revision 3942)
+++ src/northbridge/amd/lx/raminit.c	(working copy)
@@ -31,11 +31,11 @@
 {
 	print_debug("===========================");
 	print_debug(s);
-	print_debug("======================================\r\n");
+	print_debug("======================================\n");
 }
 void hcf(void)
 {
-	print_emerg("DIE\r\n");
+	print_emerg("DIE\n");
 	/* this guarantees we flush the UART fifos (if any) and also 
 	 * ensures that things, in general, keep going so no debug output 
 	 * is lost
@@ -198,7 +198,7 @@
 
 	/* current speed > max speed? */
 	if (GeodeLinkSpeed() > speed) {
-		print_emerg("DIMM overclocked. Check GeodeLink Speed\r\n");
+		print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
 		POST_CODE(POST_PLL_MEM_FAIL);
 		hcf();
 	}
@@ -338,7 +338,7 @@
 	} else if ((casmap0 &= casmap1)) {
 		spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)];
 	} else {
-		print_emerg("DIMM CAS Latencies not compatible\r\n");
+		print_emerg("DIMM CAS Latencies not compatible\n");
 		POST_CODE(ERROR_DIFF_DIMMS);
 		hcf();
 	}
@@ -530,7 +530,7 @@
 	msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET;
 	wrmsr(MC_CFCLK_DBUG, msr);
 
-	print_info("Enabled MTest for TLA debug\r\n");
+	print_info("Enabled MTest for TLA debug\n");
 }
 
 static void sdram_set_registers(const struct mem_controller *ctrl)
@@ -574,7 +574,7 @@
 	banner("Check DIMM 0");
 	/* Check DIMM is not Register and not Buffered DIMMs. */
 	if ((spd_byte != 0xFF) && (spd_byte & 3)) {
-		print_emerg("DIMM0 NOT COMPATIBLE\r\n");
+		print_emerg("DIMM0 NOT COMPATIBLE\n");
 		POST_CODE(ERROR_UNSUPPORTED_DIMM);
 		hcf();
 	}
@@ -647,7 +647,7 @@
 	msr = rdmsr(MC_CF07_DATA);
 	if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) == 
 			((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {
-		print_emerg("No memory in the system\r\n");
+		print_emerg("No memory in the system\n");
 		POST_CODE(ERROR_NO_DIMMS);
 		hcf();
 	}
Index: src/northbridge/amd/lx/pll_reset.c
===================================================================
--- src/northbridge/amd/lx/pll_reset.c	(revision 3942)
+++ src/northbridge/amd/lx/pll_reset.c	(working copy)
@@ -68,7 +68,7 @@
 		__asm__ __volatile__("hlt\n");
 
 	}
-	print_debug("Done pll_reset\r\n");
+	print_debug("Done pll_reset\n");
 	return;
 }
 
Index: src/northbridge/amd/amdk8/coherent_ht.c
===================================================================
--- src/northbridge/amd/amdk8/coherent_ht.c	(revision 3942)
+++ src/northbridge/amd/amdk8/coherent_ht.c	(working copy)
@@ -113,9 +113,9 @@
 {
 #if 1
 #if CONFIG_USE_PRINTK_IN_CAR
-	printk_debug("%s%02x\r\n", strval, byteval);
+	printk_debug("%s%02x\n", strval, byteval);
 #else
-	print_debug(strval); print_debug_hex8(byteval); print_debug("\r\n");
+	print_debug(strval); print_debug_hex8(byteval); print_debug("\n");
 #endif
 #endif
 }
@@ -155,7 +155,7 @@
 		HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P;
 	pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val);
 
-	print_spew("done.\r\n");
+	print_spew("done.\n");
 
 }
 
@@ -206,7 +206,7 @@
 	val &= ~((1<<1)|(1<<0));
 	pci_write_config32(NODE_HT(node), 0x6c, val);
 
-	print_spew(" done.\r\n");
+	print_spew(" done.\n");
 }
 
 static void fill_row(u8 node, u8 row, u32 value)
@@ -256,7 +256,7 @@
 	val |= node;  /* new node        */
 	pci_write_config32(NODE_HT(7), 0x60, val);
 
-	print_spew(" done.\r\n");
+	print_spew(" done.\n");
 }
 
 static int verify_connection(u8 dest)
@@ -519,7 +519,7 @@
 		pci_write_config32(NODE_MP(7), reg, value);
 
 	}
-	print_spew("done\r\n");
+	print_spew("done\n");
 }
 
 #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1*/
@@ -658,7 +658,7 @@
 
 static void setup_uniprocessor(void)
 {
-	print_spew("Enabling UP settings\r\n");
+	print_spew("Enabling UP settings\n");
 #if CONFIG_LOGICAL_CPUS==1
 	unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3;
 	if (tmp>0) return;
@@ -1484,7 +1484,7 @@
 {
 	unsigned nodes;
 
-	print_spew("Enabling SMP settings\r\n");
+	print_spew("Enabling SMP settings\n");
 
 	nodes = setup_smp2();
 #if CONFIG_MAX_PHYSICAL_CPUS > 2
@@ -1503,10 +1503,10 @@
 #endif
 
 #if CONFIG_USE_PRINTK_IN_CAR
-	printk_debug("%02x nodes initialized.\r\n", nodes);
+	printk_debug("%02x nodes initialized.\n", nodes);
 #else
 	print_debug_hex8(nodes);
-	print_debug(" nodes initialized.\r\n");
+	print_debug(" nodes initialized.\n");
 #endif
 
 	return nodes;
@@ -1526,14 +1526,14 @@
 #if CONFIG_MAX_PHYSICAL_CPUS > 2
 	case 0x02: /* MPCap    */
 		if(nodes > 2) {
-			print_err("Going back to DP\r\n");
+			print_err("Going back to DP\n");
 			return 2;
 		}
 		break;
 #endif
 	case 0x00: /* Non SMP */
 		if(nodes >1 ) {
-			print_err("Going back to UP\r\n");
+			print_err("Going back to UP\n");
 			return 1;
 		}
 		break;
@@ -1611,7 +1611,7 @@
 	 * registers on Hammer A0 revision.
 	 */
 
-	print_spew("coherent_ht_finalize\r\n");
+	print_spew("coherent_ht_finalize\n");
 #if K8_REV_F_SUPPORT == 0
 	rev_a0 = is_cpu_rev_a0();
 #endif
@@ -1652,7 +1652,7 @@
 #endif
 	}
 
-	print_spew("done\r\n");
+	print_spew("done\n");
 }
 
 static int apply_cpu_errata_fixes(unsigned nodes)
Index: src/northbridge/amd/amdk8/raminit_test.c
===================================================================
--- src/northbridge/amd/amdk8/raminit_test.c	(revision 3942)
+++ src/northbridge/amd/amdk8/raminit_test.c	(working copy)
@@ -394,7 +394,7 @@
 #if 0
 	print_debug("spd_count: ");
 	print_debug_hex32(spd_count);
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 
 }
@@ -410,9 +410,9 @@
 	reset_tests();
 	spd_fail_count = i;
 
-	print_debug("\r\nSPD will fail after: ");
+	print_debug("\nSPD will fail after: ");
 	print_debug_hex32(spd_fail_count);
-	print_debug(" accesses.\r\n");
+	print_debug(" accesses.\n");
 
 	memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
 	memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
Index: src/northbridge/amd/amdk8/raminit.c
===================================================================
--- src/northbridge/amd/amdk8/raminit.c	(revision 3942)
+++ src/northbridge/amd/amdk8/raminit.c	(working copy)
@@ -32,7 +32,7 @@
 	int i;
 //	print_debug("setting up resource map....");
 #if 0
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 	for(i = 0; i < max; i += 3) {
 		device_t dev;
@@ -40,12 +40,12 @@
 		unsigned long reg;
 #if 0
 	#if CONFIG_USE_PRINTK_IN_CAR
-		prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]);
+		printk_debug("%08x <- %08x\n", register_values[i], register_values[i+2]);
 	#else
 		print_debug_hex32(register_values[i]);
 		print_debug(" <-");
 		print_debug_hex32(register_values[i+2]);
-		print_debug("\r\n");
+		print_debug("\n");
 	#endif
 #endif
 		dev = register_values[i] & ~0xfff;
@@ -61,7 +61,7 @@
 		pci_write_config32(register_values[i], reg);
 #endif
 	}
-//	print_debug("done.\r\n");
+//	print_debug("done.\n");
 }
 #endif
 
@@ -549,13 +549,13 @@
 
 #if 1
 	if (!controller_present(ctrl)) {
-//		print_debug("No memory controller present\r\n");
+//		print_debug("No memory controller present\n");
 		return;
 	}
 #endif
 	print_spew("setting up CPU");
 	print_spew_hex8(ctrl->node_id);
-	print_spew(" northbridge registers\r\n");
+	print_spew(" northbridge registers\n");
 	max = ARRAY_SIZE(register_values);
 	for(i = 0; i < max; i += 3) {
 		device_t dev;
@@ -563,12 +563,12 @@
 		unsigned long reg;
 #if 0
 	#if CONFIG_USE_PRINTK_IN_CAR
-		prink_debug("%08x <- %08x\r\n", register_values[i], register_values[i+2]);
+		printk_debug("%08x <- %08x\n", register_values[i], register_values[i+2]);
 	#else
 		print_spew_hex32(register_values[i]);
 		print_spew(" <-");
 		print_spew_hex32(register_values[i+2]);
-		print_spew("\r\n");
+		print_spew("\n");
 	#endif
 #endif
 		dev = (register_values[i] & ~0xfff) - PCI_DEV(0, 0x18, 0) + ctrl->f0;
@@ -585,7 +585,7 @@
 		pci_write_config32(register_values[i], reg);
 #endif
 	}
-	print_spew("done.\r\n");
+	print_spew("done.\n");
 }
 
 
@@ -720,7 +720,7 @@
 	goto out;
 
  val_err:
-	die("Bad SPD value\r\n");
+	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
 hw_err:
 	sz.side1 = 0;
@@ -898,7 +898,7 @@
 	/* Report the amount of memory. */
 	print_spew("RAM: 0x");
 	print_spew_hex32(tom_k);
-	print_spew(" KB\r\n");
+	print_spew(" KB\n");
 
 	/* Now set top of memory */
 	msr_t msr;
@@ -1013,7 +1013,7 @@
 		if(is_dual_channel(ctrl)) {
 		/* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
 			if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
-//     				print_debug("8 4GB chip selects cannot be interleaved\r\n");
+//     				print_debug("8 4GB chip selects cannot be interleaved\n");
 				return 0;
 			}
 			csbase_inc <<=1;
@@ -1023,7 +1023,7 @@
 		csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode];
 		if(is_dual_channel(ctrl)) {
 			if( (bits==3) && (common_cs_mode > 8)) {
-//				print_debug("8 cs_mode>8 chip selects cannot be interleaved\r\n");
+//				print_debug("8 cs_mode>8 chip selects cannot be interleaved\n");
 				return 0;
 			}
 			csbase_inc <<=1;
@@ -1050,7 +1050,7 @@
 		csbase += csbase_inc;
 	}
 
-	print_spew("Interleaved\r\n");
+	print_spew("Interleaved\n");
 
 	/* Return the memory size in K */
 	return common_size << (15 + bits);
@@ -1149,7 +1149,7 @@
 	if (read_option(CMOS_VSTART_interleave_chip_selects, CMOS_VLEN_interleave_chip_selects, 1) != 0) {
 		tom_k = interleave_chip_selects(ctrl);
 	} else {
-		print_debug("Interleaving disabled\r\n");
+		print_debug("Interleaving disabled\n");
 		tom_k = 0;
 	}
 	if (!tom_k) {
@@ -1166,7 +1166,7 @@
 {
 	print_debug("disabling dimm");
 	print_debug_hex8(index);
-	print_debug("\r\n");
+	print_debug("\n");
 	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
 	pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
 	dimm_mask &= ~(1 << index);
@@ -1223,9 +1223,9 @@
 	pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
 #if 0
 	if (is_registered(ctrl)) {
-		print_debug("Registered\r\n");
+		print_debug("Registered\n");
 	} else {
-		print_debug("Unbuffered\r\n");
+		print_debug("Unbuffered\n");
 	}
 #endif
 	return dimm_mask;
@@ -1320,7 +1320,7 @@
 			}
 		}
 	}
-	print_spew("Enabling dual channel memory\r\n");
+	print_spew("Enabling dual channel memory\n");
 	uint32_t dcl;
 	dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
 	dcl &= ~DCL_32ByteEn;
@@ -1350,7 +1350,7 @@
 {
 	static const struct mem_param speed[] = {
 		{
-			.name	    = "100Mhz\r\n",
+			.name	    = "100Mhz\n",
 			.cycle_time = 0xa0,
 			.divisor    = (10 <<1),
 			.tRC	    = 0x46,
@@ -1364,7 +1364,7 @@
 			.rdpreamble = { ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0), ((9 << 1) + 0) }
 		},
 		{
-			.name	    = "133Mhz\r\n",
+			.name	    = "133Mhz\n",
 			.cycle_time = 0x75,
 			.divisor    = (7<<1)+1,
 			.tRC	    = 0x41,
@@ -1378,7 +1378,7 @@
 			.rdpreamble = { ((8 << 1) + 0), ((7 << 1) + 0), ((7 << 1) + 1), ((7 << 1) + 0) }
 		},
 		{
-			.name	    = "166Mhz\r\n",
+			.name	    = "166Mhz\n",
 			.cycle_time = 0x60,
 			.divisor    = (6<<1),
 			.tRC	    = 0x3C,
@@ -1392,7 +1392,7 @@
 			.rdpreamble = { ((7 << 1) + 1), ((6 << 1) + 0), ((6 << 1) + 1), ((6 << 1) + 0) }
 		},
 		{
-			.name	    = "200Mhz\r\n",
+			.name	    = "200Mhz\n",
 			.cycle_time = 0x50,
 			.divisor    = (5<<1),
 			.tRC	    = 0x37,
@@ -1941,7 +1941,7 @@
 
 	clocks = param->dtl_trwt[lat][mtype];
 	if ((clocks < DTH_TRWT_MIN) || (clocks > DTH_TRWT_MAX)) {
-		die("Unknown Trwt\r\n");
+		die("Unknown Trwt\n");
 	}
 
 	dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
@@ -2114,7 +2114,7 @@
 	long dimm_mask;
 #if 1
 	if (!controller_present(ctrl)) {
-//		print_debug("No memory controller present\r\n");
+//		print_debug("No memory controller present\n");
 		return;
 	}
 #endif
@@ -2122,7 +2122,7 @@
 	activate_spd_rom(ctrl);
 	dimm_mask = spd_detect_dimms(ctrl);
 	if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
-		print_debug("No memory for this cpu\r\n");
+		print_debug("No memory for this cpu\n");
 		return;
 	}
 	dimm_mask = spd_enable_2channels(ctrl, dimm_mask);
@@ -2146,7 +2146,7 @@
 	return;
  hw_spd_err:
 	/* Unrecoverable error reading SPD data */
-	print_err("SPD error - reset\r\n");
+	print_err("SPD error - reset\n");
 	hard_reset();
 	return;
 }
@@ -2272,7 +2272,7 @@
 
 	/* Error if I don't have memory */
 	if (memory_end_k(ctrl, controllers) == 0) {
-		die("No memory\r\n");
+		die("No memory\n");
 	}
 
 	/* Before enabling memory start the memory clocks */
@@ -2313,7 +2313,7 @@
 		dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
 		if (dcl & DCL_DimmEccEn) {
 			uint32_t mnc;
-			print_spew("ECC enabled\r\n");
+			print_spew("ECC enabled\n");
 			mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
 			mnc |= MNC_ECC_EN;
 			if (dcl & DCL_128BitEn) {
@@ -2352,7 +2352,7 @@
 			}
 		} while(((dcl & DCL_DramInit) != 0) && (loops < TIMEOUT_LOOPS));
 		if (loops >= TIMEOUT_LOOPS) {
-			print_debug(" failed\r\n");
+			print_debug(" failed\n");
 			continue;
 		}
 
@@ -2365,7 +2365,7 @@
 			} while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) );
 		}
 
-		print_debug(" done\r\n");
+		print_debug(" done\n");
 	}
 
 #if HW_MEM_HOLE_SIZEK != 0
@@ -2397,7 +2397,7 @@
 	/* The first 1M is now setup, use it */
 	cache_lbmem(MTRR_TYPE_WRBACK);
 
-	print_debug(" done\r\n");
+	print_debug(" done\n");
 #endif
 }
 
Index: src/northbridge/amd/amdk8/setup_resource_map.c
===================================================================
--- src/northbridge/amd/amdk8/setup_resource_map.c	(revision 3942)
+++ src/northbridge/amd/amdk8/setup_resource_map.c	(working copy)
@@ -5,7 +5,7 @@
 	int i;
 //      print_debug("setting up resource map offset....");
 #if 0
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 	for(i = 0; i < max; i += 3) {
 		device_t dev;
@@ -13,12 +13,12 @@
 		unsigned long reg;
 #if 0
 	#if CONFIG_USE_PRINTK_IN_CAR
-		prink_debug("%08x <- %08x\r\n", register_values[i] +  offset_pci_dev, register_values[i+2]);
+		printk_debug("%08x <- %08x\n", register_values[i] +  offset_pci_dev, register_values[i+2]);
 	#else
 		print_debug_hex32(register_values[i] + offset_pci_dev);
 		print_debug(" <-");
 		print_debug_hex32(register_values[i+2]);
-		print_debug("\r\n");
+		print_debug("\n");
 	#endif
 #endif
 		dev = (register_values[i] & ~0xfff) + offset_pci_dev;
@@ -34,7 +34,7 @@
 		pci_write_config32(register_values[i], reg);
 #endif
 	}
-//      print_debug("done.\r\n");
+//      print_debug("done.\n");
 }
 
 #define RES_PCI_IO 0x10
@@ -52,12 +52,12 @@
 #endif
 
 #if RES_DEBUG
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 	for(i = 0; i < max; i += 4) {
 #if RES_DEBUG
 	#if CONFIG_USE_PRINTK_IN_CAR
-		printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
+		printk_debug("%04x: %02x %08x <- & %08x | %08x\n",
 			i>>2, register_values[i],
 			register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
 			register_values[i+2],
@@ -75,7 +75,7 @@
 		print_debug_hex32(register_values[i+3] +
 			(((register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0)
 			);
-		print_debug("\r\n");
+		print_debug("\n");
 	#endif
 #endif
 		switch (register_values[i]) {
@@ -134,7 +134,7 @@
 	}
 
 #if RES_DEBUG
-	print_debug("done.\r\n");
+	print_debug("done.\n");
 #endif
 }
 static void setup_resource_map_x(const unsigned int *register_values, int max)
@@ -147,12 +147,12 @@
 #endif
 
 #if RES_DEBUG
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 	for(i = 0; i < max; i += 4) {
 #if RES_DEBUG
 	#if CONFIG_USE_PRINTK_IN_CAR
-		printk_debug("%04x: %02x %08x <- & %08x | %08x\r\n",
+		printk_debug("%04x: %02x %08x <- & %08x | %08x\n",
 			i/4, register_values[i],register_values[i+1], register_values[i+2], register_values[i+3]);
 	#else
 		print_debug_hex16(i/4);
@@ -164,7 +164,7 @@
 		print_debug_hex32(register_values[i+2]);
 		print_debug(" | ");
 		print_debug_hex32(register_values[i+3]);
-		print_debug("\r\n");
+		print_debug("\n");
 	#endif
 #endif
 		switch (register_values[i]) {
@@ -223,7 +223,7 @@
 	}
 
 #if RES_DEBUG
-	print_debug("done.\r\n");
+	print_debug("done.\n");
 #endif
 }
 
@@ -258,7 +258,7 @@
 		print_debug(" -> ");
 		reg = inb(where);
 		print_debug_hex8(reg);
-		print_debug("\r\n");
+		print_debug("\n");
 #endif
 	}
 }
@@ -297,7 +297,7 @@
 		print_debug(" -> ");
 		reg = inl(where);
 		print_debug_hex32(reg);
-		print_debug("\r\n");
+		print_debug("\n");
 #endif
 	}
 }
@@ -324,7 +324,7 @@
 		print_debug(" RB ");
 		reg = read32(where);
 		print_debug_hex32(reg);
-		print_debug("\r\n");
+		print_debug("\n");
 #endif
 	}
 }
Index: src/northbridge/amd/amdk8/northbridge.c
===================================================================
--- src/northbridge/amd/amdk8/northbridge.c	(revision 3942)
+++ src/northbridge/amd/amdk8/northbridge.c	(working copy)
@@ -1247,7 +1247,7 @@
 				       e0_later_single_core = 0;
 	       			}
 				if(e0_later_single_core) {
-					printk_debug("\tFound Rev E or Rev F later single core\r\n");
+					printk_debug("\tFound Rev E or Rev F later single core\n");
 
 					j=1;
 				}
Index: src/northbridge/amd/amdk8/raminit_f_dqs.c
===================================================================
--- src/northbridge/amd/amdk8/raminit_f_dqs.c	(revision 3942)
+++ src/northbridge/amd/amdk8/raminit_f_dqs.c	(working copy)
@@ -30,7 +30,7 @@
 {
 #if DQS_TRAIN_DEBUG > 0
 	if(DQS_TRAIN_DEBUG > level) {
-		printk_debug("%s%x\r\n", str, val);
+		printk_debug("%s%x\n", str, val);
 	}
 #endif
 }
@@ -39,7 +39,7 @@
 {
 #if DQS_TRAIN_DEBUG > 0
 	if(DQS_TRAIN_DEBUG > level) {
-		printk_debug("%s%08x%s%08x\r\n", str, val, str2, val2);
+		printk_debug("%s%08x%s%08x\n", str, val, str2, val2);
 	}
 #endif
 }
@@ -48,14 +48,14 @@
 {
 #if DQS_TRAIN_DEBUG > 0
 	if(DQS_TRAIN_DEBUG > level) {
-		printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2);
+		printk_debug("%s[%02x]=%08x%08x\n", str, i, val, val2);
 	}
 #endif
 }
 
 static inline void print_debug_dqs_tsc_x(const char *str, unsigned i, unsigned val, unsigned val2)
 {
-	printk_debug("%s[%02x]=%08x%08x\r\n", str, i, val, val2);
+	printk_debug("%s[%02x]=%08x%08x\n", str, i, val, val2);
 
 }
 
@@ -586,7 +586,7 @@
 		}
 	}
 
-	print_debug_dqs("\r\nTrainRcvEn: 0 ctrl", ctrl->node_id, 0);
+	print_debug_dqs("\nTrainRcvEn: 0 ctrl", ctrl->node_id, 0);
 
 	print_debug_addr("TrainRcvEn: buf_a:", buf_a);
 
@@ -1404,7 +1404,7 @@
 
 	}
 
-	print_debug_dqs("\r\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0);
+	print_debug_dqs("\nTrainDQSRdWrPos: 0 ctrl ", ctrl->node_id, 0);
 
 	printk_debug("TrainDQSRdWrPos: buf_a:%p\n", buf_a);
 
@@ -1528,25 +1528,25 @@
 
 static unsigned train_DqsRcvrEn(const struct mem_controller *ctrl, unsigned Pass, struct sys_info *sysinfo)
 {
-	print_debug_dqs("\r\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0);
+	print_debug_dqs("\ntrain_DqsRcvrEn: begin ctrl ", ctrl->node_id, 0);
 	if(TrainRcvrEn(ctrl, Pass, sysinfo)) {
 		return 1;
 	}
-	print_debug_dqs("\r\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0);
+	print_debug_dqs("\ntrain_DqsRcvrEn: end ctrl ", ctrl->node_id, 0);
 	return 0;
 
 }
 static unsigned train_DqsPos(const struct mem_controller *ctrl, struct sys_info *sysinfo)
 {
-	print_debug_dqs("\r\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0);
+	print_debug_dqs("\ntrain_DqsPos: begin ctrl ", ctrl->node_id, 0);
 	if(TrainDQSRdWrPos(ctrl, sysinfo) != 0) {
-		printk_err("\r\nDQS Training Rd Wr failed ctrl%02x\r\n", ctrl->node_id);
+		printk_err("\nDQS Training Rd Wr failed ctrl%02x\n", ctrl->node_id);
 		return 1;
 	}
 	else {
 		SetEccDQSRdWrPos(ctrl, sysinfo);
 	}
-	print_debug_dqs("\r\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0);
+	print_debug_dqs("\ntrain_DqsPos: end ctrl ", ctrl->node_id, 0);
 	return 0;
 
 }
@@ -1703,7 +1703,7 @@
 		}
 		sizek = 1 << align;
 #if MEM_TRAIN_SEQ != 1
-		printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\r\n",
+		printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type %s\n",
 			reg, range_startk >>10, sizek >> 10,
 			(type==MTRR_TYPE_UNCACHEABLE)?"UC":
 			    ((type==MTRR_TYPE_WRBACK)?"WB":"Other")
@@ -1858,7 +1858,7 @@
 
 		printk_debug("DQS Training:RcvrEn:Pass1: %02x\n", i);
 		if(train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out;
-       		printk_debug(" done\r\n");
+       		printk_debug(" done\n");
 	}
 
 	tsc[1] = rdtsc();
@@ -1876,7 +1876,7 @@
 
 		printk_debug("DQS Training:DQSPos: %02x\n", i);
 		if(train_DqsPos(ctrl+i, sysinfo)) goto out;
-		printk_debug(" done\r\n");
+		printk_debug(" done\n");
 	}
 
 	tsc[3] = rdtsc();
@@ -1889,7 +1889,7 @@
 
 		printk_debug("DQS Training:RcvrEn:Pass2: %02x\n", i);
 		if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out;
-		printk_debug(" done\r\n");
+		printk_debug(" done\n");
 		sysinfo->mem_trained[i]=1;
 	}
 
@@ -1938,7 +1938,7 @@
 	}
 
 	if(v) {
-		printk_debug(" done\r\n");
+		printk_debug(" done\n");
 		tsc[1] = rdtsc();
 		printk_debug("set DQS timing:DQSPos: %02x\n", i);
 	}
@@ -1949,7 +1949,7 @@
 	}
 
 	if(v) {
-		printk_debug(" done\r\n");
+		printk_debug(" done\n");
 		tsc[2] = rdtsc();
 
 		printk_debug("set DQS timing:RcvrEn:Pass2: %02x\n", i);
@@ -1960,7 +1960,7 @@
 	}
 
 	if(v) {
-		printk_debug(" done\r\n");
+		printk_debug(" done\n");
 
 		tsc[3] = rdtsc();
 	}
Index: src/northbridge/amd/amdk8/debug.c
===================================================================
--- src/northbridge/amd/amdk8/debug.c	(revision 3942)
+++ src/northbridge/amd/amdk8/debug.c	(working copy)
@@ -7,9 +7,9 @@
 {
 #if CACHE_AS_RAM_ADDRESS_DEBUG == 1
 	#if CONFIG_USE_PRINTK_IN_CAR
-		printk_debug("------Address debug: %s%x------\r\n", str, val);
+		printk_debug("------Address debug: %s%x------\n", str, val);
 	#else
-		print_debug ("------Address debug: "); print_debug(str); print_debug_hex32(val); print_debug("------\r\n");
+		print_debug ("------Address debug: "); print_debug(str); print_debug_hex32(val); print_debug("------\n");
 	#endif
 #endif
 }
@@ -44,11 +44,11 @@
 		}
 		print_debug_pci_dev(dev);
 #if CONFIG_USE_PRINTK_IN_CAR
-		printk_debug(" %04x:%04x\r\n", (id & 0xffff), (id>>16));
+		printk_debug(" %04x:%04x\n", (id & 0xffff), (id>>16));
 #else
 		print_debug(" ");
 		print_debug_hex32(id);
-		print_debug("\r\n");
+		print_debug("\n");
 #endif
 		if(((dev>>12) & 0x07) == 0) {
 			uint8_t hdr_type;
@@ -69,9 +69,9 @@
 		unsigned char val;
 		if ((i & 0x0f) == 0) {
 #if CONFIG_USE_PRINTK_IN_CAR
-			printk_debug("\r\n%02x:",i);
+			printk_debug("\n%02x:",i);
 #else
-			print_debug("\r\n");
+			print_debug("\n");
 			print_debug_hex8(i);
 			print_debug_char(':');
 #endif
@@ -84,7 +84,7 @@
 		print_debug_hex8(val);
 #endif
 	}
-	print_debug("\r\n");
+	print_debug("\n");
 }
 
 #if K8_REV_F_SUPPORT == 1
@@ -99,9 +99,9 @@
 		uint32_t val;
 		int j;
 #if CONFIG_USE_PRINTK_IN_CAR
-		printk_debug("\r\n%02x:",i);
+		printk_debug("\n%02x:",i);
 #else
-		print_debug("\r\n");
+		print_debug("\n");
 		print_debug_hex8(i);
 		print_debug_char(':');
 #endif
@@ -116,7 +116,7 @@
 		}
 
 	}
-	print_debug("\r\n");
+	print_debug("\n");
 }
 #endif
 
@@ -178,7 +178,7 @@
 static void dump_spd_registers(const struct mem_controller *ctrl)
 {
 	int i;
-	print_debug("\r\n");
+	print_debug("\n");
 	for(i = 0; i < 4; i++) {
 		unsigned device;
 		device = ctrl->channel0[i];
@@ -197,9 +197,9 @@
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
 #if CONFIG_USE_PRINTK_IN_CAR
-					printk_debug("\r\n%02x: ", j);
+					printk_debug("\n%02x: ", j);
 #else
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 #endif
@@ -216,7 +216,7 @@
 				print_debug_char(' ');
 #endif
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 		device = ctrl->channel1[i];
 		if (device) {
@@ -234,9 +234,9 @@
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
 #if CONFIG_USE_PRINTK_IN_CAR
-					printk_debug("\r\n%02x: ", j);
+					printk_debug("\n%02x: ", j);
 #else
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 #endif
@@ -253,14 +253,14 @@
 				print_debug_char(' ');
 #endif
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
 static void dump_smbus_registers(void)
 {
 	unsigned device;
-	print_debug("\r\n");
+	print_debug("\n");
 	for(device = 1; device < 0x80; device++) {
 		int j;
 		if( smbus_read_byte(device, 0) < 0 ) continue;
@@ -279,9 +279,9 @@
 			}
 			if ((j & 0xf) == 0) {
 #if CONFIG_USE_PRINTK_IN_CAR
-				printk_debug("\r\n%02x: ",j);
+				printk_debug("\n%02x: ",j);
 #else
-				print_debug("\r\n");
+				print_debug("\n");
 				print_debug_hex8(j);
 				print_debug(": ");
 #endif
@@ -294,7 +294,7 @@
 			print_debug_char(' ');
 #endif
 		}
-		print_debug("\r\n");
+		print_debug("\n");
 	}
 }
 #endif
@@ -305,10 +305,10 @@
 	int i;
 	udelay(2000);
 #if CONFIG_USE_PRINTK_IN_CAR
-	printk_debug("%04x:\r\n", port);
+	printk_debug("%04x:\n", port);
 #else
 	print_debug_hex16(port);
-	print_debug(":\r\n");
+	print_debug(":\n");
 #endif
 	for(i=0;i<256;i++) {
 		uint8_t val;
@@ -328,7 +328,7 @@
 		print_debug_hex8(val);
 #endif
 		if ((i & 0x0f) == 0x0f) {
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 		port++;
 	}
@@ -341,9 +341,9 @@
 	for(i=start;i<end;i++) {
 		if((i & 0xf)==0) {
 #if CONFIG_USE_PRINTK_IN_CAR
-			printk_debug("\r\n%08x:", i);
+			printk_debug("\n%08x:", i);
 #else
-			print_debug("\r\n");
+			print_debug("\n");
 			print_debug_hex32(i);
 			print_debug(":");
 #endif
@@ -355,6 +355,6 @@
 	     	print_debug_hex8((unsigned char)*((unsigned char *)i));
 #endif
 	}
-	print_debug("\r\n");
+	print_debug("\n");
  }
 #endif
Index: src/northbridge/amd/amdk8/incoherent_ht.c
===================================================================
--- src/northbridge/amd/amdk8/incoherent_ht.c	(revision 3942)
+++ src/northbridge/amd/amdk8/incoherent_ht.c	(working copy)
@@ -30,7 +30,7 @@
 
 static inline void print_linkn_in (const char *strval, uint8_t byteval)
 {
-	printk_debug("%s%02x\r\n", strval, byteval);
+	printk_debug("%s%02x\n", strval, byteval);
 }
 
 static uint8_t ht_lookup_capability(device_t dev, uint16_t val)
@@ -131,7 +131,7 @@
 	uint32_t id;
 
 	freq_cap = pci_read_config16(dev, pos);
-	printk_spew("pos=0x%x, unfiltered freq_cap=0x%x\r\n", pos, freq_cap);
+	printk_spew("pos=0x%x, unfiltered freq_cap=0x%x\n", pos, freq_cap);
 	freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
 
 	id = pci_read_config32(dev, 0);
@@ -161,8 +161,8 @@
 	#endif
 	}
 
-	printk_spew("pos=0x%x, filtered freq_cap=0x%x\r\n", pos, freq_cap);
-	//printk_spew("capping to 800/600/400/200 MHz\r\n");
+	printk_spew("pos=0x%x, filtered freq_cap=0x%x\n", pos, freq_cap);
+	//printk_spew("capping to 800/600/400/200 MHz\n");
 	//freq_cap &= 0x3f;
 	return freq_cap;
 }
@@ -224,14 +224,14 @@
 	int needs_reset;
 	/* Set link width and frequency */
 
-	printk_spew("entering ht_optimize_link\r\n");
+	printk_spew("entering ht_optimize_link\n");
 	/* Initially assume everything is already optimized and I don't need a reset */
 	needs_reset = 0;
 
 	/* Get the frequency capabilities */
 	freq_cap1 = ht_read_freq_cap(dev1, pos1 + LINK_FREQ_CAP(offs1));
 	freq_cap2 = ht_read_freq_cap(dev2, pos2 + LINK_FREQ_CAP(offs2));
-	printk_spew("freq_cap1=0x%x, freq_cap2=0x%x\r\n", freq_cap1, freq_cap2);
+	printk_spew("freq_cap1=0x%x, freq_cap2=0x%x\n", freq_cap1, freq_cap2);
 
 	/* Calculate the highest possible frequency */
 	freq = log2(freq_cap1 & freq_cap2);
@@ -240,11 +240,11 @@
 	old_freq = pci_read_config8(dev1, pos1 + LINK_FREQ(offs1));
 	old_freq &= 0x0f;
 	needs_reset |= old_freq != freq;
-	printk_spew("dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset);
+	printk_spew("dev1 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset);
 	old_freq = pci_read_config8(dev2, pos2 + LINK_FREQ(offs2));
 	old_freq &= 0x0f;
 	needs_reset |= old_freq != freq;
-	printk_spew("dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\r\n", old_freq, freq, needs_reset);
+	printk_spew("dev2 old_freq=0x%x, freq=0x%x, needs_reset=0x%0x\n", old_freq, freq, needs_reset);
 
 	/* Set the Calculated link frequency */
 	pci_write_config8(dev1, pos1 + LINK_FREQ(offs1), freq);
@@ -253,45 +253,45 @@
 	/* Get the width capabilities */
 	width_cap1 = ht_read_width_cap(dev1, pos1 + LINK_WIDTH(offs1));
 	width_cap2 = ht_read_width_cap(dev2, pos2 + LINK_WIDTH(offs2));
-	printk_spew("width_cap1=0x%x, width_cap2=0x%x\r\n", width_cap1, width_cap2);
+	printk_spew("width_cap1=0x%x, width_cap2=0x%x\n", width_cap1, width_cap2);
 
 	/* Calculate dev1's input width */
 	ln_width1 = link_width_to_pow2[width_cap1 & 7];
 	ln_width2 = link_width_to_pow2[(width_cap2 >> 4) & 7];
-	printk_spew("dev1 input ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2);
+	printk_spew("dev1 input ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2);
 	if (ln_width1 > ln_width2) {
 		ln_width1 = ln_width2;
 	}
 	width = pow2_to_link_width[ln_width1];
-	printk_spew("dev1 input width=0x%x\r\n", width);
+	printk_spew("dev1 input width=0x%x\n", width);
 	/* Calculate dev1's output width */
 	ln_width1 = link_width_to_pow2[(width_cap1 >> 4) & 7];
 	ln_width2 = link_width_to_pow2[width_cap2 & 7];
-	printk_spew("dev1 output ln_width1=0x%x, ln_width2=0x%x\r\n", ln_width1, ln_width2);
+	printk_spew("dev1 output ln_width1=0x%x, ln_width2=0x%x\n", ln_width1, ln_width2);
 	if (ln_width1 > ln_width2) {
 		ln_width1 = ln_width2;
 	}
 	width |= pow2_to_link_width[ln_width1] << 4;
-	printk_spew("dev1 input|output width=0x%x\r\n", width);
+	printk_spew("dev1 input|output width=0x%x\n", width);
 
 	/* See if I am changing dev1's width */
 	old_width = pci_read_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1);
 	old_width &= 0x77;
 	needs_reset |= old_width != width;
-	printk_spew("old dev1 input|output width=0x%x\r\n", width);
+	printk_spew("old dev1 input|output width=0x%x\n", width);
 
 	/* Set dev1's widths */
 	pci_write_config8(dev1, pos1 + LINK_WIDTH(offs1) + 1, width);
 
 	/* Calculate dev2's width */
 	width = ((width & 0x70) >> 4) | ((width & 0x7) << 4);
-	printk_spew("dev2 input|output width=0x%x\r\n", width);
+	printk_spew("dev2 input|output width=0x%x\n", width);
 
 	/* See if I am changing dev2's width */
 	old_width = pci_read_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1);
 	old_width &= 0x77;
 	needs_reset |= old_width != width;
-	printk_spew("old dev2 input|output width=0x%x\r\n", width);
+	printk_spew("old dev2 input|output width=0x%x\n", width);
 
 	/* Set dev2's widths */
 	pci_write_config8(dev2, pos2 + LINK_WIDTH(offs2) + 1, width);
@@ -491,7 +491,7 @@
 			print_err("udev="); print_err_hex32(udev);
 			print_err("\tupos="); print_err_hex32(upos);
 			print_err("\tuoffs="); print_err_hex32(uoffs);
-			print_err("\tHT link capability not found\r\n");
+			print_err("\tHT link capability not found\n");
 			break;
 		}
 
@@ -982,16 +982,16 @@
 
 	unsigned link_pair_num = sysinfo->link_pair_num;
 
-	printk_spew("entering optimize_link_incoherent_ht\r\n");
-	printk_spew("sysinfo->link_pair_num=0x%x\r\n", link_pair_num);
+	printk_spew("entering optimize_link_incoherent_ht\n");
+	printk_spew("sysinfo->link_pair_num=0x%x\n", link_pair_num);
 	for(i=0; i< link_pair_num; i++) {
 		struct link_pair_st *link_pair= &sysinfo->link_pair[i];
 		reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs);
-		printk_spew("after ht_optimize_link for link pair %d, reset_needed=0x%x\r\n", i, reset_needed);
+		printk_spew("after ht_optimize_link for link pair %d, reset_needed=0x%x\n", i, reset_needed);
 	}
 
 	reset_needed |= optimize_link_read_pointers_chain(sysinfo->ht_c_num);
-	printk_spew("after optimize_link_read_pointers_chain, reset_needed=0x%x\r\n", reset_needed);
+	printk_spew("after optimize_link_read_pointers_chain, reset_needed=0x%x\n", reset_needed);
 
 	return reset_needed;
 
Index: src/northbridge/intel/e7501/raminit.c
===================================================================
--- src/northbridge/intel/e7501/raminit.c	(revision 3942)
+++ src/northbridge/intel/e7501/raminit.c	(working copy)
@@ -38,7 +38,7 @@
 #endif
 
 #define E7501_SDRAM_MODE	(SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4)
-#define SPD_ERROR			"Error reading SPD info\r\n"
+#define SPD_ERROR			"Error reading SPD info\n"
 
 // NOTE: This used to be 0x100000.
 //		 That doesn't work on systems where A20M# is asserted, because
@@ -484,7 +484,7 @@
 static void die_on_spd_error(int spd_return_value)
 {
 	if (spd_return_value < 0)
-		die("Error reading SPD info\r\n");
+		die("Error reading SPD info\n");
 }
 
 //----------------------------------------------------------------------------------
@@ -525,7 +525,7 @@
 	value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS);
 	if (value < 0) goto hw_err;
 	if (value > 2) 
-		die("Bad SPD value\r\n");
+		die("Bad SPD value\n");
 	if (value == 2) {
 
 		pgsz.side2 = pgsz.side1;		// Assume symmetric banks until we know differently
@@ -758,7 +758,7 @@
 		spd_value = spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
 		if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
 			
-			print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
+			print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
 			continue;
 		}
 
@@ -783,11 +783,11 @@
 			dimm_mask |= ((1<<i) | (1<<(MAX_DIMM_SOCKETS_PER_CHANNEL + i)));
 		}
 		else
-			print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
+			print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
 #else
 		switch (bDualChannel) {
 		case 0:
-			print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\r\n");
+			print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
 			break;
 		
 		default:
@@ -878,7 +878,7 @@
 
 				RAM_DEBUG_MESSAGE("    Sending RAM command to 0x");
 				RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits);
-				RAM_DEBUG_MESSAGE("\r\n");
+				RAM_DEBUG_MESSAGE("\n");
 				read32(dimm_start_address + e7501_mode_bits);
 
 				// Set the start of the next DIMM
@@ -1025,10 +1025,10 @@
         RAM_DEBUG_HEX32(sz.side1);
         RAM_DEBUG_MESSAGE(" ");
         RAM_DEBUG_HEX32(sz.side2);
-        RAM_DEBUG_MESSAGE("\r\n");
+        RAM_DEBUG_MESSAGE("\n");
 
 		if (sz.side1 == 0)
-			die("Bad SPD value\r\n");
+			die("Bad SPD value\n");
 
 		total_dram_64M_multiple = configure_dimm_row_boundaries(ctrl, sz, total_dram_64M_multiple, i);
 	}
@@ -1114,7 +1114,7 @@
 		
 		uint8_t byte;
 
-		RAM_DEBUG_MESSAGE("Initializing ECC state...\r\n");
+		RAM_DEBUG_MESSAGE("Initializing ECC state...\n");
 		/* Initialize ECC bits , use ECC zero mode (new to 7501)*/
 		pci_write_config8(ctrl->d0, MCHCFGNS, 0x06);
 		pci_write_config8(ctrl->d0, MCHCFGNS, 0x07);
@@ -1126,7 +1126,7 @@
 		} while ( (byte & 0x08 ) == 0);
 
 		pci_write_config8(ctrl->d0, MCHCFGNS, byte & 0xfc);
-		RAM_DEBUG_MESSAGE("ECC state initialized.\r\n");	
+		RAM_DEBUG_MESSAGE("ECC state initialized.\n");	
 
 		/* Clear the ECC error bits */
 		pci_write_config8(ctrl->d0f1, DRAM_FERR, 0x03);
@@ -1382,7 +1382,7 @@
 		}
 	}
 	else
-		die("No CAS# latencies compatible with all DIMMs!!\r\n");
+		die("No CAS# latencies compatible with all DIMMs!!\n");
 
 	pci_write_config32(ctrl->d0, DRT, dram_timing);
 
@@ -1471,14 +1471,14 @@
 		die_on_spd_error(value);
 		value &= 0x7f;		// Mask off self-refresh bit
 		if(value > MAX_SPD_REFRESH_RATE) { 
-			print_err("unsupported refresh rate\r\n");
+			print_err("unsupported refresh rate\n");
 			continue;
 		}
 		
 		// Get the appropriate E7501 refresh mode for this DIMM
 		dimm_refresh_mode = refresh_rate_map[value];
 		if (dimm_refresh_mode > 7) {
-			print_err("unsupported refresh rate\r\n");
+			print_err("unsupported refresh rate\n");
 			continue;
 		}
 
@@ -1693,7 +1693,7 @@
 	uint32_t dword;
 	uint8_t maybe_strength_control;
 
-	RAM_DEBUG_MESSAGE("Setting RCOMP registers.\r\n");
+	RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n");
 
 	/*enable access to the rcomp bar*/
 	dword = pci_read_config32(ctrl->d0, MAYBE_MCHTST);
@@ -1818,8 +1818,8 @@
 		return;
 
 	/* 1 & 2 Power up and start clocks */
-	RAM_DEBUG_MESSAGE("Ram Enable 1\r\n");
-	RAM_DEBUG_MESSAGE("Ram Enable 2\r\n");
+	RAM_DEBUG_MESSAGE("Ram Enable 1\n");
+	RAM_DEBUG_MESSAGE("Ram Enable 2\n");
 
 	/* A 200us delay is needed */
 
@@ -1827,23 +1827,23 @@
 	EXTRA_DELAY
 
 	/* 3. Apply NOP */
-	RAM_DEBUG_MESSAGE("Ram Enable 3\r\n");
+	RAM_DEBUG_MESSAGE("Ram Enable 3\n");
 	do_ram_command(ctrl, RAM_COMMAND_NOP, 0);
 	EXTRA_DELAY
 
 	/* 4 Precharge all */
-	RAM_DEBUG_MESSAGE("Ram Enable 4\r\n");
+	RAM_DEBUG_MESSAGE("Ram Enable 4\n");
 	do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0);
 	EXTRA_DELAY
 	
 	/* wait until the all banks idle state... */
 	/* 5. Issue EMRS to enable DLL */
-	RAM_DEBUG_MESSAGE("Ram Enable 5\r\n");
+	RAM_DEBUG_MESSAGE("Ram Enable 5\n");
 	do_ram_command(ctrl, RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE | SDRAM_EXTMODE_DRIVE_NORMAL);
 	EXTRA_DELAY
 	
 	/* 6. Reset DLL */
-	RAM_DEBUG_MESSAGE("Ram Enable 6\r\n");
+	RAM_DEBUG_MESSAGE("Ram Enable 6\n");
 	set_ram_mode(ctrl, E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET);
 	EXTRA_DELAY
 
@@ -1855,12 +1855,12 @@
 	EXTRA_DELAY
 	
 	/* 7 Precharge all */
-	RAM_DEBUG_MESSAGE("Ram Enable 7\r\n");
+	RAM_DEBUG_MESSAGE("Ram Enable 7\n");
 	do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0);
 	EXTRA_DELAY
 	
 	/* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */
-	RAM_DEBUG_MESSAGE("Ram Enable 8\r\n");
+	RAM_DEBUG_MESSAGE("Ram Enable 8\n");
 	do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
 	EXTRA_DELAY
 	do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
@@ -1880,17 +1880,17 @@
 	EXTRA_DELAY
 
 	/* 9 mode register set */
-	RAM_DEBUG_MESSAGE("Ram Enable 9\r\n");
+	RAM_DEBUG_MESSAGE("Ram Enable 9\n");
 	set_ram_mode(ctrl, E7501_SDRAM_MODE | SDRAM_MODE_NORMAL);
 	EXTRA_DELAY
 	
 	/* 10 DDR Receive FIFO RE-Sync */
-	RAM_DEBUG_MESSAGE("Ram Enable 10\r\n");
+	RAM_DEBUG_MESSAGE("Ram Enable 10\n");
 	RAM_RESET_DDR_PTR(ctrl);
 	EXTRA_DELAY
 	
 	/* 11 normal operation */
-	RAM_DEBUG_MESSAGE("Ram Enable 11\r\n");
+	RAM_DEBUG_MESSAGE("Ram Enable 11\n");
 	do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0);
 	EXTRA_DELAY
 
@@ -1910,7 +1910,7 @@
 	dram_controller_mode |= (1<<17);		// NOTE: undocumented reserved bit
 	pci_write_config32(ctrl->d0, DRC, dram_controller_mode);
 
-	RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\r\n");
+	RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n");
 	DUMPNORTH();
 
 //	verify_ram();
@@ -1930,19 +1930,19 @@
 {
 	uint8_t dimm_mask;
 
-	RAM_DEBUG_MESSAGE("Reading SPD data...\r\n");
+	RAM_DEBUG_MESSAGE("Reading SPD data...\n");
 
    //activate_spd_rom(ctrl);	Not necessary for this chipset
 
     dimm_mask = spd_get_supported_dimms(ctrl);
 
 	if (dimm_mask == 0) {
-		print_debug("No usable memory for this controller\r\n");
+		print_debug("No usable memory for this controller\n");
     } else {
 
 		enable_e7501_clocks(ctrl, dimm_mask);
 
-		RAM_DEBUG_MESSAGE("setting based on SPD data...\r\n");
+		RAM_DEBUG_MESSAGE("setting based on SPD data...\n");
 
 		configure_e7501_row_attributes(ctrl, dimm_mask);
 		configure_e7501_dram_controller_mode(ctrl, dimm_mask);
@@ -1951,7 +1951,7 @@
 
 		configure_e7501_dram_timing(ctrl, dimm_mask);
 		DO_DELAY
-		RAM_DEBUG_MESSAGE("done\r\n");
+		RAM_DEBUG_MESSAGE("done\n");
 	}
 
 	// NOTE: configure_e7501_ram_addresses() is NOT called here.
@@ -1976,7 +1976,7 @@
 //
 static void sdram_set_registers(const struct mem_controller *ctrl)
 {
-	RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\r\n");
+	RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n");
 	DUMPNORTH();
 
 	ram_set_rcomp_regs(ctrl);
Index: src/northbridge/intel/e7501/debug.c
===================================================================
--- src/northbridge/intel/e7501/debug.c	(revision 3942)
+++ src/northbridge/intel/e7501/debug.c	(working copy)
@@ -27,7 +27,7 @@
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		print_debug("\r\n");
+		print_debug("\n");
 	}
 }
 
@@ -40,9 +40,9 @@
 		unsigned char val;
 		if ((i & 0x0f) == 0) {
 #if CONFIG_USE_INIT
-                        printk_debug("\r\n%02x:",i);
+                        printk_debug("\n%02x:",i);
 #else
-			print_debug("\r\n");
+			print_debug("\n");
 			print_debug_hex8(i);
 			print_debug_char(':');
 #endif
@@ -55,7 +55,7 @@
 		print_debug_hex8(val);
 #endif
 	}
-	print_debug("\r\n");
+	print_debug("\n");
 }
 
 static void dump_pci_devices(void)
@@ -95,7 +95,7 @@
 static void dump_spd_registers(const struct mem_controller *ctrl)
 {
 	int i;
-	print_debug("\r\n");
+	print_debug("\n");
 	for(i = 0; i < 4; i++) {
 		unsigned device;
 		device = ctrl->channel0[i];
@@ -114,9 +114,9 @@
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
 #if CONFIG_USE_INIT
-					printk_debug("\r\n%02x: ", j);
+					printk_debug("\n%02x: ", j);
 #else
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 #endif
@@ -133,7 +133,7 @@
 				print_debug_char(' ');
 #endif
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 		device = ctrl->channel1[i];
 		if (device) {
@@ -151,9 +151,9 @@
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
 #if CONFIG_USE_INIT
-                                        printk_debug("\r\n%02x: ", j);
+                                        printk_debug("\n%02x: ", j);
 #else
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 #endif
@@ -170,14 +170,14 @@
 				print_debug_char(' ');
 #endif
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
 static void dump_smbus_registers(void)
 {
 	unsigned device;
-        print_debug("\r\n");
+        print_debug("\n");
         for(device = 1; device < 0x80; device++) {
                 int j;
 		if( smbus_read_byte(device, 0) < 0 ) continue;
@@ -196,9 +196,9 @@
                         }
                         if ((j & 0xf) == 0) {
 #if CONFIG_USE_INIT
-				printk_debug("\r\n%02x: ",j);
+				printk_debug("\n%02x: ",j);
 #else
-                	        print_debug("\r\n");
+                	        print_debug("\n");
                                 print_debug_hex8(j);
                                 print_debug(": ");
 #endif
@@ -211,7 +211,7 @@
                         print_debug_char(' ');
 #endif
                 }
-                print_debug("\r\n");
+                print_debug("\n");
 	}	
 }
 
@@ -220,10 +220,10 @@
 
 	int i;
 #if CONFIG_USE_INIT
-	printk_debug("%04x:\r\n", port);
+	printk_debug("%04x:\n", port);
 #else
         print_debug_hex16(port);
-        print_debug(":\r\n");
+        print_debug(":\n");
 #endif
         for(i=0;i<256;i++) {
                 uint8_t val;
@@ -243,7 +243,7 @@
                 print_debug_hex8(val);
 #endif
                 if ((i & 0x0f) == 0x0f) {
-                        print_debug("\r\n");
+                        print_debug("\n");
                 }
 		port++;
         }
@@ -256,9 +256,9 @@
         for(i=start;i<end;i++) {
 		if((i & 0xf)==0) {
 #if CONFIG_USE_INIT
-			printk_debug("\r\n%08x:", i);
+			printk_debug("\n%08x:", i);
 #else	
-			print_debug("\r\n");
+			print_debug("\n");
 			print_debug_hex32(i);
 			print_debug(":");
 #endif
@@ -270,6 +270,6 @@
              	print_debug_hex8((unsigned char)*((unsigned char *)i));
 #endif
         }
-        print_debug("\r\n");
+        print_debug("\n");
  }
 #endif
Index: src/northbridge/intel/e7520/raminit_test.c
===================================================================
--- src/northbridge/intel/e7520/raminit_test.c	(revision 3942)
+++ src/northbridge/intel/e7520/raminit_test.c	(working copy)
@@ -394,7 +394,7 @@
 #if 0
 	print_debug("spd_count: ");
 	print_debug_hex32(spd_count);
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 	
 }
@@ -410,9 +410,9 @@
 	reset_tests();
 	spd_fail_count = i;
 
-	print_debug("\r\nSPD will fail after: ");
+	print_debug("\nSPD will fail after: ");
 	print_debug_hex32(spd_fail_count);
-	print_debug(" accesses.\r\n");
+	print_debug(" accesses.\n");
 	
 	memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
 	memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
Index: src/northbridge/intel/e7520/raminit.c
===================================================================
--- src/northbridge/intel/e7520/raminit.c	(revision 3942)
+++ src/northbridge/intel/e7520/raminit.c	(working copy)
@@ -75,7 +75,7 @@
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-	print_spew("done.\r\n");
+	print_spew("done.\n");
 }
 
 
@@ -156,7 +156,7 @@
 	goto out;
 
  val_err:
-	die("Bad SPD value\r\n");
+	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
 hw_err:
 	sz.side1 = 0;
@@ -284,7 +284,7 @@
 	goto out;
 
  val_err:
-	die("Bad SPD value\r\n");
+	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
 hw_err:
 	dra = 0;
@@ -539,7 +539,7 @@
 		
 	}
 	else {
-		die("Invalid SPD 9 bus speed.\r\n");
+		die("Invalid SPD 9 bus speed.\n");
 	}
 
 	/* 0x78 DRT */
@@ -577,7 +577,7 @@
 					ecc = 2;
 				}
 				else if (ecc == 1) {
-					die("ERROR - Mixed DDR & DDR2 RAM\r\n");
+					die("ERROR - Mixed DDR & DDR2 RAM\n");
 				}
 			} 
 			else if ( reg == 7 ) {
@@ -585,15 +585,15 @@
 					ecc = 1;
 				}
 				else if ( ecc > 1 ) {
-					die("ERROR - Mixed DDR & DDR2 RAM\r\n");
+					die("ERROR - Mixed DDR & DDR2 RAM\n");
 				}
 			}	
 			else {
-				die("ERROR - RAM not DDR\r\n");
+				die("ERROR - RAM not DDR\n");
 			}
 		}
 		else {
-			die("ERROR - Non ECC memory dimm\r\n");
+			die("ERROR - Non ECC memory dimm\n");
 		}
 
 		value = spd_read_byte(ctrl->channel0[cnt], 12);	/*refresh rate*/
@@ -622,10 +622,10 @@
 	ecc = 2;
 	if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
 		ecc = 0;  /* ECC off in CMOS so disable it */
-		print_debug("ECC off\r\n");
+		print_debug("ECC off\n");
 	}
 	else {
-		print_debug("ECC on\r\n");
+		print_debug("ECC on\n");
 	}
 	drc &= ~(3 << 20); /* clear the ecc bits */
 	drc |= (ecc << 20);  /* or in the calculated ecc bits */
@@ -655,7 +655,7 @@
 	goto out;
 
  val_err:
-	die("Bad SPD value\r\n");
+	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
 hw_err:
 	drc = 0;
@@ -670,7 +670,7 @@
 	/* Test if we can read the spd and if ram is ddr or ddr2 */
 	dimm_mask = spd_detect_dimms(ctrl);
 	if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
-		print_err("No memory for this cpu\r\n");
+		print_err("No memory for this cpu\n");
 		return;
 	}
 	return;
@@ -772,12 +772,12 @@
 		data32 = 0x777becdc; /* ESSD */
 		break;
 	    }
-	    die("Error - First dimm slot empty\r\n");
+	    die("Error - First dimm slot empty\n");
 	}
 
 	print_debug("ODT Value = ");
 	print_debug_hex32(data32);
-	print_debug("\r\n");
+	print_debug("\n");
 
   	pci_write_config32(ctrl->f0, 0xb0, data32);
 
@@ -1010,7 +1010,7 @@
 	print_debug_hex32(recena);
 	print_debug(",  Receive enable B = ");
 	print_debug_hex32(recenb);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	/* clear out the calibration area */
 	write32(BAR+DCALDATA+(16*4), 0x00000000);
@@ -1076,7 +1076,7 @@
 		0xffffffff, 0xffffffff, 0x000000ff};
 
 	mask = spd_detect_dimms(ctrl);
-	print_debug("Starting SDRAM Enable\r\n");
+	print_debug("Starting SDRAM Enable\n");
 
 	/* 0x80 */
 #ifdef DIMM_MAP_LOGICAL
@@ -1088,7 +1088,7 @@
 	/* set dram type and Front Side Bus freq. */
 	drc = spd_set_dram_controller_mode(ctrl, mask);
 	if( drc == 0) {
-		die("Error calculating DRC\r\n");
+		die("Error calculating DRC\n");
 	}
 	pll_setup(drc);
 	data32 = drc & ~(3 << 20);  /* clear ECC mode */
@@ -1125,7 +1125,7 @@
 	for(i=0;i<8;i++) { /* loop throught each dimm to test for row */
 		print_debug("DIMM ");
 		print_debug_hex8(i);
-		print_debug("\r\n");
+		print_debug("\n");
 		/* Apply NOP */
 		do_delay();
 		
@@ -1308,7 +1308,7 @@
 	write32(BAR+DCALCSR, 0x0008000f);
 
 	/* clear memory and init ECC */
-	print_debug("Clearing memory\r\n");
+	print_debug("Clearing memory\n");
 	for(i=0;i<64;i+=4) {
 		write32(BAR+DCALDATA+i, 0x00000000);
 	}
@@ -1325,13 +1325,13 @@
 	data32 |= (1 << 31);
 	pci_write_config32(ctrl->f0, 0x98, data32);
 	/* wait for completion */
-	print_debug("Waiting for mem complete\r\n");
+	print_debug("Waiting for mem complete\n");
 	while(1) {
 		data32 = pci_read_config32(ctrl->f0, 0x98);
 		if( (data32 & (1<<31)) == 0)
 			break;
 	}
-	print_debug("Done\r\n");
+	print_debug("Done\n");
 	
 	/* Set initialization complete */
 	/* 0x7c DRC */
Index: src/northbridge/intel/e7520/memory_initialized.c
===================================================================
--- src/northbridge/intel/e7520/memory_initialized.c	(revision 3942)
+++ src/northbridge/intel/e7520/memory_initialized.c	(working copy)
@@ -7,7 +7,7 @@
         drc = pci_read_config32(NB_DEV, DRC);
         //print_debug("memory_initialized: DRC: ");
         //print_debug_hex32(drc);
-        //print_debug("\r\n");
+        //print_debug("\n");
 
     	return (drc & (1<<29));
 }	
Index: src/northbridge/intel/i855gme/raminit.c
===================================================================
--- src/northbridge/intel/i855gme/raminit.c	(revision 3942)
+++ src/northbridge/intel/i855gme/raminit.c	(working copy)
@@ -31,7 +31,7 @@
 static void sdram_set_registers(const struct mem_controller *ctrl)
 {
 	/*
-	print_debug("Before configuration:\r\n");
+	print_debug("Before configuration:\n");
 	dump_pci_devices();
 	*/
 }
@@ -212,7 +212,7 @@
 	adjusted_mode = ((mode & 0x800) << (13 - 11)) | ((mode & 0x3ff) << (12 - 9));
 	print_debug("Setting mode: ");
 	print_debug_hex32(adjusted_mode + addr);
-	print_debug("\r\n");
+	print_debug("\n");
 	read32(adjusted_mode + addr);
 }
 
@@ -229,39 +229,39 @@
 {
 	int i;
 	uint32_t rank1 = (1 << 30) / 2;
-	print_debug("Ram enable 1\r\n");
+	print_debug("Ram enable 1\n");
 	delay();
 	delay();
 	
-	print_debug("Ram enable 2\r\n");
+	print_debug("Ram enable 2\n");
 	ram_command(ctrl, 1, 0);
 	ram_command(ctrl, 1, rank1);
 	delay();
 	delay();
 
-	print_debug("Ram enable 3\r\n");
+	print_debug("Ram enable 3\n");
 	ram_command(ctrl, 2, 0);
 	ram_command(ctrl, 2, rank1);
 	delay();
 	delay();
 
-	print_debug("Ram enable 4\r\n");
+	print_debug("Ram enable 4\n");
 	ram_command_mrs(ctrl, 4, SDRAM_EXTMODE_DLL_ENABLE, 0);
 	ram_command_mrs(ctrl, 4, SDRAM_EXTMODE_DLL_ENABLE, rank1);
 	delay();
 	delay();
 	
-	print_debug("Ram enable 5\r\n");
+	print_debug("Ram enable 5\n");
 	ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, 0);
 	ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_DLL_RESET, rank1);
 	
-	print_debug("Ram enable 6\r\n");
+	print_debug("Ram enable 6\n");
 	ram_command(ctrl, 2, 0);
 	ram_command(ctrl, 2, rank1);
 	delay();
 	delay();
 	
-	print_debug("Ram enable 7\r\n");
+	print_debug("Ram enable 7\n");
 	for(i = 0; i < 8; i++) {
 		ram_command(ctrl, 6, 0);
 		ram_command(ctrl, 6, rank1);
@@ -269,28 +269,28 @@
 		delay();
 	}
 
-	print_debug("Ram enable 8\r\n");
+	print_debug("Ram enable 8\n");
 	ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_NORMAL, 0);
 	ram_command_mrs(ctrl, 3, VG85X_MODE | SDRAM_MODE_NORMAL, rank1);
 
-	print_debug("Ram enable 9\r\n");
+	print_debug("Ram enable 9\n");
 	ram_command(ctrl, 7, 0);
 	ram_command(ctrl, 7, rank1);
 	delay();
 	delay();
 	
-	print_debug("Ram enable 9\r\n");
+	print_debug("Ram enable 9\n");
 	set_initialize_complete(ctrl);
 	
 	delay();
 	delay();
 	delay();
 	
-	print_debug("After configuration:\r\n");
+	print_debug("After configuration:\n");
 	/* dump_pci_devices(); */
 	
 	/*
-	print_debug("\n\n***** RAM TEST *****\r\n");	
+	print_debug("\n\n***** RAM TEST *****\n");	
 	ram_check(0, 0xa0000);
 	ram_check(0x100000, 0x40000000);
 	*/
Index: src/northbridge/intel/i855gme/debug.c
===================================================================
--- src/northbridge/intel/i855gme/debug.c	(revision 3942)
+++ src/northbridge/intel/i855gme/debug.c	(working copy)
@@ -60,7 +60,7 @@
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		print_debug("\r\n");
+		print_debug("\n");
 	}
 }
 
@@ -68,7 +68,7 @@
 {
 	int i;
 	print_debug_pci_dev(dev);
-	print_debug("\r\n");
+	print_debug("\n");
 	
 	for(i = 0; i <= 255; i++) {
 		unsigned char val;
@@ -80,7 +80,7 @@
 		print_debug_char(' ');
 		print_debug_hex8(val);
 		if ((i & 0x0f) == 0x0f) {
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -105,7 +105,7 @@
 static void dump_spd_registers(const struct mem_controller *ctrl)
 {
 	int i;
-	print_debug("\r\n");
+	print_debug("\n");
 	for(i = 0; i < 2; i++) {
 		unsigned device;
 		device = ctrl->channel0[i];
@@ -119,20 +119,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 #if 0
 		device = ctrl->channel1[i];
@@ -146,20 +146,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 #endif
 	}
@@ -167,7 +167,7 @@
 static void dump_smbus_registers(void)
 {
         int i;
-        print_debug("\r\n");
+        print_debug("\n");
         for(i = 1; i < 0x80; i++) {
                 unsigned device;
                 device = i;
@@ -178,20 +178,20 @@
                 	int status; 
                         unsigned char byte;
                         if ((j & 0xf) == 0) {
-                	        print_debug("\r\n");
+                	        print_debug("\n");
                                 print_debug_hex8(j);
                                 print_debug(": ");
                         }
                         status = smbus_read_byte(device, j);
                         if (status < 0) {
-                                print_debug("bad device\r\n");
+                                print_debug("bad device\n");
                                 break;
                         }
                         byte = status & 0xff;
                         print_debug_hex8(byte);
                         print_debug_char(' ');
                 }
-                print_debug("\r\n");
+                print_debug("\n");
 	}	
 }
 #endif
Index: src/northbridge/intel/e7525/raminit_test.c
===================================================================
--- src/northbridge/intel/e7525/raminit_test.c	(revision 3942)
+++ src/northbridge/intel/e7525/raminit_test.c	(working copy)
@@ -361,9 +361,9 @@
 	reset_tests();
 	spd_fail_count = i;
 
-	print_debug("\r\nSPD will fail after: ");
+	print_debug("\nSPD will fail after: ");
 	print_debug_hex32(spd_fail_count);
-	print_debug(" accesses.\r\n");
+	print_debug(" accesses.\n");
 	
 	memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
 	memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
Index: src/northbridge/intel/e7525/raminit.c
===================================================================
--- src/northbridge/intel/e7525/raminit.c	(revision 3942)
+++ src/northbridge/intel/e7525/raminit.c	(working copy)
@@ -75,7 +75,7 @@
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-	print_spew("done.\r\n");
+	print_spew("done.\n");
 }
 
 
@@ -156,7 +156,7 @@
 	goto out;
 
  val_err:
-	die("Bad SPD value\r\n");
+	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
 hw_err:
 	sz.side1 = 0;
@@ -284,7 +284,7 @@
 	goto out;
 
  val_err:
-	die("Bad SPD value\r\n");
+	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
 hw_err:
 	dra = 0;
@@ -539,7 +539,7 @@
 		
 	}
 	else {
-		die("Invalid SPD 9 bus speed.\r\n");
+		die("Invalid SPD 9 bus speed.\n");
 	}
 
 	/* 0x78 DRT */
@@ -577,7 +577,7 @@
 					ecc = 2;
 				}
 				else if (ecc == 1) {
-					die("ERROR - Mixed DDR & DDR2 RAM\r\n");
+					die("ERROR - Mixed DDR & DDR2 RAM\n");
 				}
 			} 
 			else if ( reg == 7 ) {
@@ -585,15 +585,15 @@
 					ecc = 1;
 				}
 				else if ( ecc > 1 ) {
-					die("ERROR - Mixed DDR & DDR2 RAM\r\n");
+					die("ERROR - Mixed DDR & DDR2 RAM\n");
 				}
 			}	
 			else {
-				die("ERROR - RAM not DDR\r\n");
+				die("ERROR - RAM not DDR\n");
 			}
 		}
 		else {
-			die("ERROR - Non ECC memory dimm\r\n");
+			die("ERROR - Non ECC memory dimm\n");
 		}
 
 		value = spd_read_byte(ctrl->channel0[cnt], 12);	/*refresh rate*/
@@ -622,10 +622,10 @@
 	ecc = 2;
 	if (read_option(CMOS_VSTART_ECC_memory,CMOS_VLEN_ECC_memory,1) == 0) {
 		ecc = 0;  /* ECC off in CMOS so disable it */
-		print_debug("ECC off\r\n");
+		print_debug("ECC off\n");
 	}
 	else {
-		print_debug("ECC on\r\n");
+		print_debug("ECC on\n");
 	}
 	drc &= ~(3 << 20); /* clear the ecc bits */
 	drc |= (ecc << 20);  /* or in the calculated ecc bits */
@@ -655,7 +655,7 @@
 	goto out;
 
  val_err:
-	die("Bad SPD value\r\n");
+	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
 hw_err:
 	drc = 0;
@@ -670,7 +670,7 @@
 	/* Test if we can read the spd and if ram is ddr or ddr2 */
 	dimm_mask = spd_detect_dimms(ctrl);
 	if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
-		print_err("No memory for this cpu\r\n");
+		print_err("No memory for this cpu\n");
 		return;
 	}
 	return;
@@ -743,12 +743,12 @@
 		data32 = 0x777becdc; /* ESSD */
 		break;
 	    }
-	    die("Error - First dimm slot empty\r\n");
+	    die("Error - First dimm slot empty\n");
 	}
 
 	print_debug("ODT Value = ");
 	print_debug_hex32(data32);
-	print_debug("\r\n");
+	print_debug("\n");
 
   	pci_write_config32(ctrl->f0, 0xb0, data32);
 
@@ -981,7 +981,7 @@
 	print_debug_hex32(recena);
 	print_debug(",  Receive enable B = ");
 	print_debug_hex32(recenb);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	/* clear out the calibration area */
 	write32(BAR+DCALDATA+(16*4), 0x00000000);
@@ -1047,7 +1047,7 @@
 		0xffffffff, 0xffffffff, 0x000000ff};
 
 	mask = spd_detect_dimms(ctrl);
-	print_debug("Starting SDRAM Enable\r\n");
+	print_debug("Starting SDRAM Enable\n");
 
 	/* 0x80 */
 #ifdef DIMM_MAP_LOGICAL
@@ -1059,7 +1059,7 @@
 	/* set dram type and Front Side Bus freq. */
 	drc = spd_set_dram_controller_mode(ctrl, mask);
 	if( drc == 0) {
-		die("Error calculating DRC\r\n");
+		die("Error calculating DRC\n");
 	}
 	data32 = drc & ~(3 << 20);  /* clear ECC mode */
 	data32 = data32 & ~(7 << 8);  /* clear refresh rates */
@@ -1095,7 +1095,7 @@
 	for(i=0;i<8;i++) { /* loop throught each dimm to test for row */
 		print_debug("DIMM ");
 		print_debug_hex8(i);
-		print_debug("\r\n");
+		print_debug("\n");
 		/* Apply NOP */
 		do_delay();
 		
@@ -1275,7 +1275,7 @@
 	write32(BAR+DCALCSR, 0x0008000f);
 
 	/* clear memory and init ECC */
-	print_debug("Clearing memory\r\n");
+	print_debug("Clearing memory\n");
 	for(i=0;i<64;i+=4) {
 		write32(BAR+DCALDATA+i, 0x00000000);
 	}
@@ -1292,13 +1292,13 @@
 	data32 |= (1 << 31);
 	pci_write_config32(ctrl->f0, 0x98, data32);
 	/* wait for completion */
-	print_debug("Waiting for mem complete\r\n");
+	print_debug("Waiting for mem complete\n");
 	while(1) {
 		data32 = pci_read_config32(ctrl->f0, 0x98);
 		if( (data32 & (1<<31)) == 0)
 			break;
 	}
-	print_debug("Done\r\n");
+	print_debug("Done\n");
 	
 	/* Set initialization complete */
 	/* 0x7c DRC */
Index: src/northbridge/intel/i855pm/raminit.c
===================================================================
--- src/northbridge/intel/i855pm/raminit.c	(revision 3942)
+++ src/northbridge/intel/i855pm/raminit.c	(working copy)
@@ -69,7 +69,7 @@
 #if DEBUG_RAM_CONFIG >=2
         print_debug("P:");
         print_debug_hex8(value);
-        print_debug("\r\n");
+        print_debug("\n");
 #endif
         /* %ecx - initial address to read from */
         /* Compute the offset */
@@ -83,7 +83,7 @@
 #if DEBUG_RAM_CONFIG  
                 print_debug("R:");
                 print_debug_hex8(byte);
-                print_debug("\r\n");
+                print_debug("\n");
 #endif
 
                 pci_write_config8(ctrl->d0, 0x70, byte);
@@ -92,13 +92,13 @@
 #if DEBUG_RAM_CONFIG  >= 2
                 print_debug("R:");
                 print_debug_hex32(dword);
-                print_debug("\r\n");
+                print_debug("\n");
 #endif
 
 		result = read32(dword);
 		
 #if DEBUG_RAM_CONFIG
-		print_debug("Done\r\n");
+		print_debug("Done\n");
 #endif
                 /* Go to the next base address */
                 dword += 0x0200000;
@@ -391,7 +391,7 @@
                 print_debug_hex32(register_values[i]);
                 print_debug(" <-");
                 print_debug_hex32(register_values[i+2]);
-                print_debug("\r\n");
+                print_debug("\n");
 #endif
                 reg = pci_read_config32(ctrl->d0,register_values[i]);
                 reg &= register_values[i+1];
@@ -477,7 +477,7 @@
         goto out;
 
  val_err:
-        die("Bad SPD value\r\n");
+        die("Bad SPD value\n");
         /* If an hw_error occurs report that I have no memory */
 hw_err:
 	pgsz.side1 = 0;
@@ -600,11 +600,11 @@
 #if DEBUG_RAM_CONFIG
 	print_debug("returned size log 2 in bits is :");
 	print_debug_hex32(value);
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 	goto out;
  val_err:
-        die("Bad SPD value\r\n");
+        die("Bad SPD value\n");
         /* If an hw_error occurs report that I have no memory */
 hw_err:
         sz.side1 = 0;
@@ -661,7 +661,7 @@
 		print_debug_hex32(sz.side1);
 		print_debug(" ");
 		print_debug_hex32(sz.side2);
-		print_debug("\r\n");
+		print_debug("\n");
 #endif
 	
 		/* Test to see if the dimm is present */
@@ -669,7 +669,7 @@
 
 			/* Test for a valid dimm width */
 			if((sz.side1 <15) || (sz.side1>18) ) {
-				print_err("unsupported page size\r\n");
+				print_err("unsupported page size\n");
 			}
 
 			/* Convert to the format needed for the DRA register */
@@ -690,7 +690,7 @@
         
 	                        /* Test for a valid dimm width */
         	                if((sz.side2 <15) || (sz.side2>18) ) {
-                	                print_err("unsupported page size\r\n");
+                	                print_err("unsupported page size\n");
                         	}
 
                         	/* Convert to the format needed for the DRA register */
@@ -711,9 +711,9 @@
 	return dimm_mask;
 
 }
-#define spd_pre_init  "Reading SPD data...\r\n"
-#define spd_pre_set "setting based on SPD data...\r\n"
-#define spd_post_init "done\r\n"
+#define spd_pre_init  "Reading SPD data...\n"
+#define spd_pre_set "setting based on SPD data...\n"
+#define spd_post_init "done\n"
 
 
 static const uint32_t refresh_rate_rank[]= {
@@ -756,7 +756,7 @@
 #if 0 /* DEBUG_RAM_CONFIG*/
 	print_debug("spd_detect_dimms: 0x70.l is:");
 	print_debug_hex32(dword);
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 
 #if 0
@@ -780,34 +780,34 @@
                 if(value < 0) continue;
 		if(value !=2 ) {
 #if DEBUG_RAM_CONFIG
-	print_debug("spd_detect_dimms:\r\n");
+	print_debug("spd_detect_dimms:\n");
 #endif
 			/* Clear the ecc enable */
 			dword &= ~(3 << 20);
 #if 0 &&DEBUG_RAM_CONFIG
 	print_debug("spd_detect_dimms: no ecc so set:");
 	print_debug_hex32(dword);
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 
 		}
 		value = spd_read_byte(ctrl->channel0[i], 12);  /* SDRAM refresh rate */
 		if(value < 0 ) continue;
 		value &= 0x7f;
-		if(value > MAX_SPD_REFRESH_RATE) { print_err("unsupported refresh rate\r\n");}
-/*		if(value == 0xff) { print_err("unsupported refresh rate\r\n");}*/
+		if(value > MAX_SPD_REFRESH_RATE) { print_err("unsupported refresh rate\n");}
+/*		if(value == 0xff) { print_err("unsupported refresh rate\n");}*/
 		
 #if DEBUG_RAM_CONFIG
 	print_debug("spd_detect_dimms: ref rate index:");
 	print_debug_hex8(value);
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 	if (value == 2) /* have to go faster */
 	  refrate = 2;
 #if 0 &&DEBUG_RAM_CONFIG
 	print_debug("spd_detect_dimms: dword is now w/refresh:");
 	print_debug_hex32(dword);
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 		/* no applicability here but there are similar things
 		 * we'll try later. 
@@ -1062,7 +1062,7 @@
 	print_debug_hex32(ramindex);
 	print_debug(" and speed ");
 	print_debug_hex32(rambusfrequency);
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 
 	/* for now, since we are on deadline, set to "known good" and 
@@ -1116,7 +1116,7 @@
 			uint32_t tmp;
 			/* Die if the value is to large */
 			if(value>7) {
-				die ("unsupported_rcd\r\n");
+				die ("unsupported_rcd\n");
 			}
 			/* Convert to clocks - 5 */
 			value -=5;
@@ -1171,14 +1171,14 @@
         int i;  
         dimm_mask = 0;  
 #if DEBUG_RAM_CONFIG
-	print_debug("spd_detect_dimms:\r\n");
+	print_debug("spd_detect_dimms:\n");
 #endif
         for(i = 0; i < DIMM_SOCKETS; i++) {
                 int byte;
                 unsigned device;
 #if DEBUG_RAM_CONFIG
 		print_debug_hex32(i);
-		print_debug("\r\n");
+		print_debug("\n");
 #endif
                 device = ctrl->channel0[i];
                 if (device) {
@@ -1226,7 +1226,7 @@
 	print_debug_hex8(memsz);
 	print_debug(" to ");
 	print_debug_hex8(0x40 + index);
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 	byte = memsz;
         pci_write_config8(ctrl->d0, 0x40+index, byte);
@@ -1260,7 +1260,7 @@
                 print_debug_hex32(sz.side1);
                 print_debug(" ");
                 print_debug_hex32(sz.side2);
-                print_debug("\r\n");
+                print_debug("\n");
 #endif
 
                 if (sz.side1 == 0) {
@@ -1352,7 +1352,7 @@
 
  hw_spd_err:
         /* Unrecoverable error reading SPD data */
-        print_err("SPD error - reset\r\n");
+        print_err("SPD error - reset\n");
         hard_reset();
         return;
 }
@@ -1382,8 +1382,8 @@
 #define SPECIAL_FINISHUP()   CALL_LABEL(dram_finish)
 
 
-#define ecc_pre_init	"Initializing ECC state...\r\n"
-#define ecc_post_init	"ECC state initialized.\r\n"
+#define ecc_pre_init	"Initializing ECC state...\n"
+#define ecc_post_init	"ECC state initialized.\n"
 static void dram_finish(const struct mem_controller *ctrl)
 {
 	uint32_t dword;
@@ -1416,17 +1416,17 @@
 }
 
 #if ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG
-#define ram_enable_1    "Ram Enable 1\r\n"
-#define ram_enable_2	"Ram Enable 2\r\n"
-#define ram_enable_3 	"Ram Enable 3\r\n"
-#define ram_enable_4 	"Ram Enable 4\r\n"
-#define ram_enable_5 	"Ram Enable 5\r\n"
-#define ram_enable_6 	"Ram Enable 6\r\n"
-#define ram_enable_7 	"Ram Enable 7\r\n"
-#define ram_enable_8 	"Ram Enable 8\r\n"
-#define ram_enable_9 	"Ram Enable 9\r\n"
-#define ram_enable_10 	"Ram Enable 10\r\n"
-#define ram_enable_11 	"Ram Enable 11\r\n"
+#define ram_enable_1    "Ram Enable 1\n"
+#define ram_enable_2	"Ram Enable 2\n"
+#define ram_enable_3 	"Ram Enable 3\n"
+#define ram_enable_4 	"Ram Enable 4\n"
+#define ram_enable_5 	"Ram Enable 5\n"
+#define ram_enable_6 	"Ram Enable 6\n"
+#define ram_enable_7 	"Ram Enable 7\n"
+#define ram_enable_8 	"Ram Enable 8\n"
+#define ram_enable_9 	"Ram Enable 9\n"
+#define ram_enable_10 	"Ram Enable 10\n"
+#define ram_enable_11 	"Ram Enable 11\n"
 #endif
 
 	/* Estimate that SLOW_DOWN_IO takes about 50&76us*/
@@ -1586,7 +1586,7 @@
 	*c = 'a';
 	print_debug("Test: ");
 	print_debug_hex8(*c);
-	print_debug("\r\n");
+	print_debug("\n");
 	}
 	
 
Index: src/northbridge/intel/i855pm/debug.c
===================================================================
--- src/northbridge/intel/i855pm/debug.c	(revision 3942)
+++ src/northbridge/intel/i855pm/debug.c	(working copy)
@@ -27,7 +27,7 @@
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		print_debug("\r\n");
+		print_debug("\n");
 	}
 }
 
@@ -35,7 +35,7 @@
 {
 	int i;
 	print_debug_pci_dev(dev);
-	print_debug("\r\n");
+	print_debug("\n");
 	
 	for(i = 0; i <= 255; i++) {
 		unsigned char val;
@@ -47,7 +47,7 @@
 		print_debug_char(' ');
 		print_debug_hex8(val);
 		if ((i & 0x0f) == 0x0f) {
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -72,7 +72,7 @@
 static void dump_spd_registers(const struct mem_controller *ctrl)
 {
 	int i;
-	print_debug("\r\n");
+	print_debug("\n");
 	for(i = 0; i < 4; i++) {
 		unsigned device;
 		device = ctrl->channel0[i];
@@ -86,20 +86,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 #if 0
 		device = ctrl->channel1[i];
@@ -113,20 +113,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 #endif
 	}
@@ -134,7 +134,7 @@
 static void dump_smbus_registers(void)
 {
         int i;
-        print_debug("\r\n");
+        print_debug("\n");
         for(i = 1; i < 0x80; i++) {
                 unsigned device;
                 device = i;
@@ -145,20 +145,20 @@
                 	int status; 
                         unsigned char byte;
                         if ((j & 0xf) == 0) {
-                	        print_debug("\r\n");
+                	        print_debug("\n");
                                 print_debug_hex8(j);
                                 print_debug(": ");
                         }
                         status = smbus_read_byte(device, j);
                         if (status < 0) {
-                                print_debug("bad device\r\n");
+                                print_debug("bad device\n");
                                 break;
                         }
                         byte = status & 0xff;
                         print_debug_hex8(byte);
                         print_debug_char(' ');
                 }
-                print_debug("\r\n");
+                print_debug("\n");
 	}	
 }
 #endif
Index: src/northbridge/intel/i440bx/raminit.c
===================================================================
--- src/northbridge/intel/i440bx/raminit.c	(revision 3942)
+++ src/northbridge/intel/i440bx/raminit.c	(working copy)
@@ -403,7 +403,7 @@
 			PRINT_DEBUG_HEX16(reg16);
 			PRINT_DEBUG(" to 0x");
 			PRINT_DEBUG_HEX32(addr);
-			PRINT_DEBUG("\r\n");
+			PRINT_DEBUG("\n");
 #endif
 
 			read32(addr);
@@ -435,7 +435,7 @@
 		PRINT_DEBUG_HEX8(reg);
 		PRINT_DEBUG(") for DIMM ");
 		PRINT_DEBUG_HEX8(i);
-		PRINT_DEBUG("\r\n");
+		PRINT_DEBUG("\n");
 	}
 
 	pci_write_config8(NB, DRAMC, reg);
@@ -450,7 +450,7 @@
 	int i, max;
 	uint8_t reg;
 
-	PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n");
+	PRINT_DEBUG("Northbridge prior to SDRAM init:\n");
 	DUMPNORTH();
 
 	max = ARRAY_SIZE(register_values);
@@ -466,7 +466,7 @@
 		PRINT_DEBUG_HEX8(register_values[i]);
 		PRINT_DEBUG(" to 0x");
 		PRINT_DEBUG_HEX8(reg);
-		PRINT_DEBUG("\r\n");
+		PRINT_DEBUG("\n");
 	}
 }
 
@@ -534,38 +534,38 @@
 	udelay(200);
 
 	/* 1. Apply NOP. Wait 200 clock cycles (200us should do). */
-	PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
+	PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
 	do_ram_command(RAM_COMMAND_NOP);
 	udelay(200);
 
 	/* 2. Precharge all. Wait tRP. */
-	PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
+	PRINT_DEBUG("RAM Enable 2: Precharge all\n");
 	do_ram_command(RAM_COMMAND_PRECHARGE);
 	udelay(1);
 
 	/* 3. Perform 8 refresh cycles. Wait tRC each time. */
-	PRINT_DEBUG("RAM Enable 3: CBR\r\n");
+	PRINT_DEBUG("RAM Enable 3: CBR\n");
 	for (i = 0; i < 8; i++) {
 		do_ram_command(RAM_COMMAND_CBR);
 		udelay(1);
 	}
 
 	/* 4. Mode register set. Wait two memory cycles. */
-	PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
+	PRINT_DEBUG("RAM Enable 4: Mode register set\n");
 	do_ram_command(RAM_COMMAND_MRS);
 	udelay(2);
 
 	/* 5. Normal operation. */
-	PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
+	PRINT_DEBUG("RAM Enable 5: Normal operation\n");
 	do_ram_command(RAM_COMMAND_NORMAL);
 	udelay(1);
 
 	/* 6. Finally enable refresh. */
-	PRINT_DEBUG("RAM Enable 6: Enable refresh\r\n");
+	PRINT_DEBUG("RAM Enable 6: Enable refresh\n");
 	// pci_write_config8(NB, PMCR, 0x10);
 	spd_enable_refresh();
 	udelay(1);
 
-	PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
+	PRINT_DEBUG("Northbridge following SDRAM init:\n");
 	DUMPNORTH();
 }
Index: src/northbridge/intel/i440bx/debug.c
===================================================================
--- src/northbridge/intel/i440bx/debug.c	(revision 3942)
+++ src/northbridge/intel/i440bx/debug.c	(working copy)
@@ -2,7 +2,7 @@
 static void dump_spd_registers(void)
 {
 	int i;
-	print_debug("\r\n");
+	print_debug("\n");
 	for(i = 0; i < DIMM_SOCKETS; i++) {
 		unsigned device;
 		device = DIMM_SPD_BASE + i;
@@ -16,20 +16,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = spd_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
Index: src/northbridge/intel/i82810/raminit.c
===================================================================
--- src/northbridge/intel/i82810/raminit.c	(revision 3942)
+++ src/northbridge/intel/i82810/raminit.c	(working copy)
@@ -141,7 +141,7 @@
 			PRINT_DEBUG_HEX8(reg8);
 			PRINT_DEBUG(" to 0x");
 			PRINT_DEBUG_HEX32(addr);
-			PRINT_DEBUG("\r\n");
+			PRINT_DEBUG("\n");
 
 			read32(addr);
 		}
@@ -153,7 +153,7 @@
 			PRINT_DEBUG_HEX8(reg8);
 			PRINT_DEBUG(" to 0x");
 			PRINT_DEBUG_HEX32(addr);
-			PRINT_DEBUG("\r\n");
+			PRINT_DEBUG("\n");
 
 			read32(addr);
 		}
@@ -183,14 +183,14 @@
 		if (smbus_read_byte(DIMM_SPD_BASE + i, 2) == 4) {
 			print_debug("Found DIMM in slot ");
 			print_debug_hex8(i);
-			print_debug("\r\n");
+			print_debug("\n");
 
 			dimm_size = smbus_read_byte(DIMM_SPD_BASE + i, 31);
 
 			/* WISHLIST: would be nice to display it as decimal? */
 			print_debug("DIMM is 0x");
 			print_debug_hex8(dimm_size * 4);
-			print_debug("MB\r\n");
+			print_debug("MB\n");
 
 			/* The i810 can't handle DIMMs larger than 128MB per
 			 * side. This will fail if the DIMM uses a
@@ -200,9 +200,9 @@
 			 */
 			if (dimm_size > 32) {
 				print_err("DIMM row sizes larger than 128MB not"
-					  "supported on i810\r\n");
+					  "supported on i810\n");
 				print_err
-				    ("Attempting to treat as 128MB DIMM\r\n");
+				    ("Attempting to treat as 128MB DIMM\n");
 				dimm_size = 32;
 			}
 
@@ -214,19 +214,19 @@
 
 			print_debug("After translation, dimm_size is 0x");
 			print_debug_hex8(dimm_size);
-			print_debug("\r\n");
+			print_debug("\n");
 
 			/* If the DIMM is dual-sided, the DRP value is +2 */
 			/* TODO: Figure out asymetrical configurations. */
 			if ((smbus_read_byte(DIMM_SPD_BASE + i, 127) | 0xf) ==
 			    0xff) {
-				print_debug("DIMM is dual-sided\r\n");
+				print_debug("DIMM is dual-sided\n");
 				dimm_size += 2;
 			}
 		} else {
 			print_debug("No DIMM found in slot ");
 			print_debug_hex8(i);
-			print_debug("\r\n");
+			print_debug("\n");
 
 			/* If there's no DIMM in the slot, set value to 0. */
 			dimm_size = 0x00;
@@ -238,7 +238,7 @@
 
 	print_debug("DRP calculated to 0x");
 	print_debug_hex8(drp);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	pci_write_config8(PCI_DEV(0, 0, 0), DRP, drp);
 }
@@ -343,32 +343,32 @@
 	int i;
 
 	/* 1. Apply NOP. */
-	PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
+	PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
 	do_ram_command(RAM_COMMAND_NOP);
 	udelay(200);
 
 	/* 2. Precharge all. Wait tRP. */
-	PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
+	PRINT_DEBUG("RAM Enable 2: Precharge all\n");
 	do_ram_command(RAM_COMMAND_PRECHARGE);
 	udelay(1);
 
 	/* 3. Perform 8 refresh cycles. Wait tRC each time. */
-	PRINT_DEBUG("RAM Enable 3: CBR\r\n");
+	PRINT_DEBUG("RAM Enable 3: CBR\n");
 	for (i = 0; i < 8; i++) {
 		do_ram_command(RAM_COMMAND_CBR);
 		udelay(1);
 	}
 
 	/* 4. Mode register set. Wait two memory cycles. */
-	PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
+	PRINT_DEBUG("RAM Enable 4: Mode register set\n");
 	do_ram_command(RAM_COMMAND_MRS);
 	udelay(2);
 
 	/* 5. Normal operation (enables refresh) */
-	PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
+	PRINT_DEBUG("RAM Enable 5: Normal operation\n");
 	do_ram_command(RAM_COMMAND_NORMAL);
 	udelay(1);
 
-	PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
+	PRINT_DEBUG("Northbridge following SDRAM init:\n");
 	DUMPNORTH();
 }
Index: src/northbridge/intel/i82810/debug.c
===================================================================
--- src/northbridge/intel/i82810/debug.c	(revision 3942)
+++ src/northbridge/intel/i82810/debug.c	(working copy)
@@ -2,7 +2,7 @@
 static void dump_spd_registers(void)
 {
 	int i;
-	print_debug("\r\n");
+	print_debug("\n");
 	for(i = 0; i < DIMM_SOCKETS; i++) {
 		unsigned device;
 		device = DIMM_SPD_BASE + i;
@@ -16,20 +16,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
Index: src/northbridge/intel/i3100/raminit.c
===================================================================
--- src/northbridge/intel/i3100/raminit.c	(revision 3942)
+++ src/northbridge/intel/i3100/raminit.c	(working copy)
@@ -77,7 +77,7 @@
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-	print_spew("done.\r\n");
+	print_spew("done.\n");
 }
 
 struct dimm_size {
@@ -150,7 +150,7 @@
 	goto out;
 
  val_err:
-	die("Bad SPD value\r\n");
+	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
  hw_err:
 	sz.side1 = 0;
@@ -278,7 +278,7 @@
 	goto out;
 
  val_err:
-	die("Bad SPD value\r\n");
+	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
  hw_err:
 	dra = 0;
@@ -529,7 +529,7 @@
 
 	}
 	else {
-		die("Invalid SPD 9 bus speed.\r\n");
+		die("Invalid SPD 9 bus speed.\n");
 	}
 
 	/* 0x78 DRT */
@@ -557,7 +557,7 @@
 			continue;
 		}
 		value = spd_read_byte(ctrl->channel0[cnt], 11);	/* ECC */
-		if (value != 2) die("ERROR - Non ECC memory dimm\r\n");
+		if (value != 2) die("ERROR - Non ECC memory dimm\n");
 
 		value = spd_read_byte(ctrl->channel0[cnt], 12);	/*refresh rate*/
 		value &= 0x0f;    /* clip self refresh bit */
@@ -596,7 +596,7 @@
 	goto out;
 
  val_err:
-	die("Bad SPD value\r\n");
+	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
  hw_err:
 	drc = 0;
@@ -611,7 +611,7 @@
 	/* Test if we can read the spd and if ram is ddr or ddr2 */
 	dimm_mask = spd_detect_dimms(ctrl);
 	if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
-		print_err("No memory for this cpu\r\n");
+		print_err("No memory for this cpu\n");
 		return;
 	}
 	return;
@@ -684,12 +684,12 @@
 		data32 = 0x777becdc; /* ESSD */
 		break;
 	    }
-	    die("Error - First dimm slot empty\r\n");
+	    die("Error - First dimm slot empty\n");
 	}
 
 	print_debug("ODT Value = ");
 	print_debug_hex32(data32);
-	print_debug("\r\n");
+	print_debug("\n");
 
   	pci_write_config32(ctrl->f0, DDR2ODTC, data32);
 
@@ -922,7 +922,7 @@
 	print_debug_hex32(recena);
 	print_debug(",  Receive enable B = ");
 	print_debug_hex32(recenb);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	/* clear out the calibration area */
 	write32(MCBAR+DCALDATA+(16*4), 0x00000000);
@@ -978,7 +978,7 @@
 		0xffffffff, 0xffffffff, 0x000000ff};
 
 	mask = spd_detect_dimms(ctrl);
-	print_debug("Starting SDRAM Enable\r\n");
+	print_debug("Starting SDRAM Enable\n");
 
 	/* 0x80 */
 #ifdef DIMM_MAP_LOGICAL
@@ -990,7 +990,7 @@
 	/* set dram type and Front Side Bus freq. */
 	drc = spd_set_dram_controller_mode(ctrl, mask);
 	if( drc == 0) {
-		die("Error calculating DRC\r\n");
+		die("Error calculating DRC\n");
 	}
 	data32 = drc & ~(3 << 20);  /* clear ECC mode */
 	data32 = data32 & ~(7 << 8);  /* clear refresh rates */
@@ -1025,7 +1025,7 @@
 	for(i=0;i<8;i+=2) { /* loop through each dimm to test */
 		print_debug("DIMM ");
 		print_debug_hex8(i);
-		print_debug("\r\n");
+		print_debug("\n");
 		/* Apply NOP */
 		do_delay();
 
@@ -1178,7 +1178,7 @@
 	write32(MCBAR+DCALCSR, 0x0008000f);
 
 	/* clear memory and init ECC */
-	print_debug("Clearing memory\r\n");
+	print_debug("Clearing memory\n");
 	for(i=0;i<64;i+=4) {
 		write32(MCBAR+DCALDATA+i, 0x00000000);
 	}
@@ -1195,13 +1195,13 @@
 	data32 |= (1 << 31);
 	pci_write_config32(ctrl->f0, 0x98, data32);
 	/* wait for completion */
-	print_debug("Waiting for mem complete\r\n");
+	print_debug("Waiting for mem complete\n");
 	while(1) {
 		data32 = pci_read_config32(ctrl->f0, 0x98);
 		if( (data32 & (1<<31)) == 0)
 			break;
 	}
-	print_debug("Done\r\n");
+	print_debug("Done\n");
 
 	/* Set initialization complete */
 	/* 0x7c DRC */
Index: src/northbridge/intel/i3100/raminit_ep80579.c
===================================================================
--- src/northbridge/intel/i3100/raminit_ep80579.c	(revision 3942)
+++ src/northbridge/intel/i3100/raminit_ep80579.c	(working copy)
@@ -123,7 +123,7 @@
 	goto out;
 
  val_err:
-	die("Bad SPD value\r\n");
+	die("Bad SPD value\n");
 	/* If an hw_error occurs report that I have no memory */
  hw_err:
 	sz.side1 = 0;
@@ -135,7 +135,7 @@
 	print_debug_hex8(sz.side1);
 	print_debug(".");
 	print_debug_hex8(sz.side2);
-	print_debug("\r\n");
+	print_debug("\n");
 	return sz;
 
 }
@@ -168,14 +168,14 @@
 	}
 	print_debug("DRB = ");
 	print_debug_hex32(pci_read_config32(ctrl->f0, DRB));
-	print_debug("\r\n");
+	print_debug("\n");
 
 	cum >>= 1;
 	/* set TOM top of memory */
 	pci_write_config16(ctrl->f0, TOM, cum);
 	print_debug("TOM = ");
 	print_debug_hex16(cum);
-	print_debug("\r\n");
+	print_debug("\n");
 	/* set TOLM top of low memory */
 	if (cum > 0x18) {
 		cum = 0x18;
@@ -184,7 +184,7 @@
 	pci_write_config16(ctrl->f0, TOLM, cum);
 	print_debug("TOLM = ");
 	print_debug_hex16(cum);
-	print_debug("\r\n");
+	print_debug("\n");
 	return 0;
 }
 
@@ -203,7 +203,7 @@
 			print_debug_hex8(device);
 			print_debug(" = ");
 			print_debug_hex8(byte);
-			print_debug("\r\n");
+			print_debug("\n");
 			if (byte == 8) {
 				dimm_mask |= (1 << i);
 			}
@@ -228,29 +228,29 @@
 		}
 
 		value = spd_read_byte(ctrl->channel0[i], SPD_NUM_ROWS);
-		if (value < 0) die("Bad SPD data\r\n");
-		if ((value & 0xf) == 0) die("Invalid # of rows\r\n");
+		if (value < 0) die("Bad SPD data\n");
+		if ((value & 0xf) == 0) die("Invalid # of rows\n");
 		dra |= (((value-13) & 0x7) << 23);
 		dra |= (((value-13) & 0x7) << 29);
 		reg += value & 0xf;
 
 		value = spd_read_byte(ctrl->channel0[i], SPD_NUM_COLUMNS);
-		if (value < 0) die("Bad SPD data\r\n");
-		if ((value & 0xf) == 0) die("Invalid # of columns\r\n");
+		if (value < 0) die("Bad SPD data\n");
+		if ((value & 0xf) == 0) die("Invalid # of columns\n");
 		dra |= (((value-10) & 0x7) << 20);
 		dra |= (((value-10) & 0x7) << 26);
 		reg += value & 0xf;
 
 		value = spd_read_byte(ctrl->channel0[i], SPD_NUM_BANKS_PER_SDRAM);
-		if (value < 0) die("Bad SPD data\r\n");
-		if ((value & 0xff) == 0) die("Invalid # of banks\r\n");
+		if (value < 0) die("Bad SPD data\n");
+		if ((value & 0xff) == 0) die("Invalid # of banks\n");
 		reg += log2(value & 0xff);
 
 		print_debug("dimm ");
 		print_debug_hex8(i);
 		print_debug(" reg = ");
 		print_debug_hex8(reg);
-		print_debug("\r\n");
+		print_debug("\n");
 
 		/* set device density */
 		dra |= ((31-reg));
@@ -271,7 +271,7 @@
 		print_debug_hex8(i);
 		print_debug(" = ");
 		print_debug_hex32(dra);
-		print_debug("\r\n");
+		print_debug("\n");
 
 		pci_write_config32(ctrl->f0, DRA + (i*4), dra);
 	}
@@ -321,10 +321,10 @@
 	else if (val & 0x40)
 		cl = 6;
 	else
-		die("CAS latency mismatch\r\n");
+		die("CAS latency mismatch\n");
 	print_debug("cl = ");
 	print_debug_hex8(cl);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	ci = cycle[index];
 
@@ -350,10 +350,10 @@
 	}
 	print_debug("trc = ");
 	print_debug_hex8(trc);
-	print_debug("\r\n");
+	print_debug("\n");
 	print_debug("trfc = ");
 	print_debug_hex8(trfc);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	/* Tras, Trtp, Twtr in cycles */
 	for (i = 0; i < DIMM_SOCKETS; i++) {
@@ -375,38 +375,38 @@
 	}
 	print_debug("tras = ");
 	print_debug_hex8(tras);
-	print_debug("\r\n");
+	print_debug("\n");
 	print_debug("trtp = ");
 	print_debug_hex8(trtp);
-	print_debug("\r\n");
+	print_debug("\n");
 	print_debug("twtr = ");
 	print_debug_hex8(twtr);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	val = (drt0[index] | ((trc - 11) << 12) | ((cl - 3) << 9)
 	       | ((cl - 3) << 6) | ((cl - 3) << 3));
 	print_debug("drt0 = ");
 	print_debug_hex32(val);
-	print_debug("\r\n");
+	print_debug("\n");
 	pci_write_config32(ctrl->f0, DRT0, val);
 
 	val = (drt1[index] | ((tras - 8) << 28) | ((trtp - 2) << 25)
 	       | (twtr << 15));
 	print_debug("drt1 = ");
 	print_debug_hex32(val);
-	print_debug("\r\n");
+	print_debug("\n");
 	pci_write_config32(ctrl->f0, DRT1, val);
 
 	val = (magic[index]);
 	print_debug("magic = ");
 	print_debug_hex32(val);
-	print_debug("\r\n");
+	print_debug("\n");
 	pci_write_config32(PCI_DEV(0, 0x08, 0), 0xcc, val);
 
 	val = (mrs[index] | (cl << 20));
 	print_debug("mrs = ");
 	print_debug_hex32(val);
-	print_debug("\r\n");
+	print_debug("\n");
 	return val;
 }
 
@@ -423,11 +423,11 @@
 		if (!(dimm_mask & (1 << i)))
 			continue;
 		if ((spd_read_byte(ctrl->channel0[i], SPD_MODULE_DATA_WIDTH_LSB) & 0xf0) != 0x40)
-			die("ERROR: Only 64-bit DIMMs supported\r\n");
+			die("ERROR: Only 64-bit DIMMs supported\n");
 		if (!(spd_read_byte(ctrl->channel0[i], SPD_DIMM_CONFIG_TYPE) & 0x02))
-			die("ERROR: Only ECC DIMMs supported\r\n");
+			die("ERROR: Only ECC DIMMs supported\n");
 		if (spd_read_byte(ctrl->channel0[i], SPD_PRIMARY_SDRAM_WIDTH) != 0x08)
-			die("ERROR: Only x8 DIMMs supported\r\n");
+			die("ERROR: Only x8 DIMMs supported\n");
 
 		value = spd_read_byte(ctrl->channel0[i], SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
 		if (value > cycle)
@@ -435,7 +435,7 @@
 	}
 	print_debug("cycle = ");
 	print_debug_hex8(cycle);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	drc |= (1 << 20); /* enable ECC */
 	drc |= (3 << 30); /* enable CKE on each DIMM */
@@ -447,42 +447,42 @@
 	print_debug("msr 0xcd = ");
 	print_debug_hex32(msr.hi);
 	print_debug_hex32(msr.lo);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	/* TODO check that this msr really indicates fsb speed! */
 	if (msr.lo & 0x07) {
-		print_info("533 MHz FSB\r\n");
+		print_info("533 MHz FSB\n");
 		if (cycle <= 0x25) {
 			drc |= 0x5;
-			print_info("400 MHz DDR\r\n");
+			print_info("400 MHz DDR\n");
 		} else if (cycle <= 0x30) {
 			drc |= 0x7;
-			print_info("333 MHz DDR\r\n");
+			print_info("333 MHz DDR\n");
 		} else if (cycle <= 0x3d) {
 			drc |= 0x4;
-			print_info("266 MHz DDR\r\n");
+			print_info("266 MHz DDR\n");
 		} else {
 			drc |= 0x2;
-			print_info("200 MHz DDR\r\n");
+			print_info("200 MHz DDR\n");
 		}
 	}
 	else {
-		print_info("400 MHz FSB\r\n");
+		print_info("400 MHz FSB\n");
 		if (cycle <= 0x30) {
 			drc |= 0x7;
-			print_info("333 MHz DDR\r\n");
+			print_info("333 MHz DDR\n");
 		} else if (cycle <= 0x3d) {
 			drc |= 0x0;
-			print_info("266 MHz DDR\r\n");
+			print_info("266 MHz DDR\n");
 		} else {
 			drc |= 0x2;
-			print_info("200 MHz DDR\r\n");
+			print_info("200 MHz DDR\n");
 		}
 	}
 
 	print_debug("DRC = ");
 	print_debug_hex32(drc);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	return drc;
 }
@@ -495,7 +495,7 @@
 	/* Test if we can read the SPD */
 	dimm_mask = spd_detect_dimms(ctrl);
 	if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
-		print_err("No memory for this cpu\r\n");
+		print_err("No memory for this cpu\n");
 		return;
 	}
 	return;
@@ -525,14 +525,14 @@
 
 	print_debug("ODT Value = ");
 	print_debug_hex32(data32);
-	print_debug("\r\n");
+	print_debug("\n");
 
   	pci_write_config32(ctrl->f0, DDR2ODTC, data32);
 
 	for (i = 0; i < 2; i++) {
 		print_debug("ODT CS");
 		print_debug_hex8(i);
-		print_debug("\r\n");
+		print_debug("\n");
 
 		write32(BAR+DCALADDR, 0x0b840001);
 		write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21));
@@ -548,14 +548,14 @@
 	int i;
 	for (i = 0x0; i < 0x2a0; i += 4) {
 		if ((i % 16) == 0) {
-			print_debug("\r\n");
+			print_debug("\n");
 			print_debug_hex16(i);
 			print_debug(": ");
 		}
 		print_debug_hex32(read32(BAR+i));
 		print_debug(" ");
 	}
-	print_debug("\r\n");
+	print_debug("\n");
 }
 
 
@@ -571,12 +571,12 @@
 	u16 data16;
 
 	mask = spd_detect_dimms(ctrl);
-	print_debug("Starting SDRAM Enable\r\n");
+	print_debug("Starting SDRAM Enable\n");
 
 	/* Set DRAM type and Front Side Bus frequency */
 	drc = spd_set_dram_controller_mode(ctrl, mask);
 	if (drc == 0) {
-		die("Error calculating DRC\r\n");
+		die("Error calculating DRC\n");
 	}
 	data32 = drc & ~(3 << 20);  /* clear ECC mode */
 	data32 = data32 | (3 << 5);  /* temp turn off ODT */
@@ -601,7 +601,7 @@
 	for (cs = 0; cs < 2; cs++) {
 		print_debug("NOP CS");
 		print_debug_hex8(cs);
-		print_debug("\r\n");
+		print_debug("\n");
 		udelay(16);
 		write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21)));
 		write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21)));
@@ -615,7 +615,7 @@
 	for (cs = 0; cs < 2; cs++) {
 		print_debug("NOP CS");
 		print_debug_hex8(cs);
-		print_debug("\r\n");
+		print_debug("\n");
 		write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21))); 
 		data32 = read32(BAR+DCALCSR);
 		while (data32 & 0x80000000)
@@ -627,7 +627,7 @@
 	for (cs = 0; cs < 2; cs++) {	
 		print_debug("Precharge CS");
 		print_debug_hex8(cs);
-		print_debug("\r\n");
+		print_debug("\n");
 		write32(BAR+DCALADDR, 0x04000000);
 		write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
 		data32 = read32(BAR+DCALCSR);
@@ -640,7 +640,7 @@
 	for (cs = 0; cs < 2; cs++) {	
 		print_debug("EMRS CS");
 		print_debug_hex8(cs);
-		print_debug("\r\n");
+		print_debug("\n");
 		write32(BAR+DCALADDR, 0x0b840001);
 		write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
 		data32 = read32(BAR+DCALCSR);
@@ -652,7 +652,7 @@
 	for (cs = 0; cs < 2; cs++) {	
 		print_debug("MRS CS");
 		print_debug_hex8(cs);
-		print_debug("\r\n");
+		print_debug("\n");
 		write32(BAR+DCALADDR, mode_reg);
 		write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
 		data32 = read32(BAR+DCALCSR);
@@ -665,7 +665,7 @@
 	for (cs = 0; cs < 2; cs++) {	
 		print_debug("Precharge CS");
 		print_debug_hex8(cs);
-		print_debug("\r\n");
+		print_debug("\n");
 		write32(BAR+DCALADDR, 0x04000000);
 		write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
 		data32 = read32(BAR+DCALCSR);
@@ -679,7 +679,7 @@
 		for (cs = 0; cs < 2; cs++) {	
 			print_debug("Refresh CS");
 			print_debug_hex8(cs);
-			print_debug("\r\n");
+			print_debug("\n");
 			write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
 			data32 = read32(BAR+DCALCSR);
 			while (data32 & 0x80000000)
@@ -692,7 +692,7 @@
 	for (cs = 0; cs < 2; cs++) {	
 		print_debug("MRS CS");
 		print_debug_hex8(cs);
-		print_debug("\r\n");
+		print_debug("\n");
 		write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
 		write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
 		data32 = read32(BAR+DCALCSR);
@@ -705,7 +705,7 @@
 	for (cs = 0; cs < 2; cs++) {
 		print_debug("EMRS CS");
 		print_debug_hex8(cs);
-		print_debug("\r\n");
+		print_debug("\n");
 		write32(BAR+DCALADDR, 0x0b840001);
 		write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
 		data32 = read32(BAR+DCALCSR);
@@ -729,7 +729,7 @@
 	for (cs = 0; cs < 1; cs++) {
 		print_debug("receive enable calibration CS");
 		print_debug_hex8(cs);
-		print_debug("\r\n");
+		print_debug("\n");
 		write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21)));
 		data32 = read32(BAR+DCALCSR);
 		while (data32 & 0x80000000)
@@ -756,17 +756,17 @@
 			continue;
 		print_debug("clear memory CS");
 		print_debug_hex8(cs);
-		print_debug("\r\n");
+		print_debug("\n");
 		write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16));
 		data32 = read32(BAR+MBCSR);
 		while (data32 & 0x80000000)
 			data32 = read32(BAR+MBCSR);
 		if (data32 & 0x40000000)
-			print_debug("failed!\r\n");
+			print_debug("failed!\n");
 	}
 
 	/* Clear read/write FIFO pointers */
-	print_debug("clear read/write fifo pointers\r\n");
+	print_debug("clear read/write fifo pointers\n");
 	write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1<<15));
 	udelay(16);
 	write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1<<15));
@@ -774,7 +774,7 @@
 
 	dump_dcal_regs();
 
-	print_debug("Done\r\n");
+	print_debug("Done\n");
 
 	/* Set initialization complete */
 	drc |= (1 << 29);
Index: src/northbridge/intel/i82830/raminit.c
===================================================================
--- src/northbridge/intel/i82830/raminit.c	(revision 3942)
+++ src/northbridge/intel/i82830/raminit.c	(working copy)
@@ -100,7 +100,7 @@
 			PRINT_DEBUG_HEX32(reg32);
 			PRINT_DEBUG(" to 0x");
 			PRINT_DEBUG_HEX32((dimm_start * 32 * 1024 * 1024) + addr_offset);
-			PRINT_DEBUG("\r\n");
+			PRINT_DEBUG("\n");
 			read32((dimm_start * 32 * 1024 * 1024) + addr_offset);
 		}
 		/* Set the start of the next DIMM. */
@@ -178,28 +178,28 @@
 		if (spd_read_byte(device, 2) == 0x4) {
 			print_debug("Found DIMM in slot ");
 			print_debug_hex8(i);
-			print_debug("\r\n");
+			print_debug("\n");
 
 			sz = spd_get_dimm_size(device);
 
 			/* WISHLIST: would be nice to display it as decimal? */
 			print_debug("DIMM is 0x");
 			print_debug_hex16(sz.side1);
-			print_debug(" on side 1\r\n");
+			print_debug(" on side 1\n");
 			print_debug("DIMM is 0x");
 			print_debug_hex16(sz.side2);
-			print_debug(" on side 2\r\n");
+			print_debug(" on side 2\n");
 
 			/* Test for PC133 (i82830 only supports PC133) */
 			/* PC133 SPD9 - cycle time is always 75 */
 			if (spd_read_byte(device, 9) != 0x75) {
-				print_err("SPD9 DIMM Is Not PC133 Compatable\r\n");
-				die("HALT\r\n");
+				print_err("SPD9 DIMM Is Not PC133 Compatable\n");
+				die("HALT\n");
 			}
 			/* PC133 SPD10 - access time is always 54 */
 			if (spd_read_byte(device, 10) != 0x54) {
-				print_err("SPD10 DIMM Is Not PC133 Compatable\r\n");
-				die("HALT\r\n");
+				print_err("SPD10 DIMM Is Not PC133 Compatable\n");
+				die("HALT\n");
 			}
 
 			/* The i82830 only supports a symmetrical dual-sided dimms
@@ -207,23 +207,23 @@
 			 * side or larger than 256MB per side.
 			 */
 			if ((sz.side2 != 0) && (sz.side1 != sz.side2)) {
-				print_err("This northbridge only supports\r\n");
-				print_err("symmetrical dual-sided DIMMs\r\n");
-				print_err("booting as a single-sided DIMM\r\n");
+				print_err("This northbridge only supports\n");
+				print_err("symmetrical dual-sided DIMMs\n");
+				print_err("booting as a single-sided DIMM\n");
 				sz.side2 = 0;
 			}
 			if ((sz.side1 < 32)) {
-				print_err("DIMMs smaller than 32MB per side\r\n");
-				print_err("are not supported on this northbridge\r\n");
-				die("HALT\r\n");
+				print_err("DIMMs smaller than 32MB per side\n");
+				print_err("are not supported on this northbridge\n");
+				die("HALT\n");
 			}
 
 			if ((sz.side1 > 256)) {
 				print_err
-				    ("DIMMs larger than 256MB per side\r\n");
+				    ("DIMMs larger than 256MB per side\n");
 				print_err
-				    ("are not supported on this northbridge\r\n");
-				die("HALT\r\n");
+				    ("are not supported on this northbridge\n");
+				die("HALT\n");
 			}
 
 			/* We need to divide size by 32 to set up the
@@ -236,7 +236,7 @@
 		} else {
 			PRINT_DEBUG("No DIMM found in slot ");
 			PRINT_DEBUG_HEX8(i);
-			PRINT_DEBUG("\r\n");
+			PRINT_DEBUG("\n");
 
 			/* If there's no DIMM in the slot, set value to 0. */
 			drb1 = 0;
@@ -250,12 +250,12 @@
 			PRINT_DEBUG_HEX8(DRB);
 			PRINT_DEBUG(" has been set to 0x");
 			PRINT_DEBUG_HEX8(drb1);
-			PRINT_DEBUG("\r\n");
+			PRINT_DEBUG("\n");
 			PRINT_DEBUG("DRB1 0x");
 			PRINT_DEBUG_HEX8(DRB + 1);
 			PRINT_DEBUG(" has been set to 0x");
 			PRINT_DEBUG_HEX8(drb1 + drb2);
-			PRINT_DEBUG("\r\n");
+			PRINT_DEBUG("\n");
 		} else if (i == 1) {
 			value = pci_read_config8(ctrl->d0, DRB + 1);
 			pci_write_config8(ctrl->d0, DRB + 2, value + drb1);
@@ -265,12 +265,12 @@
 			PRINT_DEBUG_HEX8(DRB + 2);
 			PRINT_DEBUG(" has been set to 0x");
 			PRINT_DEBUG_HEX8(value + drb1);
-			PRINT_DEBUG("\r\n");
+			PRINT_DEBUG("\n");
 			PRINT_DEBUG("DRB3 0x");
 			PRINT_DEBUG_HEX8(DRB + 3);
 			PRINT_DEBUG(" has been set to 0x");
 			PRINT_DEBUG_HEX8(value + drb1 + drb2);
-			PRINT_DEBUG("\r\n");
+			PRINT_DEBUG("\n");
 
 			/* We need to set the highest DRB value to 0x64 and 0x65.
 			 * These are supposed to be "Reserved" but memory will
@@ -295,7 +295,7 @@
 		if (spd_read_byte(device, 2) == 0x4) {
 			print_debug("Found DIMM in slot ");
 			print_debug_hex8(i);
-			print_debug(", setting DRA...\r\n");
+			print_debug(", setting DRA...\n");
 
 			dra = 0x00;
 
@@ -324,8 +324,8 @@
 				} else if (dra == 16) {
 					dra = 0xF3; /* 16KB */
 				} else {
-					print_err("Page size not supported\r\n");
-					die("HALT\r\n");
+					print_err("Page size not supported\n");
+					die("HALT\n");
 				}
 			} else if (value == 2) {
 				if (dra == 2) {
@@ -337,18 +337,18 @@
 				} else if (dra == 16) {
 					dra = 0x33; /* 16KB */
 				} else {
-					print_err("Page size not supported\r\n");
-					die("HALT\r\n");
+					print_err("Page size not supported\n");
+					die("HALT\n");
 				}
 			} else {
-				print_err("# of banks of DIMM not supported\r\n");
-				die("HALT\r\n");
+				print_err("# of banks of DIMM not supported\n");
+				die("HALT\n");
 			}
 
 		} else {
 			PRINT_DEBUG("No DIMM found in slot ");
 			PRINT_DEBUG_HEX8(i);
-			PRINT_DEBUG(", setting DRA to 0xFF\r\n");
+			PRINT_DEBUG(", setting DRA to 0xFF\n");
 
 			/* If there's no DIMM in the slot, set dra value to 0xFF. */
 			dra = 0xFF;
@@ -360,7 +360,7 @@
 		PRINT_DEBUG_HEX8(DRA + i);
 		PRINT_DEBUG(" has been set to 0x");
 		PRINT_DEBUG_HEX8(dra);
-		PRINT_DEBUG("\r\n");
+		PRINT_DEBUG("\n");
 	}
 }
 
@@ -392,7 +392,7 @@
 	uint16_t value;
 	int igd_memory = 0;
 
-	PRINT_DEBUG("Setting initial registers....\r\n");
+	PRINT_DEBUG("Setting initial registers....\n");
 
 	/* Set the value for GMCH Control Register #0 */
 	pci_write_config16(ctrl->d0, GCC0, 0xA072);
@@ -446,7 +446,7 @@
 	/* Set the value for Extended System Management RAM Control Register */
 	pci_write_config8(ctrl->d0, ESMRAMC, 0x38);
 
-	PRINT_DEBUG("Initial registers have been set.\r\n");
+	PRINT_DEBUG("Initial registers have been set.\n");
 }
 
 static void sdram_set_spd_registers(const struct mem_controller *ctrl)
@@ -466,17 +466,17 @@
 	udelay(200);
 
 	/* 1. Apply NOP. */
-	PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
+	PRINT_DEBUG("RAM Enable 1: Apply NOP\n");
 	do_ram_command(ctrl, RAM_COMMAND_NOP, 0);
 	udelay(200);
 
 	/* 2. Precharge all. Wait tRP. */
-	PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
+	PRINT_DEBUG("RAM Enable 2: Precharge all\n");
 	do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0);
 	udelay(1);
 
 	/* 3. Perform 8 refresh cycles. Wait tRC each time. */
-	PRINT_DEBUG("RAM Enable 3: CBR\r\n");
+	PRINT_DEBUG("RAM Enable 3: CBR\n");
 	for (i = 0; i < 8; i++) {
 		do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
 		udelay(1);
@@ -484,21 +484,21 @@
 
 	/* 4. Mode register set. Wait two memory cycles. */
 	/* TODO: Set offset according to DRT values */
-	PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
+	PRINT_DEBUG("RAM Enable 4: Mode register set\n");
 	do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0);
 	udelay(2);
 
 	/* 5. Normal operation (enables refresh) */
-	PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
+	PRINT_DEBUG("RAM Enable 5: Normal operation\n");
 	do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0);
 	udelay(1);
 
 	/* 6. Enable refresh and Set initialization complete. */
-	PRINT_DEBUG("RAM Enable 6: Enable Refresh and IC\r\n");
+	PRINT_DEBUG("RAM Enable 6: Enable Refresh and IC\n");
 	reg32 = pci_read_config32(ctrl->d0, DRC);
 	reg32 |= ((RAM_COMMAND_REFRESH << 8) | (RAM_COMMAND_IC << 29));
 	pci_write_config32(ctrl->d0, DRC, reg32);
 
-	PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
+	PRINT_DEBUG("Northbridge following SDRAM init:\n");
 	DUMPNORTH();
 }
Index: src/arch/i386/lib/console.c
===================================================================
--- src/arch/i386/lib/console.c	(revision 3942)
+++ src/arch/i386/lib/console.c	(working copy)
@@ -28,12 +28,12 @@
 static void console_init(void)
 {
 	static const char console_test[] = 
-		"\r\n\r\ncoreboot-"
+		"\n\ncoreboot-"
 		COREBOOT_VERSION
 		COREBOOT_EXTRA_VERSION
 		" "
 		COREBOOT_BUILD
-		" starting...\r\n";
+		" starting...\n";
 	print_info(console_test);
 }
 
Index: src/drivers/generic/debug/debug_dev.c
===================================================================
--- src/drivers/generic/debug/debug_dev.c	(revision 3942)
+++ src/drivers/generic/debug/debug_dev.c	(working copy)
@@ -90,16 +90,16 @@
 		unsigned char byte;
 		status = smbus_read_byte(dev, j);
 		if (status < 0) {
-		//	printk_debug("bad device status= %08x\r\n", status);
+		//	printk_debug("bad device status= %08x\n", status);
 			break;
 		}
                 if ((j & 0xf) == 0) {
-                        printk_debug("\r\n%02x: ", j);
+                        printk_debug("\n%02x: ", j);
                 }  
 		byte = status & 0xff;
 		printk_debug("%02x ", byte);
 	}
-	printk_debug("\r\n");
+	printk_debug("\n");
 }
 
 static void print_smbus_regs_all(struct device *dev)
Index: src/drivers/ati/ragexl/xlinit.c
===================================================================
--- src/drivers/ati/ragexl/xlinit.c	(revision 3942)
+++ src/drivers/ati/ragexl/xlinit.c	(working copy)
@@ -541,7 +541,7 @@
 #endif
 
 #if 0
-	printk_debug("ati_regbase = 0x%08x, frame_buffer = 0x%08x\r\n", info->ati_regbase, info->frame_buffer);
+	printk_debug("ati_regbase = 0x%08x, frame_buffer = 0x%08x\n", info->ati_regbase, info->frame_buffer);
 #endif
 
     	chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);
@@ -561,7 +561,7 @@
     	return ;
 
 found:
-    	printk_info("ati_ragexl_init: %s [0x%04x rev 0x%02x]\r\n", chipname, type, rev);
+    	printk_info("ati_ragexl_init: %s [0x%04x rev 0x%02x]\n", chipname, type, rev);
 #if 0
     	if (M64_HAS(INTEGRATED)) {
         	/* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
Index: src/drivers/i2c/adm1027/adm1027.c
===================================================================
--- src/drivers/i2c/adm1027/adm1027.c	(revision 3942)
+++ src/drivers/i2c/adm1027/adm1027.c	(working copy)
@@ -27,7 +27,7 @@
 	result = smbus_read_byte(dev, ADM1027_REG_CONFIG1);
 
 	if (!(result & CFG1_RDY)) {
-		printk_debug("ADM1027: monitoring not ready\r\n");
+		printk_debug("ADM1027: monitoring not ready\n");
 		return;
 	}
 	result = (result | CFG1_STRT);
@@ -35,9 +35,9 @@
 
 	result = smbus_read_byte(dev, ADM1027_REG_CONFIG1);
 	if (!(result & CFG1_STRT)) {
-		printk_debug("ADM1027: monitoring would not enable\r\n");
+		printk_debug("ADM1027: monitoring would not enable\n");
 	}
-	printk_debug("ADM1027: monitoring enabled\r\n");
+	printk_debug("ADM1027: monitoring enabled\n");
 }
 
 static void adm1027_init(device_t dev)
Index: util/romcc/tests/simple_test27.c
===================================================================
--- util/romcc/tests/simple_test27.c	(revision 3942)
+++ util/romcc/tests/simple_test27.c	(working copy)
@@ -113,14 +113,14 @@
 
 void main(void)
 {
-	static const char msg[] = "hello world\r\n";
+	static const char msg[] = "hello world\n";
 	uart_init();
 #if 0
 	print_debug(msg);
 #endif
 #if 1
-	print_debug("hello world\r\n");
-	print_debug("how are you today\r\n");
+	print_debug("hello world\n");
+	print_debug("how are you today\n");
 #endif
 	while(1) {
 		;
Index: util/romcc/tests/simple_test29.c
===================================================================
--- util/romcc/tests/simple_test29.c	(revision 3942)
+++ util/romcc/tests/simple_test29.c	(working copy)
@@ -27,11 +27,11 @@
 static void console_init(void)
 {
         static const char console_test[] =
-                "\r\n\r\nLinuxBIOS-"
+                "\n\nLinuxBIOS-"
                 "1.1.0"
                 ".0Fallback"
                 " "
                 "Mon Jun 9 18:15:20 MDT 2003"
-                " starting...\r\n";
+                " starting...\n";
         __console_tx_string(6, console_test);
 }
Index: util/romcc/tests/hello_world.c
===================================================================
--- util/romcc/tests/hello_world.c	(revision 3942)
+++ util/romcc/tests/hello_world.c	(working copy)
@@ -113,14 +113,14 @@
 
 void main(void)
 {
-	static const char msg[] = "hello world\r\n";
+	static const char msg[] = "hello world\n";
 	uart_init();
 #if 0
 	print_debug(msg);
 #endif
 #if 1
-	print_debug("hello world\r\n");
-	print_debug("how are you today\r\n");
+	print_debug("hello world\n");
+	print_debug("how are you today\n");
 #endif
 	while(1) {
 		;
Index: util/romcc/tests/linux_test2.c
===================================================================
--- util/romcc/tests/linux_test2.c	(revision 3942)
+++ util/romcc/tests/linux_test2.c	(working copy)
@@ -640,7 +640,7 @@
 	};
 	int i;
 	int max;
-	print_debug("setting up coherent ht domain....\r\n");
+	print_debug("setting up coherent ht domain....\n");
 	max = sizeof(register_values)/sizeof(register_values[0]);
 	for(i = 0; i < max; i += 3) {
 		unsigned long reg;
@@ -648,7 +648,7 @@
 		print_debug_hex32(register_values[i]);
 		print_debug(" <-");
 		print_debug_hex32(register_values[i+2]);
-		print_debug("\r\n");
+		print_debug("\n");
 #endif
 #if 0
 		reg = pci_read_config32(register_values[i]);
@@ -657,12 +657,12 @@
 		pci_write_config32(register_values[i], reg);
 #endif
 	}
-	print_debug("done.\r\n");
+	print_debug("done.\n");
 }
 
 static void main(void)
 {
-	static const char msg[] = "hello world\r\n";
+	static const char msg[] = "hello world\n";
 #if 0
 	write(STDOUT_FILENO, msg, sizeof(msg));
 #endif
Index: util/romcc/tests/linux_test6.c
===================================================================
--- util/romcc/tests/linux_test6.c	(revision 3942)
+++ util/romcc/tests/linux_test6.c	(working copy)
@@ -6,11 +6,11 @@
 	static const int value[] = { 1, 0 };
 	const char *str;
 	if (value[1]) {
-		print_debug("A\r\n");
-		str = "Unbuffered\r\n";
+		print_debug("A\n");
+		str = "Unbuffered\n";
 	} else {
-		print_debug("B\r\n");
-		str = "Registered\r\n";
+		print_debug("B\n");
+		str = "Registered\n";
 	}
 	print_debug(str);
 	_exit(0);
Index: util/romcc/tests/linux_test8.c
===================================================================
--- util/romcc/tests/linux_test8.c	(revision 3942)
+++ util/romcc/tests/linux_test8.c	(working copy)
@@ -15,7 +15,7 @@
 static void test(void)
 {
 	static const struct mem_param param0 = {
-		.name = "166Mhz\r\n",
+		.name = "166Mhz\n",
 		.cycle_time = 0x60,
 		.divisor = (6<<1),
 		.tRC = 0x3C,
@@ -34,6 +34,6 @@
 	clocks = (value + (param->divisor << 1) - 1)/(param->divisor << 1);
 	print_debug("clocks: ");
 	print_debug_hex32(clocks);
-	print_debug("\r\n");
+	print_debug("\n");
 	_exit(0);
 }
Index: util/romcc/tests/simple_test30.c
===================================================================
--- util/romcc/tests/simple_test30.c	(revision 3942)
+++ util/romcc/tests/simple_test30.c	(working copy)
@@ -1054,7 +1054,7 @@
 	};
 	int i;
 	int max;
-	print_debug("setting up coherent ht domain....\r\n");
+	print_debug("setting up coherent ht domain....\n");
 	max = sizeof(register_values)/sizeof(register_values[0]);
 	for(i = 0; i < max; i += 3) {
 		unsigned long reg;
@@ -1062,7 +1062,7 @@
 		print_debug_hex32(register_values[i]);
 		print_debug(" <-");
 		print_debug_hex32(register_values[i+2]);
-		print_debug("\r\n");
+		print_debug("\n");
 #endif
 #if 0
 		reg = pci_read_config32(register_values[i]);
@@ -1071,12 +1071,12 @@
 		pci_write_config32(register_values[i], reg);
 #endif
 	}
-	print_debug("done.\r\n");
+	print_debug("done.\n");
 }
 
 static void main(void)
 {
-	static const char msg[] = "hello world\r\n";
+	static const char msg[] = "hello world\n";
 #if 0
 	write(STDOUT_FILENO, msg, sizeof(msg));
 #endif
Index: util/romcc/tests/hello_world2.c
===================================================================
--- util/romcc/tests/hello_world2.c	(revision 3942)
+++ util/romcc/tests/hello_world2.c	(working copy)
@@ -113,13 +113,13 @@
 
 void main(void)
 {
-	static const char msg[] = "hello world\r\n";
+	static const char msg[] = "hello world\n";
 	uart_init();
 #if 0
 	print_debug(msg);
 #endif
 #if 1
-	print_debug("hello world\r\n");
+	print_debug("hello world\n");
 #endif
 	while(1) {
 		;
Index: util/romcc/tests/simple_test15.c
===================================================================
--- util/romcc/tests/simple_test15.c	(revision 3942)
+++ util/romcc/tests/simple_test15.c	(working copy)
@@ -42,6 +42,6 @@
 
 static void main(void)
 {
-	print_debug("one\r\n");
-        print_debug("two\r\n");
+	print_debug("one\n");
+        print_debug("two\n");
 }
Index: util/romcc/tests/simple_test34.c
===================================================================
--- util/romcc/tests/simple_test34.c	(revision 3942)
+++ util/romcc/tests/simple_test34.c	(working copy)
@@ -55,7 +55,7 @@
 	print_debug("TOP_MEM: ");
 	print_debug_hex32(msr.hi);
 	print_debug_hex32(msr.lo);
-	print_debug("\r\n");
+	print_debug("\n");
 
 	start = 0;
 	stop = msr.lo;
@@ -63,7 +63,7 @@
         print_debug_hex32(start);
         print_debug("-");
         print_debug_hex32(stop);
-        print_debug("\r\n");
+        print_debug("\n");
 
         print_debug("DRAM verify: ");
         print_debug_hex32(start);
Index: util/romcc/tests/simple_test74.c
===================================================================
--- util/romcc/tests/simple_test74.c	(revision 3942)
+++ util/romcc/tests/simple_test74.c	(working copy)
@@ -82,7 +82,7 @@
 
 static void main(void)
 {
-	static const char msg[] = "hello world\r\n";
+	static const char msg[] = "hello world\n";
 	write(STDOUT_FILENO, msg, sizeof(msg));
 	_exit(0);
 }
Index: util/romcc/tests/simple_test76.c
===================================================================
--- util/romcc/tests/simple_test76.c	(revision 3942)
+++ util/romcc/tests/simple_test76.c	(working copy)
@@ -63,7 +63,7 @@
 
 static void main(void)
 {
-	static const char msg[] = "hello world\r\n";
+	static const char msg[] = "hello world\n";
 	write(STDOUT_FILENO, msg, sizeof(msg));
 	_exit(0);
 }
Index: util/romcc/tests/simple_test59.c
===================================================================
--- util/romcc/tests/simple_test59.c	(revision 3942)
+++ util/romcc/tests/simple_test59.c	(working copy)
@@ -409,11 +409,11 @@
 	static const int value[] = { 1 };
 	const char *str;
 	if (value[1]) {
-		print_debug("A\r\n");
-		str = "Unbuffered\r\n";
+		print_debug("A\n");
+		str = "Unbuffered\n";
 	} else {
-		print_debug("B\r\n");
-		str = "Registered\r\n";
+		print_debug("B\n");
+		str = "Registered\n";
 	}
 	print_debug(str);
 	_exit(0);
Index: util/romcc/tests/simple_test8.c
===================================================================
--- util/romcc/tests/simple_test8.c	(revision 3942)
+++ util/romcc/tests/simple_test8.c	(working copy)
@@ -2,7 +2,7 @@
 
 void main(void)
 {
-	static const char msg[] = "hello world\r\n";
+	static const char msg[] = "hello world\n";
 	char *str;
 	char ch;
 	str = msg;
Index: util/romcc/tests/raminit_test3.c
===================================================================
--- util/romcc/tests/raminit_test3.c	(revision 3942)
+++ util/romcc/tests/raminit_test3.c	(working copy)
@@ -324,12 +324,12 @@
 static void console_init(void)
 {
         static const char console_test[] =
-                "\r\n\r\nLinuxBIOS-"
+                "\n\nLinuxBIOS-"
                 "1.1.0"
                 ".0Fallback"
                 " "
                 "Mon Jun 9 18:15:20 MDT 2003"
-                " starting...\r\n";
+                " starting...\n";
         print_info(console_test);
 }
 # 7 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" 2
@@ -358,7 +358,7 @@
         print_debug_hex32(start);
         print_debug("-");
         print_debug_hex32(stop);
-        print_debug("\r\n");
+        print_debug("\n");
         for(addr = start; addr < stop ; addr += 4) {
 
                 if ((addr & 0xffff) == 0) {
@@ -369,7 +369,7 @@
         };
 
         print_debug_hex32(addr);
-        print_debug("\r\nDRAM filled\r\n");
+        print_debug("\nDRAM filled\n");
 }
 
 void ram_verify(unsigned long start, unsigned long stop)
@@ -382,7 +382,7 @@
         print_debug_hex32(start);
         print_debug_char('-');
         print_debug_hex32(stop);
-        print_debug("\r\n");
+        print_debug("\n");
         for(addr = start; addr < stop ; addr += 4) {
                 unsigned long value;
 
@@ -396,12 +396,12 @@
                         print_err_hex32(addr);
                         print_err_char(':');
                         print_err_hex32(value);
-                        print_err("\r\n");
+                        print_err("\n");
                 }
         }
 
         print_debug_hex32(addr);
-        print_debug("\r\nDRAM verified\r\n");
+        print_debug("\nDRAM verified\n");
 }
 
 
@@ -417,7 +417,7 @@
         print_debug_hex32(start);
         print_debug("-");
         print_debug_hex32(stop);
-        print_debug("\r\n");
+        print_debug("\n");
         ram_fill(start, stop);
         ram_verify(start, stop);
         print_debug("Done.\n");
@@ -558,7 +558,7 @@
         };
         int i;
         int max;
-        print_debug("setting up CPU0 northbridge registers\r\n");
+        print_debug("setting up CPU0 northbridge registers\n");
         max = sizeof(register_values)/sizeof(register_values[0]);
         for(i = 0; i < max; i += 3) {
                 unsigned long reg;
@@ -573,7 +573,7 @@
                 reg |= register_values[i+2];
                 pci_write_config32(register_values[i], reg);
         }
-        print_debug("done.\r\n");
+        print_debug("done.\n");
 }
 # 743 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
 static void sdram_set_spd_registers(void)
@@ -594,7 +594,7 @@
         dcl = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x90) & 0xFF)));
         print_debug("dcl: ");
         print_debug_hex32(dcl);
-        print_debug("\r\n");
+        print_debug("\n");
         dcl |= (1<<3);
         pci_write_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x07) << 8) | ((0x90) & 0xFF)), dcl);
         dcl &= ~(1<<3);
@@ -614,9 +614,9 @@
                 }
         } while(((dcl & (1<<8)) != 0) && (loops < 300000));
         if (loops >= 300000) {
-                print_debug(" failed\r\n");
+                print_debug(" failed\n");
         } else {
-                print_debug(" done\r\n");
+                print_debug(" done\n");
         }
 # 803 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
 }
@@ -628,7 +628,7 @@
 # 1 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/sdram/generic_sdram.c" 1
 void sdram_no_memory(void)
 {
-        print_err("No memory!!\r\n");
+        print_err("No memory!!\n");
         while(1) {
                 hlt();
         }
@@ -637,29 +637,29 @@
 
 void sdram_initialize(void)
 {
-        print_debug("Ram1\r\n");
+        print_debug("Ram1\n");
 
         sdram_set_registers();
 
-        print_debug("Ram2\r\n");
+        print_debug("Ram2\n");
 
         sdram_set_spd_registers();
 
-        print_debug("Ram3\r\n");
+        print_debug("Ram3\n");
 
 
 
 
         sdram_enable();
 
-        print_debug("Ram4\r\n");
+        print_debug("Ram4\n");
         sdram_first_normal_reference();
 
-        print_debug("Ram5\r\n");
+        print_debug("Ram5\n");
         sdram_enable_refresh();
         sdram_special_finishup();
 
-        print_debug("Ram6\r\n");
+        print_debug("Ram6\n");
 }
 # 810 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c" 2
 
@@ -672,7 +672,7 @@
         msr = rdmsr(0x1b);
         bsp = !!(msr.lo & (1 << 8));
         if (bsp) {
-                print_debug("Bootstrap cpu\r\n");
+                print_debug("Bootstrap cpu\n");
         }
 
         return bsp;
@@ -689,7 +689,7 @@
 # 849 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
         cpu_init = (htic & (1<<6));
         if (cpu_init) {
-                print_debug("CPU INIT Detected.\r\n");
+                print_debug("CPU INIT Detected.\n");
         }
         return cpu_init;
 }
@@ -777,7 +777,7 @@
         };
         int i;
         int max;
-        print_debug("setting up coherent ht domain....\r\n");
+        print_debug("setting up coherent ht domain....\n");
         max = sizeof(register_values)/sizeof(register_values[0]);
         for(i = 0; i < max; i += 3) {
                 unsigned long reg;
@@ -792,7 +792,7 @@
                 reg |= register_values[i+2] & ~register_values[i+1];
                 pci_write_config32(register_values[i], reg);
         }
-        print_debug("done.\r\n");
+        print_debug("done.\n");
 }
 
 static void enumerate_ht_chain(void)
@@ -857,7 +857,7 @@
                 print_debug_hex8(addr >> 11);
                 print_debug_char('.');
                 print_debug_hex8((addr >> 8) & 7);
-                print_debug("\r\n");
+                print_debug("\n");
         }
 }
 # 1525 "/home/eric/projects/linuxbios/checkin/solo/freebios2/src/mainboard/amd/solo/auto.c"
@@ -874,10 +874,10 @@
                 }
         }
         if (addr > ( (((0) & 0xFF) << 16) | (((0x1f) & 0x1f) << 11) | (((0x7) & 0x07) << 8) | ((0) & 0xFF))) {
-                die("SMBUS controller not found\r\n");
+                die("SMBUS controller not found\n");
         }
         uint8_t enable;
-        print_debug("SMBus controller enabled\r\n");
+        print_debug("SMBus controller enabled\n");
         pci_write_config32(addr + 0x58, 0x1000 | 1);
         enable = pci_read_config8(addr + 0x41);
         pci_write_config8(addr + 0x41, enable | (1 << 7));
@@ -971,7 +971,7 @@
 {
         unsigned device;
         device = (0xa << 3);
-        print_debug("\r\n");
+        print_debug("\n");
         while(device <= ((0xa << 3) +1)) {
                 int i;
                 print_debug("dimm: ");
@@ -980,13 +980,13 @@
                         int status;
                         unsigned char byte;
                         if ((i & 0xf) == 0) {
-                                print_debug("\r\n");
+                                print_debug("\n");
                                 print_debug_hex8(i);
                                 print_debug(": ");
                         }
                         status = smbus_read_byte(device, i);
                         if (status < 0) {
-                                print_debug("bad device\r\n");
+                                print_debug("bad device\n");
                                 continue;
                         }
                         byte = status & 0xff;
@@ -994,7 +994,7 @@
                         print_debug_char(' ');
                 }
                 device += 1;
-                print_debug("\r\n");
+                print_debug("\n");
         }
 }
 
@@ -1007,20 +1007,20 @@
                 int status;
                 unsigned char byte;
                 if ((i & 0xf) == 0) {
-                        print_debug("\r\n");
+                        print_debug("\n");
                         print_debug_hex8(i);
                         print_debug(": ");
                 }
                 status = smbus_read_byte((0xa << 3), i);
                 if (status < 0) {
-                        print_debug("bad device\r\n");
+                        print_debug("bad device\n");
                         break;
                 }
                 byte = status & 0xff;
                 print_debug_hex8(byte);
                 print_debug_char(' ');
         }
-        print_debug("\r\n");
+        print_debug("\n");
 }
 
 
@@ -1028,7 +1028,7 @@
 static void dump_spd_registers2(void)
 {
         unsigned dev;
-        print_debug("\r\n");
+        print_debug("\n");
         for(dev = (0xa << 3); dev <= ((0xa << 3) +1); dev += 1) {
                 print_debug("dimm: ");
                 print_debug_hex8(dev);
@@ -1036,12 +1036,12 @@
                 unsigned char byte;
                 status = smbus_read_byte(dev, 0);
                 if (status < 0) {
-                        print_debug("bad device\r\n");
+                        print_debug("bad device\n");
                         continue;
                 }
                 byte = status & 0xff;
                 print_debug_hex8(byte);
-                print_debug("\r\n");
+                print_debug("\n");
         }
 }
 
Index: util/romcc/tests/raminit_test5.c
===================================================================
--- util/romcc/tests/raminit_test5.c	(revision 3942)
+++ util/romcc/tests/raminit_test5.c	(working copy)
@@ -357,12 +357,12 @@
 static void console_init(void)
 {
         static const char console_test[] =
-                "\r\n\r\nLinuxBIOS-"
+                "\n\nLinuxBIOS-"
                 "1.1.0"
                 ".0Fallback"
                 " "
                 "Thu Jun 19 05:42:16 MDT 2003"
-                " starting...\r\n";
+                " starting...\n";
         print_info(console_test);
 }
 
@@ -416,7 +416,7 @@
         print_debug_hex32(start);
         print_debug("-");
         print_debug_hex32(stop);
-        print_debug("\r\n");
+        print_debug("\n");
         for(addr = start; addr < stop ; addr += 4) {
 
                 if (!(addr & 0xffff)) {
@@ -427,7 +427,7 @@
         };
 
         print_debug_hex32(addr);
-        print_debug("\r\nDRAM filled\r\n");
+        print_debug("\nDRAM filled\n");
 }
 
 static void ram_verify(unsigned long start, unsigned long stop)
@@ -440,7 +440,7 @@
         print_debug_hex32(start);
         print_debug_char('-');
         print_debug_hex32(stop);
-        print_debug("\r\n");
+        print_debug("\n");
         for(addr = start; addr < stop ; addr += 4) {
                 unsigned long value;
 
@@ -454,12 +454,12 @@
                         print_err_hex32(addr);
                         print_err_char(':');
                         print_err_hex32(value);
-                        print_err("\r\n");
+                        print_err("\n");
                 }
         }
 
         print_debug_hex32(addr);
-        print_debug("\r\nDRAM verified\r\n");
+        print_debug("\nDRAM verified\n");
 }
 
 
@@ -475,7 +475,7 @@
         print_debug_hex32(start);
         print_debug("-");
         print_debug_hex32(stop);
-        print_debug("\r\n");
+        print_debug("\n");
         ram_fill(start, stop);
         ram_verify(start, stop);
         print_debug("Done.\n");
@@ -539,10 +539,10 @@
         device_t dev;
         dev = pci_locate_device(((((0x746b) & 0xFFFF) << 16) | ((0x1022) & 0xFFFF)), 0);
         if (dev == (0xffffffffU)) {
-                die("SMBUS controller not found\r\n");
+                die("SMBUS controller not found\n");
         }
         uint8_t enable;
-        print_debug("SMBus controller enabled\r\n");
+        print_debug("SMBus controller enabled\n");
         pci_write_config32(dev, 0x58, 0x1000 | 1);
         enable = pci_read_config8(dev, 0x41);
         pci_write_config8(dev, 0x41, enable | (1 << 7));
@@ -649,7 +649,7 @@
 static void setup_resource_map(const unsigned int *register_values, int max)
 {
         int i;
-        print_debug("setting up resource map....\r\n");
+        print_debug("setting up resource map....\n");
         for(i = 0; i < max; i += 3) {
                 device_t dev;
                 unsigned where;
@@ -673,7 +673,7 @@
 
 
         }
-        print_debug("done.\r\n");
+        print_debug("done.\n");
 }
 
 static void setup_default_resource_map(void)
@@ -845,7 +845,7 @@
         };
         int i;
         int max;
-        print_debug("setting up CPU0 northbridge registers\r\n");
+        print_debug("setting up CPU0 northbridge registers\n");
         max = sizeof(register_values)/sizeof(register_values[0]);
         for(i = 0; i < max; i += 3) {
                 device_t dev;
@@ -871,7 +871,7 @@
 
 
         }
-        print_debug("done.\r\n");
+        print_debug("done.\n");
 }
 
 
@@ -950,7 +950,7 @@
         print_debug_hex32(sz.side2);
         print_debug_char(',');
         print_debug_hex32(index);
-        print_debug(")\r\n");
+        print_debug(")\n");
 
         if (sz.side1 != sz.side2) {
                 sz.side2 = 0;
@@ -1114,7 +1114,7 @@
         dcl = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x90);
         print_debug("dcl: ");
         print_debug_hex32(dcl);
-        print_debug("\r\n");
+        print_debug("\n");
         dcl |= (1<<3);
         pci_write_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x90, dcl);
         dcl &= ~(1<<3);
@@ -1134,9 +1134,9 @@
                 }
         } while(((dcl & (1<<8)) != 0) && (loops < 300000));
         if (loops >= 300000) {
-                print_debug(" failed\r\n");
+                print_debug(" failed\n");
         } else {
-                print_debug(" done\r\n");
+                print_debug(" done\n");
         }
 
 }
@@ -1176,7 +1176,7 @@
         };
         int i;
         int max;
-        print_debug("setting up coherent ht domain....\r\n");
+        print_debug("setting up coherent ht domain....\n");
         max = sizeof(register_values)/sizeof(register_values[0]);
         for(i = 0; i < max; i += 3) {
                 device_t dev;
@@ -1201,13 +1201,13 @@
 
 
         }
-        print_debug("done.\r\n");
+        print_debug("done.\n");
 }
 
 
 void sdram_no_memory(void)
 {
-        print_err("No memory!!\r\n");
+        print_err("No memory!!\n");
         while(1) {
                 hlt();
         }
@@ -1216,29 +1216,29 @@
 
 void sdram_initialize(void)
 {
-        print_debug("Ram1\r\n");
+        print_debug("Ram1\n");
 
         sdram_set_registers();
 
-        print_debug("Ram2\r\n");
+        print_debug("Ram2\n");
 
         sdram_set_spd_registers();
 
-        print_debug("Ram3\r\n");
+        print_debug("Ram3\n");
 
 
 
 
         sdram_enable();
 
-        print_debug("Ram4\r\n");
+        print_debug("Ram4\n");
         sdram_first_normal_reference();
 
-        print_debug("Ram5\r\n");
+        print_debug("Ram5\n");
         sdram_enable_refresh();
         sdram_special_finishup();
 
-        print_debug("Ram6\r\n");
+        print_debug("Ram6\n");
 }
 
 
@@ -1251,9 +1251,9 @@
         msr = rdmsr(0x1b);
         bsp = !!(msr.lo & (1 << 8));
         if (bsp) {
-                print_debug("Bootstrap processor\r\n");
+                print_debug("Bootstrap processor\n");
         } else {
-                print_debug("Application processor\r\n");
+                print_debug("Application processor\n");
         }
 
         return bsp;
@@ -1270,7 +1270,7 @@
 
         cpu_init = (htic & (1<<6));
         if (cpu_init) {
-                print_debug("CPU INIT Detected.\r\n");
+                print_debug("CPU INIT Detected.\n");
         }
         return cpu_init;
 }
@@ -1300,7 +1300,7 @@
                         continue;
                 }
                 print_debug_pci_dev(dev);
-                print_debug("\r\n");
+                print_debug("\n");
         }
 }
 
@@ -1309,7 +1309,7 @@
 {
         int i;
         print_debug_pci_dev(dev);
-        print_debug("\r\n");
+        print_debug("\n");
 
         for(i = 0; i <= 255; i++) {
                 unsigned char val;
@@ -1321,7 +1321,7 @@
                 print_debug_char(' ');
                 print_debug_hex8(val);
                 if ((i & 0x0f) == 0x0f) {
-                        print_debug("\r\n");
+                        print_debug("\n");
                 }
         }
 }
@@ -1330,7 +1330,7 @@
 {
         unsigned device;
         device = (0xa << 3);
-        print_debug("\r\n");
+        print_debug("\n");
         while(device <= ((0xa << 3) +1)) {
                 int i;
                 print_debug("dimm: ");
@@ -1339,13 +1339,13 @@
                         int status;
                         unsigned char byte;
                         if ((i & 0xf) == 0) {
-                                print_debug("\r\n");
+                                print_debug("\n");
                                 print_debug_hex8(i);
                                 print_debug(": ");
                         }
                         status = smbus_read_byte(device, i);
                         if (status < 0) {
-                                print_debug("bad device\r\n");
+                                print_debug("bad device\n");
                                 break;
                         }
                         byte = status & 0xff;
@@ -1353,7 +1353,7 @@
                         print_debug_char(' ');
                 }
                 device += 1;
-                print_debug("\r\n");
+                print_debug("\n");
         }
 }
 
@@ -1386,7 +1386,7 @@
                 print_debug("TOP_MEM: ");
                 print_debug_hex32(msr.hi);
                 print_debug_hex32(msr.lo);
-                print_debug("\r\n");
+                print_debug("\n");
                 ram_check(0x00000000, msr.lo);
         }
 }
Index: util/romcc/tests/raminit_test7.c
===================================================================
--- util/romcc/tests/raminit_test7.c	(revision 3942)
+++ util/romcc/tests/raminit_test7.c	(working copy)
@@ -386,12 +386,12 @@
 static void console_init(void)
 {
 	static const char console_test[] = 
-		"\r\n\r\nLinuxBIOS-"
+		"\n\nLinuxBIOS-"
 		"1.1.4"  
 		".0Fallback"  
 		" "
 		"Thu Oct 9 20:29:48 MDT 2003"  
-		" starting...\r\n";
+		" starting...\n";
 	print_info(console_test);
 }
 static void die(const char *str)
@@ -424,7 +424,7 @@
 	print_debug_hex32(start);
 	print_debug("-");
 	print_debug_hex32(stop);
-	print_debug("\r\n");
+	print_debug("\n");
 	for(addr = start; addr < stop ; addr += 4) {
 		 
 		if (!(addr & 0xffff)) {
@@ -435,7 +435,7 @@
 	};
 	 
 	print_debug_hex32(addr);
-	print_debug("\r\nDRAM filled\r\n");
+	print_debug("\nDRAM filled\n");
 }
 static void ram_verify(unsigned long start, unsigned long stop)
 {
@@ -445,7 +445,7 @@
 	print_debug_hex32(start);
 	print_debug_char('-');
 	print_debug_hex32(stop);
-	print_debug("\r\n");
+	print_debug("\n");
 	for(addr = start; addr < stop ; addr += 4) {
 		unsigned long value;
 		 
@@ -459,12 +459,12 @@
 			print_err_hex32(addr);
 			print_err_char(':');
 			print_err_hex32(value);
-			print_err("\r\n");
+			print_err("\n");
 		}
 	}
 	 
 	print_debug_hex32(addr);
-	print_debug("\r\nDRAM verified\r\n");
+	print_debug("\nDRAM verified\n");
 }
 void ram_check(unsigned long start, unsigned long stop)
 {
@@ -474,10 +474,10 @@
 	print_debug_hex32(start);
 	print_debug("-");	
 	print_debug_hex32(stop);
-	print_debug("\r\n");
+	print_debug("\n");
 	ram_fill(start, stop);
 	ram_verify(start, stop);
-	print_debug("Done.\r\n");
+	print_debug("Done.\n");
 }
 static int enumerate_ht_chain(unsigned link)
 {
@@ -529,10 +529,10 @@
 	device_t dev;
 	dev = pci_locate_device(((((  0x746b ) & 0xFFFF) << 16) | (( 0x1022 ) & 0xFFFF)) , 0);
 	if (dev == (0xffffffffU) ) {
-		die("SMBUS controller not found\r\n");
+		die("SMBUS controller not found\n");
 	}
 	uint8_t enable;
-	print_debug("SMBus controller enabled\r\n");
+	print_debug("SMBus controller enabled\n");
 	pci_write_config32(dev, 0x58, 0x0f00  | 1);
 	enable = pci_read_config8(dev, 0x41);
 	pci_write_config8(dev, 0x41, enable | (1 << 7));
@@ -748,14 +748,14 @@
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		print_debug("\r\n");
+		print_debug("\n");
 	}
 }
 static void dump_pci_device(unsigned dev)
 {
 	int i;
 	print_debug_pci_dev(dev);
-	print_debug("\r\n");
+	print_debug("\n");
 	
 	for(i = 0; i <= 255; i++) {
 		unsigned char val;
@@ -767,7 +767,7 @@
 		print_debug_char(' ');
 		print_debug_hex8(val);
 		if ((i & 0x0f) == 0x0f) {
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -790,7 +790,7 @@
 static void dump_spd_registers(const struct mem_controller *ctrl)
 {
 	int i;
-	print_debug("\r\n");
+	print_debug("\n");
 	for(i = 0; i < 4; i++) {
 		unsigned device;
 		device = ctrl->channel0[i];
@@ -804,20 +804,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 		device = ctrl->channel1[i];
 		if (device) {
@@ -830,20 +830,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -898,7 +898,7 @@
 		{ 0x00010404, 0x00050101 }
 	};
 	if(maxnodes>2) {
-		print_debug("this mainboard is only designed for 2 cpus\r\n");
+		print_debug("this mainboard is only designed for 2 cpus\n");
 		maxnodes=2;
 	}
 	if (!(node>=maxnodes || row>=maxnodes)) {
@@ -940,7 +940,7 @@
 static void setup_resource_map(const unsigned int *register_values, int max)
 {
 	int i;
-	print_debug("setting up resource map....\r\n");
+	print_debug("setting up resource map....\n");
 	for(i = 0; i < max; i += 3) {
 		device_t dev;
 		unsigned where;
@@ -952,7 +952,7 @@
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-	print_debug("done.\r\n");
+	print_debug("done.\n");
 }
 static void setup_default_resource_map(void)
 {
@@ -1089,7 +1089,7 @@
 	int max;
 	print_debug("setting up CPU");
 	print_debug_hex8(ctrl->node_id);
-	print_debug(" northbridge registers\r\n");
+	print_debug(" northbridge registers\n");
 	max = sizeof(register_values)/sizeof(register_values[0]);
 	for(i = 0; i < max; i += 3) {
 		device_t dev;
@@ -1102,7 +1102,7 @@
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-	print_debug("done.\r\n");
+	print_debug("done.\n");
 }
 static int is_dual_channel(const struct mem_controller *ctrl)
 {
@@ -1263,7 +1263,7 @@
 	 
 	print_debug("RAM: 0x");
 	print_debug_hex32(tom_k);
-	print_debug(" KB\r\n");
+	print_debug(" KB\n");
 	 
 	msr_t msr;
 	msr.lo = (tom_k & 0x003fffff) << 10;
@@ -1326,7 +1326,7 @@
 	}
 	 
 	if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
-		print_debug("8 4GB chip selects cannot be interleaved\r\n");
+		print_debug("8 4GB chip selects cannot be interleaved\n");
 		return 0;
 	}
 	 
@@ -1351,7 +1351,7 @@
 		csbase += csbase_inc;
 	}
 	
-	print_debug("Interleaved\r\n");
+	print_debug("Interleaved\n");
 	 
 	return common_size << (15 + bits);
 }
@@ -1442,7 +1442,7 @@
 {
 	print_debug("disabling dimm"); 
 	print_debug_hex8(index); 
-	print_debug("\r\n");
+	print_debug("\n");
 	pci_write_config32(ctrl->f2, 0x40  + (((index << 1)+0)<<2), 0);
 	pci_write_config32(ctrl->f2, 0x40  + (((index << 1)+1)<<2), 0);
 }
@@ -1539,7 +1539,7 @@
 			}
 		}
 	}
-	print_debug("Enabling dual channel memory\r\n");
+	print_debug("Enabling dual channel memory\n");
 	uint32_t dcl;
 	dcl = pci_read_config32(ctrl->f2, 0x90 );
 	dcl &= ~(1<<19) ;
@@ -1560,7 +1560,7 @@
 {
 	static const struct mem_param speed[] = {
 		{
-			.name	    = "100Mhz\r\n",
+			.name	    = "100Mhz\n",
 			.cycle_time = 0xa0,
 			.divisor    = (10 <<1),
 			.tRC	    = 0x46,
@@ -1571,7 +1571,7 @@
 			.dtl_twr    = 2,
 		},
 		{
-			.name	    = "133Mhz\r\n",
+			.name	    = "133Mhz\n",
 			.cycle_time = 0x75,
 			.divisor    = (7<<1)+1,
 			.tRC	    = 0x41,
@@ -1582,7 +1582,7 @@
 			.dtl_twr    = 2,
 		},
 		{
-			.name	    = "166Mhz\r\n",
+			.name	    = "166Mhz\n",
 			.cycle_time = 0x60,
 			.divisor    = (6<<1),
 			.tRC	    = 0x3C,
@@ -1593,7 +1593,7 @@
 			.dtl_twr    = 3,
 		},
 		{
-			.name	    = "200Mhz\r\n",
+			.name	    = "200Mhz\n",
 			.cycle_time = 0x50,
 			.divisor    = (5<<1),
 			.tRC	    = 0x37,
@@ -2258,7 +2258,7 @@
 		dcl = pci_read_config32(ctrl[i].f2, 0x90 );
 		if (dcl & (1<<17) ) {
 			uint32_t mnc;
-			print_debug("ECC enabled\r\n");
+			print_debug("ECC enabled\n");
 			mnc = pci_read_config32(ctrl[i].f3, 0x44 );
 			mnc |= (1 << 22) ;
 			if (dcl & (1<<16) ) {
@@ -2287,9 +2287,9 @@
 			}
 		} while(((dcl & (1<<8) ) != 0) && (loops < 300000 ));
 		if (loops >= 300000 ) {
-			print_debug(" failed\r\n");
+			print_debug(" failed\n");
 		} else {
-			print_debug(" done\r\n");
+			print_debug(" done\n");
 		}
 		if (dcl & (1<<17) ) {
 			print_debug("Clearing memory: ");
@@ -2317,7 +2317,7 @@
 			print_debug_hex32(zstart);
 			print_debug("-");
 			print_debug_hex32(zend);
-			print_debug("\r\n");
+			print_debug("\n");
 			
 			 
 			msr = rdmsr(0x2ff );
@@ -2415,7 +2415,7 @@
 			 
 			pci_write_config32(ctrl[i].f3, 0x58 , 
 				(22  << 16) | (22  << 8) | (22  << 0));
-			print_debug("done\r\n");
+			print_debug("done\n");
 		}
 	}
 }
@@ -2436,7 +2436,7 @@
 	val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 0  ) & 0x1f) << 11) | ((( 0 )  & 0x7) << 8))  , 0x68);
 	val |= (1<<10)|(1<<9)|(1<<8)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|(1 << 0);
 	pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 0  ) & 0x1f) << 11) | ((( 0 )  & 0x7) << 8))  , 0x68, val);
-	print_debug("done.\r\n");
+	print_debug("done.\n");
 }
  
 static void wait_ap_stop(u8 node) 
@@ -2483,7 +2483,7 @@
 		wait_ap_stop(node);
 	}
  
-	print_debug(" done.\r\n");
+	print_debug(" done.\n");
 }
 static void rename_temp_node(u8 node)
 {
@@ -2494,7 +2494,7 @@
 	val &= (~7);   
         val |= node;    
 	pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 7  ) & 0x1f) << 11) | ((( 0 )  & 0x7) << 8))  , 0x60, val);
-	print_debug(" done.\r\n");
+	print_debug(" done.\n");
 }
 static bool check_connection(u8 src, u8 dest, u8 link)
 {
@@ -2587,7 +2587,7 @@
 	};
 	uint8_t row;
 	int i;
-	print_debug("setup_remote_node\r\n");
+	print_debug("setup_remote_node\n");
 	for(row=0; row<cpus; row++)
 		setup_remote_row(node, row, cpus);
 	 
@@ -2598,24 +2598,24 @@
 		value = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 0  ) & 0x1f) << 11) | ((( 1 )  & 0x7) << 8))  , reg);
 		pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 7  ) & 0x1f) << 11) | ((( 1 )  & 0x7) << 8))  , reg, value);
 	}
-	print_debug("setup_remote_done\r\n");
+	print_debug("setup_remote_done\n");
 }
 static u8 setup_uniprocessor(void)
 {
-	print_debug("Enabling UP settings\r\n");
+	print_debug("Enabling UP settings\n");
 	disable_probes();
 	return 1;
 }
 static u8 setup_smp(void)
 {
 	u8 cpus=2;
-	print_debug("Enabling SMP settings\r\n");
+	print_debug("Enabling SMP settings\n");
 	setup_row(0,0,cpus);
 	 
 	setup_temp_row(0,1,cpus);
 	
 	if (!check_connection(0, 7, 0x20  )) {
-		print_debug("No connection to Node 1.\r\n");
+		print_debug("No connection to Node 1.\n");
 		fill_row( 0 ,7,0x00010101 ) ;	 
 		setup_uniprocessor();	 
 		return 1;
@@ -2630,7 +2630,7 @@
 	fill_row( 0 ,7,0x00010101 ) ;	 
 	
 	print_debug_hex32(cpus);
-	print_debug(" nodes initialized.\r\n");
+	print_debug(" nodes initialized.\n");
 	return cpus;
 }
 static unsigned detect_mp_capabilities(unsigned cpus)
@@ -2639,7 +2639,7 @@
 	bool mp_cap= (-1) ;
 	print_debug("detect_mp_capabilities: ");
 	print_debug_hex32(cpus);
-	print_debug("\r\n");
+	print_debug("\n");
 	if (cpus>2)
 		mask=0x06;	 
 	else
@@ -2651,7 +2651,7 @@
 	if (mp_cap)
 		return cpus;
 	 
-	print_debug("One of the CPUs is not MP capable. Going back to UP\r\n");
+	print_debug("One of the CPUs is not MP capable. Going back to UP\n");
 	for (node=cpus; node>0; node--)
 	    for (row=cpus; row>0; row--)
 		fill_row(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node-1  ) & 0x1f) << 11) | ((( 0 )  & 0x7) << 8))  , row-1, 0x00010101 );
@@ -2664,7 +2664,7 @@
 	bool rev_a0;
 	
 	 
-	print_debug("coherent_ht_finalize\r\n");
+	print_debug("coherent_ht_finalize\n");
 	rev_a0= is_cpu_rev_a0();
 	for (node=0; node<cpus; node++) {
 		u32 val;
@@ -2681,7 +2681,7 @@
 			pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node  ) & 0x1f) << 11) | ((( 0 )  & 0x7) << 8))  ,0xd4,0);
 		}
 	}
-	print_debug("done\r\n");
+	print_debug("done\n");
 }
 static int setup_coherent_ht_domain(void)
 {
@@ -2697,7 +2697,7 @@
 }
 void sdram_no_memory(void)
 {
-	print_err("No memory!!\r\n");
+	print_err("No memory!!\n");
 	while(1) { 
 		hlt(); 
 	}
@@ -2710,20 +2710,20 @@
 	for(i = 0; i < controllers; i++) {
 		print_debug("Ram1.");
 		print_debug_hex8(i);
-		print_debug("\r\n");
+		print_debug("\n");
 		sdram_set_registers(ctrl + i);
 	}
 	 
 	for(i = 0; i < controllers; i++) {
 		print_debug("Ram2.");
 		print_debug_hex8(i);
-		print_debug("\r\n");
+		print_debug("\n");
 		sdram_set_spd_registers(ctrl + i);
 	}
 	 
-	print_debug("Ram3\r\n");
+	print_debug("Ram3\n");
 	sdram_enable(controllers, ctrl);
-	print_debug("Ram4\r\n");
+	print_debug("Ram4\n");
 }
 static void enable_lapic(void)
 {
Index: util/romcc/tests/simple_test22.c
===================================================================
--- util/romcc/tests/simple_test22.c	(revision 3942)
+++ util/romcc/tests/simple_test22.c	(working copy)
@@ -300,7 +300,7 @@
 
 static void main(void)
 {
-	static const char msg[] = "hello world\r\n";
+	static const char msg[] = "hello world\n";
 	write(STDOUT_FILENO, msg, sizeof(msg));
 	_exit(0);
 }
Index: util/romcc/tests/simple_test60.c
===================================================================
--- util/romcc/tests/simple_test60.c	(revision 3942)
+++ util/romcc/tests/simple_test60.c	(working copy)
@@ -12,7 +12,7 @@
 static void test(void)
 {
 	static const struct mem_param param0 = {
-		.name = "166Mhz\r\n",
+		.name = "166Mhz\n",
 		.cycle_time = 0x60,
 		.divisor = (6<<1),
 		.tRC = 0x3C,
Index: util/romcc/tests/linux_test1.c
===================================================================
--- util/romcc/tests/linux_test1.c	(revision 3942)
+++ util/romcc/tests/linux_test1.c	(working copy)
@@ -2,7 +2,7 @@
 
 static void main(void)
 {
-	static const char msg[] = "hello world\r\n";
+	static const char msg[] = "hello world\n";
 	write(STDOUT_FILENO, msg, sizeof(msg));
 	_exit(0);
 }
Index: util/romcc/tests/linux_test5.c
===================================================================
--- util/romcc/tests/linux_test5.c	(revision 3942)
+++ util/romcc/tests/linux_test5.c	(working copy)
@@ -93,7 +93,7 @@
 {
 	print_debug("disabling dimm"); 
 	print_debug_hex8(index); 
-	print_debug("\r\n");
+	print_debug("\n");
 #if 0
 	pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CSBASE + (((index << 1)+0)<<2), 0);
 	pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CSBASE + (((index << 1)+1)<<2), 0);
@@ -179,7 +179,7 @@
 	print_debug_hex8(min_cycle_time); 
 	print_debug(" min_latency: ");
 	print_debug_hex8(min_latency);
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 
 	/* Compute the least latency with the fastest clock supported
@@ -240,7 +240,7 @@
 				print_debug_hex8(new_cycle_time); 
 				print_debug(" new_latency: ");
 				print_debug_hex8(new_latency);
-				print_debug("\r\n");
+				print_debug("\n");
 #endif
 			}
 			debug('G');
@@ -253,7 +253,7 @@
 		print_debug_hex8(new_cycle_time); 
 		print_debug(" new_latency: ");
 		print_debug_hex8(new_latency);
-		print_debug("\r\n");
+		print_debug("\n");
 #endif
 		if (new_latency > 4){
 			continue;
@@ -274,7 +274,7 @@
 		print_debug_hex8(min_cycle_time); 
 		print_debug(" min_latency: ");
 		print_debug_hex8(min_latency);
-		print_debug("\r\n");
+		print_debug("\n");
 #endif
 	}
 	/* Make a second pass through the dimms and disable
@@ -328,7 +328,7 @@
 	print_debug_hex8(min_cycle_time); 
 	print_debug(" min_latency: ");
 	print_debug_hex8(min_latency);
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 	/* Now that I know the minimum cycle time lookup the memory parameters */
 	param = get_mem_param(min_cycle_time);
Index: util/romcc/tests/hello_world1.c
===================================================================
--- util/romcc/tests/hello_world1.c	(revision 3942)
+++ util/romcc/tests/hello_world1.c	(working copy)
@@ -113,14 +113,14 @@
 
 void main(void)
 {
-	static const char msg[] = "hello world\r\n";
+	static const char msg[] = "hello world\n";
 	uart_init();
 #if 0
 	print_debug(msg);
 #endif
 #if 1
-	print_debug("hello world\r\n");
-	print_debug("how are you today\r\n");
+	print_debug("hello world\n");
+	print_debug("how are you today\n");
 #endif
 	while(1) {
 		;
Index: util/romcc/tests/simple_test54.c
===================================================================
--- util/romcc/tests/simple_test54.c	(revision 3942)
+++ util/romcc/tests/simple_test54.c	(working copy)
@@ -505,7 +505,7 @@
 {
 	print_debug("disabling dimm"); 
 	print_debug_hex8(index); 
-	print_debug("\r\n");
+	print_debug("\n");
 #if 0
 	pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CSBASE + (((index << 1)+0)<<2), 0);
 	pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CSBASE + (((index << 1)+1)<<2), 0);
@@ -591,7 +591,7 @@
 	print_debug_hex8(min_cycle_time); 
 	print_debug(" min_latency: ");
 	print_debug_hex8(min_latency);
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 
 	/* Compute the least latency with the fastest clock supported
@@ -652,7 +652,7 @@
 				print_debug_hex8(new_cycle_time); 
 				print_debug(" new_latency: ");
 				print_debug_hex8(new_latency);
-				print_debug("\r\n");
+				print_debug("\n");
 #endif
 			}
 			debug('G');
@@ -665,7 +665,7 @@
 		print_debug_hex8(new_cycle_time); 
 		print_debug(" new_latency: ");
 		print_debug_hex8(new_latency);
-		print_debug("\r\n");
+		print_debug("\n");
 #endif
 		if (new_latency > 4){
 			continue;
@@ -686,7 +686,7 @@
 		print_debug_hex8(min_cycle_time); 
 		print_debug(" min_latency: ");
 		print_debug_hex8(min_latency);
-		print_debug("\r\n");
+		print_debug("\n");
 #endif
 	}
 	/* Make a second pass through the dimms and disable
@@ -740,7 +740,7 @@
 	print_debug_hex8(min_cycle_time); 
 	print_debug(" min_latency: ");
 	print_debug_hex8(min_latency);
-	print_debug("\r\n");
+	print_debug("\n");
 #endif
 	/* Now that I know the minimum cycle time lookup the memory parameters */
 	param = get_mem_param(min_cycle_time);
Index: util/romcc/tests/simple_test58.c
===================================================================
--- util/romcc/tests/simple_test58.c	(revision 3942)
+++ util/romcc/tests/simple_test58.c	(working copy)
@@ -2,7 +2,7 @@
 {
 	const char *str;
 	unsigned char ch;
-	str = "one\r\n";
+	str = "one\n";
 	while((ch = *str++) != '\0') {
 		__builtin_outb(ch, 0x3f0);
 	}
Index: util/romcc/tests/simple_test9.c
===================================================================
--- util/romcc/tests/simple_test9.c	(revision 3942)
+++ util/romcc/tests/simple_test9.c	(working copy)
@@ -2,7 +2,7 @@
 
 void main(void)
 {
-	static const char msg[] = "hello world\r\n";
+	static const char msg[] = "hello world\n";
 	char *str;
 	char ch;
 	str = msg;
Index: util/romcc/tests/raminit_test4.c
===================================================================
--- util/romcc/tests/raminit_test4.c	(revision 3942)
+++ util/romcc/tests/raminit_test4.c	(working copy)
@@ -345,12 +345,12 @@
 static void console_init(void)
 {
         static const char console_test[] =
-                "\r\n\r\nLinuxBIOS-"
+                "\n\nLinuxBIOS-"
                 "1.1.0"
                 ".0Fallback"
                 " "
                 "Fri Jun 13 21:02:41 MDT 2003"
-                " starting...\r\n";
+                " starting...\n";
         print_info(console_test);
 }
 
@@ -388,7 +388,7 @@
         print_debug_hex32(start);
         print_debug("-");
         print_debug_hex32(stop);
-        print_debug("\r\n");
+        print_debug("\n");
         for(addr = start; addr < stop ; addr += 4) {
 
                 if ((addr & 0xffff) == 0) {
@@ -399,7 +399,7 @@
         };
 
         print_debug_hex32(addr);
-        print_debug("\r\nDRAM filled\r\n");
+        print_debug("\nDRAM filled\n");
 }
 
 void ram_verify(unsigned long start, unsigned long stop)
@@ -412,7 +412,7 @@
         print_debug_hex32(start);
         print_debug_char('-');
         print_debug_hex32(stop);
-        print_debug("\r\n");
+        print_debug("\n");
         for(addr = start; addr < stop ; addr += 4) {
                 unsigned long value;
 
@@ -426,12 +426,12 @@
                         print_err_hex32(addr);
                         print_err_char(':');
                         print_err_hex32(value);
-                        print_err("\r\n");
+                        print_err("\n");
                 }
         }
 
         print_debug_hex32(addr);
-        print_debug("\r\nDRAM verified\r\n");
+        print_debug("\nDRAM verified\n");
 }
 
 
@@ -447,7 +447,7 @@
         print_debug_hex32(start);
         print_debug("-");
         print_debug_hex32(stop);
-        print_debug("\r\n");
+        print_debug("\n");
         ram_fill(start, stop);
         ram_verify(start, stop);
         print_debug("Done.\n");
@@ -511,10 +511,10 @@
         device_t dev;
         dev = pci_locate_device(((((0x746b) & 0xFFFF) << 16) | ((0x1022) & 0xFFFF)), 0);
         if (dev == (0xffffffffU)) {
-                die("SMBUS controller not found\r\n");
+                die("SMBUS controller not found\n");
         }
         uint8_t enable;
-        print_debug("SMBus controller enabled\r\n");
+        print_debug("SMBus controller enabled\n");
         pci_write_config32(dev, 0x58, 0x1000 | 1);
         enable = pci_read_config8(dev, 0x41);
         pci_write_config8(dev, 0x41, enable | (1 << 7));
@@ -609,7 +609,7 @@
 static void setup_resource_map(const unsigned int *register_values, int max)
 {
         int i;
-        print_debug("setting up resource map....\r\n");
+        print_debug("setting up resource map....\n");
         for(i = 0; i < max; i += 3) {
                 device_t dev;
                 unsigned where;
@@ -633,7 +633,7 @@
 
 
         }
-        print_debug("done.\r\n");
+        print_debug("done.\n");
 }
 
 static void setup_default_resource_map(void)
@@ -805,7 +805,7 @@
         };
         int i;
         int max;
-        print_debug("setting up CPU0 northbridge registers\r\n");
+        print_debug("setting up CPU0 northbridge registers\n");
         max = sizeof(register_values)/sizeof(register_values[0]);
         for(i = 0; i < max; i += 3) {
                 device_t dev;
@@ -831,7 +831,7 @@
 
 
         }
-        print_debug("done.\r\n");
+        print_debug("done.\n");
 }
 # 1132 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c"
 static void sdram_set_spd_registers(void)
@@ -852,7 +852,7 @@
         dcl = pci_read_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x90);
         print_debug("dcl: ");
         print_debug_hex32(dcl);
-        print_debug("\r\n");
+        print_debug("\n");
         dcl |= (1<<3);
         pci_write_config32(( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((2) & 0x7) << 8)), 0x90, dcl);
         dcl &= ~(1<<3);
@@ -872,9 +872,9 @@
                 }
         } while(((dcl & (1<<8)) != 0) && (loops < 300000));
         if (loops >= 300000) {
-                print_debug(" failed\r\n");
+                print_debug(" failed\n");
         } else {
-                print_debug(" done\r\n");
+                print_debug(" done\n");
         }
 # 1192 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/northbridge/amd/amdk8/raminit.c"
 }
@@ -915,7 +915,7 @@
         };
         int i;
         int max;
-        print_debug("setting up coherent ht domain....\r\n");
+        print_debug("setting up coherent ht domain....\n");
         max = sizeof(register_values)/sizeof(register_values[0]);
         for(i = 0; i < max; i += 3) {
                 device_t dev;
@@ -940,13 +940,13 @@
 
 
         }
-        print_debug("done.\r\n");
+        print_debug("done.\n");
 }
 # 12 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/mainboard/arima/hdama/auto.c" 2
 # 1 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/sdram/generic_sdram.c" 1
 void sdram_no_memory(void)
 {
-        print_err("No memory!!\r\n");
+        print_err("No memory!!\n");
         while(1) {
                 hlt();
         }
@@ -955,29 +955,29 @@
 
 void sdram_initialize(void)
 {
-        print_debug("Ram1\r\n");
+        print_debug("Ram1\n");
 
         sdram_set_registers();
 
-        print_debug("Ram2\r\n");
+        print_debug("Ram2\n");
 
         sdram_set_spd_registers();
 
-        print_debug("Ram3\r\n");
+        print_debug("Ram3\n");
 
 
 
 
         sdram_enable();
 
-        print_debug("Ram4\r\n");
+        print_debug("Ram4\n");
         sdram_first_normal_reference();
 
-        print_debug("Ram5\r\n");
+        print_debug("Ram5\n");
         sdram_enable_refresh();
         sdram_special_finishup();
 
-        print_debug("Ram6\r\n");
+        print_debug("Ram6\n");
 }
 # 13 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/mainboard/arima/hdama/auto.c" 2
 
@@ -990,7 +990,7 @@
         msr = rdmsr(0x1b);
         bsp = !!(msr.lo & (1 << 8));
         if (bsp) {
-                print_debug("Bootstrap cpu\r\n");
+                print_debug("Bootstrap cpu\n");
         }
 
         return bsp;
@@ -1007,7 +1007,7 @@
 # 52 "/home/eric/projects/linuxbios/checkin/hdama/freebios2/src/mainboard/arima/hdama/auto.c"
         cpu_init = (htic & (1<<6));
         if (cpu_init) {
-                print_debug("CPU INIT Detected.\r\n");
+                print_debug("CPU INIT Detected.\n");
         }
         return cpu_init;
 }
@@ -1030,7 +1030,7 @@
                 print_debug_hex8(dev >> 11);
                 print_debug_char('.');
                 print_debug_hex8((dev >> 8) & 7);
-                print_debug("\r\n");
+                print_debug("\n");
         }
 }
 
@@ -1039,7 +1039,7 @@
 {
         unsigned device;
         device = (0xa << 3);
-        print_debug("\r\n");
+        print_debug("\n");
         while(device <= ((0xa << 3) +7)) {
                 int i;
                 print_debug("dimm: ");
@@ -1048,13 +1048,13 @@
                         int status;
                         unsigned char byte;
                         if ((i & 0xf) == 0) {
-                                print_debug("\r\n");
+                                print_debug("\n");
                                 print_debug_hex8(i);
                                 print_debug(": ");
                         }
                         status = smbus_read_byte(device, i);
                         if (status < 0) {
-                                print_debug("bad device\r\n");
+                                print_debug("bad device\n");
                                 break;
                         }
                         byte = status & 0xff;
@@ -1062,7 +1062,7 @@
                         print_debug_char(' ');
                 }
                 device += 1;
-                print_debug("\r\n");
+                print_debug("\n");
         }
 }
 
Index: util/romcc/tests/raminit_test6.c
===================================================================
--- util/romcc/tests/raminit_test6.c	(revision 3942)
+++ util/romcc/tests/raminit_test6.c	(working copy)
@@ -381,12 +381,12 @@
 static void console_init(void)
 {
 	static const char console_test[] = 
-		"\r\n\r\nLinuxBIOS-"
+		"\n\nLinuxBIOS-"
 		"1.1.4"  
 		".0Fallback"  
 		" "
 		"Thu Oct 9 20:29:48 MDT 2003"  
-		" starting...\r\n";
+		" starting...\n";
 	print_info(console_test);
 }
 static void die(const char *str)
@@ -419,7 +419,7 @@
 	print_debug_hex32(start);
 	print_debug("-");
 	print_debug_hex32(stop);
-	print_debug("\r\n");
+	print_debug("\n");
 	for(addr = start; addr < stop ; addr += 4) {
 		 
 		if (!(addr & 0xffff)) {
@@ -430,7 +430,7 @@
 	};
 	 
 	print_debug_hex32(addr);
-	print_debug("\r\nDRAM filled\r\n");
+	print_debug("\nDRAM filled\n");
 }
 static void ram_verify(unsigned long start, unsigned long stop)
 {
@@ -440,7 +440,7 @@
 	print_debug_hex32(start);
 	print_debug_char('-');
 	print_debug_hex32(stop);
-	print_debug("\r\n");
+	print_debug("\n");
 	for(addr = start; addr < stop ; addr += 4) {
 		unsigned long value;
 		 
@@ -454,12 +454,12 @@
 			print_err_hex32(addr);
 			print_err_char(':');
 			print_err_hex32(value);
-			print_err("\r\n");
+			print_err("\n");
 		}
 	}
 	 
 	print_debug_hex32(addr);
-	print_debug("\r\nDRAM verified\r\n");
+	print_debug("\nDRAM verified\n");
 }
 void ram_check(unsigned long start, unsigned long stop)
 {
@@ -469,10 +469,10 @@
 	print_debug_hex32(start);
 	print_debug("-");	
 	print_debug_hex32(stop);
-	print_debug("\r\n");
+	print_debug("\n");
 	ram_fill(start, stop);
 	ram_verify(start, stop);
-	print_debug("Done.\r\n");
+	print_debug("Done.\n");
 }
 static int enumerate_ht_chain(unsigned link)
 {
@@ -524,10 +524,10 @@
 	device_t dev;
 	dev = pci_locate_device(((((  0x746b ) & 0xFFFF) << 16) | (( 0x1022 ) & 0xFFFF)) , 0);
 	if (dev == (0xffffffffU) ) {
-		die("SMBUS controller not found\r\n");
+		die("SMBUS controller not found\n");
 	}
 	uint8_t enable;
-	print_debug("SMBus controller enabled\r\n");
+	print_debug("SMBus controller enabled\n");
 	pci_write_config32(dev, 0x58, 0x0f00  | 1);
 	enable = pci_read_config8(dev, 0x41);
 	pci_write_config8(dev, 0x41, enable | (1 << 7));
@@ -743,14 +743,14 @@
 			continue;
 		}
 		print_debug_pci_dev(dev);
-		print_debug("\r\n");
+		print_debug("\n");
 	}
 }
 static void dump_pci_device(unsigned dev)
 {
 	int i;
 	print_debug_pci_dev(dev);
-	print_debug("\r\n");
+	print_debug("\n");
 	
 	for(i = 0; i <= 255; i++) {
 		unsigned char val;
@@ -762,7 +762,7 @@
 		print_debug_char(' ');
 		print_debug_hex8(val);
 		if ((i & 0x0f) == 0x0f) {
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -785,7 +785,7 @@
 static void dump_spd_registers(const struct mem_controller *ctrl)
 {
 	int i;
-	print_debug("\r\n");
+	print_debug("\n");
 	for(i = 0; i < 4; i++) {
 		unsigned device;
 		device = ctrl->channel0[i];
@@ -799,20 +799,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 		device = ctrl->channel1[i];
 		if (device) {
@@ -825,20 +825,20 @@
 				int status;
 				unsigned char byte;
 				if ((j & 0xf) == 0) {
-					print_debug("\r\n");
+					print_debug("\n");
 					print_debug_hex8(j);
 					print_debug(": ");
 				}
 				status = smbus_read_byte(device, j);
 				if (status < 0) {
-					print_debug("bad device\r\n");
+					print_debug("bad device\n");
 					break;
 				}
 				byte = status & 0xff;
 				print_debug_hex8(byte);
 				print_debug_char(' ');
 			}
-			print_debug("\r\n");
+			print_debug("\n");
 		}
 	}
 }
@@ -893,7 +893,7 @@
 		{ 0x00010404, 0x00050101 }
 	};
 	if(maxnodes>2) {
-		print_debug("this mainboard is only designed for 2 cpus\r\n");
+		print_debug("this mainboard is only designed for 2 cpus\n");
 		maxnodes=2;
 	}
 	if (!(node>=maxnodes || row>=maxnodes)) {
@@ -935,7 +935,7 @@
 static void setup_resource_map(const unsigned int *register_values, int max)
 {
 	int i;
-	print_debug("setting up resource map....\r\n");
+	print_debug("setting up resource map....\n");
 	for(i = 0; i < max; i += 3) {
 		device_t dev;
 		unsigned where;
@@ -947,7 +947,7 @@
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-	print_debug("done.\r\n");
+	print_debug("done.\n");
 }
 static void setup_default_resource_map(void)
 {
@@ -1084,7 +1084,7 @@
 	int max;
 	print_debug("setting up CPU");
 	print_debug_hex8(ctrl->node_id);
-	print_debug(" northbridge registers\r\n");
+	print_debug(" northbridge registers\n");
 	max = sizeof(register_values)/sizeof(register_values[0]);
 	for(i = 0; i < max; i += 3) {
 		device_t dev;
@@ -1097,7 +1097,7 @@
 		reg |= register_values[i+2];
 		pci_write_config32(dev, where, reg);
 	}
-	print_debug("done.\r\n");
+	print_debug("done.\n");
 }
 static int is_dual_channel(const struct mem_controller *ctrl)
 {
@@ -1258,7 +1258,7 @@
 	 
 	print_debug("RAM: 0x");
 	print_debug_hex32(tom_k);
-	print_debug(" KB\r\n");
+	print_debug(" KB\n");
 	 
 	msr_t msr;
 	msr.lo = (tom_k & 0x003fffff) << 10;
@@ -1321,7 +1321,7 @@
 	}
 	 
 	if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
-		print_debug("8 4GB chip selects cannot be interleaved\r\n");
+		print_debug("8 4GB chip selects cannot be interleaved\n");
 		return 0;
 	}
 	 
@@ -1346,7 +1346,7 @@
 		csbase += csbase_inc;
 	}
 	
-	print_debug("Interleaved\r\n");
+	print_debug("Interleaved\n");
 	 
 	return common_size << (15 + bits);
 }
@@ -1437,7 +1437,7 @@
 {
 	print_debug("disabling dimm"); 
 	print_debug_hex8(index); 
-	print_debug("\r\n");
+	print_debug("\n");
 	pci_write_config32(ctrl->f2, 0x40  + (((index << 1)+0)<<2), 0);
 	pci_write_config32(ctrl->f2, 0x40  + (((index << 1)+1)<<2), 0);
 }
@@ -1534,7 +1534,7 @@
 			}
 		}
 	}
-	print_debug("Enabling dual channel memory\r\n");
+	print_debug("Enabling dual channel memory\n");
 	uint32_t dcl;
 	dcl = pci_read_config32(ctrl->f2, 0x90 );
 	dcl &= ~(1<<19) ;
@@ -1555,7 +1555,7 @@
 {
 	static const struct mem_param speed[] = {
 		{
-			.name	    = "100Mhz\r\n",
+			.name	    = "100Mhz\n",
 			.cycle_time = 0xa0,
 			.divisor    = (10 <<1),
 			.tRC	    = 0x46,
@@ -1566,7 +1566,7 @@
 			.dtl_twr    = 2,
 		},
 		{
-			.name	    = "133Mhz\r\n",
+			.name	    = "133Mhz\n",
 			.cycle_time = 0x75,
 			.divisor    = (7<<1)+1,
 			.tRC	    = 0x41,
@@ -1577,7 +1577,7 @@
 			.dtl_twr    = 2,
 		},
 		{
-			.name	    = "166Mhz\r\n",
+			.name	    = "166Mhz\n",
 			.cycle_time = 0x60,
 			.divisor    = (6<<1),
 			.tRC	    = 0x3C,
@@ -1588,7 +1588,7 @@
 			.dtl_twr    = 3,
 		},
 		{
-			.name	    = "200Mhz\r\n",
+			.name	    = "200Mhz\n",
 			.cycle_time = 0x50,
 			.divisor    = (5<<1),
 			.tRC	    = 0x37,
@@ -2253,7 +2253,7 @@
 		dcl = pci_read_config32(ctrl[i].f2, 0x90 );
 		if (dcl & (1<<17) ) {
 			uint32_t mnc;
-			print_debug("ECC enabled\r\n");
+			print_debug("ECC enabled\n");
 			mnc = pci_read_config32(ctrl[i].f3, 0x44 );
 			mnc |= (1 << 22) ;
 			if (dcl & (1<<16) ) {
@@ -2282,9 +2282,9 @@
 			}
 		} while(((dcl & (1<<8) ) != 0) && (loops < 300000 ));
 		if (loops >= 300000 ) {
-			print_debug(" failed\r\n");
+			print_debug(" failed\n");
 		} else {
-			print_debug(" done\r\n");
+			print_debug(" done\n");
 		}
 		if (dcl & (1<<17) ) {
 			print_debug("Clearing memory: ");
@@ -2312,7 +2312,7 @@
 			print_debug_hex32(zstart);
 			print_debug("-");
 			print_debug_hex32(zend);
-			print_debug("\r\n");
+			print_debug("\n");
 			
 			 
 			msr = rdmsr(0x2ff );
@@ -2410,7 +2410,7 @@
 			 
 			pci_write_config32(ctrl[i].f3, 0x58 , 
 				(22  << 16) | (22  << 8) | (22  << 0));
-			print_debug("done\r\n");
+			print_debug("done\n");
 		}
 	}
 }
@@ -2431,7 +2431,7 @@
 	val=pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 0  ) & 0x1f) << 11) | ((( 0 )  & 0x7) << 8))  , 0x68);
 	val |= (1<<10)|(1<<9)|(1<<8)|(1<<4)|(1<<3)|(1<<2)|(1<<1)|(1 << 0);
 	pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 0  ) & 0x1f) << 11) | ((( 0 )  & 0x7) << 8))  , 0x68, val);
-	print_debug("done.\r\n");
+	print_debug("done.\n");
 }
  
 static void wait_ap_stop(u8 node) 
@@ -2478,7 +2478,7 @@
 		wait_ap_stop(node);
 	}
  
-	print_debug(" done.\r\n");
+	print_debug(" done.\n");
 }
 static void rename_temp_node(u8 node)
 {
@@ -2489,7 +2489,7 @@
 	val &= (~7);   
         val |= node;    
 	pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 7  ) & 0x1f) << 11) | ((( 0 )  & 0x7) << 8))  , 0x60, val);
-	print_debug(" done.\r\n");
+	print_debug(" done.\n");
 }
 static bool check_connection(u8 src, u8 dest, u8 link)
 {
@@ -2582,7 +2582,7 @@
 	};
 	uint8_t row;
 	int i;
-	print_debug("setup_remote_node\r\n");
+	print_debug("setup_remote_node\n");
 	for(row=0; row<cpus; row++)
 		setup_remote_row(node, row, cpus);
 	 
@@ -2593,24 +2593,24 @@
 		value = pci_read_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 0  ) & 0x1f) << 11) | ((( 1 )  & 0x7) << 8))  , reg);
 		pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ 7  ) & 0x1f) << 11) | ((( 1 )  & 0x7) << 8))  , reg, value);
 	}
-	print_debug("setup_remote_done\r\n");
+	print_debug("setup_remote_done\n");
 }
 static u8 setup_uniprocessor(void)
 {
-	print_debug("Enabling UP settings\r\n");
+	print_debug("Enabling UP settings\n");
 	disable_probes();
 	return 1;
 }
 static u8 setup_smp(void)
 {
 	u8 cpus=2;
-	print_debug("Enabling SMP settings\r\n");
+	print_debug("Enabling SMP settings\n");
 	setup_row(0,0,cpus);
 	 
 	setup_temp_row(0,1,cpus);
 	
 	if (!check_connection(0, 7, 0x20  )) {
-		print_debug("No connection to Node 1.\r\n");
+		print_debug("No connection to Node 1.\n");
 		fill_row( 0 ,7,0x00010101 ) ;	 
 		setup_uniprocessor();	 
 		return 1;
@@ -2625,7 +2625,7 @@
 	fill_row( 0 ,7,0x00010101 ) ;	 
 	
 	print_debug_hex32(cpus);
-	print_debug(" nodes initialized.\r\n");
+	print_debug(" nodes initialized.\n");
 	return cpus;
 }
 static unsigned detect_mp_capabilities(unsigned cpus)
@@ -2634,7 +2634,7 @@
 	bool mp_cap= (-1) ;
 	print_debug("detect_mp_capabilities: ");
 	print_debug_hex32(cpus);
-	print_debug("\r\n");
+	print_debug("\n");
 	if (cpus>2)
 		mask=0x06;	 
 	else
@@ -2646,7 +2646,7 @@
 	if (mp_cap)
 		return cpus;
 	 
-	print_debug("One of the CPUs is not MP capable. Going back to UP\r\n");
+	print_debug("One of the CPUs is not MP capable. Going back to UP\n");
 	for (node=cpus; node>0; node--)
 	    for (row=cpus; row>0; row--)
 		fill_row(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node-1  ) & 0x1f) << 11) | ((( 0 )  & 0x7) << 8))  , row-1, 0x00010101 );
@@ -2659,7 +2659,7 @@
 	bool rev_a0;
 	
 	 
-	print_debug("coherent_ht_finalize\r\n");
+	print_debug("coherent_ht_finalize\n");
 	rev_a0= is_cpu_rev_a0();
 	for (node=0; node<cpus; node++) {
 		u32 val;
@@ -2676,7 +2676,7 @@
 			pci_write_config32(( ((( 0 ) & 0xFF) << 16) | ((( 24+ node  ) & 0x1f) << 11) | ((( 0 )  & 0x7) << 8))  ,0xd4,0);
 		}
 	}
-	print_debug("done\r\n");
+	print_debug("done\n");
 }
 static int setup_coherent_ht_domain(void)
 {
@@ -2692,7 +2692,7 @@
 }
 void sdram_no_memory(void)
 {
-	print_err("No memory!!\r\n");
+	print_err("No memory!!\n");
 	while(1) { 
 		hlt(); 
 	}
@@ -2705,20 +2705,20 @@
 	for(i = 0; i < controllers; i++) {
 		print_debug("Ram1.");
 		print_debug_hex8(i);
-		print_debug("\r\n");
+		print_debug("\n");
 		sdram_set_registers(ctrl + i);
 	}
 	 
 	for(i = 0; i < controllers; i++) {
 		print_debug("Ram2.");
 		print_debug_hex8(i);
-		print_debug("\r\n");
+		print_debug("\n");
 		sdram_set_spd_registers(ctrl + i);
 	}
 	 
-	print_debug("Ram3\r\n");
+	print_debug("Ram3\n");
 	sdram_enable(controllers, ctrl);
-	print_debug("Ram4\r\n");
+	print_debug("Ram4\n");
 }
 static void enable_lapic(void)
 {
Index: util/romcc/tests/simple_test23.c
===================================================================
--- util/romcc/tests/simple_test23.c	(revision 3942)
+++ util/romcc/tests/simple_test23.c	(working copy)
@@ -13,6 +13,6 @@
 
 static void main(void)
 {
-	print("hello world\r\n");
-	print("how are you today\r\n");
+	print("hello world\n");
+	print("how are you today\n");
 }
